projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
serial: sh-sci: Fix race condition between RX worker and cleanup
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
79904420
GU		 110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
73a19e4c
GL		 112 struct scatterlist sg_rx[2];
113 size_t buf_len_rx;
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
3089f381 119 unsigned int rx_timeout;
73a19e4c 120#endif
e552de24 121
d535a230 122 struct notifier_block freq_transition;
e108b2ca
PM		 123};
124
1da177e4 125/* Function prototypes */
d535a230 126static void sci_start_tx(struct uart_port *port);
b129a8cc 127static void sci_stop_tx(struct uart_port *port);
d535a230 128static void sci_start_rx(struct uart_port *port);
1da177e4 129
e108b2ca 130#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 131
e108b2ca
PM		 132static struct sci_port sci_ports[SCI_NPORTS];
133static struct uart_driver sci_uart_driver;
1da177e4 134
e7c98dc7
MT		 135static inline struct sci_port *
136to_sci_port(struct uart_port *uart)
137{
138 return container_of(uart, struct sci_port, port);
139}
140
61a6976b
PM		 141struct plat_sci_reg {
142 u8 offset, size;
143};
144
145/* Helper for invalidating specific entries of an inherited map. */
146#define sci_reg_invalid { .offset = 0, .size = 0 }
147
d3184e68 148static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151 },
152
153 /*
154 * Common SCI definitions, dependent on the port's regshift
155 * value.
156 */
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
f303b364 170 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 171 [SCPCR] = sci_reg_invalid,
172 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 173 },
174
175 /*
176 * Common definitions for legacy IrDA ports, dependent on
177 * regshift value.
178 */
179 [SCIx_IRDA_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 [SCFCR] = { 0x06, 8 },
187 [SCFDR] = { 0x07, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
f303b364 192 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 193 [SCPCR] = sci_reg_invalid,
194 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 195 },
196
197 /*
198 * Common SCIFA definitions.
199 */
200 [SCIx_SCIFA_REGTYPE] = {
201 [SCSMR] = { 0x00, 16 },
202 [SCBRR] = { 0x04, 8 },
203 [SCSCR] = { 0x08, 16 },
204 [SCxTDR] = { 0x20, 8 },
205 [SCxSR] = { 0x14, 16 },
206 [SCxRDR] = { 0x24, 8 },
207 [SCFCR] = { 0x18, 16 },
208 [SCFDR] = { 0x1c, 16 },
209 [SCTFDR] = sci_reg_invalid,
210 [SCRFDR] = sci_reg_invalid,
211 [SCSPTR] = sci_reg_invalid,
212 [SCLSR] = sci_reg_invalid,
f303b364 213 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 214 [SCPCR] = { 0x30, 16 },
215 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 216 },
217
218 /*
219 * Common SCIFB definitions.
220 */
221 [SCIx_SCIFB_REGTYPE] = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x40, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x60, 8 },
228 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 229 [SCFDR] = sci_reg_invalid,
230 [SCTFDR] = { 0x38, 16 },
231 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 232 [SCSPTR] = sci_reg_invalid,
233 [SCLSR] = sci_reg_invalid,
f303b364 234 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 235 [SCPCR] = { 0x30, 16 },
236 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 237 },
238
3af1f8a4
PE		 239 /*
240 * Common SH-2(A) SCIF definitions for ports with FIFO data
241 * count registers.
242 */
243 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x0c, 8 },
248 [SCxSR] = { 0x10, 16 },
249 [SCxRDR] = { 0x14, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = { 0x1c, 16 },
252 [SCTFDR] = sci_reg_invalid,
253 [SCRFDR] = sci_reg_invalid,
254 [SCSPTR] = { 0x20, 16 },
255 [SCLSR] = { 0x24, 16 },
f303b364 256 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 257 [SCPCR] = sci_reg_invalid,
258 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 259 },
260
61a6976b
PM		 261 /*
262 * Common SH-3 SCIF definitions.
263 */
264 [SCIx_SH3_SCIF_REGTYPE] = {
265 [SCSMR] = { 0x00, 8 },
266 [SCBRR] = { 0x02, 8 },
267 [SCSCR] = { 0x04, 8 },
268 [SCxTDR] = { 0x06, 8 },
269 [SCxSR] = { 0x08, 16 },
270 [SCxRDR] = { 0x0a, 8 },
271 [SCFCR] = { 0x0c, 8 },
272 [SCFDR] = { 0x0e, 16 },
273 [SCTFDR] = sci_reg_invalid,
274 [SCRFDR] = sci_reg_invalid,
275 [SCSPTR] = sci_reg_invalid,
276 [SCLSR] = sci_reg_invalid,
f303b364 277 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 278 [SCPCR] = sci_reg_invalid,
279 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 280 },
281
282 /*
283 * Common SH-4(A) SCIF(B) definitions.
284 */
285 [SCIx_SH4_SCIF_REGTYPE] = {
286 [SCSMR] = { 0x00, 16 },
287 [SCBRR] = { 0x04, 8 },
288 [SCSCR] = { 0x08, 16 },
289 [SCxTDR] = { 0x0c, 8 },
290 [SCxSR] = { 0x10, 16 },
291 [SCxRDR] = { 0x14, 8 },
292 [SCFCR] = { 0x18, 16 },
293 [SCFDR] = { 0x1c, 16 },
294 [SCTFDR] = sci_reg_invalid,
295 [SCRFDR] = sci_reg_invalid,
296 [SCSPTR] = { 0x20, 16 },
297 [SCLSR] = { 0x24, 16 },
f303b364 298 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 299 [SCPCR] = sci_reg_invalid,
300 [SCPDR] = sci_reg_invalid,
f303b364
UH		 301 },
302
303 /*
304 * Common HSCIF definitions.
305 */
306 [SCIx_HSCIF_REGTYPE] = {
307 [SCSMR] = { 0x00, 16 },
308 [SCBRR] = { 0x04, 8 },
309 [SCSCR] = { 0x08, 16 },
310 [SCxTDR] = { 0x0c, 8 },
311 [SCxSR] = { 0x10, 16 },
312 [SCxRDR] = { 0x14, 8 },
313 [SCFCR] = { 0x18, 16 },
314 [SCFDR] = { 0x1c, 16 },
315 [SCTFDR] = sci_reg_invalid,
316 [SCRFDR] = sci_reg_invalid,
317 [SCSPTR] = { 0x20, 16 },
318 [SCLSR] = { 0x24, 16 },
319 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 320 [SCPCR] = sci_reg_invalid,
321 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 322 },
323
324 /*
325 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
326 * register.
327 */
328 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
329 [SCSMR] = { 0x00, 16 },
330 [SCBRR] = { 0x04, 8 },
331 [SCSCR] = { 0x08, 16 },
332 [SCxTDR] = { 0x0c, 8 },
333 [SCxSR] = { 0x10, 16 },
334 [SCxRDR] = { 0x14, 8 },
335 [SCFCR] = { 0x18, 16 },
336 [SCFDR] = { 0x1c, 16 },
337 [SCTFDR] = sci_reg_invalid,
338 [SCRFDR] = sci_reg_invalid,
339 [SCSPTR] = sci_reg_invalid,
340 [SCLSR] = { 0x24, 16 },
f303b364 341 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 342 [SCPCR] = sci_reg_invalid,
343 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 344 },
345
346 /*
347 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
348 * count registers.
349 */
350 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
351 [SCSMR] = { 0x00, 16 },
352 [SCBRR] = { 0x04, 8 },
353 [SCSCR] = { 0x08, 16 },
354 [SCxTDR] = { 0x0c, 8 },
355 [SCxSR] = { 0x10, 16 },
356 [SCxRDR] = { 0x14, 8 },
357 [SCFCR] = { 0x18, 16 },
358 [SCFDR] = { 0x1c, 16 },
359 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
360 [SCRFDR] = { 0x20, 16 },
361 [SCSPTR] = { 0x24, 16 },
362 [SCLSR] = { 0x28, 16 },
f303b364 363 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 364 [SCPCR] = sci_reg_invalid,
365 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 366 },
367
368 /*
369 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
370 * registers.
371 */
372 [SCIx_SH7705_SCIF_REGTYPE] = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x20, 8 },
377 [SCxSR] = { 0x14, 16 },
378 [SCxRDR] = { 0x24, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCTFDR] = sci_reg_invalid,
382 [SCRFDR] = sci_reg_invalid,
383 [SCSPTR] = sci_reg_invalid,
384 [SCLSR] = sci_reg_invalid,
f303b364 385 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 386 [SCPCR] = sci_reg_invalid,
387 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 388 },
389};
390
72b294cf
PM		 391#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
392
61a6976b
PM		 393/*
394 * The "offset" here is rather misleading, in that it refers to an enum
395 * value relative to the port mapping rather than the fixed offset
396 * itself, which needs to be manually retrieved from the platform's
397 * register map for the given port.
398 */
399static unsigned int sci_serial_in(struct uart_port *p, int offset)
400{
d3184e68 401 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 402
403 if (reg->size == 8)
404 return ioread8(p->membase + (reg->offset << p->regshift));
405 else if (reg->size == 16)
406 return ioread16(p->membase + (reg->offset << p->regshift));
407 else
408 WARN(1, "Invalid register access\n");
409
410 return 0;
411}
412
413static void sci_serial_out(struct uart_port *p, int offset, int value)
414{
d3184e68 415 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 416
417 if (reg->size == 8)
418 iowrite8(value, p->membase + (reg->offset << p->regshift));
419 else if (reg->size == 16)
420 iowrite16(value, p->membase + (reg->offset << p->regshift));
421 else
422 WARN(1, "Invalid register access\n");
423}
424
61a6976b
PM		 425static int sci_probe_regmap(struct plat_sci_port *cfg)
426{
427 switch (cfg->type) {
428 case PORT_SCI:
429 cfg->regtype = SCIx_SCI_REGTYPE;
430 break;
431 case PORT_IRDA:
432 cfg->regtype = SCIx_IRDA_REGTYPE;
433 break;
434 case PORT_SCIFA:
435 cfg->regtype = SCIx_SCIFA_REGTYPE;
436 break;
437 case PORT_SCIFB:
438 cfg->regtype = SCIx_SCIFB_REGTYPE;
439 break;
440 case PORT_SCIF:
441 /*
442 * The SH-4 is a bit of a misnomer here, although that's
443 * where this particular port layout originated. This
444 * configuration (or some slight variation thereof)
445 * remains the dominant model for all SCIFs.
446 */
447 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
448 break;
f303b364
UH		 449 case PORT_HSCIF:
450 cfg->regtype = SCIx_HSCIF_REGTYPE;
451 break;
61a6976b 452 default:
6c13d5d2 453 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 454 return -EINVAL;
455 }
456
457 return 0;
458}
459
23241d43
PM		 460static void sci_port_enable(struct sci_port *sci_port)
461{
462 if (!sci_port->port.dev)
463 return;
464
465 pm_runtime_get_sync(sci_port->port.dev);
466
b016b646 467 clk_prepare_enable(sci_port->iclk);
23241d43 468 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 469 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 470}
471
472static void sci_port_disable(struct sci_port *sci_port)
473{
474 if (!sci_port->port.dev)
475 return;
476
caec7038
LP		 477 /* Cancel the break timer to ensure that the timer handler will not try
478 * to access the hardware with clocks and power disabled. Reset the
479 * break flag to make the break debouncing state machine ready for the
480 * next break.
481 */
482 del_timer_sync(&sci_port->break_timer);
483 sci_port->break_flag = 0;
484
b016b646
LP		 485 clk_disable_unprepare(sci_port->fclk);
486 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 487
488 pm_runtime_put_sync(sci_port->port.dev);
489}
490
a1b5b43f
GU		 491static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
492{
493 if (port->type == PORT_SCI) {
494 /* Just store the mask */
495 serial_port_out(port, SCxSR, mask);
496 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
497 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
498 /* Only clear the status bits we want to clear */
499 serial_port_out(port, SCxSR,
500 serial_port_in(port, SCxSR) & mask);
501 } else {
502 /* Store the mask, clear parity/framing errors */
503 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
504 }
505}
506
07d2a1a1 507#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 508
509#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 510static int sci_poll_get_char(struct uart_port *port)
1da177e4 511{
1da177e4
LT		 512 unsigned short status;
513 int c;
514
e108b2ca 515 do {
b12bb29f 516 status = serial_port_in(port, SCxSR);
1da177e4 517 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 518 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 519 continue;
520 }
3f255eb3
JW		 521 break;
522 } while (1);
523
524 if (!(status & SCxSR_RDxF(port)))
525 return NO_POLL_CHAR;
07d2a1a1 526
b12bb29f 527 c = serial_port_in(port, SCxRDR);
07d2a1a1 528
e7c98dc7 529 /* Dummy read */
b12bb29f 530 serial_port_in(port, SCxSR);
a1b5b43f 531 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 532
533 return c;
534}
1f6fd5c9 535#endif
1da177e4 536
07d2a1a1 537static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 538{
1da177e4
LT		 539 unsigned short status;
540
1da177e4 541 do {
b12bb29f 542 status = serial_port_in(port, SCxSR);
1da177e4
LT		 543 } while (!(status & SCxSR_TDxE(port)));
544
b12bb29f 545 serial_port_out(port, SCxTDR, c);
a1b5b43f 546 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 547}
07d2a1a1 548#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 549
61a6976b 550static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 551{
61a6976b 552 struct sci_port *s = to_sci_port(port);
d3184e68 553 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 554
61a6976b
PM		 555 /*
556 * Use port-specific handler if provided.
557 */
558 if (s->cfg->ops && s->cfg->ops->init_pins) {
559 s->cfg->ops->init_pins(port, cflag);
560 return;
1da177e4 561 }
41504c39 562
61a6976b
PM		 563 /*
564 * For the generic path SCSPTR is necessary. Bail out if that's
565 * unavailable, too.
566 */
567 if (!reg->size)
568 return;
41504c39 569
faf02f8f
PM		 570 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
571 ((!(cflag & CRTSCTS)))) {
572 unsigned short status;
573
b12bb29f 574 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 575 status &= ~SCSPTR_CTSIO;
576 status |= SCSPTR_RTSIO;
b12bb29f 577 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 578 }
d5701647 579}
e108b2ca 580
72b294cf 581static int sci_txfill(struct uart_port *port)
e108b2ca 582{
d3184e68 583 const struct plat_sci_reg *reg;
e108b2ca 584
72b294cf
PM		 585 reg = sci_getreg(port, SCTFDR);
586 if (reg->size)
63f7ad11 587 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 588
72b294cf
PM		 589 reg = sci_getreg(port, SCFDR);
590 if (reg->size)
b12bb29f 591 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 592
b12bb29f 593 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 594}
595
73a19e4c
GL		 596static int sci_txroom(struct uart_port *port)
597{
72b294cf 598 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 599}
600
601static int sci_rxfill(struct uart_port *port)
e108b2ca 602{
d3184e68 603 const struct plat_sci_reg *reg;
72b294cf
PM		 604
605 reg = sci_getreg(port, SCRFDR);
606 if (reg->size)
63f7ad11 607 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 608
609 reg = sci_getreg(port, SCFDR);
610 if (reg->size)
b12bb29f 611 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 612
b12bb29f 613 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 614}
615
514820eb
PM		 616/*
617 * SCI helper for checking the state of the muxed port/RXD pins.
618 */
619static inline int sci_rxd_in(struct uart_port *port)
620{
621 struct sci_port *s = to_sci_port(port);
622
623 if (s->cfg->port_reg <= 0)
624 return 1;
625
0dd4d5cb 626 /* Cast for ARM damage */
e2afca69 627 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 628}
629
1da177e4
LT		 630/* ********************************************************************** *
631 * the interrupt related routines *
632 * ********************************************************************** */
633
634static void sci_transmit_chars(struct uart_port *port)
635{
ebd2c8f6 636 struct circ_buf *xmit = &port->state->xmit;
1da177e4 637 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 638 unsigned short status;
639 unsigned short ctrl;
e108b2ca 640 int count;
1da177e4 641
b12bb29f 642 status = serial_port_in(port, SCxSR);
1da177e4 643 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 644 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 645 if (uart_circ_empty(xmit))
8e698614 646 ctrl &= ~SCSCR_TIE;
e7c98dc7 647 else
8e698614 648 ctrl |= SCSCR_TIE;
b12bb29f 649 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 650 return;
651 }
652
72b294cf 653 count = sci_txroom(port);
1da177e4
LT		 654
655 do {
656 unsigned char c;
657
658 if (port->x_char) {
659 c = port->x_char;
660 port->x_char = 0;
661 } else if (!uart_circ_empty(xmit) && !stopped) {
662 c = xmit->buf[xmit->tail];
663 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
664 } else {
665 break;
666 }
667
b12bb29f 668 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 669
670 port->icount.tx++;
671 } while (--count > 0);
672
a1b5b43f 673 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 674
675 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
676 uart_write_wakeup(port);
677 if (uart_circ_empty(xmit)) {
b129a8cc 678 sci_stop_tx(port);
1da177e4 679 } else {
b12bb29f 680 ctrl = serial_port_in(port, SCSCR);
1da177e4 681
1a22f08d 682 if (port->type != PORT_SCI) {
b12bb29f 683 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 684 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 685 }
1da177e4 686
8e698614 687 ctrl |= SCSCR_TIE;
b12bb29f 688 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 689 }
690}
691
692/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 693#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 694
94c8b6db 695static void sci_receive_chars(struct uart_port *port)
1da177e4 696{
e7c98dc7 697 struct sci_port *sci_port = to_sci_port(port);
227434f8 698 struct tty_port *tport = &port->state->port;
1da177e4
LT		 699 int i, count, copied = 0;
700 unsigned short status;
33f0f88f 701 unsigned char flag;
1da177e4 702
b12bb29f 703 status = serial_port_in(port, SCxSR);
1da177e4
LT		 704 if (!(status & SCxSR_RDxF(port)))
705 return;
706
707 while (1) {
1da177e4 708 /* Don't copy more bytes than there is room for in the buffer */
227434f8 709 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 710
711 /* If for any reason we can't copy more data, we're done! */
712 if (count == 0)
713 break;
714
715 if (port->type == PORT_SCI) {
b12bb29f 716 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 717 if (uart_handle_sysrq_char(port, c) ||
718 sci_port->break_flag)
1da177e4 719 count = 0;
e7c98dc7 720 else
92a19f9c 721 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 722 } else {
e7c98dc7 723 for (i = 0; i < count; i++) {
b12bb29f 724 char c = serial_port_in(port, SCxRDR);
d97fbbed 725
b12bb29f 726 status = serial_port_in(port, SCxSR);
1da177e4
LT		 727#if defined(CONFIG_CPU_SH3)
728 /* Skip "chars" during break */
e108b2ca 729 if (sci_port->break_flag) {
1da177e4
LT		 730 if ((c == 0) &&
731 (status & SCxSR_FER(port))) {
732 count--; i--;
733 continue;
734 }
e108b2ca 735
1da177e4 736 /* Nonzero => end-of-break */
762c69e3 737 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 738 sci_port->break_flag = 0;
739
1da177e4
LT		 740 if (STEPFN(c)) {
741 count--; i--;
742 continue;
743 }
744 }
745#endif /* CONFIG_CPU_SH3 */
7d12e780 746 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 747 count--; i--;
748 continue;
749 }
750
751 /* Store data and status */
73a19e4c 752 if (status & SCxSR_FER(port)) {
33f0f88f 753 flag = TTY_FRAME;
d97fbbed 754 port->icount.frame++;
762c69e3 755 dev_notice(port->dev, "frame error\n");
73a19e4c 756 } else if (status & SCxSR_PER(port)) {
33f0f88f 757 flag = TTY_PARITY;
d97fbbed 758 port->icount.parity++;
762c69e3 759 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 760 } else
761 flag = TTY_NORMAL;
762c69e3 762
92a19f9c 763 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 764 }
765 }
766
b12bb29f 767 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 768 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 769
1da177e4
LT		 770 copied += count;
771 port->icount.rx += count;
772 }
773
774 if (copied) {
775 /* Tell the rest of the system the news. New characters! */
2e124b4a 776 tty_flip_buffer_push(tport);
1da177e4 777 } else {
b12bb29f 778 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 779 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 780 }
781}
782
783#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 784
785/*
786 * The sci generates interrupts during the break,
1da177e4
LT		 787 * 1 per millisecond or so during the break period, for 9600 baud.
788 * So dont bother disabling interrupts.
789 * But dont want more than 1 break event.
790 * Use a kernel timer to periodically poll the rx line until
791 * the break is finished.
792 */
94c8b6db 793static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 794{
bc9b3f5c 795 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 796}
94c8b6db 797
1da177e4
LT		 798/* Ensure that two consecutive samples find the break over. */
799static void sci_break_timer(unsigned long data)
800{
e108b2ca
PM		 801 struct sci_port *port = (struct sci_port *)data;
802
803 if (sci_rxd_in(&port->port) == 0) {
1da177e4 804 port->break_flag = 1;
e108b2ca
PM		 805 sci_schedule_break_timer(port);
806 } else if (port->break_flag == 1) {
1da177e4
LT		 807 /* break is over. */
808 port->break_flag = 2;
e108b2ca
PM		 809 sci_schedule_break_timer(port);
810 } else
811 port->break_flag = 0;
1da177e4
LT		 812}
813
94c8b6db 814static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 815{
816 int copied = 0;
b12bb29f 817 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 818 struct tty_port *tport = &port->state->port;
debf9507 819 struct sci_port *s = to_sci_port(port);
1da177e4 820
3ae988d9 821 /* Handle overruns */
75c249fd 822 if (status & s->overrun_mask) {
3ae988d9 823 port->icount.overrun++;
d97fbbed 824
3ae988d9
LP		 825 /* overrun error */
826 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
827 copied++;
762c69e3 828
9b971cd2 829 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 830 }
831
e108b2ca 832 if (status & SCxSR_FER(port)) {
1da177e4
LT		 833 if (sci_rxd_in(port) == 0) {
834 /* Notify of BREAK */
e7c98dc7 835 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 836
837 if (!sci_port->break_flag) {
d97fbbed
PM		 838 port->icount.brk++;
839
e108b2ca
PM		 840 sci_port->break_flag = 1;
841 sci_schedule_break_timer(sci_port);
842
1da177e4 843 /* Do sysrq handling. */
e108b2ca 844 if (uart_handle_break(port))
1da177e4 845 return 0;
762c69e3
PM		 846
847 dev_dbg(port->dev, "BREAK detected\n");
848
92a19f9c 849 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 850 copied++;
851 }
852
e108b2ca 853 } else {
1da177e4 854 /* frame error */
d97fbbed
PM		 855 port->icount.frame++;
856
92a19f9c 857 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 858 copied++;
762c69e3
PM		 859
860 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 861 }
862 }
863
e108b2ca 864 if (status & SCxSR_PER(port)) {
1da177e4 865 /* parity error */
d97fbbed
PM		 866 port->icount.parity++;
867
92a19f9c 868 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 869 copied++;
762c69e3 870
9b971cd2 871 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 872 }
873
33f0f88f 874 if (copied)
2e124b4a 875 tty_flip_buffer_push(tport);
1da177e4
LT		 876
877 return copied;
878}
879
94c8b6db 880static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 881{
92a19f9c 882 struct tty_port *tport = &port->state->port;
debf9507 883 struct sci_port *s = to_sci_port(port);
d3184e68 884 const struct plat_sci_reg *reg;
2e0842a1 885 int copied = 0;
75c249fd 886 u16 status;
d830fa45 887
2e0842a1 888 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 889 if (!reg->size)
d830fa45
PM		 890 return 0;
891
2e0842a1 892 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 893 if (status & s->overrun_mask) {
894 status &= ~s->overrun_mask;
2e0842a1 895 serial_port_out(port, s->overrun_reg, status);
d830fa45 896
d97fbbed
PM		 897 port->icount.overrun++;
898
92a19f9c 899 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 900 tty_flip_buffer_push(tport);
d830fa45 901
51b31f1c 902 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 903 copied++;
904 }
905
906 return copied;
907}
908
94c8b6db 909static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 910{
911 int copied = 0;
b12bb29f 912 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 913 struct tty_port *tport = &port->state->port;
a5660ada 914 struct sci_port *s = to_sci_port(port);
1da177e4 915
0b3d4ef6
PM		 916 if (uart_handle_break(port))
917 return 0;
918
b7a76e4b 919 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 920#if defined(CONFIG_CPU_SH3)
921 /* Debounce break */
922 s->break_flag = 1;
923#endif
d97fbbed
PM		 924
925 port->icount.brk++;
926
1da177e4 927 /* Notify of BREAK */
92a19f9c 928 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 929 copied++;
762c69e3
PM		 930
931 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 932 }
933
33f0f88f 934 if (copied)
2e124b4a 935 tty_flip_buffer_push(tport);
e108b2ca 936
d830fa45
PM		 937 copied += sci_handle_fifo_overrun(port);
938
1da177e4
LT		 939 return copied;
940}
941
73a19e4c 942static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 943{
73a19e4c
GL		 944#ifdef CONFIG_SERIAL_SH_SCI_DMA
945 struct uart_port *port = ptr;
946 struct sci_port *s = to_sci_port(port);
947
948 if (s->chan_rx) {
b12bb29f
PM		 949 u16 scr = serial_port_in(port, SCSCR);
950 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 951
952 /* Disable future Rx interrupts */
d1d4b10c 953 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 954 disable_irq_nosync(irq);
26de4f1b 955 scr |= SCSCR_RDRQE;
3089f381 956 } else {
f43dc23d 957 scr &= ~SCSCR_RIE;
3089f381 958 }
b12bb29f 959 serial_port_out(port, SCSCR, scr);
73a19e4c 960 /* Clear current interrupt */
54af5001
GU		 961 serial_port_out(port, SCxSR,
962 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
3089f381
GL		 963 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
964 jiffies, s->rx_timeout);
965 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 966
967 return IRQ_HANDLED;
968 }
969#endif
970
1da177e4
LT		 971 /* I think sci_receive_chars has to be called irrespective
972 * of whether the I_IXOFF is set, otherwise, how is the interrupt
973 * to be disabled?
974 */
73a19e4c 975 sci_receive_chars(ptr);
1da177e4
LT		 976
977 return IRQ_HANDLED;
978}
979
7d12e780 980static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 981{
982 struct uart_port *port = ptr;
fd78a76a 983 unsigned long flags;
1da177e4 984
fd78a76a 985 spin_lock_irqsave(&port->lock, flags);
1da177e4 986 sci_transmit_chars(port);
fd78a76a 987 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 988
989 return IRQ_HANDLED;
990}
991
7d12e780 992static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 993{
994 struct uart_port *port = ptr;
995
996 /* Handle errors */
997 if (port->type == PORT_SCI) {
998 if (sci_handle_errors(port)) {
999 /* discard character in rx buffer */
b12bb29f 1000 serial_port_in(port, SCxSR);
a1b5b43f 1001 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 1002 }
1003 } else {
d830fa45 1004 sci_handle_fifo_overrun(port);
7d12e780 1005 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 1006 }
1007
a1b5b43f 1008 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 1009
1010 /* Kick the transmission */
7d12e780 1011 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 1012
1013 return IRQ_HANDLED;
1014}
1015
7d12e780 1016static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 1017{
1018 struct uart_port *port = ptr;
1019
1020 /* Handle BREAKs */
1021 sci_handle_breaks(port);
a1b5b43f 1022 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 1023
1024 return IRQ_HANDLED;
1025}
1026
f43dc23d
PM		 1027static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1028{
1029 /*
1030 * Not all ports (such as SCIFA) will support REIE. Rather than
1031 * special-casing the port type, we check the port initialization
1032 * IRQ enable mask to see whether the IRQ is desired at all. If
1033 * it's unset, it's logically inferred that there's no point in
1034 * testing for it.
1035 */
ce6738b6 1036 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 1037}
1038
7d12e780 1039static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 1040{
cb772fe7 1041 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
a8884e34 1042 struct uart_port *port = ptr;
73a19e4c 1043 struct sci_port *s = to_sci_port(port);
a8884e34 1044 irqreturn_t ret = IRQ_NONE;
1da177e4 1045
b12bb29f
PM		 1046 ssr_status = serial_port_in(port, SCxSR);
1047 scr_status = serial_port_in(port, SCSCR);
2e0842a1 1048 if (s->overrun_reg == SCxSR)
cb772fe7 1049 orer_status = ssr_status;
2e0842a1
GU		 1050 else {
1051 if (sci_getreg(port, s->overrun_reg)->size)
1052 orer_status = serial_port_in(port, s->overrun_reg);
cb772fe7
NI		 1053 }
1054
f43dc23d 1055 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 1056
1057 /* Tx Interrupt */
f43dc23d 1058 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 1059 !s->chan_tx)
a8884e34 1060 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 1061
73a19e4c
GL		 1062 /*
1063 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1064 * DR flags
1065 */
1066 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
e0a12a27 1067 (scr_status & SCSCR_RIE))
a8884e34 1068 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1069
1da177e4 1070 /* Error Interrupt */
dd4da3a5 1071 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1072 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1073
1da177e4 1074 /* Break Interrupt */
dd4da3a5 1075 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1076 ret = sci_br_interrupt(irq, ptr);
1da177e4 1077
8b6ff84c 1078 /* Overrun Interrupt */
90803072 1079 if (orer_status & s->overrun_mask) {
cb772fe7 1080 sci_handle_fifo_overrun(port);
90803072
YS		 1081 ret = IRQ_HANDLED;
1082 }
8b6ff84c 1083
a8884e34 1084 return ret;
1da177e4
LT		 1085}
1086
1da177e4 1087/*
25985edc 1088 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1089 * ports' baud rate when the peripheral clock changes.
1090 */
e108b2ca
PM		 1091static int sci_notifier(struct notifier_block *self,
1092 unsigned long phase, void *p)
1da177e4 1093{
e552de24
MD		 1094 struct sci_port *sci_port;
1095 unsigned long flags;
1da177e4 1096
d535a230
PM		 1097 sci_port = container_of(self, struct sci_port, freq_transition);
1098
0b443ead 1099 if (phase == CPUFREQ_POSTCHANGE) {
d535a230 1100 struct uart_port *port = &sci_port->port;
073e84c9 1101
d535a230
PM		 1102 spin_lock_irqsave(&port->lock, flags);
1103 port->uartclk = clk_get_rate(sci_port->iclk);
1104 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1105 }
1da177e4 1106
1da177e4
LT		 1107 return NOTIFY_OK;
1108}
501b825d 1109
d56a91e8 1110static const struct sci_irq_desc {
9174fc8f
PM		 1111 const char *desc;
1112 irq_handler_t handler;
1113} sci_irq_desc[] = {
1114 /*
1115 * Split out handlers, the default case.
1116 */
1117 [SCIx_ERI_IRQ] = {
1118 .desc = "rx err",
1119 .handler = sci_er_interrupt,
1120 },
1121
1122 [SCIx_RXI_IRQ] = {
1123 .desc = "rx full",
1124 .handler = sci_rx_interrupt,
1125 },
1126
1127 [SCIx_TXI_IRQ] = {
1128 .desc = "tx empty",
1129 .handler = sci_tx_interrupt,
1130 },
1131
1132 [SCIx_BRI_IRQ] = {
1133 .desc = "break",
1134 .handler = sci_br_interrupt,
1135 },
1136
1137 /*
1138 * Special muxed handler.
1139 */
1140 [SCIx_MUX_IRQ] = {
1141 .desc = "mux",
1142 .handler = sci_mpxed_interrupt,
1143 },
1144};
1145
1da177e4
LT		 1146static int sci_request_irq(struct sci_port *port)
1147{
9174fc8f
PM		 1148 struct uart_port *up = &port->port;
1149 int i, j, ret = 0;
1150
1151 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
d56a91e8 1152 const struct sci_irq_desc *desc;
1fcc91a6 1153 int irq;
9174fc8f
PM		 1154
1155 if (SCIx_IRQ_IS_MUXED(port)) {
1156 i = SCIx_MUX_IRQ;
1157 irq = up->irq;
0e8963de 1158 } else {
1fcc91a6 1159 irq = port->irqs[i];
9174fc8f 1160
0e8963de
PM		 1161 /*
1162 * Certain port types won't support all of the
1163 * available interrupt sources.
1164 */
1fcc91a6 1165 if (unlikely(irq < 0))
0e8963de
PM		 1166 continue;
1167 }
1168
9174fc8f
PM		 1169 desc = sci_irq_desc + i;
1170 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1171 dev_name(up->dev), desc->desc);
4205463c 1172 if (!port->irqstr[j])
9174fc8f 1173 goto out_nomem;
9174fc8f
PM		 1174
1175 ret = request_irq(irq, desc->handler, up->irqflags,
1176 port->irqstr[j], port);
1177 if (unlikely(ret)) {
1178 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1179 goto out_noirq;
1da177e4
LT		 1180 }
1181 }
1182
1183 return 0;
9174fc8f
PM		 1184
1185out_noirq:
1186 while (--i >= 0)
1fcc91a6 1187 free_irq(port->irqs[i], port);
9174fc8f
PM		 1188
1189out_nomem:
1190 while (--j >= 0)
1191 kfree(port->irqstr[j]);
1192
1193 return ret;
1da177e4
LT		 1194}
1195
1196static void sci_free_irq(struct sci_port *port)
1197{
1198 int i;
1199
9174fc8f
PM		 1200 /*
1201 * Intentionally in reverse order so we iterate over the muxed
1202 * IRQ first.
1203 */
1204 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1205 int irq = port->irqs[i];
0e8963de
PM		 1206
1207 /*
1208 * Certain port types won't support all of the available
1209 * interrupt sources.
1210 */
1fcc91a6 1211 if (unlikely(irq < 0))
0e8963de
PM		 1212 continue;
1213
1fcc91a6 1214 free_irq(port->irqs[i], port);
9174fc8f 1215 kfree(port->irqstr[i]);
1da177e4 1216
9174fc8f
PM		 1217 if (SCIx_IRQ_IS_MUXED(port)) {
1218 /* If there's only one IRQ, we're done. */
1219 return;
1da177e4
LT		 1220 }
1221 }
1222}
1223
1224static unsigned int sci_tx_empty(struct uart_port *port)
1225{
b12bb29f 1226 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1227 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1228
1229 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1230}
1231
cdf7c42f
PM		 1232/*
1233 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1234 * CTS/RTS is supported in hardware by at least one port and controlled
1235 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1236 * handled via the ->init_pins() op, which is a bit of a one-way street,
1237 * lacking any ability to defer pin control -- this will later be
1238 * converted over to the GPIO framework).
dc7e3ef7
PM		 1239 *
1240 * Other modes (such as loopback) are supported generically on certain
1241 * port types, but not others. For these it's sufficient to test for the
1242 * existence of the support register and simply ignore the port type.
cdf7c42f 1243 */
1da177e4
LT		 1244static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1245{
dc7e3ef7 1246 if (mctrl & TIOCM_LOOP) {
d3184e68 1247 const struct plat_sci_reg *reg;
dc7e3ef7
PM		 1248
1249 /*
1250 * Standard loopback mode for SCFCR ports.
1251 */
1252 reg = sci_getreg(port, SCFCR);
1253 if (reg->size)
26de4f1b
GU		 1254 serial_port_out(port, SCFCR,
1255 serial_port_in(port, SCFCR) |
1256 SCFCR_LOOP);
dc7e3ef7 1257 }
1da177e4
LT		 1258}
1259
1260static unsigned int sci_get_mctrl(struct uart_port *port)
1261{
cdf7c42f
PM		 1262 /*
1263 * CTS/RTS is handled in hardware when supported, while nothing
1264 * else is wired up. Keep it simple and simply assert DSR/CAR.
1265 */
1266 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1267}
1268
73a19e4c
GL		 1269#ifdef CONFIG_SERIAL_SH_SCI_DMA
1270static void sci_dma_tx_complete(void *arg)
1271{
1272 struct sci_port *s = arg;
1273 struct uart_port *port = &s->port;
1274 struct circ_buf *xmit = &port->state->xmit;
1275 unsigned long flags;
1276
1277 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1278
1279 spin_lock_irqsave(&port->lock, flags);
1280
79904420 1281 xmit->tail += s->tx_dma_len;
73a19e4c
GL		 1282 xmit->tail &= UART_XMIT_SIZE - 1;
1283
79904420 1284 port->icount.tx += s->tx_dma_len;
73a19e4c 1285
73a19e4c
GL		 1286 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1287 uart_write_wakeup(port);
1288
3089f381 1289 if (!uart_circ_empty(xmit)) {
49d4bcad 1290 s->cookie_tx = 0;
73a19e4c 1291 schedule_work(&s->work_tx);
49d4bcad
YT		 1292 } else {
1293 s->cookie_tx = -EINVAL;
1294 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1295 u16 ctrl = serial_port_in(port, SCSCR);
1296 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1297 }
3089f381
GL		 1298 }
1299
1300 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1301}
1302
1303/* Locking: called with port lock held */
92a19f9c 1304static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1305{
1306 struct uart_port *port = &s->port;
227434f8 1307 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1308 int i, active, room;
1309
227434f8 1310 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1311
1312 if (s->active_rx == s->cookie_rx[0]) {
1313 active = 0;
1314 } else if (s->active_rx == s->cookie_rx[1]) {
1315 active = 1;
1316 } else {
beb9487b
GU		 1317 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1318 s->active_rx);
73a19e4c
GL		 1319 return 0;
1320 }
1321
1322 if (room < count)
e2afca69 1323 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1324 count - room);
1325 if (!room)
1326 return room;
1327
1328 for (i = 0; i < room; i++)
92a19f9c 1329 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1330 TTY_NORMAL);
1331
1332 port->icount.rx += room;
1333
1334 return room;
1335}
1336
1337static void sci_dma_rx_complete(void *arg)
1338{
1339 struct sci_port *s = arg;
1340 struct uart_port *port = &s->port;
73a19e4c
GL		 1341 unsigned long flags;
1342 int count;
1343
beb9487b
GU		 1344 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1345 s->active_rx);
73a19e4c
GL		 1346
1347 spin_lock_irqsave(&port->lock, flags);
1348
92a19f9c 1349 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1350
3089f381 1351 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1352
1353 spin_unlock_irqrestore(&port->lock, flags);
1354
1355 if (count)
2e124b4a 1356 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1357
1358 schedule_work(&s->work_rx);
1359}
1360
73a19e4c
GL		 1361static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1362{
1363 struct dma_chan *chan = s->chan_rx;
1364 struct uart_port *port = &s->port;
04928b79 1365 unsigned long flags;
73a19e4c 1366
04928b79 1367 spin_lock_irqsave(&port->lock, flags);
73a19e4c
GL		 1368 s->chan_rx = NULL;
1369 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
04928b79
GU		 1370 spin_unlock_irqrestore(&port->lock, flags);
1371 dmaengine_terminate_all(chan);
8e14ba8f 1372 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2,
b9258020 1373 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
8e14ba8f 1374 dma_release_channel(chan);
73a19e4c
GL		 1375 if (enable_pio)
1376 sci_start_rx(port);
1377}
1378
1379static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1380{
1381 struct dma_chan *chan = s->chan_tx;
1382 struct uart_port *port = &s->port;
04928b79 1383 unsigned long flags;
73a19e4c 1384
04928b79 1385 spin_lock_irqsave(&port->lock, flags);
73a19e4c
GL		 1386 s->chan_tx = NULL;
1387 s->cookie_tx = -EINVAL;
04928b79
GU		 1388 spin_unlock_irqrestore(&port->lock, flags);
1389 dmaengine_terminate_all(chan);
2e301474
GU		 1390 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1391 DMA_TO_DEVICE);
73a19e4c
GL		 1392 dma_release_channel(chan);
1393 if (enable_pio)
1394 sci_start_tx(port);
1395}
1396
1397static void sci_submit_rx(struct sci_port *s)
1398{
1399 struct dma_chan *chan = s->chan_rx;
1400 int i;
1401
1402 for (i = 0; i < 2; i++) {
1403 struct scatterlist *sg = &s->sg_rx[i];
1404 struct dma_async_tx_descriptor *desc;
1405
16052827 1406 desc = dmaengine_prep_slave_sg(chan,
47aceb92
GU		 1407 sg, 1, DMA_DEV_TO_MEM,
1408 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
658daa95
GU		 1409 if (!desc)
1410 goto fail;
73a19e4c 1411
658daa95
GU		 1412 desc->callback = sci_dma_rx_complete;
1413 desc->callback_param = s;
1414 s->cookie_rx[i] = dmaengine_submit(desc);
1415 if (dma_submit_error(s->cookie_rx[i]))
1416 goto fail;
73a19e4c 1417
beb9487b
GU		 1418 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1419 s->cookie_rx[i], i);
73a19e4c
GL		 1420 }
1421
1422 s->active_rx = s->cookie_rx[0];
1423
1424 dma_async_issue_pending(chan);
658daa95
GU		 1425 return;
1426
1427fail:
1428 if (i)
1429 dmaengine_terminate_all(chan);
47aceb92 1430 for (i = 0; i < 2; i++)
658daa95 1431 s->cookie_rx[i] = -EINVAL;
658daa95
GU		 1432 s->active_rx = -EINVAL;
1433 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1434 sci_rx_dma_release(s, true);
73a19e4c
GL		 1435}
1436
1437static void work_fn_rx(struct work_struct *work)
1438{
1439 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1440 struct uart_port *port = &s->port;
1441 struct dma_async_tx_descriptor *desc;
565dd11a
GU		 1442 struct dma_tx_state state;
1443 enum dma_status status;
0907c100 1444 unsigned long flags;
73a19e4c
GL		 1445 int new;
1446
0907c100 1447 spin_lock_irqsave(&port->lock, flags);
73a19e4c
GL		 1448 if (s->active_rx == s->cookie_rx[0]) {
1449 new = 0;
1450 } else if (s->active_rx == s->cookie_rx[1]) {
1451 new = 1;
1452 } else {
beb9487b
GU		 1453 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1454 s->active_rx);
04928b79
GU		 1455 spin_unlock_irqrestore(&port->lock, flags);
1456 return;
73a19e4c 1457 }
73a19e4c 1458
565dd11a
GU		 1459 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1460 if (status != DMA_COMPLETE) {
73a19e4c 1461 /* Handle incomplete DMA receive */
73a19e4c 1462 struct dma_chan *chan = s->chan_rx;
565dd11a 1463 unsigned int read;
73a19e4c
GL		 1464 int count;
1465
2bcd90d5 1466 dmaengine_terminate_all(chan);
565dd11a
GU		 1467 read = sg_dma_len(&s->sg_rx[new]) - state.residue;
1468 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1469 s->active_rx);
73a19e4c 1470
565dd11a 1471 count = sci_dma_rx_push(s, read);
73a19e4c
GL		 1472
1473 if (count)
2e124b4a 1474 tty_flip_buffer_push(&port->state->port);
73a19e4c 1475
04928b79 1476 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c 1477
04928b79
GU		 1478 sci_submit_rx(s);
1479 return;
73a19e4c
GL		 1480 }
1481
47aceb92
GU		 1482 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[new], 1,
1483 DMA_DEV_TO_MEM,
1484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1485 if (!desc)
1486 goto fail;
1487
1488 desc->callback = sci_dma_rx_complete;
1489 desc->callback_param = s;
3e14670c 1490 s->cookie_rx[new] = dmaengine_submit(desc);
47aceb92
GU		 1491 if (dma_submit_error(s->cookie_rx[new]))
1492 goto fail;
73a19e4c 1493
73a19e4c 1494 s->active_rx = s->cookie_rx[!new];
3089f381 1495
beb9487b 1496 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
9b971cd2 1497 __func__, s->cookie_rx[new], new, s->active_rx);
0907c100 1498 spin_unlock_irqrestore(&port->lock, flags);
47aceb92
GU		 1499 return;
1500
1501fail:
04928b79 1502 spin_unlock_irqrestore(&port->lock, flags);
47aceb92
GU		 1503 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1504 sci_rx_dma_release(s, true);
73a19e4c
GL		 1505}
1506
1507static void work_fn_tx(struct work_struct *work)
1508{
1509 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1510 struct dma_async_tx_descriptor *desc;
1511 struct dma_chan *chan = s->chan_tx;
1512 struct uart_port *port = &s->port;
1513 struct circ_buf *xmit = &port->state->xmit;
79904420 1514 dma_addr_t buf;
73a19e4c
GL		 1515
1516 /*
1517 * DMA is idle now.
1518 * Port xmit buffer is already mapped, and it is one page... Just adjust
1519 * offsets and lengths. Since it is a circular buffer, we have to
1520 * transmit till the end, and then the rest. Take the port lock to get a
1521 * consistent xmit buffer state.
1522 */
1523 spin_lock_irq(&port->lock);
79904420
GU		 1524 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1525 s->tx_dma_len = min_t(unsigned int,
092248aa 1526 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1527 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1528 spin_unlock_irq(&port->lock);
1529
79904420
GU		 1530 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1531 DMA_MEM_TO_DEV,
1532 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
73a19e4c 1533 if (!desc) {
beb9487b 1534 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
73a19e4c
GL		 1535 /* switch to PIO */
1536 sci_tx_dma_release(s, true);
1537 return;
1538 }
1539
79904420
GU		 1540 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1541 DMA_TO_DEVICE);
73a19e4c
GL		 1542
1543 spin_lock_irq(&port->lock);
73a19e4c
GL		 1544 desc->callback = sci_dma_tx_complete;
1545 desc->callback_param = s;
1546 spin_unlock_irq(&port->lock);
3e14670c
GU		 1547 s->cookie_tx = dmaengine_submit(desc);
1548 if (dma_submit_error(s->cookie_tx)) {
73a19e4c
GL		 1549 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1550 /* switch to PIO */
1551 sci_tx_dma_release(s, true);
1552 return;
1553 }
1554
9b971cd2
JP		 1555 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1556 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c
GL		 1557
1558 dma_async_issue_pending(chan);
1559}
1560#endif
1561
b129a8cc 1562static void sci_start_tx(struct uart_port *port)
1da177e4 1563{
3089f381 1564 struct sci_port *s = to_sci_port(port);
e108b2ca 1565 unsigned short ctrl;
1da177e4 1566
73a19e4c 1567#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1568 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1569 u16 new, scr = serial_port_in(port, SCSCR);
3089f381 1570 if (s->chan_tx)
26de4f1b 1571 new = scr | SCSCR_TDRQE;
3089f381 1572 else
26de4f1b 1573 new = scr & ~SCSCR_TDRQE;
3089f381 1574 if (new != scr)
b12bb29f 1575 serial_port_out(port, SCSCR, new);
73a19e4c 1576 }
f43dc23d 1577
3089f381 1578 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
3e14670c 1579 dma_submit_error(s->cookie_tx)) {
49d4bcad 1580 s->cookie_tx = 0;
3089f381 1581 schedule_work(&s->work_tx);
49d4bcad 1582 }
73a19e4c 1583#endif
f43dc23d 1584
d1d4b10c 1585 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1586 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1587 ctrl = serial_port_in(port, SCSCR);
1588 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1589 }
1da177e4
LT		 1590}
1591
b129a8cc 1592static void sci_stop_tx(struct uart_port *port)
1da177e4 1593{
1da177e4
LT		 1594 unsigned short ctrl;
1595
1596 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1597 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1598
d1d4b10c 1599 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1600 ctrl &= ~SCSCR_TDRQE;
f43dc23d 1601
8e698614 1602 ctrl &= ~SCSCR_TIE;
f43dc23d 1603
b12bb29f 1604 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1605}
1606
73a19e4c 1607static void sci_start_rx(struct uart_port *port)
1da177e4 1608{
1da177e4
LT		 1609 unsigned short ctrl;
1610
b12bb29f 1611 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1612
d1d4b10c 1613 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1614 ctrl &= ~SCSCR_RDRQE;
f43dc23d 1615
b12bb29f 1616 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1617}
1618
1619static void sci_stop_rx(struct uart_port *port)
1620{
1da177e4
LT		 1621 unsigned short ctrl;
1622
b12bb29f 1623 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1624
d1d4b10c 1625 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1626 ctrl &= ~SCSCR_RDRQE;
f43dc23d
PM		 1627
1628 ctrl &= ~port_rx_irq_mask(port);
1629
b12bb29f 1630 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1631}
1632
1da177e4
LT		 1633static void sci_break_ctl(struct uart_port *port, int break_state)
1634{
bbb4ce50 1635 struct sci_port *s = to_sci_port(port);
d3184e68 1636 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1637 unsigned short scscr, scsptr;
1638
a4e02f6d
SY		 1639 /* check wheter the port has SCSPTR */
1640 if (!reg->size) {
bbb4ce50
SY		 1641 /*
1642 * Not supported by hardware. Most parts couple break and rx
1643 * interrupts together, with break detection always enabled.
1644 */
a4e02f6d 1645 return;
bbb4ce50 1646 }
a4e02f6d
SY		 1647
1648 scsptr = serial_port_in(port, SCSPTR);
1649 scscr = serial_port_in(port, SCSCR);
1650
1651 if (break_state == -1) {
1652 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1653 scscr &= ~SCSCR_TE;
1654 } else {
1655 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1656 scscr |= SCSCR_TE;
1657 }
1658
1659 serial_port_out(port, SCSPTR, scsptr);
1660 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1661}
1662
73a19e4c
GL		 1663#ifdef CONFIG_SERIAL_SH_SCI_DMA
1664static bool filter(struct dma_chan *chan, void *slave)
1665{
1666 struct sh_dmae_slave *param = slave;
1667
9b971cd2
JP		 1668 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1669 __func__, param->shdma_slave.slave_id);
73a19e4c 1670
d6fa5a4e 1671 chan->private = &param->shdma_slave;
937bb6e4 1672 return true;
73a19e4c
GL		 1673}
1674
1675static void rx_timer_fn(unsigned long arg)
1676{
1677 struct sci_port *s = (struct sci_port *)arg;
1678 struct uart_port *port = &s->port;
b12bb29f 1679 u16 scr = serial_port_in(port, SCSCR);
3089f381 1680
d1d4b10c 1681 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
26de4f1b 1682 scr &= ~SCSCR_RDRQE;
1fcc91a6 1683 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1684 }
b12bb29f 1685 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1686 dev_dbg(port->dev, "DMA Rx timed out\n");
1687 schedule_work(&s->work_rx);
1688}
1689
1690static void sci_request_dma(struct uart_port *port)
1691{
1692 struct sci_port *s = to_sci_port(port);
1693 struct sh_dmae_slave *param;
1694 struct dma_chan *chan;
1695 dma_cap_mask_t mask;
73a19e4c 1696
9b971cd2 1697 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1698
937bb6e4 1699 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1700 return;
1701
1702 dma_cap_zero(mask);
1703 dma_cap_set(DMA_SLAVE, mask);
1704
1705 param = &s->param_tx;
1706
1707 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1708 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1709
1710 s->cookie_tx = -EINVAL;
1711 chan = dma_request_channel(mask, filter, param);
1712 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1713 if (chan) {
1714 s->chan_tx = chan;
73a19e4c 1715 /* UART circular tx buffer is an aligned page. */
79904420
GU		 1716 s->tx_dma_addr = dma_map_single(chan->device->dev,
1717 port->state->xmit.buf,
1718 UART_XMIT_SIZE,
1719 DMA_TO_DEVICE);
1720 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
beb9487b 1721 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
b9258020
GU		 1722 dma_release_channel(chan);
1723 s->chan_tx = NULL;
beb9487b 1724 } else {
79904420
GU		 1725 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1726 __func__, UART_XMIT_SIZE,
1727 port->state->xmit.buf, &s->tx_dma_addr);
beb9487b 1728 }
73a19e4c 1729
73a19e4c
GL		 1730 INIT_WORK(&s->work_tx, work_fn_tx);
1731 }
1732
1733 param = &s->param_rx;
1734
1735 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1736 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1737
1738 chan = dma_request_channel(mask, filter, param);
1739 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1740 if (chan) {
1741 dma_addr_t dma[2];
1742 void *buf[2];
1743 int i;
1744
1745 s->chan_rx = chan;
1746
092248aa 1747 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
8e14ba8f
GU		 1748 buf[0] = dma_alloc_coherent(chan->device->dev,
1749 s->buf_len_rx * 2, &dma[0],
1750 GFP_KERNEL);
73a19e4c
GL		 1751
1752 if (!buf[0]) {
1753 dev_warn(port->dev,
beb9487b 1754 "Failed to allocate Rx dma buffer, using PIO\n");
b9258020
GU		 1755 dma_release_channel(chan);
1756 s->chan_rx = NULL;
1757 sci_start_rx(port);
73a19e4c
GL		 1758 return;
1759 }
1760
1761 buf[1] = buf[0] + s->buf_len_rx;
1762 dma[1] = dma[0] + s->buf_len_rx;
1763
1764 for (i = 0; i < 2; i++) {
1765 struct scatterlist *sg = &s->sg_rx[i];
1766
1767 sg_init_table(sg, 1);
1768 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1769 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1770 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1771 }
1772
1773 INIT_WORK(&s->work_rx, work_fn_rx);
1774 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1775
1776 sci_submit_rx(s);
1777 }
1778}
1779
1780static void sci_free_dma(struct uart_port *port)
1781{
1782 struct sci_port *s = to_sci_port(port);
1783
73a19e4c
GL		 1784 if (s->chan_tx)
1785 sci_tx_dma_release(s, false);
1786 if (s->chan_rx)
1787 sci_rx_dma_release(s, false);
1788}
27bd1075
PM		 1789#else
1790static inline void sci_request_dma(struct uart_port *port)
1791{
1792}
1793
1794static inline void sci_free_dma(struct uart_port *port)
1795{
1796}
73a19e4c
GL		 1797#endif
1798
1da177e4
LT		 1799static int sci_startup(struct uart_port *port)
1800{
a5660ada 1801 struct sci_port *s = to_sci_port(port);
33b48e16 1802 unsigned long flags;
073e84c9 1803 int ret;
1da177e4 1804
73a19e4c
GL		 1805 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1806
073e84c9
PM		 1807 ret = sci_request_irq(s);
1808 if (unlikely(ret < 0))
1809 return ret;
1810
73a19e4c 1811 sci_request_dma(port);
073e84c9 1812
33b48e16 1813 spin_lock_irqsave(&port->lock, flags);
d656901b 1814 sci_start_tx(port);
73a19e4c 1815 sci_start_rx(port);
33b48e16 1816 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1817
1818 return 0;
1819}
1820
1821static void sci_shutdown(struct uart_port *port)
1822{
a5660ada 1823 struct sci_port *s = to_sci_port(port);
33b48e16 1824 unsigned long flags;
1da177e4 1825
73a19e4c
GL		 1826 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1827
33b48e16 1828 spin_lock_irqsave(&port->lock, flags);
1da177e4 1829 sci_stop_rx(port);
b129a8cc 1830 sci_stop_tx(port);
33b48e16 1831 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1832
73a19e4c 1833 sci_free_dma(port);
1da177e4 1834 sci_free_irq(s);
1da177e4
LT		 1835}
1836
ec09c5eb 1837static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1838 unsigned long freq)
1839{
ec09c5eb
LP		 1840 if (s->sampling_rate)
1841 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1842
26c92f37
PM		 1843 /* Warn, but use a safe default */
1844 WARN_ON(1);
e8183a6c 1845
26c92f37
PM		 1846 return ((freq + 16 * bps) / (32 * bps) - 1);
1847}
1848
730c4e78
NI		 1849/* calculate frame length from SMR */
1850static int sci_baud_calc_frame_len(unsigned int smr_val)
1851{
1852 int len = 10;
1853
1854 if (smr_val & SCSMR_CHR)
1855 len--;
1856 if (smr_val & SCSMR_PE)
1857 len++;
1858 if (smr_val & SCSMR_STOP)
1859 len++;
1860
1861 return len;
1862}
1863
1864
f303b364
UH		 1865/* calculate sample rate, BRR, and clock select for HSCIF */
1866static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1867 int *brr, unsigned int *srr,
730c4e78 1868 unsigned int *cks, int frame_len)
f303b364 1869{
730c4e78 1870 int sr, c, br, err, recv_margin;
f303b364 1871 int min_err = 1000; /* 100% */
730c4e78 1872 int recv_max_margin = 0;
f303b364
UH		 1873
1874 /* Find the combination of sample rate and clock select with the
1875 smallest deviation from the desired baud rate. */
1876 for (sr = 8; sr <= 32; sr++) {
1877 for (c = 0; c <= 3; c++) {
1878 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1879 br = DIV_ROUND_CLOSEST(freq, (sr *
1880 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1881 br = clamp(br, 0, 255);
b7d66397
NI		 1882 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1883 (1 << (2 * c + 1)) / 1000)) -
1884 1000;
730c4e78
NI		 1885 /* Calc recv margin
1886 * M: Receive margin (%)
1887 * N: Ratio of bit rate to clock (N = sampling rate)
1888 * D: Clock duty (D = 0 to 1.0)
1889 * L: Frame length (L = 9 to 12)
1890 * F: Absolute value of clock frequency deviation
1891 *
1892 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1893 * (|D - 0.5| / N * (1 + F))|
1894 * NOTE: Usually, treat D for 0.5, F is 0 by this
1895 * calculation.
1896 */
1897 recv_margin = abs((500 -
1898 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1899 if (abs(min_err) > abs(err)) {
f303b364 1900 min_err = err;
730c4e78
NI		 1901 recv_max_margin = recv_margin;
1902 } else if ((min_err == err) &&
1903 (recv_margin > recv_max_margin))
1904 recv_max_margin = recv_margin;
1905 else
1906 continue;
1907
1908 *brr = br;
1909 *srr = sr - 1;
1910 *cks = c;
f303b364
UH		 1911 }
1912 }
1913
1914 if (min_err == 1000) {
1915 WARN_ON(1);
1916 /* use defaults */
1917 *brr = 255;
1918 *srr = 15;
1919 *cks = 0;
1920 }
1921}
1922
1ba76220
MD		 1923static void sci_reset(struct uart_port *port)
1924{
d3184e68 1925 const struct plat_sci_reg *reg;
1ba76220
MD		 1926 unsigned int status;
1927
1928 do {
b12bb29f 1929 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1930 } while (!(status & SCxSR_TEND(port)));
1931
b12bb29f 1932 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1933
0979e0e6
PM		 1934 reg = sci_getreg(port, SCFCR);
1935 if (reg->size)
b12bb29f 1936 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1937}
1938
606d099c
AC		 1939static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1940 struct ktermios *old)
1da177e4 1941{
00b9de9c 1942 struct sci_port *s = to_sci_port(port);
d3184e68 1943 const struct plat_sci_reg *reg;
730c4e78 1944 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1945 int t = -1;
d4759ded 1946 unsigned int srr = 15;
1da177e4 1947
730c4e78
NI		 1948 if ((termios->c_cflag & CSIZE) == CS7)
1949 smr_val |= SCSMR_CHR;
1950 if (termios->c_cflag & PARENB)
1951 smr_val |= SCSMR_PE;
1952 if (termios->c_cflag & PARODD)
1953 smr_val |= SCSMR_PE | SCSMR_ODD;
1954 if (termios->c_cflag & CSTOPB)
1955 smr_val |= SCSMR_STOP;
1956
154280fd
MD		 1957 /*
1958 * earlyprintk comes here early on with port->uartclk set to zero.
1959 * the clock framework is not up and running at this point so here
1960 * we assume that 115200 is the maximum baud rate. please note that
1961 * the baud rate is not programmed during earlyprintk - it is assumed
1962 * that the previous boot loader has enabled required clocks and
1963 * setup the baud rate generator hardware for us already.
1964 */
1965 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1966
154280fd 1967 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1968 if (likely(baud && port->uartclk)) {
ec09c5eb 1969 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1970 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1971 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1972 &cks, frame_len);
f303b364 1973 } else {
ec09c5eb 1974 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1975 for (cks = 0; t >= 256 && cks <= 3; cks++)
1976 t >>= 2;
1977 }
1978 }
e108b2ca 1979
23241d43 1980 sci_port_enable(s);
36003386 1981
1ba76220 1982 sci_reset(port);
1da177e4 1983
2944a331 1984 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 1985
1986 uart_update_timeout(port, termios->c_cflag, baud);
1987
9d482cc3
TY		 1988 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1989 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1990
4ffc3cdb 1991 if (t >= 0) {
26de4f1b 1992 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1993 serial_port_out(port, SCBRR, t);
f303b364
UH		 1994 reg = sci_getreg(port, HSSRR);
1995 if (reg->size)
1996 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1997 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1998 } else
1999 serial_port_out(port, SCSMR, smr_val);
1da177e4 2000
d5701647 2001 sci_init_pins(port, termios->c_cflag);
0979e0e6 2002
73c3d53f
PM		 2003 reg = sci_getreg(port, SCFCR);
2004 if (reg->size) {
b12bb29f 2005 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2006
73c3d53f 2007 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2008 if (termios->c_cflag & CRTSCTS)
2009 ctrl |= SCFCR_MCE;
2010 else
2011 ctrl &= ~SCFCR_MCE;
faf02f8f 2012 }
73c3d53f
PM		 2013
2014 /*
2015 * As we've done a sci_reset() above, ensure we don't
2016 * interfere with the FIFOs while toggling MCE. As the
2017 * reset values could still be set, simply mask them out.
2018 */
2019 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2020
b12bb29f 2021 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2022 }
b7a76e4b 2023
b12bb29f 2024 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2025
3089f381
GL		 2026#ifdef CONFIG_SERIAL_SH_SCI_DMA
2027 /*
5f6d8515 2028 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2029 * See serial_core.c::uart_update_timeout().
2030 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2031 * function calculates 1 jiffie for the data plus 5 jiffies for the
2032 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2033 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2034 * value obtained by this formula is too small. Therefore, if the value
2035 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2036 */
2037 if (s->chan_rx) {
5f6d8515
NI		 2038 unsigned int bits;
2039
2040 /* byte size and parity */
2041 switch (termios->c_cflag & CSIZE) {
2042 case CS5:
2043 bits = 7;
2044 break;
2045 case CS6:
2046 bits = 8;
2047 break;
2048 case CS7:
2049 bits = 9;
2050 break;
2051 default:
2052 bits = 10;
2053 break;
2054 }
2055
2056 if (termios->c_cflag & CSTOPB)
2057 bits++;
2058 if (termios->c_cflag & PARENB)
2059 bits++;
2060 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2061 (baud / 10), 10);
9b971cd2 2062 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2063 s->rx_timeout * 1000 / HZ, port->timeout);
2064 if (s->rx_timeout < msecs_to_jiffies(20))
2065 s->rx_timeout = msecs_to_jiffies(20);
2066 }
2067#endif
2068
1da177e4 2069 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2070 sci_start_rx(port);
36003386 2071
23241d43 2072 sci_port_disable(s);
1da177e4
LT		 2073}
2074
0174e5ca
TK		 2075static void sci_pm(struct uart_port *port, unsigned int state,
2076 unsigned int oldstate)
2077{
2078 struct sci_port *sci_port = to_sci_port(port);
2079
2080 switch (state) {
d3dfe5d9 2081 case UART_PM_STATE_OFF:
0174e5ca
TK		 2082 sci_port_disable(sci_port);
2083 break;
2084 default:
2085 sci_port_enable(sci_port);
2086 break;
2087 }
2088}
2089
1da177e4
LT		 2090static const char *sci_type(struct uart_port *port)
2091{
2092 switch (port->type) {
e7c98dc7
MT		 2093 case PORT_IRDA:
2094 return "irda";
2095 case PORT_SCI:
2096 return "sci";
2097 case PORT_SCIF:
2098 return "scif";
2099 case PORT_SCIFA:
2100 return "scifa";
d1d4b10c
GL		 2101 case PORT_SCIFB:
2102 return "scifb";
f303b364
UH		 2103 case PORT_HSCIF:
2104 return "hscif";
1da177e4
LT		 2105 }
2106
fa43972f 2107 return NULL;
1da177e4
LT		 2108}
2109
f6e9495d
PM		 2110static int sci_remap_port(struct uart_port *port)
2111{
e4d6f911 2112 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2113
2114 /*
2115 * Nothing to do if there's already an established membase.
2116 */
2117 if (port->membase)
2118 return 0;
2119
2120 if (port->flags & UPF_IOREMAP) {
e4d6f911 2121 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2122 if (unlikely(!port->membase)) {
2123 dev_err(port->dev, "can't remap port#%d\n", port->line);
2124 return -ENXIO;
2125 }
2126 } else {
2127 /*
2128 * For the simple (and majority of) cases where we don't
2129 * need to do any remapping, just cast the cookie
2130 * directly.
2131 */
3af4e960 2132 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2133 }
2134
2135 return 0;
2136}
2137
e2651647 2138static void sci_release_port(struct uart_port *port)
1da177e4 2139{
e4d6f911
YS		 2140 struct sci_port *sport = to_sci_port(port);
2141
e2651647
PM		 2142 if (port->flags & UPF_IOREMAP) {
2143 iounmap(port->membase);
2144 port->membase = NULL;
2145 }
2146
e4d6f911 2147 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2148}
2149
e2651647 2150static int sci_request_port(struct uart_port *port)
1da177e4 2151{
e2651647 2152 struct resource *res;
e4d6f911 2153 struct sci_port *sport = to_sci_port(port);
f6e9495d 2154 int ret;
1da177e4 2155
e4d6f911
YS		 2156 res = request_mem_region(port->mapbase, sport->reg_size,
2157 dev_name(port->dev));
2158 if (unlikely(res == NULL)) {
2159 dev_err(port->dev, "request_mem_region failed.");
e2651647 2160 return -EBUSY;
e4d6f911 2161 }
1da177e4 2162
f6e9495d
PM		 2163 ret = sci_remap_port(port);
2164 if (unlikely(ret != 0)) {
2165 release_resource(res);
2166 return ret;
7ff731ae 2167 }
e2651647
PM		 2168
2169 return 0;
2170}
2171
2172static void sci_config_port(struct uart_port *port, int flags)
2173{
2174 if (flags & UART_CONFIG_TYPE) {
2175 struct sci_port *sport = to_sci_port(port);
2176
2177 port->type = sport->cfg->type;
2178 sci_request_port(port);
2179 }
1da177e4
LT		 2180}
2181
2182static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2183{
1da177e4
LT		 2184 if (ser->baud_base < 2400)
2185 /* No paper tape reader for Mitch.. */
2186 return -EINVAL;
2187
2188 return 0;
2189}
2190
2191static struct uart_ops sci_uart_ops = {
2192 .tx_empty = sci_tx_empty,
2193 .set_mctrl = sci_set_mctrl,
2194 .get_mctrl = sci_get_mctrl,
2195 .start_tx = sci_start_tx,
2196 .stop_tx = sci_stop_tx,
2197 .stop_rx = sci_stop_rx,
1da177e4
LT		 2198 .break_ctl = sci_break_ctl,
2199 .startup = sci_startup,
2200 .shutdown = sci_shutdown,
2201 .set_termios = sci_set_termios,
0174e5ca 2202 .pm = sci_pm,
1da177e4
LT		 2203 .type = sci_type,
2204 .release_port = sci_release_port,
2205 .request_port = sci_request_port,
2206 .config_port = sci_config_port,
2207 .verify_port = sci_verify_port,
07d2a1a1
PM		 2208#ifdef CONFIG_CONSOLE_POLL
2209 .poll_get_char = sci_poll_get_char,
2210 .poll_put_char = sci_poll_put_char,
2211#endif
1da177e4
LT		 2212};
2213
9671f099 2214static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2215 struct sci_port *sci_port, unsigned int index,
2216 struct plat_sci_port *p, bool early)
e108b2ca 2217{
73a19e4c 2218 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2219 const struct resource *res;
2220 unsigned int i;
3127c6b2 2221 int ret;
e108b2ca 2222
50f0959a
PM		 2223 sci_port->cfg = p;
2224
73a19e4c
GL		 2225 port->ops = &sci_uart_ops;
2226 port->iotype = UPIO_MEM;
2227 port->line = index;
75136d48 2228
89b5c1ab
LP		 2229 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2230 if (res == NULL)
2231 return -ENOMEM;
1fcc91a6 2232
89b5c1ab 2233 port->mapbase = res->start;
e4d6f911 2234 sci_port->reg_size = resource_size(res);
1fcc91a6 2235
89b5c1ab
LP		 2236 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2237 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2238
89b5c1ab
LP		 2239 /* The SCI generates several interrupts. They can be muxed together or
2240 * connected to different interrupt lines. In the muxed case only one
2241 * interrupt resource is specified. In the non-muxed case three or four
2242 * interrupt resources are specified, as the BRI interrupt is optional.
2243 */
2244 if (sci_port->irqs[0] < 0)
2245 return -ENXIO;
1fcc91a6 2246
89b5c1ab
LP		 2247 if (sci_port->irqs[1] < 0) {
2248 sci_port->irqs[1] = sci_port->irqs[0];
2249 sci_port->irqs[2] = sci_port->irqs[0];
2250 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2251 }
2252
b545e4f4
LP		 2253 if (p->regtype == SCIx_PROBE_REGTYPE) {
2254 ret = sci_probe_regmap(p);
2255 if (unlikely(ret))
2256 return ret;
2257 }
2258
75136d48 2259 switch (p->type) {
d1d4b10c
GL		 2260 case PORT_SCIFB:
2261 port->fifosize = 256;
2e0842a1 2262 sci_port->overrun_reg = SCxSR;
75c249fd 2263 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2264 sci_port->sampling_rate = 16;
d1d4b10c 2265 break;
f303b364
UH		 2266 case PORT_HSCIF:
2267 port->fifosize = 128;
2e0842a1 2268 sci_port->overrun_reg = SCLSR;
75c249fd 2269 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2270 sci_port->sampling_rate = 0;
f303b364 2271 break;
75136d48 2272 case PORT_SCIFA:
73a19e4c 2273 port->fifosize = 64;
2e0842a1 2274 sci_port->overrun_reg = SCxSR;
75c249fd 2275 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2276 sci_port->sampling_rate = 16;
75136d48
MP		 2277 break;
2278 case PORT_SCIF:
73a19e4c 2279 port->fifosize = 16;
ec09c5eb 2280 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2281 sci_port->overrun_reg = SCxSR;
75c249fd 2282 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2283 sci_port->sampling_rate = 16;
ec09c5eb 2284 } else {
2e0842a1 2285 sci_port->overrun_reg = SCLSR;
75c249fd 2286 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2287 sci_port->sampling_rate = 32;
ec09c5eb 2288 }
75136d48
MP		 2289 break;
2290 default:
73a19e4c 2291 port->fifosize = 1;
2e0842a1 2292 sci_port->overrun_reg = SCxSR;
75c249fd 2293 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2294 sci_port->sampling_rate = 32;
75136d48
MP		 2295 break;
2296 }
7b6fd3bf 2297
878fbb91
LP		 2298 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2299 * match the SoC datasheet, this should be investigated. Let platform
2300 * data override the sampling rate for now.
ec09c5eb 2301 */
f84b6bdc
GU		 2302 if (p->sampling_rate)
2303 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2304
1fcc91a6 2305 if (!early) {
c7ed1ab3
PM		 2306 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2307 if (IS_ERR(sci_port->iclk)) {
2308 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2309 if (IS_ERR(sci_port->iclk)) {
2310 dev_err(&dev->dev, "can't get iclk\n");
2311 return PTR_ERR(sci_port->iclk);
2312 }
2313 }
2314
2315 /*
2316 * The function clock is optional, ignore it if we can't
2317 * find it.
2318 */
2319 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2320 if (IS_ERR(sci_port->fclk))
2321 sci_port->fclk = NULL;
2322
73a19e4c 2323 port->dev = &dev->dev;
5e50d2d6
MD		 2324
2325 pm_runtime_enable(&dev->dev);
7b6fd3bf 2326 }
e108b2ca 2327
7ed7e071
MD		 2328 sci_port->break_timer.data = (unsigned long)sci_port;
2329 sci_port->break_timer.function = sci_break_timer;
2330 init_timer(&sci_port->break_timer);
2331
debf9507
PM		 2332 /*
2333 * Establish some sensible defaults for the error detection.
2334 */
5da0f468
GU		 2335 if (p->type == PORT_SCI) {
2336 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2337 sci_port->error_clear = SCI_ERROR_CLEAR;
2338 } else {
2339 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2340 sci_port->error_clear = SCIF_ERROR_CLEAR;
2341 }
debf9507 2342
3ae988d9
LP		 2343 /*
2344 * Make the error mask inclusive of overrun detection, if
2345 * supported.
2346 */
5da0f468 2347 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2348 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2349 sci_port->error_clear &= ~sci_port->overrun_mask;
2350 }
debf9507 2351
ce6738b6 2352 port->type = p->type;
b6e4a3f1 2353 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2354 port->regshift = p->regshift;
73a19e4c 2355
ce6738b6 2356 /*
61a6976b 2357 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2358 * for the multi-IRQ ports, which is where we are primarily
2359 * concerned with the shutdown path synchronization.
2360 *
2361 * For the muxed case there's nothing more to do.
2362 */
1fcc91a6 2363 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2364 port->irqflags = 0;
73a19e4c 2365
61a6976b
PM		 2366 port->serial_in = sci_serial_in;
2367 port->serial_out = sci_serial_out;
2368
937bb6e4
GL		 2369 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2370 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2371 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2372
c7ed1ab3 2373 return 0;
e108b2ca
PM		 2374}
2375
6dae1421
LP		 2376static void sci_cleanup_single(struct sci_port *port)
2377{
6dae1421
LP		 2378 clk_put(port->iclk);
2379 clk_put(port->fclk);
2380
2381 pm_runtime_disable(port->port.dev);
2382}
2383
1da177e4 2384#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2385static void serial_console_putchar(struct uart_port *port, int ch)
2386{
2387 sci_poll_put_char(port, ch);
2388}
2389
1da177e4
LT		 2390/*
2391 * Print a string to the serial port trying not to disturb
2392 * any possible real use of the port...
2393 */
2394static void serial_console_write(struct console *co, const char *s,
2395 unsigned count)
2396{
906b17dc
PM		 2397 struct sci_port *sci_port = &sci_ports[co->index];
2398 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2399 unsigned short bits, ctrl;
2400 unsigned long flags;
2401 int locked = 1;
2402
2403 local_irq_save(flags);
2404 if (port->sysrq)
2405 locked = 0;
2406 else if (oops_in_progress)
2407 locked = spin_trylock(&port->lock);
2408 else
2409 spin_lock(&port->lock);
2410
2411 /* first save the SCSCR then disable the interrupts */
2412 ctrl = serial_port_in(port, SCSCR);
2413 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2414
501b825d 2415 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2416
2417 /* wait until fifo is empty and last bit has been transmitted */
2418 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2419 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2420 cpu_relax();
40f70c03
SK		 2421
2422 /* restore the SCSCR */
2423 serial_port_out(port, SCSCR, ctrl);
2424
2425 if (locked)
2426 spin_unlock(&port->lock);
2427 local_irq_restore(flags);
1da177e4
LT		 2428}
2429
9671f099 2430static int serial_console_setup(struct console *co, char *options)
1da177e4 2431{
dc8e6f5b 2432 struct sci_port *sci_port;
1da177e4
LT		 2433 struct uart_port *port;
2434 int baud = 115200;
2435 int bits = 8;
2436 int parity = 'n';
2437 int flow = 'n';
2438 int ret;
2439
e108b2ca 2440 /*
906b17dc 2441 * Refuse to handle any bogus ports.
1da177e4 2442 */
906b17dc 2443 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2444 return -ENODEV;
e108b2ca 2445
906b17dc
PM		 2446 sci_port = &sci_ports[co->index];
2447 port = &sci_port->port;
2448
b2267a6b
AC		 2449 /*
2450 * Refuse to handle uninitialized ports.
2451 */
2452 if (!port->ops)
2453 return -ENODEV;
2454
f6e9495d
PM		 2455 ret = sci_remap_port(port);
2456 if (unlikely(ret != 0))
2457 return ret;
e108b2ca 2458
1da177e4
LT		 2459 if (options)
2460 uart_parse_options(options, &baud, &parity, &bits, &flow);
2461
ab7cfb55 2462 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2463}
2464
2465static struct console serial_console = {
2466 .name = "ttySC",
906b17dc 2467 .device = uart_console_device,
1da177e4
LT		 2468 .write = serial_console_write,
2469 .setup = serial_console_setup,
fa5da2f7 2470 .flags = CON_PRINTBUFFER,
1da177e4 2471 .index = -1,
906b17dc 2472 .data = &sci_uart_driver,
1da177e4
LT		 2473};
2474
7b6fd3bf
MD		 2475static struct console early_serial_console = {
2476 .name = "early_ttySC",
2477 .write = serial_console_write,
2478 .flags = CON_PRINTBUFFER,
906b17dc 2479 .index = -1,
7b6fd3bf 2480};
ecdf8a46 2481
7b6fd3bf
MD		 2482static char early_serial_buf[32];
2483
9671f099 2484static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2485{
574de559 2486 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2487
2488 if (early_serial_console.data)
2489 return -EEXIST;
2490
2491 early_serial_console.index = pdev->id;
ecdf8a46 2492
1fcc91a6 2493 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2494
2495 serial_console_setup(&early_serial_console, early_serial_buf);
2496
2497 if (!strstr(early_serial_buf, "keep"))
2498 early_serial_console.flags |= CON_BOOT;
2499
2500 register_console(&early_serial_console);
2501 return 0;
2502}
6a8c9799
NI		 2503
2504#define SCI_CONSOLE (&serial_console)
2505
ecdf8a46 2506#else
9671f099 2507static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2508{
2509 return -EINVAL;
2510}
1da177e4 2511
6a8c9799
NI		 2512#define SCI_CONSOLE NULL
2513
2514#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2515
6c13d5d2 2516static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2517
2518static struct uart_driver sci_uart_driver = {
2519 .owner = THIS_MODULE,
2520 .driver_name = "sci",
1da177e4
LT		 2521 .dev_name = "ttySC",
2522 .major = SCI_MAJOR,
2523 .minor = SCI_MINOR_START,
e108b2ca 2524 .nr = SCI_NPORTS,
1da177e4
LT		 2525 .cons = SCI_CONSOLE,
2526};
2527
54507f6e 2528static int sci_remove(struct platform_device *dev)
e552de24 2529{
d535a230 2530 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2531
d535a230
PM		 2532 cpufreq_unregister_notifier(&port->freq_transition,
2533 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2534
d535a230
PM		 2535 uart_remove_one_port(&sci_uart_driver, &port->port);
2536
6dae1421 2537 sci_cleanup_single(port);
e552de24 2538
e552de24
MD		 2539 return 0;
2540}
2541
20bdcab8
BH		 2542struct sci_port_info {
2543 unsigned int type;
2544 unsigned int regtype;
2545};
2546
2547static const struct of_device_id of_sci_match[] = {
2548 {
2549 .compatible = "renesas,scif",
ff43da00 2550 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2551 .type = PORT_SCIF,
2552 .regtype = SCIx_SH4_SCIF_REGTYPE,
2553 },
2554 }, {
2555 .compatible = "renesas,scifa",
ff43da00 2556 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2557 .type = PORT_SCIFA,
2558 .regtype = SCIx_SCIFA_REGTYPE,
2559 },
2560 }, {
2561 .compatible = "renesas,scifb",
ff43da00 2562 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2563 .type = PORT_SCIFB,
2564 .regtype = SCIx_SCIFB_REGTYPE,
2565 },
2566 }, {
2567 .compatible = "renesas,hscif",
ff43da00 2568 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2569 .type = PORT_HSCIF,
2570 .regtype = SCIx_HSCIF_REGTYPE,
2571 },
e1d0be61
YS		 2572 }, {
2573 .compatible = "renesas,sci",
2574 .data = &(const struct sci_port_info) {
2575 .type = PORT_SCI,
2576 .regtype = SCIx_SCI_REGTYPE,
2577 },
20bdcab8
BH		 2578 }, {
2579 /* Terminator */
2580 },
2581};
2582MODULE_DEVICE_TABLE(of, of_sci_match);
2583
2584static struct plat_sci_port *
2585sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2586{
2587 struct device_node *np = pdev->dev.of_node;
2588 const struct of_device_id *match;
2589 const struct sci_port_info *info;
2590 struct plat_sci_port *p;
2591 int id;
2592
2593 if (!IS_ENABLED(CONFIG_OF) || !np)
2594 return NULL;
2595
2596 match = of_match_node(of_sci_match, pdev->dev.of_node);
2597 if (!match)
2598 return NULL;
2599
2600 info = match->data;
2601
2602 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2603 if (!p)
20bdcab8 2604 return NULL;
20bdcab8
BH		 2605
2606 /* Get the line number for the aliases node. */
2607 id = of_alias_get_id(np, "serial");
2608 if (id < 0) {
2609 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2610 return NULL;
2611 }
2612
2613 *dev_id = id;
2614
2615 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2616 p->type = info->type;
2617 p->regtype = info->regtype;
2618 p->scscr = SCSCR_RE | SCSCR_TE;
2619
2620 return p;
2621}
2622
9671f099 2623static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2624 unsigned int index,
2625 struct plat_sci_port *p,
2626 struct sci_port *sciport)
2627{
0ee70712
MD		 2628 int ret;
2629
2630 /* Sanity check */
2631 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2632 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2633 index+1, SCI_NPORTS);
9b971cd2 2634 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2635 return -EINVAL;
0ee70712
MD		 2636 }
2637
1fcc91a6 2638 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2639 if (ret)
2640 return ret;
0ee70712 2641
6dae1421
LP		 2642 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2643 if (ret) {
2644 sci_cleanup_single(sciport);
2645 return ret;
2646 }
2647
2648 return 0;
0ee70712
MD		 2649}
2650
9671f099 2651static int sci_probe(struct platform_device *dev)
1da177e4 2652{
20bdcab8
BH		 2653 struct plat_sci_port *p;
2654 struct sci_port *sp;
2655 unsigned int dev_id;
ecdf8a46 2656 int ret;
d535a230 2657
ecdf8a46
PM		 2658 /*
2659 * If we've come here via earlyprintk initialization, head off to
2660 * the special early probe. We don't have sufficient device state
2661 * to make it beyond this yet.
2662 */
2663 if (is_early_platform_device(dev))
2664 return sci_probe_earlyprintk(dev);
7b6fd3bf 2665
20bdcab8
BH		 2666 if (dev->dev.of_node) {
2667 p = sci_parse_dt(dev, &dev_id);
2668 if (p == NULL)
2669 return -EINVAL;
2670 } else {
2671 p = dev->dev.platform_data;
2672 if (p == NULL) {
2673 dev_err(&dev->dev, "no platform data supplied\n");
2674 return -EINVAL;
2675 }
2676
2677 dev_id = dev->id;
2678 }
2679
2680 sp = &sci_ports[dev_id];
d535a230 2681 platform_set_drvdata(dev, sp);
e552de24 2682
20bdcab8 2683 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2684 if (ret)
6dae1421 2685 return ret;
e552de24 2686
d535a230 2687 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2688
d535a230
PM		 2689 ret = cpufreq_register_notifier(&sp->freq_transition,
2690 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2691 if (unlikely(ret < 0)) {
bf13c9a8 2692 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2693 sci_cleanup_single(sp);
2694 return ret;
2695 }
1da177e4
LT		 2696
2697#ifdef CONFIG_SH_STANDARD_BIOS
2698 sh_bios_gdb_detach();
2699#endif
2700
e108b2ca 2701 return 0;
1da177e4
LT		 2702}
2703
cb876341 2704static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2705{
d535a230 2706 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2707
d535a230
PM		 2708 if (sport)
2709 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2710
e108b2ca
PM		 2711 return 0;
2712}
1da177e4 2713
cb876341 2714static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2715{
d535a230 2716 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2717
d535a230
PM		 2718 if (sport)
2719 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2720
2721 return 0;
2722}
2723
cb876341 2724static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2725
e108b2ca
PM		 2726static struct platform_driver sci_driver = {
2727 .probe = sci_probe,
b9e39c89 2728 .remove = sci_remove,
e108b2ca
PM		 2729 .driver = {
2730 .name = "sh-sci",
6daa79b3 2731 .pm = &sci_dev_pm_ops,
20bdcab8 2732 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2733 },
2734};
2735
2736static int __init sci_init(void)
2737{
2738 int ret;
2739
6c13d5d2 2740 pr_info("%s\n", banner);
e108b2ca 2741
e108b2ca
PM		 2742 ret = uart_register_driver(&sci_uart_driver);
2743 if (likely(ret == 0)) {
2744 ret = platform_driver_register(&sci_driver);
2745 if (unlikely(ret))
2746 uart_unregister_driver(&sci_uart_driver);
2747 }
2748
2749 return ret;
2750}
2751
2752static void __exit sci_exit(void)
2753{
2754 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2755 uart_unregister_driver(&sci_uart_driver);
2756}
2757
7b6fd3bf
MD		 2758#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2759early_platform_init_buffer("earlyprintk", &sci_driver,
2760 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2761#endif
1da177e4
LT		 2762module_init(sci_init);
2763module_exit(sci_exit);
2764
e108b2ca 2765MODULE_LICENSE("GPL");
e169c139 2766MODULE_ALIAS("platform:sh-sci");
7f405f9c 2767MODULE_AUTHOR("Paul Mundt");
f303b364 2768MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
This page took 0.964127 seconds and 5 git commands to generate.