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serial: sh-sci: Support resources passed through platform resources
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c
LP		 35#include <linux/gpio.h>
36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
1da177e4 42#include <linux/notifier.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
e108b2ca
PM		 62struct sci_port {
63 struct uart_port port;
64
ce6738b6
PM		 65 /* Platform configuration */
66 struct plat_sci_port *cfg;
e108b2ca 67
e108b2ca
PM		 68 /* Break timer */
69 struct timer_list break_timer;
70 int break_flag;
1534a3b3 71
501b825d
MD		 72 /* Interface clock */
73 struct clk *iclk;
c7ed1ab3
PM		 74 /* Function clock */
75 struct clk *fclk;
edad1f20 76
1fcc91a6 77 int irqs[SCIx_NR_IRQS];
9174fc8f 78 char *irqstr[SCIx_NR_IRQS];
50f0959a 79 char *gpiostr[SCIx_NR_FNS];
9174fc8f 80
73a19e4c
GL		 81 struct dma_chan *chan_tx;
82 struct dma_chan *chan_rx;
f43dc23d 83
73a19e4c 84#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 85 struct dma_async_tx_descriptor *desc_tx;
86 struct dma_async_tx_descriptor *desc_rx[2];
87 dma_cookie_t cookie_tx;
88 dma_cookie_t cookie_rx[2];
89 dma_cookie_t active_rx;
90 struct scatterlist sg_tx;
91 unsigned int sg_len_tx;
92 struct scatterlist sg_rx[2];
93 size_t buf_len_rx;
94 struct sh_dmae_slave param_tx;
95 struct sh_dmae_slave param_rx;
96 struct work_struct work_tx;
97 struct work_struct work_rx;
98 struct timer_list rx_timer;
3089f381 99 unsigned int rx_timeout;
73a19e4c 100#endif
e552de24 101
d535a230 102 struct notifier_block freq_transition;
e108b2ca
PM		 103};
104
1da177e4 105/* Function prototypes */
d535a230 106static void sci_start_tx(struct uart_port *port);
b129a8cc 107static void sci_stop_tx(struct uart_port *port);
d535a230 108static void sci_start_rx(struct uart_port *port);
1da177e4 109
e108b2ca 110#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 111
e108b2ca
PM		 112static struct sci_port sci_ports[SCI_NPORTS];
113static struct uart_driver sci_uart_driver;
1da177e4 114
e7c98dc7
MT		 115static inline struct sci_port *
116to_sci_port(struct uart_port *uart)
117{
118 return container_of(uart, struct sci_port, port);
119}
120
61a6976b
PM		 121struct plat_sci_reg {
122 u8 offset, size;
123};
124
125/* Helper for invalidating specific entries of an inherited map. */
126#define sci_reg_invalid { .offset = 0, .size = 0 }
127
128static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
129 [SCIx_PROBE_REGTYPE] = {
130 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
131 },
132
133 /*
134 * Common SCI definitions, dependent on the port's regshift
135 * value.
136 */
137 [SCIx_SCI_REGTYPE] = {
138 [SCSMR] = { 0x00, 8 },
139 [SCBRR] = { 0x01, 8 },
140 [SCSCR] = { 0x02, 8 },
141 [SCxTDR] = { 0x03, 8 },
142 [SCxSR] = { 0x04, 8 },
143 [SCxRDR] = { 0x05, 8 },
144 [SCFCR] = sci_reg_invalid,
145 [SCFDR] = sci_reg_invalid,
146 [SCTFDR] = sci_reg_invalid,
147 [SCRFDR] = sci_reg_invalid,
148 [SCSPTR] = sci_reg_invalid,
149 [SCLSR] = sci_reg_invalid,
f303b364 150 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 151 },
152
153 /*
154 * Common definitions for legacy IrDA ports, dependent on
155 * regshift value.
156 */
157 [SCIx_IRDA_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = { 0x06, 8 },
165 [SCFDR] = { 0x07, 16 },
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
f303b364 170 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 171 },
172
173 /*
174 * Common SCIFA definitions.
175 */
176 [SCIx_SCIFA_REGTYPE] = {
177 [SCSMR] = { 0x00, 16 },
178 [SCBRR] = { 0x04, 8 },
179 [SCSCR] = { 0x08, 16 },
180 [SCxTDR] = { 0x20, 8 },
181 [SCxSR] = { 0x14, 16 },
182 [SCxRDR] = { 0x24, 8 },
183 [SCFCR] = { 0x18, 16 },
184 [SCFDR] = { 0x1c, 16 },
185 [SCTFDR] = sci_reg_invalid,
186 [SCRFDR] = sci_reg_invalid,
187 [SCSPTR] = sci_reg_invalid,
188 [SCLSR] = sci_reg_invalid,
f303b364 189 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 190 },
191
192 /*
193 * Common SCIFB definitions.
194 */
195 [SCIx_SCIFB_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x40, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x60, 8 },
202 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 203 [SCFDR] = sci_reg_invalid,
204 [SCTFDR] = { 0x38, 16 },
205 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
f303b364 208 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 209 },
210
3af1f8a4
PE		 211 /*
212 * Common SH-2(A) SCIF definitions for ports with FIFO data
213 * count registers.
214 */
215 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x0c, 8 },
220 [SCxSR] = { 0x10, 16 },
221 [SCxRDR] = { 0x14, 8 },
222 [SCFCR] = { 0x18, 16 },
223 [SCFDR] = { 0x1c, 16 },
224 [SCTFDR] = sci_reg_invalid,
225 [SCRFDR] = sci_reg_invalid,
226 [SCSPTR] = { 0x20, 16 },
227 [SCLSR] = { 0x24, 16 },
f303b364 228 [HSSRR] = sci_reg_invalid,
3af1f8a4
PE		 229 },
230
61a6976b
PM		 231 /*
232 * Common SH-3 SCIF definitions.
233 */
234 [SCIx_SH3_SCIF_REGTYPE] = {
235 [SCSMR] = { 0x00, 8 },
236 [SCBRR] = { 0x02, 8 },
237 [SCSCR] = { 0x04, 8 },
238 [SCxTDR] = { 0x06, 8 },
239 [SCxSR] = { 0x08, 16 },
240 [SCxRDR] = { 0x0a, 8 },
241 [SCFCR] = { 0x0c, 8 },
242 [SCFDR] = { 0x0e, 16 },
243 [SCTFDR] = sci_reg_invalid,
244 [SCRFDR] = sci_reg_invalid,
245 [SCSPTR] = sci_reg_invalid,
246 [SCLSR] = sci_reg_invalid,
f303b364 247 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 248 },
249
250 /*
251 * Common SH-4(A) SCIF(B) definitions.
252 */
253 [SCIx_SH4_SCIF_REGTYPE] = {
254 [SCSMR] = { 0x00, 16 },
255 [SCBRR] = { 0x04, 8 },
256 [SCSCR] = { 0x08, 16 },
257 [SCxTDR] = { 0x0c, 8 },
258 [SCxSR] = { 0x10, 16 },
259 [SCxRDR] = { 0x14, 8 },
260 [SCFCR] = { 0x18, 16 },
261 [SCFDR] = { 0x1c, 16 },
262 [SCTFDR] = sci_reg_invalid,
263 [SCRFDR] = sci_reg_invalid,
264 [SCSPTR] = { 0x20, 16 },
265 [SCLSR] = { 0x24, 16 },
f303b364
UH		 266 [HSSRR] = sci_reg_invalid,
267 },
268
269 /*
270 * Common HSCIF definitions.
271 */
272 [SCIx_HSCIF_REGTYPE] = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCTFDR] = sci_reg_invalid,
282 [SCRFDR] = sci_reg_invalid,
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 [HSSRR] = { 0x40, 16 },
61a6976b
PM		 286 },
287
288 /*
289 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
290 * register.
291 */
292 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
293 [SCSMR] = { 0x00, 16 },
294 [SCBRR] = { 0x04, 8 },
295 [SCSCR] = { 0x08, 16 },
296 [SCxTDR] = { 0x0c, 8 },
297 [SCxSR] = { 0x10, 16 },
298 [SCxRDR] = { 0x14, 8 },
299 [SCFCR] = { 0x18, 16 },
300 [SCFDR] = { 0x1c, 16 },
301 [SCTFDR] = sci_reg_invalid,
302 [SCRFDR] = sci_reg_invalid,
303 [SCSPTR] = sci_reg_invalid,
304 [SCLSR] = { 0x24, 16 },
f303b364 305 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 306 },
307
308 /*
309 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
310 * count registers.
311 */
312 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
313 [SCSMR] = { 0x00, 16 },
314 [SCBRR] = { 0x04, 8 },
315 [SCSCR] = { 0x08, 16 },
316 [SCxTDR] = { 0x0c, 8 },
317 [SCxSR] = { 0x10, 16 },
318 [SCxRDR] = { 0x14, 8 },
319 [SCFCR] = { 0x18, 16 },
320 [SCFDR] = { 0x1c, 16 },
321 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
322 [SCRFDR] = { 0x20, 16 },
323 [SCSPTR] = { 0x24, 16 },
324 [SCLSR] = { 0x28, 16 },
f303b364 325 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 326 },
327
328 /*
329 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
330 * registers.
331 */
332 [SCIx_SH7705_SCIF_REGTYPE] = {
333 [SCSMR] = { 0x00, 16 },
334 [SCBRR] = { 0x04, 8 },
335 [SCSCR] = { 0x08, 16 },
336 [SCxTDR] = { 0x20, 8 },
337 [SCxSR] = { 0x14, 16 },
338 [SCxRDR] = { 0x24, 8 },
339 [SCFCR] = { 0x18, 16 },
340 [SCFDR] = { 0x1c, 16 },
341 [SCTFDR] = sci_reg_invalid,
342 [SCRFDR] = sci_reg_invalid,
343 [SCSPTR] = sci_reg_invalid,
344 [SCLSR] = sci_reg_invalid,
f303b364 345 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 346 },
347};
348
72b294cf
PM		 349#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
350
61a6976b
PM		 351/*
352 * The "offset" here is rather misleading, in that it refers to an enum
353 * value relative to the port mapping rather than the fixed offset
354 * itself, which needs to be manually retrieved from the platform's
355 * register map for the given port.
356 */
357static unsigned int sci_serial_in(struct uart_port *p, int offset)
358{
72b294cf 359 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 360
361 if (reg->size == 8)
362 return ioread8(p->membase + (reg->offset << p->regshift));
363 else if (reg->size == 16)
364 return ioread16(p->membase + (reg->offset << p->regshift));
365 else
366 WARN(1, "Invalid register access\n");
367
368 return 0;
369}
370
371static void sci_serial_out(struct uart_port *p, int offset, int value)
372{
72b294cf 373 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 374
375 if (reg->size == 8)
376 iowrite8(value, p->membase + (reg->offset << p->regshift));
377 else if (reg->size == 16)
378 iowrite16(value, p->membase + (reg->offset << p->regshift));
379 else
380 WARN(1, "Invalid register access\n");
381}
382
61a6976b
PM		 383static int sci_probe_regmap(struct plat_sci_port *cfg)
384{
385 switch (cfg->type) {
386 case PORT_SCI:
387 cfg->regtype = SCIx_SCI_REGTYPE;
388 break;
389 case PORT_IRDA:
390 cfg->regtype = SCIx_IRDA_REGTYPE;
391 break;
392 case PORT_SCIFA:
393 cfg->regtype = SCIx_SCIFA_REGTYPE;
394 break;
395 case PORT_SCIFB:
396 cfg->regtype = SCIx_SCIFB_REGTYPE;
397 break;
398 case PORT_SCIF:
399 /*
400 * The SH-4 is a bit of a misnomer here, although that's
401 * where this particular port layout originated. This
402 * configuration (or some slight variation thereof)
403 * remains the dominant model for all SCIFs.
404 */
405 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
406 break;
f303b364
UH		 407 case PORT_HSCIF:
408 cfg->regtype = SCIx_HSCIF_REGTYPE;
409 break;
61a6976b
PM		 410 default:
411 printk(KERN_ERR "Can't probe register map for given port\n");
412 return -EINVAL;
413 }
414
415 return 0;
416}
417
23241d43
PM		 418static void sci_port_enable(struct sci_port *sci_port)
419{
420 if (!sci_port->port.dev)
421 return;
422
423 pm_runtime_get_sync(sci_port->port.dev);
424
b016b646 425 clk_prepare_enable(sci_port->iclk);
23241d43 426 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 427 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 428}
429
430static void sci_port_disable(struct sci_port *sci_port)
431{
432 if (!sci_port->port.dev)
433 return;
434
caec7038
LP		 435 /* Cancel the break timer to ensure that the timer handler will not try
436 * to access the hardware with clocks and power disabled. Reset the
437 * break flag to make the break debouncing state machine ready for the
438 * next break.
439 */
440 del_timer_sync(&sci_port->break_timer);
441 sci_port->break_flag = 0;
442
b016b646
LP		 443 clk_disable_unprepare(sci_port->fclk);
444 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 445
446 pm_runtime_put_sync(sci_port->port.dev);
447}
448
07d2a1a1 449#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 450
451#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 452static int sci_poll_get_char(struct uart_port *port)
1da177e4 453{
1da177e4
LT		 454 unsigned short status;
455 int c;
456
e108b2ca 457 do {
b12bb29f 458 status = serial_port_in(port, SCxSR);
1da177e4 459 if (status & SCxSR_ERRORS(port)) {
b12bb29f 460 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 461 continue;
462 }
3f255eb3
JW		 463 break;
464 } while (1);
465
466 if (!(status & SCxSR_RDxF(port)))
467 return NO_POLL_CHAR;
07d2a1a1 468
b12bb29f 469 c = serial_port_in(port, SCxRDR);
07d2a1a1 470
e7c98dc7 471 /* Dummy read */
b12bb29f
PM		 472 serial_port_in(port, SCxSR);
473 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 474
475 return c;
476}
1f6fd5c9 477#endif
1da177e4 478
07d2a1a1 479static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 480{
1da177e4
LT		 481 unsigned short status;
482
1da177e4 483 do {
b12bb29f 484 status = serial_port_in(port, SCxSR);
1da177e4
LT		 485 } while (!(status & SCxSR_TDxE(port)));
486
b12bb29f
PM		 487 serial_port_out(port, SCxTDR, c);
488 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 489}
07d2a1a1 490#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 491
61a6976b 492static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 493{
61a6976b
PM		 494 struct sci_port *s = to_sci_port(port);
495 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 496
61a6976b
PM		 497 /*
498 * Use port-specific handler if provided.
499 */
500 if (s->cfg->ops && s->cfg->ops->init_pins) {
501 s->cfg->ops->init_pins(port, cflag);
502 return;
1da177e4 503 }
41504c39 504
61a6976b
PM		 505 /*
506 * For the generic path SCSPTR is necessary. Bail out if that's
507 * unavailable, too.
508 */
509 if (!reg->size)
510 return;
41504c39 511
faf02f8f
PM		 512 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
513 ((!(cflag & CRTSCTS)))) {
514 unsigned short status;
515
b12bb29f 516 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 517 status &= ~SCSPTR_CTSIO;
518 status |= SCSPTR_RTSIO;
b12bb29f 519 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 520 }
d5701647 521}
e108b2ca 522
72b294cf 523static int sci_txfill(struct uart_port *port)
e108b2ca 524{
72b294cf 525 struct plat_sci_reg *reg;
e108b2ca 526
72b294cf
PM		 527 reg = sci_getreg(port, SCTFDR);
528 if (reg->size)
63f7ad11 529 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 530
72b294cf
PM		 531 reg = sci_getreg(port, SCFDR);
532 if (reg->size)
b12bb29f 533 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 534
b12bb29f 535 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 536}
537
73a19e4c
GL		 538static int sci_txroom(struct uart_port *port)
539{
72b294cf 540 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 541}
542
543static int sci_rxfill(struct uart_port *port)
e108b2ca 544{
72b294cf
PM		 545 struct plat_sci_reg *reg;
546
547 reg = sci_getreg(port, SCRFDR);
548 if (reg->size)
63f7ad11 549 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 550
551 reg = sci_getreg(port, SCFDR);
552 if (reg->size)
b12bb29f 553 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 554
b12bb29f 555 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 556}
557
514820eb
PM		 558/*
559 * SCI helper for checking the state of the muxed port/RXD pins.
560 */
561static inline int sci_rxd_in(struct uart_port *port)
562{
563 struct sci_port *s = to_sci_port(port);
564
565 if (s->cfg->port_reg <= 0)
566 return 1;
567
0dd4d5cb 568 /* Cast for ARM damage */
e2afca69 569 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 570}
571
1da177e4
LT		 572/* ********************************************************************** *
573 * the interrupt related routines *
574 * ********************************************************************** */
575
576static void sci_transmit_chars(struct uart_port *port)
577{
ebd2c8f6 578 struct circ_buf *xmit = &port->state->xmit;
1da177e4 579 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 580 unsigned short status;
581 unsigned short ctrl;
e108b2ca 582 int count;
1da177e4 583
b12bb29f 584 status = serial_port_in(port, SCxSR);
1da177e4 585 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 586 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 587 if (uart_circ_empty(xmit))
8e698614 588 ctrl &= ~SCSCR_TIE;
e7c98dc7 589 else
8e698614 590 ctrl |= SCSCR_TIE;
b12bb29f 591 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 592 return;
593 }
594
72b294cf 595 count = sci_txroom(port);
1da177e4
LT		 596
597 do {
598 unsigned char c;
599
600 if (port->x_char) {
601 c = port->x_char;
602 port->x_char = 0;
603 } else if (!uart_circ_empty(xmit) && !stopped) {
604 c = xmit->buf[xmit->tail];
605 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
606 } else {
607 break;
608 }
609
b12bb29f 610 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 611
612 port->icount.tx++;
613 } while (--count > 0);
614
b12bb29f 615 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 616
617 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
618 uart_write_wakeup(port);
619 if (uart_circ_empty(xmit)) {
b129a8cc 620 sci_stop_tx(port);
1da177e4 621 } else {
b12bb29f 622 ctrl = serial_port_in(port, SCSCR);
1da177e4 623
1a22f08d 624 if (port->type != PORT_SCI) {
b12bb29f
PM		 625 serial_port_in(port, SCxSR); /* Dummy read */
626 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 627 }
1da177e4 628
8e698614 629 ctrl |= SCSCR_TIE;
b12bb29f 630 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 631 }
632}
633
634/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 635#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 636
94c8b6db 637static void sci_receive_chars(struct uart_port *port)
1da177e4 638{
e7c98dc7 639 struct sci_port *sci_port = to_sci_port(port);
227434f8 640 struct tty_port *tport = &port->state->port;
1da177e4
LT		 641 int i, count, copied = 0;
642 unsigned short status;
33f0f88f 643 unsigned char flag;
1da177e4 644
b12bb29f 645 status = serial_port_in(port, SCxSR);
1da177e4
LT		 646 if (!(status & SCxSR_RDxF(port)))
647 return;
648
649 while (1) {
1da177e4 650 /* Don't copy more bytes than there is room for in the buffer */
227434f8 651 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 652
653 /* If for any reason we can't copy more data, we're done! */
654 if (count == 0)
655 break;
656
657 if (port->type == PORT_SCI) {
b12bb29f 658 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 659 if (uart_handle_sysrq_char(port, c) ||
660 sci_port->break_flag)
1da177e4 661 count = 0;
e7c98dc7 662 else
92a19f9c 663 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 664 } else {
e7c98dc7 665 for (i = 0; i < count; i++) {
b12bb29f 666 char c = serial_port_in(port, SCxRDR);
d97fbbed 667
b12bb29f 668 status = serial_port_in(port, SCxSR);
1da177e4
LT		 669#if defined(CONFIG_CPU_SH3)
670 /* Skip "chars" during break */
e108b2ca 671 if (sci_port->break_flag) {
1da177e4
LT		 672 if ((c == 0) &&
673 (status & SCxSR_FER(port))) {
674 count--; i--;
675 continue;
676 }
e108b2ca 677
1da177e4 678 /* Nonzero => end-of-break */
762c69e3 679 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 680 sci_port->break_flag = 0;
681
1da177e4
LT		 682 if (STEPFN(c)) {
683 count--; i--;
684 continue;
685 }
686 }
687#endif /* CONFIG_CPU_SH3 */
7d12e780 688 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 689 count--; i--;
690 continue;
691 }
692
693 /* Store data and status */
73a19e4c 694 if (status & SCxSR_FER(port)) {
33f0f88f 695 flag = TTY_FRAME;
d97fbbed 696 port->icount.frame++;
762c69e3 697 dev_notice(port->dev, "frame error\n");
73a19e4c 698 } else if (status & SCxSR_PER(port)) {
33f0f88f 699 flag = TTY_PARITY;
d97fbbed 700 port->icount.parity++;
762c69e3 701 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 702 } else
703 flag = TTY_NORMAL;
762c69e3 704
92a19f9c 705 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 706 }
707 }
708
b12bb29f
PM		 709 serial_port_in(port, SCxSR); /* dummy read */
710 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 711
1da177e4
LT		 712 copied += count;
713 port->icount.rx += count;
714 }
715
716 if (copied) {
717 /* Tell the rest of the system the news. New characters! */
2e124b4a 718 tty_flip_buffer_push(tport);
1da177e4 719 } else {
b12bb29f
PM		 720 serial_port_in(port, SCxSR); /* dummy read */
721 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 722 }
723}
724
725#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 726
727/*
728 * The sci generates interrupts during the break,
1da177e4
LT		 729 * 1 per millisecond or so during the break period, for 9600 baud.
730 * So dont bother disabling interrupts.
731 * But dont want more than 1 break event.
732 * Use a kernel timer to periodically poll the rx line until
733 * the break is finished.
734 */
94c8b6db 735static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 736{
bc9b3f5c 737 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 738}
94c8b6db 739
1da177e4
LT		 740/* Ensure that two consecutive samples find the break over. */
741static void sci_break_timer(unsigned long data)
742{
e108b2ca
PM		 743 struct sci_port *port = (struct sci_port *)data;
744
745 if (sci_rxd_in(&port->port) == 0) {
1da177e4 746 port->break_flag = 1;
e108b2ca
PM		 747 sci_schedule_break_timer(port);
748 } else if (port->break_flag == 1) {
1da177e4
LT		 749 /* break is over. */
750 port->break_flag = 2;
e108b2ca
PM		 751 sci_schedule_break_timer(port);
752 } else
753 port->break_flag = 0;
1da177e4
LT		 754}
755
94c8b6db 756static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 757{
758 int copied = 0;
b12bb29f 759 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 760 struct tty_port *tport = &port->state->port;
debf9507 761 struct sci_port *s = to_sci_port(port);
1da177e4 762
debf9507
PM		 763 /*
764 * Handle overruns, if supported.
765 */
766 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
767 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 768 port->icount.overrun++;
769
debf9507 770 /* overrun error */
92a19f9c 771 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
debf9507 772 copied++;
762c69e3 773
debf9507
PM		 774 dev_notice(port->dev, "overrun error");
775 }
1da177e4
LT		 776 }
777
e108b2ca 778 if (status & SCxSR_FER(port)) {
1da177e4
LT		 779 if (sci_rxd_in(port) == 0) {
780 /* Notify of BREAK */
e7c98dc7 781 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 782
783 if (!sci_port->break_flag) {
d97fbbed
PM		 784 port->icount.brk++;
785
e108b2ca
PM		 786 sci_port->break_flag = 1;
787 sci_schedule_break_timer(sci_port);
788
1da177e4 789 /* Do sysrq handling. */
e108b2ca 790 if (uart_handle_break(port))
1da177e4 791 return 0;
762c69e3
PM		 792
793 dev_dbg(port->dev, "BREAK detected\n");
794
92a19f9c 795 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 796 copied++;
797 }
798
e108b2ca 799 } else {
1da177e4 800 /* frame error */
d97fbbed
PM		 801 port->icount.frame++;
802
92a19f9c 803 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 804 copied++;
762c69e3
PM		 805
806 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 807 }
808 }
809
e108b2ca 810 if (status & SCxSR_PER(port)) {
1da177e4 811 /* parity error */
d97fbbed
PM		 812 port->icount.parity++;
813
92a19f9c 814 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 815 copied++;
762c69e3
PM		 816
817 dev_notice(port->dev, "parity error");
1da177e4
LT		 818 }
819
33f0f88f 820 if (copied)
2e124b4a 821 tty_flip_buffer_push(tport);
1da177e4
LT		 822
823 return copied;
824}
825
94c8b6db 826static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 827{
92a19f9c 828 struct tty_port *tport = &port->state->port;
debf9507 829 struct sci_port *s = to_sci_port(port);
4b8c59a3 830 struct plat_sci_reg *reg;
d830fa45
PM		 831 int copied = 0;
832
4b8c59a3
PM		 833 reg = sci_getreg(port, SCLSR);
834 if (!reg->size)
d830fa45
PM		 835 return 0;
836
b12bb29f
PM		 837 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
838 serial_port_out(port, SCLSR, 0);
d830fa45 839
d97fbbed
PM		 840 port->icount.overrun++;
841
92a19f9c 842 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 843 tty_flip_buffer_push(tport);
d830fa45
PM		 844
845 dev_notice(port->dev, "overrun error\n");
846 copied++;
847 }
848
849 return copied;
850}
851
94c8b6db 852static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 853{
854 int copied = 0;
b12bb29f 855 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 856 struct tty_port *tport = &port->state->port;
a5660ada 857 struct sci_port *s = to_sci_port(port);
1da177e4 858
0b3d4ef6
PM		 859 if (uart_handle_break(port))
860 return 0;
861
b7a76e4b 862 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 863#if defined(CONFIG_CPU_SH3)
864 /* Debounce break */
865 s->break_flag = 1;
866#endif
d97fbbed
PM		 867
868 port->icount.brk++;
869
1da177e4 870 /* Notify of BREAK */
92a19f9c 871 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 872 copied++;
762c69e3
PM		 873
874 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 875 }
876
33f0f88f 877 if (copied)
2e124b4a 878 tty_flip_buffer_push(tport);
e108b2ca 879
d830fa45
PM		 880 copied += sci_handle_fifo_overrun(port);
881
1da177e4
LT		 882 return copied;
883}
884
73a19e4c 885static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 886{
73a19e4c
GL		 887#ifdef CONFIG_SERIAL_SH_SCI_DMA
888 struct uart_port *port = ptr;
889 struct sci_port *s = to_sci_port(port);
890
891 if (s->chan_rx) {
b12bb29f
PM		 892 u16 scr = serial_port_in(port, SCSCR);
893 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 894
895 /* Disable future Rx interrupts */
d1d4b10c 896 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 897 disable_irq_nosync(irq);
898 scr |= 0x4000;
899 } else {
f43dc23d 900 scr &= ~SCSCR_RIE;
3089f381 901 }
b12bb29f 902 serial_port_out(port, SCSCR, scr);
73a19e4c 903 /* Clear current interrupt */
b12bb29f 904 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 905 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
906 jiffies, s->rx_timeout);
907 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 908
909 return IRQ_HANDLED;
910 }
911#endif
912
1da177e4
LT		 913 /* I think sci_receive_chars has to be called irrespective
914 * of whether the I_IXOFF is set, otherwise, how is the interrupt
915 * to be disabled?
916 */
73a19e4c 917 sci_receive_chars(ptr);
1da177e4
LT		 918
919 return IRQ_HANDLED;
920}
921
7d12e780 922static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 923{
924 struct uart_port *port = ptr;
fd78a76a 925 unsigned long flags;
1da177e4 926
fd78a76a 927 spin_lock_irqsave(&port->lock, flags);
1da177e4 928 sci_transmit_chars(port);
fd78a76a 929 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 930
931 return IRQ_HANDLED;
932}
933
7d12e780 934static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 935{
936 struct uart_port *port = ptr;
937
938 /* Handle errors */
939 if (port->type == PORT_SCI) {
940 if (sci_handle_errors(port)) {
941 /* discard character in rx buffer */
b12bb29f
PM		 942 serial_port_in(port, SCxSR);
943 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 944 }
945 } else {
d830fa45 946 sci_handle_fifo_overrun(port);
7d12e780 947 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 948 }
949
b12bb29f 950 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 951
952 /* Kick the transmission */
7d12e780 953 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 954
955 return IRQ_HANDLED;
956}
957
7d12e780 958static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 959{
960 struct uart_port *port = ptr;
961
962 /* Handle BREAKs */
963 sci_handle_breaks(port);
b12bb29f 964 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 965
966 return IRQ_HANDLED;
967}
968
f43dc23d
PM		 969static inline unsigned long port_rx_irq_mask(struct uart_port *port)
970{
971 /*
972 * Not all ports (such as SCIFA) will support REIE. Rather than
973 * special-casing the port type, we check the port initialization
974 * IRQ enable mask to see whether the IRQ is desired at all. If
975 * it's unset, it's logically inferred that there's no point in
976 * testing for it.
977 */
ce6738b6 978 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 979}
980
7d12e780 981static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 982{
44e18e9e 983 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 984 struct uart_port *port = ptr;
73a19e4c 985 struct sci_port *s = to_sci_port(port);
a8884e34 986 irqreturn_t ret = IRQ_NONE;
1da177e4 987
b12bb29f
PM		 988 ssr_status = serial_port_in(port, SCxSR);
989 scr_status = serial_port_in(port, SCSCR);
f43dc23d 990 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 991
992 /* Tx Interrupt */
f43dc23d 993 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 994 !s->chan_tx)
a8884e34 995 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 996
73a19e4c
GL		 997 /*
998 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
999 * DR flags
1000 */
1001 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 1002 (scr_status & SCSCR_RIE))
a8884e34 1003 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1004
1da177e4 1005 /* Error Interrupt */
dd4da3a5 1006 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1007 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1008
1da177e4 1009 /* Break Interrupt */
dd4da3a5 1010 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1011 ret = sci_br_interrupt(irq, ptr);
1da177e4 1012
a8884e34 1013 return ret;
1da177e4
LT		 1014}
1015
1da177e4 1016/*
25985edc 1017 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1018 * ports' baud rate when the peripheral clock changes.
1019 */
e108b2ca
PM		 1020static int sci_notifier(struct notifier_block *self,
1021 unsigned long phase, void *p)
1da177e4 1022{
e552de24
MD		 1023 struct sci_port *sci_port;
1024 unsigned long flags;
1da177e4 1025
d535a230
PM		 1026 sci_port = container_of(self, struct sci_port, freq_transition);
1027
1da177e4 1028 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 1029 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 1030 struct uart_port *port = &sci_port->port;
073e84c9 1031
d535a230
PM		 1032 spin_lock_irqsave(&port->lock, flags);
1033 port->uartclk = clk_get_rate(sci_port->iclk);
1034 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1035 }
1da177e4 1036
1da177e4
LT		 1037 return NOTIFY_OK;
1038}
501b825d 1039
9174fc8f
PM		 1040static struct sci_irq_desc {
1041 const char *desc;
1042 irq_handler_t handler;
1043} sci_irq_desc[] = {
1044 /*
1045 * Split out handlers, the default case.
1046 */
1047 [SCIx_ERI_IRQ] = {
1048 .desc = "rx err",
1049 .handler = sci_er_interrupt,
1050 },
1051
1052 [SCIx_RXI_IRQ] = {
1053 .desc = "rx full",
1054 .handler = sci_rx_interrupt,
1055 },
1056
1057 [SCIx_TXI_IRQ] = {
1058 .desc = "tx empty",
1059 .handler = sci_tx_interrupt,
1060 },
1061
1062 [SCIx_BRI_IRQ] = {
1063 .desc = "break",
1064 .handler = sci_br_interrupt,
1065 },
1066
1067 /*
1068 * Special muxed handler.
1069 */
1070 [SCIx_MUX_IRQ] = {
1071 .desc = "mux",
1072 .handler = sci_mpxed_interrupt,
1073 },
1074};
1075
1da177e4
LT		 1076static int sci_request_irq(struct sci_port *port)
1077{
9174fc8f
PM		 1078 struct uart_port *up = &port->port;
1079 int i, j, ret = 0;
1080
1081 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1082 struct sci_irq_desc *desc;
1fcc91a6 1083 int irq;
9174fc8f
PM		 1084
1085 if (SCIx_IRQ_IS_MUXED(port)) {
1086 i = SCIx_MUX_IRQ;
1087 irq = up->irq;
0e8963de 1088 } else {
1fcc91a6 1089 irq = port->irqs[i];
9174fc8f 1090
0e8963de
PM		 1091 /*
1092 * Certain port types won't support all of the
1093 * available interrupt sources.
1094 */
1fcc91a6 1095 if (unlikely(irq < 0))
0e8963de
PM		 1096 continue;
1097 }
1098
9174fc8f
PM		 1099 desc = sci_irq_desc + i;
1100 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1101 dev_name(up->dev), desc->desc);
1102 if (!port->irqstr[j]) {
1103 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1104 desc->desc);
1105 goto out_nomem;
1da177e4 1106 }
9174fc8f
PM		 1107
1108 ret = request_irq(irq, desc->handler, up->irqflags,
1109 port->irqstr[j], port);
1110 if (unlikely(ret)) {
1111 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1112 goto out_noirq;
1da177e4
LT		 1113 }
1114 }
1115
1116 return 0;
9174fc8f
PM		 1117
1118out_noirq:
1119 while (--i >= 0)
1fcc91a6 1120 free_irq(port->irqs[i], port);
9174fc8f
PM		 1121
1122out_nomem:
1123 while (--j >= 0)
1124 kfree(port->irqstr[j]);
1125
1126 return ret;
1da177e4
LT		 1127}
1128
1129static void sci_free_irq(struct sci_port *port)
1130{
1131 int i;
1132
9174fc8f
PM		 1133 /*
1134 * Intentionally in reverse order so we iterate over the muxed
1135 * IRQ first.
1136 */
1137 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1138 int irq = port->irqs[i];
0e8963de
PM		 1139
1140 /*
1141 * Certain port types won't support all of the available
1142 * interrupt sources.
1143 */
1fcc91a6 1144 if (unlikely(irq < 0))
0e8963de
PM		 1145 continue;
1146
1fcc91a6 1147 free_irq(port->irqs[i], port);
9174fc8f 1148 kfree(port->irqstr[i]);
1da177e4 1149
9174fc8f
PM		 1150 if (SCIx_IRQ_IS_MUXED(port)) {
1151 /* If there's only one IRQ, we're done. */
1152 return;
1da177e4
LT		 1153 }
1154 }
1155}
1156
50f0959a
PM		 1157static const char *sci_gpio_names[SCIx_NR_FNS] = {
1158 "sck", "rxd", "txd", "cts", "rts",
1159};
1160
1161static const char *sci_gpio_str(unsigned int index)
1162{
1163 return sci_gpio_names[index];
1164}
1165
9671f099 1166static void sci_init_gpios(struct sci_port *port)
50f0959a
PM		 1167{
1168 struct uart_port *up = &port->port;
1169 int i;
1170
1171 if (!port->cfg)
1172 return;
1173
1174 for (i = 0; i < SCIx_NR_FNS; i++) {
1175 const char *desc;
1176 int ret;
1177
1178 if (!port->cfg->gpios[i])
1179 continue;
1180
1181 desc = sci_gpio_str(i);
1182
1183 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1184 dev_name(up->dev), desc);
1185
1186 /*
1187 * If we've failed the allocation, we can still continue
1188 * on with a NULL string.
1189 */
1190 if (!port->gpiostr[i])
1191 dev_notice(up->dev, "%s string allocation failure\n",
1192 desc);
1193
1194 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1195 if (unlikely(ret != 0)) {
1196 dev_notice(up->dev, "failed %s gpio request\n", desc);
1197
1198 /*
1199 * If we can't get the GPIO for whatever reason,
1200 * no point in keeping the verbose string around.
1201 */
1202 kfree(port->gpiostr[i]);
1203 }
1204 }
1205}
1206
1207static void sci_free_gpios(struct sci_port *port)
1208{
1209 int i;
1210
1211 for (i = 0; i < SCIx_NR_FNS; i++)
1212 if (port->cfg->gpios[i]) {
1213 gpio_free(port->cfg->gpios[i]);
1214 kfree(port->gpiostr[i]);
1215 }
1216}
1217
1da177e4
LT		 1218static unsigned int sci_tx_empty(struct uart_port *port)
1219{
b12bb29f 1220 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1221 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1222
1223 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1224}
1225
cdf7c42f
PM		 1226/*
1227 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1228 * CTS/RTS is supported in hardware by at least one port and controlled
1229 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1230 * handled via the ->init_pins() op, which is a bit of a one-way street,
1231 * lacking any ability to defer pin control -- this will later be
1232 * converted over to the GPIO framework).
dc7e3ef7
PM		 1233 *
1234 * Other modes (such as loopback) are supported generically on certain
1235 * port types, but not others. For these it's sufficient to test for the
1236 * existence of the support register and simply ignore the port type.
cdf7c42f 1237 */
1da177e4
LT		 1238static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1239{
dc7e3ef7
PM		 1240 if (mctrl & TIOCM_LOOP) {
1241 struct plat_sci_reg *reg;
1242
1243 /*
1244 * Standard loopback mode for SCFCR ports.
1245 */
1246 reg = sci_getreg(port, SCFCR);
1247 if (reg->size)
b12bb29f 1248 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1249 }
1da177e4
LT		 1250}
1251
1252static unsigned int sci_get_mctrl(struct uart_port *port)
1253{
cdf7c42f
PM		 1254 /*
1255 * CTS/RTS is handled in hardware when supported, while nothing
1256 * else is wired up. Keep it simple and simply assert DSR/CAR.
1257 */
1258 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1259}
1260
73a19e4c
GL		 1261#ifdef CONFIG_SERIAL_SH_SCI_DMA
1262static void sci_dma_tx_complete(void *arg)
1263{
1264 struct sci_port *s = arg;
1265 struct uart_port *port = &s->port;
1266 struct circ_buf *xmit = &port->state->xmit;
1267 unsigned long flags;
1268
1269 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1270
1271 spin_lock_irqsave(&port->lock, flags);
1272
f354a381 1273 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1274 xmit->tail &= UART_XMIT_SIZE - 1;
1275
f354a381 1276 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1277
1278 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1279 s->desc_tx = NULL;
1280
73a19e4c
GL		 1281 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1282 uart_write_wakeup(port);
1283
3089f381 1284 if (!uart_circ_empty(xmit)) {
49d4bcad 1285 s->cookie_tx = 0;
73a19e4c 1286 schedule_work(&s->work_tx);
49d4bcad
YT		 1287 } else {
1288 s->cookie_tx = -EINVAL;
1289 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1290 u16 ctrl = serial_port_in(port, SCSCR);
1291 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1292 }
3089f381
GL		 1293 }
1294
1295 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1296}
1297
1298/* Locking: called with port lock held */
92a19f9c 1299static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1300{
1301 struct uart_port *port = &s->port;
227434f8 1302 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1303 int i, active, room;
1304
227434f8 1305 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1306
1307 if (s->active_rx == s->cookie_rx[0]) {
1308 active = 0;
1309 } else if (s->active_rx == s->cookie_rx[1]) {
1310 active = 1;
1311 } else {
1312 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1313 return 0;
1314 }
1315
1316 if (room < count)
e2afca69 1317 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1318 count - room);
1319 if (!room)
1320 return room;
1321
1322 for (i = 0; i < room; i++)
92a19f9c 1323 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1324 TTY_NORMAL);
1325
1326 port->icount.rx += room;
1327
1328 return room;
1329}
1330
1331static void sci_dma_rx_complete(void *arg)
1332{
1333 struct sci_port *s = arg;
1334 struct uart_port *port = &s->port;
73a19e4c
GL		 1335 unsigned long flags;
1336 int count;
1337
3089f381 1338 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1339
1340 spin_lock_irqsave(&port->lock, flags);
1341
92a19f9c 1342 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1343
3089f381 1344 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1345
1346 spin_unlock_irqrestore(&port->lock, flags);
1347
1348 if (count)
2e124b4a 1349 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1350
1351 schedule_work(&s->work_rx);
1352}
1353
73a19e4c
GL		 1354static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1355{
1356 struct dma_chan *chan = s->chan_rx;
1357 struct uart_port *port = &s->port;
73a19e4c
GL		 1358
1359 s->chan_rx = NULL;
1360 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1361 dma_release_channel(chan);
85b8e3ff
GL		 1362 if (sg_dma_address(&s->sg_rx[0]))
1363 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1364 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1365 if (enable_pio)
1366 sci_start_rx(port);
1367}
1368
1369static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1370{
1371 struct dma_chan *chan = s->chan_tx;
1372 struct uart_port *port = &s->port;
73a19e4c
GL		 1373
1374 s->chan_tx = NULL;
1375 s->cookie_tx = -EINVAL;
1376 dma_release_channel(chan);
1377 if (enable_pio)
1378 sci_start_tx(port);
1379}
1380
1381static void sci_submit_rx(struct sci_port *s)
1382{
1383 struct dma_chan *chan = s->chan_rx;
1384 int i;
1385
1386 for (i = 0; i < 2; i++) {
1387 struct scatterlist *sg = &s->sg_rx[i];
1388 struct dma_async_tx_descriptor *desc;
1389
16052827 1390 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1391 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1392
1393 if (desc) {
1394 s->desc_rx[i] = desc;
1395 desc->callback = sci_dma_rx_complete;
1396 desc->callback_param = s;
1397 s->cookie_rx[i] = desc->tx_submit(desc);
1398 }
1399
1400 if (!desc || s->cookie_rx[i] < 0) {
1401 if (i) {
1402 async_tx_ack(s->desc_rx[0]);
1403 s->cookie_rx[0] = -EINVAL;
1404 }
1405 if (desc) {
1406 async_tx_ack(desc);
1407 s->cookie_rx[i] = -EINVAL;
1408 }
1409 dev_warn(s->port.dev,
1410 "failed to re-start DMA, using PIO\n");
1411 sci_rx_dma_release(s, true);
1412 return;
1413 }
3089f381
GL		 1414 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1415 s->cookie_rx[i], i);
73a19e4c
GL		 1416 }
1417
1418 s->active_rx = s->cookie_rx[0];
1419
1420 dma_async_issue_pending(chan);
1421}
1422
1423static void work_fn_rx(struct work_struct *work)
1424{
1425 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1426 struct uart_port *port = &s->port;
1427 struct dma_async_tx_descriptor *desc;
1428 int new;
1429
1430 if (s->active_rx == s->cookie_rx[0]) {
1431 new = 0;
1432 } else if (s->active_rx == s->cookie_rx[1]) {
1433 new = 1;
1434 } else {
1435 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1436 return;
1437 }
1438 desc = s->desc_rx[new];
1439
1440 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1441 DMA_COMPLETE) {
73a19e4c 1442 /* Handle incomplete DMA receive */
73a19e4c 1443 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1444 struct shdma_desc *sh_desc = container_of(desc,
1445 struct shdma_desc, async_tx);
73a19e4c
GL		 1446 unsigned long flags;
1447 int count;
1448
05827630 1449 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
e2afca69 1450 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1451 sh_desc->partial, sh_desc->cookie);
1452
1453 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1454 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1455 spin_unlock_irqrestore(&port->lock, flags);
1456
1457 if (count)
2e124b4a 1458 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1459
1460 sci_submit_rx(s);
1461
1462 return;
1463 }
1464
1465 s->cookie_rx[new] = desc->tx_submit(desc);
1466 if (s->cookie_rx[new] < 0) {
1467 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1468 sci_rx_dma_release(s, true);
1469 return;
1470 }
1471
73a19e4c 1472 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1473
1474 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1475 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1476}
1477
1478static void work_fn_tx(struct work_struct *work)
1479{
1480 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1481 struct dma_async_tx_descriptor *desc;
1482 struct dma_chan *chan = s->chan_tx;
1483 struct uart_port *port = &s->port;
1484 struct circ_buf *xmit = &port->state->xmit;
1485 struct scatterlist *sg = &s->sg_tx;
1486
1487 /*
1488 * DMA is idle now.
1489 * Port xmit buffer is already mapped, and it is one page... Just adjust
1490 * offsets and lengths. Since it is a circular buffer, we have to
1491 * transmit till the end, and then the rest. Take the port lock to get a
1492 * consistent xmit buffer state.
1493 */
1494 spin_lock_irq(&port->lock);
1495 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1496 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1497 sg->offset;
f354a381 1498 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1499 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1500 spin_unlock_irq(&port->lock);
1501
f354a381 1502 BUG_ON(!sg_dma_len(sg));
73a19e4c 1503
16052827 1504 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1505 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1506 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1507 if (!desc) {
1508 /* switch to PIO */
1509 sci_tx_dma_release(s, true);
1510 return;
1511 }
1512
1513 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1514
1515 spin_lock_irq(&port->lock);
1516 s->desc_tx = desc;
1517 desc->callback = sci_dma_tx_complete;
1518 desc->callback_param = s;
1519 spin_unlock_irq(&port->lock);
1520 s->cookie_tx = desc->tx_submit(desc);
1521 if (s->cookie_tx < 0) {
1522 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1523 /* switch to PIO */
1524 sci_tx_dma_release(s, true);
1525 return;
1526 }
1527
1528 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1529 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1530
1531 dma_async_issue_pending(chan);
1532}
1533#endif
1534
b129a8cc 1535static void sci_start_tx(struct uart_port *port)
1da177e4 1536{
3089f381 1537 struct sci_port *s = to_sci_port(port);
e108b2ca 1538 unsigned short ctrl;
1da177e4 1539
73a19e4c 1540#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1541 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1542 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1543 if (s->chan_tx)
1544 new = scr | 0x8000;
1545 else
1546 new = scr & ~0x8000;
1547 if (new != scr)
b12bb29f 1548 serial_port_out(port, SCSCR, new);
73a19e4c 1549 }
f43dc23d 1550
3089f381 1551 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1552 s->cookie_tx < 0) {
1553 s->cookie_tx = 0;
3089f381 1554 schedule_work(&s->work_tx);
49d4bcad 1555 }
73a19e4c 1556#endif
f43dc23d 1557
d1d4b10c 1558 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1559 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1560 ctrl = serial_port_in(port, SCSCR);
1561 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1562 }
1da177e4
LT		 1563}
1564
b129a8cc 1565static void sci_stop_tx(struct uart_port *port)
1da177e4 1566{
1da177e4
LT		 1567 unsigned short ctrl;
1568
1569 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1570 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1571
d1d4b10c 1572 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1573 ctrl &= ~0x8000;
f43dc23d 1574
8e698614 1575 ctrl &= ~SCSCR_TIE;
f43dc23d 1576
b12bb29f 1577 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1578}
1579
73a19e4c 1580static void sci_start_rx(struct uart_port *port)
1da177e4 1581{
1da177e4
LT		 1582 unsigned short ctrl;
1583
b12bb29f 1584 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1585
d1d4b10c 1586 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1587 ctrl &= ~0x4000;
f43dc23d 1588
b12bb29f 1589 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1590}
1591
1592static void sci_stop_rx(struct uart_port *port)
1593{
1da177e4
LT		 1594 unsigned short ctrl;
1595
b12bb29f 1596 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1597
d1d4b10c 1598 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1599 ctrl &= ~0x4000;
f43dc23d
PM		 1600
1601 ctrl &= ~port_rx_irq_mask(port);
1602
b12bb29f 1603 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1604}
1605
1606static void sci_enable_ms(struct uart_port *port)
1607{
d39ec6ce
PM		 1608 /*
1609 * Not supported by hardware, always a nop.
1610 */
1da177e4
LT		 1611}
1612
1613static void sci_break_ctl(struct uart_port *port, int break_state)
1614{
bbb4ce50 1615 struct sci_port *s = to_sci_port(port);
a4e02f6d 1616 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1617 unsigned short scscr, scsptr;
1618
a4e02f6d
SY		 1619 /* check wheter the port has SCSPTR */
1620 if (!reg->size) {
bbb4ce50
SY		 1621 /*
1622 * Not supported by hardware. Most parts couple break and rx
1623 * interrupts together, with break detection always enabled.
1624 */
a4e02f6d 1625 return;
bbb4ce50 1626 }
a4e02f6d
SY		 1627
1628 scsptr = serial_port_in(port, SCSPTR);
1629 scscr = serial_port_in(port, SCSCR);
1630
1631 if (break_state == -1) {
1632 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1633 scscr &= ~SCSCR_TE;
1634 } else {
1635 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1636 scscr |= SCSCR_TE;
1637 }
1638
1639 serial_port_out(port, SCSPTR, scsptr);
1640 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1641}
1642
73a19e4c
GL		 1643#ifdef CONFIG_SERIAL_SH_SCI_DMA
1644static bool filter(struct dma_chan *chan, void *slave)
1645{
1646 struct sh_dmae_slave *param = slave;
1647
1648 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1649 param->shdma_slave.slave_id);
73a19e4c 1650
d6fa5a4e 1651 chan->private = &param->shdma_slave;
937bb6e4 1652 return true;
73a19e4c
GL		 1653}
1654
1655static void rx_timer_fn(unsigned long arg)
1656{
1657 struct sci_port *s = (struct sci_port *)arg;
1658 struct uart_port *port = &s->port;
b12bb29f 1659 u16 scr = serial_port_in(port, SCSCR);
3089f381 1660
d1d4b10c 1661 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1662 scr &= ~0x4000;
1fcc91a6 1663 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1664 }
b12bb29f 1665 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1666 dev_dbg(port->dev, "DMA Rx timed out\n");
1667 schedule_work(&s->work_rx);
1668}
1669
1670static void sci_request_dma(struct uart_port *port)
1671{
1672 struct sci_port *s = to_sci_port(port);
1673 struct sh_dmae_slave *param;
1674 struct dma_chan *chan;
1675 dma_cap_mask_t mask;
1676 int nent;
1677
937bb6e4
GL		 1678 dev_dbg(port->dev, "%s: port %d\n", __func__,
1679 port->line);
73a19e4c 1680
937bb6e4 1681 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1682 return;
1683
1684 dma_cap_zero(mask);
1685 dma_cap_set(DMA_SLAVE, mask);
1686
1687 param = &s->param_tx;
1688
1689 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1690 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1691
1692 s->cookie_tx = -EINVAL;
1693 chan = dma_request_channel(mask, filter, param);
1694 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1695 if (chan) {
1696 s->chan_tx = chan;
1697 sg_init_table(&s->sg_tx, 1);
1698 /* UART circular tx buffer is an aligned page. */
e2afca69 1699 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1700 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1701 UART_XMIT_SIZE,
1702 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1703 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1704 if (!nent)
1705 sci_tx_dma_release(s, false);
1706 else
e2afca69
LP		 1707 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1708 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1709 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1710
1711 s->sg_len_tx = nent;
1712
1713 INIT_WORK(&s->work_tx, work_fn_tx);
1714 }
1715
1716 param = &s->param_rx;
1717
1718 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1719 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1720
1721 chan = dma_request_channel(mask, filter, param);
1722 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1723 if (chan) {
1724 dma_addr_t dma[2];
1725 void *buf[2];
1726 int i;
1727
1728 s->chan_rx = chan;
1729
1730 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1731 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1732 &dma[0], GFP_KERNEL);
1733
1734 if (!buf[0]) {
1735 dev_warn(port->dev,
1736 "failed to allocate dma buffer, using PIO\n");
1737 sci_rx_dma_release(s, true);
1738 return;
1739 }
1740
1741 buf[1] = buf[0] + s->buf_len_rx;
1742 dma[1] = dma[0] + s->buf_len_rx;
1743
1744 for (i = 0; i < 2; i++) {
1745 struct scatterlist *sg = &s->sg_rx[i];
1746
1747 sg_init_table(sg, 1);
1748 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1749 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1750 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1751 }
1752
1753 INIT_WORK(&s->work_rx, work_fn_rx);
1754 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1755
1756 sci_submit_rx(s);
1757 }
1758}
1759
1760static void sci_free_dma(struct uart_port *port)
1761{
1762 struct sci_port *s = to_sci_port(port);
1763
73a19e4c
GL		 1764 if (s->chan_tx)
1765 sci_tx_dma_release(s, false);
1766 if (s->chan_rx)
1767 sci_rx_dma_release(s, false);
1768}
27bd1075
PM		 1769#else
1770static inline void sci_request_dma(struct uart_port *port)
1771{
1772}
1773
1774static inline void sci_free_dma(struct uart_port *port)
1775{
1776}
73a19e4c
GL		 1777#endif
1778
1da177e4
LT		 1779static int sci_startup(struct uart_port *port)
1780{
a5660ada 1781 struct sci_port *s = to_sci_port(port);
33b48e16 1782 unsigned long flags;
073e84c9 1783 int ret;
1da177e4 1784
73a19e4c
GL		 1785 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1786
073e84c9
PM		 1787 ret = sci_request_irq(s);
1788 if (unlikely(ret < 0))
1789 return ret;
1790
73a19e4c 1791 sci_request_dma(port);
073e84c9 1792
33b48e16 1793 spin_lock_irqsave(&port->lock, flags);
d656901b 1794 sci_start_tx(port);
73a19e4c 1795 sci_start_rx(port);
33b48e16 1796 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1797
1798 return 0;
1799}
1800
1801static void sci_shutdown(struct uart_port *port)
1802{
a5660ada 1803 struct sci_port *s = to_sci_port(port);
33b48e16 1804 unsigned long flags;
1da177e4 1805
73a19e4c
GL		 1806 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1807
33b48e16 1808 spin_lock_irqsave(&port->lock, flags);
1da177e4 1809 sci_stop_rx(port);
b129a8cc 1810 sci_stop_tx(port);
33b48e16 1811 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1812
73a19e4c 1813 sci_free_dma(port);
1da177e4 1814 sci_free_irq(s);
1da177e4
LT		 1815}
1816
26c92f37
PM		 1817static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1818 unsigned long freq)
1819{
1820 switch (algo_id) {
1821 case SCBRR_ALGO_1:
6557b1f6 1822 return freq / (16 * bps);
26c92f37 1823 case SCBRR_ALGO_2:
6557b1f6 1824 return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
26c92f37 1825 case SCBRR_ALGO_3:
6557b1f6 1826 return freq / (8 * bps);
26c92f37 1827 case SCBRR_ALGO_4:
6557b1f6 1828 return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
26c92f37
PM		 1829 }
1830
1831 /* Warn, but use a safe default */
1832 WARN_ON(1);
e8183a6c 1833
26c92f37
PM		 1834 return ((freq + 16 * bps) / (32 * bps) - 1);
1835}
1836
f303b364
UH		 1837/* calculate sample rate, BRR, and clock select for HSCIF */
1838static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1839 int *brr, unsigned int *srr,
1840 unsigned int *cks)
1841{
1842 int sr, c, br, err;
1843 int min_err = 1000; /* 100% */
1844
1845 /* Find the combination of sample rate and clock select with the
1846 smallest deviation from the desired baud rate. */
1847 for (sr = 8; sr <= 32; sr++) {
1848 for (c = 0; c <= 3; c++) {
1849 /* integerized formulas from HSCIF documentation */
1850 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1851 if (br < 0 || br > 255)
1852 continue;
1853 err = freq / ((br + 1) * bps * sr *
1854 (1 << (2 * c + 1)) / 1000) - 1000;
1855 if (min_err > err) {
1856 min_err = err;
1857 *brr = br;
1858 *srr = sr - 1;
1859 *cks = c;
1860 }
1861 }
1862 }
1863
1864 if (min_err == 1000) {
1865 WARN_ON(1);
1866 /* use defaults */
1867 *brr = 255;
1868 *srr = 15;
1869 *cks = 0;
1870 }
1871}
1872
1ba76220
MD		 1873static void sci_reset(struct uart_port *port)
1874{
0979e0e6 1875 struct plat_sci_reg *reg;
1ba76220
MD		 1876 unsigned int status;
1877
1878 do {
b12bb29f 1879 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1880 } while (!(status & SCxSR_TEND(port)));
1881
b12bb29f 1882 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1883
0979e0e6
PM		 1884 reg = sci_getreg(port, SCFCR);
1885 if (reg->size)
b12bb29f 1886 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1887}
1888
606d099c
AC		 1889static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1890 struct ktermios *old)
1da177e4 1891{
00b9de9c 1892 struct sci_port *s = to_sci_port(port);
0979e0e6 1893 struct plat_sci_reg *reg;
d4759ded 1894 unsigned int baud, smr_val, max_baud, cks = 0;
a2159b52 1895 int t = -1;
d4759ded 1896 unsigned int srr = 15;
1da177e4 1897
154280fd
MD		 1898 /*
1899 * earlyprintk comes here early on with port->uartclk set to zero.
1900 * the clock framework is not up and running at this point so here
1901 * we assume that 115200 is the maximum baud rate. please note that
1902 * the baud rate is not programmed during earlyprintk - it is assumed
1903 * that the previous boot loader has enabled required clocks and
1904 * setup the baud rate generator hardware for us already.
1905 */
1906 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1907
154280fd 1908 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364
UH		 1909 if (likely(baud && port->uartclk)) {
1910 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1911 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1912 &cks);
1913 } else {
1914 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1915 port->uartclk);
1916 for (cks = 0; t >= 256 && cks <= 3; cks++)
1917 t >>= 2;
1918 }
1919 }
e108b2ca 1920
23241d43 1921 sci_port_enable(s);
36003386 1922
1ba76220 1923 sci_reset(port);
1da177e4 1924
b12bb29f 1925 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1926
1da177e4
LT		 1927 if ((termios->c_cflag & CSIZE) == CS7)
1928 smr_val |= 0x40;
1929 if (termios->c_cflag & PARENB)
1930 smr_val |= 0x20;
1931 if (termios->c_cflag & PARODD)
1932 smr_val |= 0x30;
1933 if (termios->c_cflag & CSTOPB)
1934 smr_val |= 0x08;
1935
1936 uart_update_timeout(port, termios->c_cflag, baud);
1937
9d482cc3
TY		 1938 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1939 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1940
4ffc3cdb 1941 if (t >= 0) {
9d482cc3 1942 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1943 serial_port_out(port, SCBRR, t);
f303b364
UH		 1944 reg = sci_getreg(port, HSSRR);
1945 if (reg->size)
1946 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1947 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1948 } else
1949 serial_port_out(port, SCSMR, smr_val);
1da177e4 1950
d5701647 1951 sci_init_pins(port, termios->c_cflag);
0979e0e6 1952
73c3d53f
PM		 1953 reg = sci_getreg(port, SCFCR);
1954 if (reg->size) {
b12bb29f 1955 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1956
73c3d53f 1957 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1958 if (termios->c_cflag & CRTSCTS)
1959 ctrl |= SCFCR_MCE;
1960 else
1961 ctrl &= ~SCFCR_MCE;
faf02f8f 1962 }
73c3d53f
PM		 1963
1964 /*
1965 * As we've done a sci_reset() above, ensure we don't
1966 * interfere with the FIFOs while toggling MCE. As the
1967 * reset values could still be set, simply mask them out.
1968 */
1969 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1970
b12bb29f 1971 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1972 }
b7a76e4b 1973
b12bb29f 1974 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1975
3089f381
GL		 1976#ifdef CONFIG_SERIAL_SH_SCI_DMA
1977 /*
1978 * Calculate delay for 1.5 DMA buffers: see
1979 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1980 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1981 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1982 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1983 * sizes), but it has been found out experimentally, that this is not
1984 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1985 * as a minimum seem to work perfectly.
1986 */
1987 if (s->chan_rx) {
1988 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1989 port->fifosize / 2;
1990 dev_dbg(port->dev,
1991 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1992 s->rx_timeout * 1000 / HZ, port->timeout);
1993 if (s->rx_timeout < msecs_to_jiffies(20))
1994 s->rx_timeout = msecs_to_jiffies(20);
1995 }
1996#endif
1997
1da177e4 1998 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1999 sci_start_rx(port);
36003386 2000
23241d43 2001 sci_port_disable(s);
1da177e4
LT		 2002}
2003
0174e5ca
TK		 2004static void sci_pm(struct uart_port *port, unsigned int state,
2005 unsigned int oldstate)
2006{
2007 struct sci_port *sci_port = to_sci_port(port);
2008
2009 switch (state) {
2010 case 3:
2011 sci_port_disable(sci_port);
2012 break;
2013 default:
2014 sci_port_enable(sci_port);
2015 break;
2016 }
2017}
2018
1da177e4
LT		 2019static const char *sci_type(struct uart_port *port)
2020{
2021 switch (port->type) {
e7c98dc7
MT		 2022 case PORT_IRDA:
2023 return "irda";
2024 case PORT_SCI:
2025 return "sci";
2026 case PORT_SCIF:
2027 return "scif";
2028 case PORT_SCIFA:
2029 return "scifa";
d1d4b10c
GL		 2030 case PORT_SCIFB:
2031 return "scifb";
f303b364
UH		 2032 case PORT_HSCIF:
2033 return "hscif";
1da177e4
LT		 2034 }
2035
fa43972f 2036 return NULL;
1da177e4
LT		 2037}
2038
e2651647 2039static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 2040{
e2651647
PM		 2041 /*
2042 * Pick an arbitrary size that encapsulates all of the base
2043 * registers by default. This can be optimized later, or derived
2044 * from platform resource data at such a time that ports begin to
2045 * behave more erratically.
2046 */
f303b364
UH		 2047 if (port->type == PORT_HSCIF)
2048 return 96;
2049 else
2050 return 64;
1da177e4
LT		 2051}
2052
f6e9495d
PM		 2053static int sci_remap_port(struct uart_port *port)
2054{
2055 unsigned long size = sci_port_size(port);
2056
2057 /*
2058 * Nothing to do if there's already an established membase.
2059 */
2060 if (port->membase)
2061 return 0;
2062
2063 if (port->flags & UPF_IOREMAP) {
2064 port->membase = ioremap_nocache(port->mapbase, size);
2065 if (unlikely(!port->membase)) {
2066 dev_err(port->dev, "can't remap port#%d\n", port->line);
2067 return -ENXIO;
2068 }
2069 } else {
2070 /*
2071 * For the simple (and majority of) cases where we don't
2072 * need to do any remapping, just cast the cookie
2073 * directly.
2074 */
2075 port->membase = (void __iomem *)port->mapbase;
2076 }
2077
2078 return 0;
2079}
2080
e2651647 2081static void sci_release_port(struct uart_port *port)
1da177e4 2082{
e2651647
PM		 2083 if (port->flags & UPF_IOREMAP) {
2084 iounmap(port->membase);
2085 port->membase = NULL;
2086 }
2087
2088 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2089}
2090
e2651647 2091static int sci_request_port(struct uart_port *port)
1da177e4 2092{
e2651647
PM		 2093 unsigned long size = sci_port_size(port);
2094 struct resource *res;
f6e9495d 2095 int ret;
1da177e4 2096
1020520e 2097 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2098 if (unlikely(res == NULL))
2099 return -EBUSY;
1da177e4 2100
f6e9495d
PM		 2101 ret = sci_remap_port(port);
2102 if (unlikely(ret != 0)) {
2103 release_resource(res);
2104 return ret;
7ff731ae 2105 }
e2651647
PM		 2106
2107 return 0;
2108}
2109
2110static void sci_config_port(struct uart_port *port, int flags)
2111{
2112 if (flags & UART_CONFIG_TYPE) {
2113 struct sci_port *sport = to_sci_port(port);
2114
2115 port->type = sport->cfg->type;
2116 sci_request_port(port);
2117 }
1da177e4
LT		 2118}
2119
2120static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2121{
1da177e4
LT		 2122 if (ser->baud_base < 2400)
2123 /* No paper tape reader for Mitch.. */
2124 return -EINVAL;
2125
2126 return 0;
2127}
2128
2129static struct uart_ops sci_uart_ops = {
2130 .tx_empty = sci_tx_empty,
2131 .set_mctrl = sci_set_mctrl,
2132 .get_mctrl = sci_get_mctrl,
2133 .start_tx = sci_start_tx,
2134 .stop_tx = sci_stop_tx,
2135 .stop_rx = sci_stop_rx,
2136 .enable_ms = sci_enable_ms,
2137 .break_ctl = sci_break_ctl,
2138 .startup = sci_startup,
2139 .shutdown = sci_shutdown,
2140 .set_termios = sci_set_termios,
0174e5ca 2141 .pm = sci_pm,
1da177e4
LT		 2142 .type = sci_type,
2143 .release_port = sci_release_port,
2144 .request_port = sci_request_port,
2145 .config_port = sci_config_port,
2146 .verify_port = sci_verify_port,
07d2a1a1
PM		 2147#ifdef CONFIG_CONSOLE_POLL
2148 .poll_get_char = sci_poll_get_char,
2149 .poll_put_char = sci_poll_put_char,
2150#endif
1da177e4
LT		 2151};
2152
9671f099 2153static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2154 struct sci_port *sci_port, unsigned int index,
2155 struct plat_sci_port *p, bool early)
e108b2ca 2156{
73a19e4c 2157 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2158 const struct resource *res;
2159 unsigned int i;
3127c6b2 2160 int ret;
e108b2ca 2161
50f0959a
PM		 2162 sci_port->cfg = p;
2163
73a19e4c
GL		 2164 port->ops = &sci_uart_ops;
2165 port->iotype = UPIO_MEM;
2166 port->line = index;
75136d48 2167
1fcc91a6
LP		 2168 if (dev->num_resources) {
2169 /* Device has resources, use them. */
2170 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2171 if (res == NULL)
2172 return -ENOMEM;
2173
2174 port->mapbase = res->start;
2175
2176 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2177 sci_port->irqs[i] = platform_get_irq(dev, i);
2178
2179 /* The SCI generates several interrupts. They can be muxed
2180 * together or connected to different interrupt lines. In the
2181 * muxed case only one interrupt resource is specified. In the
2182 * non-muxed case three or four interrupt resources are
2183 * specified, as the BRI interrupt is optional.
2184 */
2185 if (sci_port->irqs[0] < 0)
2186 return -ENXIO;
2187
2188 if (sci_port->irqs[1] < 0) {
2189 sci_port->irqs[1] = sci_port->irqs[0];
2190 sci_port->irqs[2] = sci_port->irqs[0];
2191 sci_port->irqs[3] = sci_port->irqs[0];
2192 }
2193 } else {
2194 /* No resources, use old-style platform data. */
2195 port->mapbase = p->mapbase;
2196 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2197 sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
2198 }
2199
75136d48 2200 switch (p->type) {
d1d4b10c
GL		 2201 case PORT_SCIFB:
2202 port->fifosize = 256;
2203 break;
f303b364
UH		 2204 case PORT_HSCIF:
2205 port->fifosize = 128;
2206 break;
75136d48 2207 case PORT_SCIFA:
73a19e4c 2208 port->fifosize = 64;
75136d48
MP		 2209 break;
2210 case PORT_SCIF:
73a19e4c 2211 port->fifosize = 16;
75136d48
MP		 2212 break;
2213 default:
73a19e4c 2214 port->fifosize = 1;
75136d48
MP		 2215 break;
2216 }
7b6fd3bf 2217
3127c6b2
PM		 2218 if (p->regtype == SCIx_PROBE_REGTYPE) {
2219 ret = sci_probe_regmap(p);
fc97114b 2220 if (unlikely(ret))
3127c6b2
PM		 2221 return ret;
2222 }
61a6976b 2223
1fcc91a6 2224 if (!early) {
c7ed1ab3
PM		 2225 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2226 if (IS_ERR(sci_port->iclk)) {
2227 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2228 if (IS_ERR(sci_port->iclk)) {
2229 dev_err(&dev->dev, "can't get iclk\n");
2230 return PTR_ERR(sci_port->iclk);
2231 }
2232 }
2233
2234 /*
2235 * The function clock is optional, ignore it if we can't
2236 * find it.
2237 */
2238 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2239 if (IS_ERR(sci_port->fclk))
2240 sci_port->fclk = NULL;
2241
73a19e4c 2242 port->dev = &dev->dev;
5e50d2d6 2243
50f0959a
PM		 2244 sci_init_gpios(sci_port);
2245
5e50d2d6 2246 pm_runtime_enable(&dev->dev);
7b6fd3bf 2247 }
e108b2ca 2248
7ed7e071
MD		 2249 sci_port->break_timer.data = (unsigned long)sci_port;
2250 sci_port->break_timer.function = sci_break_timer;
2251 init_timer(&sci_port->break_timer);
2252
debf9507
PM		 2253 /*
2254 * Establish some sensible defaults for the error detection.
2255 */
2256 if (!p->error_mask)
2257 p->error_mask = (p->type == PORT_SCI) ?
2258 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2259
2260 /*
2261 * Establish sensible defaults for the overrun detection, unless
2262 * the part has explicitly disabled support for it.
2263 */
2264 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2265 if (p->type == PORT_SCI)
2266 p->overrun_bit = 5;
2267 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2268 p->overrun_bit = 9;
2269 else
2270 p->overrun_bit = 0;
2271
2272 /*
2273 * Make the error mask inclusive of overrun detection, if
2274 * supported.
2275 */
2276 p->error_mask |= (1 << p->overrun_bit);
2277 }
2278
ce6738b6 2279 port->type = p->type;
b6e4a3f1 2280 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2281 port->regshift = p->regshift;
73a19e4c 2282
ce6738b6 2283 /*
61a6976b 2284 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2285 * for the multi-IRQ ports, which is where we are primarily
2286 * concerned with the shutdown path synchronization.
2287 *
2288 * For the muxed case there's nothing more to do.
2289 */
1fcc91a6 2290 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2291 port->irqflags = 0;
73a19e4c 2292
61a6976b
PM		 2293 port->serial_in = sci_serial_in;
2294 port->serial_out = sci_serial_out;
2295
937bb6e4
GL		 2296 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2297 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2298 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2299
c7ed1ab3 2300 return 0;
e108b2ca
PM		 2301}
2302
6dae1421
LP		 2303static void sci_cleanup_single(struct sci_port *port)
2304{
2305 sci_free_gpios(port);
2306
2307 clk_put(port->iclk);
2308 clk_put(port->fclk);
2309
2310 pm_runtime_disable(port->port.dev);
2311}
2312
1da177e4 2313#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2314static void serial_console_putchar(struct uart_port *port, int ch)
2315{
2316 sci_poll_put_char(port, ch);
2317}
2318
1da177e4
LT		 2319/*
2320 * Print a string to the serial port trying not to disturb
2321 * any possible real use of the port...
2322 */
2323static void serial_console_write(struct console *co, const char *s,
2324 unsigned count)
2325{
906b17dc
PM		 2326 struct sci_port *sci_port = &sci_ports[co->index];
2327 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2328 unsigned short bits, ctrl;
2329 unsigned long flags;
2330 int locked = 1;
2331
2332 local_irq_save(flags);
2333 if (port->sysrq)
2334 locked = 0;
2335 else if (oops_in_progress)
2336 locked = spin_trylock(&port->lock);
2337 else
2338 spin_lock(&port->lock);
2339
2340 /* first save the SCSCR then disable the interrupts */
2341 ctrl = serial_port_in(port, SCSCR);
2342 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2343
501b825d 2344 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2345
2346 /* wait until fifo is empty and last bit has been transmitted */
2347 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2348 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2349 cpu_relax();
40f70c03
SK		 2350
2351 /* restore the SCSCR */
2352 serial_port_out(port, SCSCR, ctrl);
2353
2354 if (locked)
2355 spin_unlock(&port->lock);
2356 local_irq_restore(flags);
1da177e4
LT		 2357}
2358
9671f099 2359static int serial_console_setup(struct console *co, char *options)
1da177e4 2360{
dc8e6f5b 2361 struct sci_port *sci_port;
1da177e4
LT		 2362 struct uart_port *port;
2363 int baud = 115200;
2364 int bits = 8;
2365 int parity = 'n';
2366 int flow = 'n';
2367 int ret;
2368
e108b2ca 2369 /*
906b17dc 2370 * Refuse to handle any bogus ports.
1da177e4 2371 */
906b17dc 2372 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2373 return -ENODEV;
e108b2ca 2374
906b17dc
PM		 2375 sci_port = &sci_ports[co->index];
2376 port = &sci_port->port;
2377
b2267a6b
AC		 2378 /*
2379 * Refuse to handle uninitialized ports.
2380 */
2381 if (!port->ops)
2382 return -ENODEV;
2383
f6e9495d
PM		 2384 ret = sci_remap_port(port);
2385 if (unlikely(ret != 0))
2386 return ret;
e108b2ca 2387
1da177e4
LT		 2388 if (options)
2389 uart_parse_options(options, &baud, &parity, &bits, &flow);
2390
ab7cfb55 2391 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2392}
2393
2394static struct console serial_console = {
2395 .name = "ttySC",
906b17dc 2396 .device = uart_console_device,
1da177e4
LT		 2397 .write = serial_console_write,
2398 .setup = serial_console_setup,
fa5da2f7 2399 .flags = CON_PRINTBUFFER,
1da177e4 2400 .index = -1,
906b17dc 2401 .data = &sci_uart_driver,
1da177e4
LT		 2402};
2403
7b6fd3bf
MD		 2404static struct console early_serial_console = {
2405 .name = "early_ttySC",
2406 .write = serial_console_write,
2407 .flags = CON_PRINTBUFFER,
906b17dc 2408 .index = -1,
7b6fd3bf 2409};
ecdf8a46 2410
7b6fd3bf
MD		 2411static char early_serial_buf[32];
2412
9671f099 2413static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2414{
574de559 2415 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2416
2417 if (early_serial_console.data)
2418 return -EEXIST;
2419
2420 early_serial_console.index = pdev->id;
ecdf8a46 2421
1fcc91a6 2422 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2423
2424 serial_console_setup(&early_serial_console, early_serial_buf);
2425
2426 if (!strstr(early_serial_buf, "keep"))
2427 early_serial_console.flags |= CON_BOOT;
2428
2429 register_console(&early_serial_console);
2430 return 0;
2431}
6a8c9799
NI		 2432
2433#define SCI_CONSOLE (&serial_console)
2434
ecdf8a46 2435#else
9671f099 2436static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2437{
2438 return -EINVAL;
2439}
1da177e4 2440
6a8c9799
NI		 2441#define SCI_CONSOLE NULL
2442
2443#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2444
2445static char banner[] __initdata =
f303b364 2446 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
1da177e4
LT		 2447
2448static struct uart_driver sci_uart_driver = {
2449 .owner = THIS_MODULE,
2450 .driver_name = "sci",
1da177e4
LT		 2451 .dev_name = "ttySC",
2452 .major = SCI_MAJOR,
2453 .minor = SCI_MINOR_START,
e108b2ca 2454 .nr = SCI_NPORTS,
1da177e4
LT		 2455 .cons = SCI_CONSOLE,
2456};
2457
54507f6e 2458static int sci_remove(struct platform_device *dev)
e552de24 2459{
d535a230 2460 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2461
d535a230
PM		 2462 cpufreq_unregister_notifier(&port->freq_transition,
2463 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2464
d535a230
PM		 2465 uart_remove_one_port(&sci_uart_driver, &port->port);
2466
6dae1421 2467 sci_cleanup_single(port);
e552de24 2468
e552de24
MD		 2469 return 0;
2470}
2471
9671f099 2472static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2473 unsigned int index,
2474 struct plat_sci_port *p,
2475 struct sci_port *sciport)
2476{
0ee70712
MD		 2477 int ret;
2478
2479 /* Sanity check */
2480 if (unlikely(index >= SCI_NPORTS)) {
2481 dev_notice(&dev->dev, "Attempting to register port "
2482 "%d when only %d are available.\n",
2483 index+1, SCI_NPORTS);
2484 dev_notice(&dev->dev, "Consider bumping "
2485 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2486 return -EINVAL;
0ee70712
MD		 2487 }
2488
1fcc91a6 2489 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2490 if (ret)
2491 return ret;
0ee70712 2492
6dae1421
LP		 2493 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2494 if (ret) {
2495 sci_cleanup_single(sciport);
2496 return ret;
2497 }
2498
2499 return 0;
0ee70712
MD		 2500}
2501
9671f099 2502static int sci_probe(struct platform_device *dev)
1da177e4 2503{
3ba35baa 2504 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
d535a230 2505 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2506 int ret;
d535a230 2507
ecdf8a46
PM		 2508 /*
2509 * If we've come here via earlyprintk initialization, head off to
2510 * the special early probe. We don't have sufficient device state
2511 * to make it beyond this yet.
2512 */
2513 if (is_early_platform_device(dev))
2514 return sci_probe_earlyprintk(dev);
7b6fd3bf 2515
d535a230 2516 platform_set_drvdata(dev, sp);
e552de24 2517
906b17dc 2518 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2519 if (ret)
6dae1421 2520 return ret;
e552de24 2521
d535a230 2522 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2523
d535a230
PM		 2524 ret = cpufreq_register_notifier(&sp->freq_transition,
2525 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2526 if (unlikely(ret < 0)) {
2527 sci_cleanup_single(sp);
2528 return ret;
2529 }
1da177e4
LT		 2530
2531#ifdef CONFIG_SH_STANDARD_BIOS
2532 sh_bios_gdb_detach();
2533#endif
2534
e108b2ca 2535 return 0;
1da177e4
LT		 2536}
2537
6daa79b3 2538static int sci_suspend(struct device *dev)
1da177e4 2539{
d535a230 2540 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2541
d535a230
PM		 2542 if (sport)
2543 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2544
e108b2ca
PM		 2545 return 0;
2546}
1da177e4 2547
6daa79b3 2548static int sci_resume(struct device *dev)
e108b2ca 2549{
d535a230 2550 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2551
d535a230
PM		 2552 if (sport)
2553 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2554
2555 return 0;
2556}
2557
47145210 2558static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2559 .suspend = sci_suspend,
2560 .resume = sci_resume,
2561};
2562
e108b2ca
PM		 2563static struct platform_driver sci_driver = {
2564 .probe = sci_probe,
b9e39c89 2565 .remove = sci_remove,
e108b2ca
PM		 2566 .driver = {
2567 .name = "sh-sci",
2568 .owner = THIS_MODULE,
6daa79b3 2569 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2570 },
2571};
2572
2573static int __init sci_init(void)
2574{
2575 int ret;
2576
2577 printk(banner);
2578
e108b2ca
PM		 2579 ret = uart_register_driver(&sci_uart_driver);
2580 if (likely(ret == 0)) {
2581 ret = platform_driver_register(&sci_driver);
2582 if (unlikely(ret))
2583 uart_unregister_driver(&sci_uart_driver);
2584 }
2585
2586 return ret;
2587}
2588
2589static void __exit sci_exit(void)
2590{
2591 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2592 uart_unregister_driver(&sci_uart_driver);
2593}
2594
7b6fd3bf
MD		 2595#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2596early_platform_init_buffer("earlyprintk", &sci_driver,
2597 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2598#endif
1da177e4
LT		 2599module_init(sci_init);
2600module_exit(sci_exit);
2601
e108b2ca 2602MODULE_LICENSE("GPL");
e169c139 2603MODULE_ALIAS("platform:sh-sci");
7f405f9c 2604MODULE_AUTHOR("Paul Mundt");
f303b364 2605MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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