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serial: sh-sci: Fix TX buffer mapping leak
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 struct dma_async_tx_descriptor *desc_tx;
108 struct dma_async_tx_descriptor *desc_rx[2];
109 dma_cookie_t cookie_tx;
110 dma_cookie_t cookie_rx[2];
111 dma_cookie_t active_rx;
79904420
GU		 112 dma_addr_t tx_dma_addr;
113 unsigned int tx_dma_len;
73a19e4c
GL		 114 struct scatterlist sg_rx[2];
115 size_t buf_len_rx;
116 struct sh_dmae_slave param_tx;
117 struct sh_dmae_slave param_rx;
118 struct work_struct work_tx;
119 struct work_struct work_rx;
120 struct timer_list rx_timer;
3089f381 121 unsigned int rx_timeout;
73a19e4c 122#endif
e552de24 123
d535a230 124 struct notifier_block freq_transition;
e108b2ca
PM		 125};
126
1da177e4 127/* Function prototypes */
d535a230 128static void sci_start_tx(struct uart_port *port);
b129a8cc 129static void sci_stop_tx(struct uart_port *port);
d535a230 130static void sci_start_rx(struct uart_port *port);
1da177e4 131
e108b2ca 132#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 133
e108b2ca
PM		 134static struct sci_port sci_ports[SCI_NPORTS];
135static struct uart_driver sci_uart_driver;
1da177e4 136
e7c98dc7
MT		 137static inline struct sci_port *
138to_sci_port(struct uart_port *uart)
139{
140 return container_of(uart, struct sci_port, port);
141}
142
61a6976b
PM		 143struct plat_sci_reg {
144 u8 offset, size;
145};
146
147/* Helper for invalidating specific entries of an inherited map. */
148#define sci_reg_invalid { .offset = 0, .size = 0 }
149
d3184e68 150static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 151 [SCIx_PROBE_REGTYPE] = {
152 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
153 },
154
155 /*
156 * Common SCI definitions, dependent on the port's regshift
157 * value.
158 */
159 [SCIx_SCI_REGTYPE] = {
160 [SCSMR] = { 0x00, 8 },
161 [SCBRR] = { 0x01, 8 },
162 [SCSCR] = { 0x02, 8 },
163 [SCxTDR] = { 0x03, 8 },
164 [SCxSR] = { 0x04, 8 },
165 [SCxRDR] = { 0x05, 8 },
166 [SCFCR] = sci_reg_invalid,
167 [SCFDR] = sci_reg_invalid,
168 [SCTFDR] = sci_reg_invalid,
169 [SCRFDR] = sci_reg_invalid,
170 [SCSPTR] = sci_reg_invalid,
171 [SCLSR] = sci_reg_invalid,
f303b364 172 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 173 [SCPCR] = sci_reg_invalid,
174 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 175 },
176
177 /*
178 * Common definitions for legacy IrDA ports, dependent on
179 * regshift value.
180 */
181 [SCIx_IRDA_REGTYPE] = {
182 [SCSMR] = { 0x00, 8 },
183 [SCBRR] = { 0x01, 8 },
184 [SCSCR] = { 0x02, 8 },
185 [SCxTDR] = { 0x03, 8 },
186 [SCxSR] = { 0x04, 8 },
187 [SCxRDR] = { 0x05, 8 },
188 [SCFCR] = { 0x06, 8 },
189 [SCFDR] = { 0x07, 16 },
190 [SCTFDR] = sci_reg_invalid,
191 [SCRFDR] = sci_reg_invalid,
192 [SCSPTR] = sci_reg_invalid,
193 [SCLSR] = sci_reg_invalid,
f303b364 194 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 195 [SCPCR] = sci_reg_invalid,
196 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 197 },
198
199 /*
200 * Common SCIFA definitions.
201 */
202 [SCIx_SCIFA_REGTYPE] = {
203 [SCSMR] = { 0x00, 16 },
204 [SCBRR] = { 0x04, 8 },
205 [SCSCR] = { 0x08, 16 },
206 [SCxTDR] = { 0x20, 8 },
207 [SCxSR] = { 0x14, 16 },
208 [SCxRDR] = { 0x24, 8 },
209 [SCFCR] = { 0x18, 16 },
210 [SCFDR] = { 0x1c, 16 },
211 [SCTFDR] = sci_reg_invalid,
212 [SCRFDR] = sci_reg_invalid,
213 [SCSPTR] = sci_reg_invalid,
214 [SCLSR] = sci_reg_invalid,
f303b364 215 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 216 [SCPCR] = { 0x30, 16 },
217 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 218 },
219
220 /*
221 * Common SCIFB definitions.
222 */
223 [SCIx_SCIFB_REGTYPE] = {
224 [SCSMR] = { 0x00, 16 },
225 [SCBRR] = { 0x04, 8 },
226 [SCSCR] = { 0x08, 16 },
227 [SCxTDR] = { 0x40, 8 },
228 [SCxSR] = { 0x14, 16 },
229 [SCxRDR] = { 0x60, 8 },
230 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 231 [SCFDR] = sci_reg_invalid,
232 [SCTFDR] = { 0x38, 16 },
233 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 234 [SCSPTR] = sci_reg_invalid,
235 [SCLSR] = sci_reg_invalid,
f303b364 236 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 237 [SCPCR] = { 0x30, 16 },
238 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 239 },
240
3af1f8a4
PE		 241 /*
242 * Common SH-2(A) SCIF definitions for ports with FIFO data
243 * count registers.
244 */
245 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x0c, 8 },
250 [SCxSR] = { 0x10, 16 },
251 [SCxRDR] = { 0x14, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCFDR] = { 0x1c, 16 },
254 [SCTFDR] = sci_reg_invalid,
255 [SCRFDR] = sci_reg_invalid,
256 [SCSPTR] = { 0x20, 16 },
257 [SCLSR] = { 0x24, 16 },
f303b364 258 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 259 [SCPCR] = sci_reg_invalid,
260 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 261 },
262
61a6976b
PM		 263 /*
264 * Common SH-3 SCIF definitions.
265 */
266 [SCIx_SH3_SCIF_REGTYPE] = {
267 [SCSMR] = { 0x00, 8 },
268 [SCBRR] = { 0x02, 8 },
269 [SCSCR] = { 0x04, 8 },
270 [SCxTDR] = { 0x06, 8 },
271 [SCxSR] = { 0x08, 16 },
272 [SCxRDR] = { 0x0a, 8 },
273 [SCFCR] = { 0x0c, 8 },
274 [SCFDR] = { 0x0e, 16 },
275 [SCTFDR] = sci_reg_invalid,
276 [SCRFDR] = sci_reg_invalid,
277 [SCSPTR] = sci_reg_invalid,
278 [SCLSR] = sci_reg_invalid,
f303b364 279 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 280 [SCPCR] = sci_reg_invalid,
281 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 282 },
283
284 /*
285 * Common SH-4(A) SCIF(B) definitions.
286 */
287 [SCIx_SH4_SCIF_REGTYPE] = {
288 [SCSMR] = { 0x00, 16 },
289 [SCBRR] = { 0x04, 8 },
290 [SCSCR] = { 0x08, 16 },
291 [SCxTDR] = { 0x0c, 8 },
292 [SCxSR] = { 0x10, 16 },
293 [SCxRDR] = { 0x14, 8 },
294 [SCFCR] = { 0x18, 16 },
295 [SCFDR] = { 0x1c, 16 },
296 [SCTFDR] = sci_reg_invalid,
297 [SCRFDR] = sci_reg_invalid,
298 [SCSPTR] = { 0x20, 16 },
299 [SCLSR] = { 0x24, 16 },
f303b364 300 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 301 [SCPCR] = sci_reg_invalid,
302 [SCPDR] = sci_reg_invalid,
f303b364
UH		 303 },
304
305 /*
306 * Common HSCIF definitions.
307 */
308 [SCIx_HSCIF_REGTYPE] = {
309 [SCSMR] = { 0x00, 16 },
310 [SCBRR] = { 0x04, 8 },
311 [SCSCR] = { 0x08, 16 },
312 [SCxTDR] = { 0x0c, 8 },
313 [SCxSR] = { 0x10, 16 },
314 [SCxRDR] = { 0x14, 8 },
315 [SCFCR] = { 0x18, 16 },
316 [SCFDR] = { 0x1c, 16 },
317 [SCTFDR] = sci_reg_invalid,
318 [SCRFDR] = sci_reg_invalid,
319 [SCSPTR] = { 0x20, 16 },
320 [SCLSR] = { 0x24, 16 },
321 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 322 [SCPCR] = sci_reg_invalid,
323 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 324 },
325
326 /*
327 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
328 * register.
329 */
330 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
331 [SCSMR] = { 0x00, 16 },
332 [SCBRR] = { 0x04, 8 },
333 [SCSCR] = { 0x08, 16 },
334 [SCxTDR] = { 0x0c, 8 },
335 [SCxSR] = { 0x10, 16 },
336 [SCxRDR] = { 0x14, 8 },
337 [SCFCR] = { 0x18, 16 },
338 [SCFDR] = { 0x1c, 16 },
339 [SCTFDR] = sci_reg_invalid,
340 [SCRFDR] = sci_reg_invalid,
341 [SCSPTR] = sci_reg_invalid,
342 [SCLSR] = { 0x24, 16 },
f303b364 343 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 344 [SCPCR] = sci_reg_invalid,
345 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 346 },
347
348 /*
349 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
350 * count registers.
351 */
352 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
353 [SCSMR] = { 0x00, 16 },
354 [SCBRR] = { 0x04, 8 },
355 [SCSCR] = { 0x08, 16 },
356 [SCxTDR] = { 0x0c, 8 },
357 [SCxSR] = { 0x10, 16 },
358 [SCxRDR] = { 0x14, 8 },
359 [SCFCR] = { 0x18, 16 },
360 [SCFDR] = { 0x1c, 16 },
361 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
362 [SCRFDR] = { 0x20, 16 },
363 [SCSPTR] = { 0x24, 16 },
364 [SCLSR] = { 0x28, 16 },
f303b364 365 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 366 [SCPCR] = sci_reg_invalid,
367 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 368 },
369
370 /*
371 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
372 * registers.
373 */
374 [SCIx_SH7705_SCIF_REGTYPE] = {
375 [SCSMR] = { 0x00, 16 },
376 [SCBRR] = { 0x04, 8 },
377 [SCSCR] = { 0x08, 16 },
378 [SCxTDR] = { 0x20, 8 },
379 [SCxSR] = { 0x14, 16 },
380 [SCxRDR] = { 0x24, 8 },
381 [SCFCR] = { 0x18, 16 },
382 [SCFDR] = { 0x1c, 16 },
383 [SCTFDR] = sci_reg_invalid,
384 [SCRFDR] = sci_reg_invalid,
385 [SCSPTR] = sci_reg_invalid,
386 [SCLSR] = sci_reg_invalid,
f303b364 387 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 388 [SCPCR] = sci_reg_invalid,
389 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 390 },
391};
392
72b294cf
PM		 393#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
394
61a6976b
PM		 395/*
396 * The "offset" here is rather misleading, in that it refers to an enum
397 * value relative to the port mapping rather than the fixed offset
398 * itself, which needs to be manually retrieved from the platform's
399 * register map for the given port.
400 */
401static unsigned int sci_serial_in(struct uart_port *p, int offset)
402{
d3184e68 403 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 404
405 if (reg->size == 8)
406 return ioread8(p->membase + (reg->offset << p->regshift));
407 else if (reg->size == 16)
408 return ioread16(p->membase + (reg->offset << p->regshift));
409 else
410 WARN(1, "Invalid register access\n");
411
412 return 0;
413}
414
415static void sci_serial_out(struct uart_port *p, int offset, int value)
416{
d3184e68 417 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 418
419 if (reg->size == 8)
420 iowrite8(value, p->membase + (reg->offset << p->regshift));
421 else if (reg->size == 16)
422 iowrite16(value, p->membase + (reg->offset << p->regshift));
423 else
424 WARN(1, "Invalid register access\n");
425}
426
61a6976b
PM		 427static int sci_probe_regmap(struct plat_sci_port *cfg)
428{
429 switch (cfg->type) {
430 case PORT_SCI:
431 cfg->regtype = SCIx_SCI_REGTYPE;
432 break;
433 case PORT_IRDA:
434 cfg->regtype = SCIx_IRDA_REGTYPE;
435 break;
436 case PORT_SCIFA:
437 cfg->regtype = SCIx_SCIFA_REGTYPE;
438 break;
439 case PORT_SCIFB:
440 cfg->regtype = SCIx_SCIFB_REGTYPE;
441 break;
442 case PORT_SCIF:
443 /*
444 * The SH-4 is a bit of a misnomer here, although that's
445 * where this particular port layout originated. This
446 * configuration (or some slight variation thereof)
447 * remains the dominant model for all SCIFs.
448 */
449 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
450 break;
f303b364
UH		 451 case PORT_HSCIF:
452 cfg->regtype = SCIx_HSCIF_REGTYPE;
453 break;
61a6976b 454 default:
6c13d5d2 455 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 456 return -EINVAL;
457 }
458
459 return 0;
460}
461
23241d43
PM		 462static void sci_port_enable(struct sci_port *sci_port)
463{
464 if (!sci_port->port.dev)
465 return;
466
467 pm_runtime_get_sync(sci_port->port.dev);
468
b016b646 469 clk_prepare_enable(sci_port->iclk);
23241d43 470 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 471 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 472}
473
474static void sci_port_disable(struct sci_port *sci_port)
475{
476 if (!sci_port->port.dev)
477 return;
478
caec7038
LP		 479 /* Cancel the break timer to ensure that the timer handler will not try
480 * to access the hardware with clocks and power disabled. Reset the
481 * break flag to make the break debouncing state machine ready for the
482 * next break.
483 */
484 del_timer_sync(&sci_port->break_timer);
485 sci_port->break_flag = 0;
486
b016b646
LP		 487 clk_disable_unprepare(sci_port->fclk);
488 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 489
490 pm_runtime_put_sync(sci_port->port.dev);
491}
492
a1b5b43f
GU		 493static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
494{
495 if (port->type == PORT_SCI) {
496 /* Just store the mask */
497 serial_port_out(port, SCxSR, mask);
498 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
499 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
500 /* Only clear the status bits we want to clear */
501 serial_port_out(port, SCxSR,
502 serial_port_in(port, SCxSR) & mask);
503 } else {
504 /* Store the mask, clear parity/framing errors */
505 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
506 }
507}
508
07d2a1a1 509#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 510
511#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 512static int sci_poll_get_char(struct uart_port *port)
1da177e4 513{
1da177e4
LT		 514 unsigned short status;
515 int c;
516
e108b2ca 517 do {
b12bb29f 518 status = serial_port_in(port, SCxSR);
1da177e4 519 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 520 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 521 continue;
522 }
3f255eb3
JW		 523 break;
524 } while (1);
525
526 if (!(status & SCxSR_RDxF(port)))
527 return NO_POLL_CHAR;
07d2a1a1 528
b12bb29f 529 c = serial_port_in(port, SCxRDR);
07d2a1a1 530
e7c98dc7 531 /* Dummy read */
b12bb29f 532 serial_port_in(port, SCxSR);
a1b5b43f 533 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 534
535 return c;
536}
1f6fd5c9 537#endif
1da177e4 538
07d2a1a1 539static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 540{
1da177e4
LT		 541 unsigned short status;
542
1da177e4 543 do {
b12bb29f 544 status = serial_port_in(port, SCxSR);
1da177e4
LT		 545 } while (!(status & SCxSR_TDxE(port)));
546
b12bb29f 547 serial_port_out(port, SCxTDR, c);
a1b5b43f 548 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 549}
07d2a1a1 550#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 551
61a6976b 552static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 553{
61a6976b 554 struct sci_port *s = to_sci_port(port);
d3184e68 555 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 556
61a6976b
PM		 557 /*
558 * Use port-specific handler if provided.
559 */
560 if (s->cfg->ops && s->cfg->ops->init_pins) {
561 s->cfg->ops->init_pins(port, cflag);
562 return;
1da177e4 563 }
41504c39 564
61a6976b
PM		 565 /*
566 * For the generic path SCSPTR is necessary. Bail out if that's
567 * unavailable, too.
568 */
569 if (!reg->size)
570 return;
41504c39 571
faf02f8f
PM		 572 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
573 ((!(cflag & CRTSCTS)))) {
574 unsigned short status;
575
b12bb29f 576 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 577 status &= ~SCSPTR_CTSIO;
578 status |= SCSPTR_RTSIO;
b12bb29f 579 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 580 }
d5701647 581}
e108b2ca 582
72b294cf 583static int sci_txfill(struct uart_port *port)
e108b2ca 584{
d3184e68 585 const struct plat_sci_reg *reg;
e108b2ca 586
72b294cf
PM		 587 reg = sci_getreg(port, SCTFDR);
588 if (reg->size)
63f7ad11 589 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 590
72b294cf
PM		 591 reg = sci_getreg(port, SCFDR);
592 if (reg->size)
b12bb29f 593 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 594
b12bb29f 595 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 596}
597
73a19e4c
GL		 598static int sci_txroom(struct uart_port *port)
599{
72b294cf 600 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 601}
602
603static int sci_rxfill(struct uart_port *port)
e108b2ca 604{
d3184e68 605 const struct plat_sci_reg *reg;
72b294cf
PM		 606
607 reg = sci_getreg(port, SCRFDR);
608 if (reg->size)
63f7ad11 609 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 610
611 reg = sci_getreg(port, SCFDR);
612 if (reg->size)
b12bb29f 613 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 614
b12bb29f 615 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 616}
617
514820eb
PM		 618/*
619 * SCI helper for checking the state of the muxed port/RXD pins.
620 */
621static inline int sci_rxd_in(struct uart_port *port)
622{
623 struct sci_port *s = to_sci_port(port);
624
625 if (s->cfg->port_reg <= 0)
626 return 1;
627
0dd4d5cb 628 /* Cast for ARM damage */
e2afca69 629 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 630}
631
1da177e4
LT		 632/* ********************************************************************** *
633 * the interrupt related routines *
634 * ********************************************************************** */
635
636static void sci_transmit_chars(struct uart_port *port)
637{
ebd2c8f6 638 struct circ_buf *xmit = &port->state->xmit;
1da177e4 639 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 640 unsigned short status;
641 unsigned short ctrl;
e108b2ca 642 int count;
1da177e4 643
b12bb29f 644 status = serial_port_in(port, SCxSR);
1da177e4 645 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 646 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 647 if (uart_circ_empty(xmit))
8e698614 648 ctrl &= ~SCSCR_TIE;
e7c98dc7 649 else
8e698614 650 ctrl |= SCSCR_TIE;
b12bb29f 651 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 652 return;
653 }
654
72b294cf 655 count = sci_txroom(port);
1da177e4
LT		 656
657 do {
658 unsigned char c;
659
660 if (port->x_char) {
661 c = port->x_char;
662 port->x_char = 0;
663 } else if (!uart_circ_empty(xmit) && !stopped) {
664 c = xmit->buf[xmit->tail];
665 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
666 } else {
667 break;
668 }
669
b12bb29f 670 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 671
672 port->icount.tx++;
673 } while (--count > 0);
674
a1b5b43f 675 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 676
677 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
678 uart_write_wakeup(port);
679 if (uart_circ_empty(xmit)) {
b129a8cc 680 sci_stop_tx(port);
1da177e4 681 } else {
b12bb29f 682 ctrl = serial_port_in(port, SCSCR);
1da177e4 683
1a22f08d 684 if (port->type != PORT_SCI) {
b12bb29f 685 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 686 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 687 }
1da177e4 688
8e698614 689 ctrl |= SCSCR_TIE;
b12bb29f 690 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 691 }
692}
693
694/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 695#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 696
94c8b6db 697static void sci_receive_chars(struct uart_port *port)
1da177e4 698{
e7c98dc7 699 struct sci_port *sci_port = to_sci_port(port);
227434f8 700 struct tty_port *tport = &port->state->port;
1da177e4
LT		 701 int i, count, copied = 0;
702 unsigned short status;
33f0f88f 703 unsigned char flag;
1da177e4 704
b12bb29f 705 status = serial_port_in(port, SCxSR);
1da177e4
LT		 706 if (!(status & SCxSR_RDxF(port)))
707 return;
708
709 while (1) {
1da177e4 710 /* Don't copy more bytes than there is room for in the buffer */
227434f8 711 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 712
713 /* If for any reason we can't copy more data, we're done! */
714 if (count == 0)
715 break;
716
717 if (port->type == PORT_SCI) {
b12bb29f 718 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 719 if (uart_handle_sysrq_char(port, c) ||
720 sci_port->break_flag)
1da177e4 721 count = 0;
e7c98dc7 722 else
92a19f9c 723 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 724 } else {
e7c98dc7 725 for (i = 0; i < count; i++) {
b12bb29f 726 char c = serial_port_in(port, SCxRDR);
d97fbbed 727
b12bb29f 728 status = serial_port_in(port, SCxSR);
1da177e4
LT		 729#if defined(CONFIG_CPU_SH3)
730 /* Skip "chars" during break */
e108b2ca 731 if (sci_port->break_flag) {
1da177e4
LT		 732 if ((c == 0) &&
733 (status & SCxSR_FER(port))) {
734 count--; i--;
735 continue;
736 }
e108b2ca 737
1da177e4 738 /* Nonzero => end-of-break */
762c69e3 739 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 740 sci_port->break_flag = 0;
741
1da177e4
LT		 742 if (STEPFN(c)) {
743 count--; i--;
744 continue;
745 }
746 }
747#endif /* CONFIG_CPU_SH3 */
7d12e780 748 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 749 count--; i--;
750 continue;
751 }
752
753 /* Store data and status */
73a19e4c 754 if (status & SCxSR_FER(port)) {
33f0f88f 755 flag = TTY_FRAME;
d97fbbed 756 port->icount.frame++;
762c69e3 757 dev_notice(port->dev, "frame error\n");
73a19e4c 758 } else if (status & SCxSR_PER(port)) {
33f0f88f 759 flag = TTY_PARITY;
d97fbbed 760 port->icount.parity++;
762c69e3 761 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 762 } else
763 flag = TTY_NORMAL;
762c69e3 764
92a19f9c 765 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 766 }
767 }
768
b12bb29f 769 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 770 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 771
1da177e4
LT		 772 copied += count;
773 port->icount.rx += count;
774 }
775
776 if (copied) {
777 /* Tell the rest of the system the news. New characters! */
2e124b4a 778 tty_flip_buffer_push(tport);
1da177e4 779 } else {
b12bb29f 780 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 781 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 782 }
783}
784
785#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 786
787/*
788 * The sci generates interrupts during the break,
1da177e4
LT		 789 * 1 per millisecond or so during the break period, for 9600 baud.
790 * So dont bother disabling interrupts.
791 * But dont want more than 1 break event.
792 * Use a kernel timer to periodically poll the rx line until
793 * the break is finished.
794 */
94c8b6db 795static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 796{
bc9b3f5c 797 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 798}
94c8b6db 799
1da177e4
LT		 800/* Ensure that two consecutive samples find the break over. */
801static void sci_break_timer(unsigned long data)
802{
e108b2ca
PM		 803 struct sci_port *port = (struct sci_port *)data;
804
805 if (sci_rxd_in(&port->port) == 0) {
1da177e4 806 port->break_flag = 1;
e108b2ca
PM		 807 sci_schedule_break_timer(port);
808 } else if (port->break_flag == 1) {
1da177e4
LT		 809 /* break is over. */
810 port->break_flag = 2;
e108b2ca
PM		 811 sci_schedule_break_timer(port);
812 } else
813 port->break_flag = 0;
1da177e4
LT		 814}
815
94c8b6db 816static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 817{
818 int copied = 0;
b12bb29f 819 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 820 struct tty_port *tport = &port->state->port;
debf9507 821 struct sci_port *s = to_sci_port(port);
1da177e4 822
3ae988d9 823 /* Handle overruns */
75c249fd 824 if (status & s->overrun_mask) {
3ae988d9 825 port->icount.overrun++;
d97fbbed 826
3ae988d9
LP		 827 /* overrun error */
828 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
829 copied++;
762c69e3 830
9b971cd2 831 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 832 }
833
e108b2ca 834 if (status & SCxSR_FER(port)) {
1da177e4
LT		 835 if (sci_rxd_in(port) == 0) {
836 /* Notify of BREAK */
e7c98dc7 837 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 838
839 if (!sci_port->break_flag) {
d97fbbed
PM		 840 port->icount.brk++;
841
e108b2ca
PM		 842 sci_port->break_flag = 1;
843 sci_schedule_break_timer(sci_port);
844
1da177e4 845 /* Do sysrq handling. */
e108b2ca 846 if (uart_handle_break(port))
1da177e4 847 return 0;
762c69e3
PM		 848
849 dev_dbg(port->dev, "BREAK detected\n");
850
92a19f9c 851 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 852 copied++;
853 }
854
e108b2ca 855 } else {
1da177e4 856 /* frame error */
d97fbbed
PM		 857 port->icount.frame++;
858
92a19f9c 859 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 860 copied++;
762c69e3
PM		 861
862 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 863 }
864 }
865
e108b2ca 866 if (status & SCxSR_PER(port)) {
1da177e4 867 /* parity error */
d97fbbed
PM		 868 port->icount.parity++;
869
92a19f9c 870 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 871 copied++;
762c69e3 872
9b971cd2 873 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 874 }
875
33f0f88f 876 if (copied)
2e124b4a 877 tty_flip_buffer_push(tport);
1da177e4
LT		 878
879 return copied;
880}
881
94c8b6db 882static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 883{
92a19f9c 884 struct tty_port *tport = &port->state->port;
debf9507 885 struct sci_port *s = to_sci_port(port);
d3184e68 886 const struct plat_sci_reg *reg;
2e0842a1 887 int copied = 0;
75c249fd 888 u16 status;
d830fa45 889
2e0842a1 890 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 891 if (!reg->size)
d830fa45
PM		 892 return 0;
893
2e0842a1 894 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 895 if (status & s->overrun_mask) {
896 status &= ~s->overrun_mask;
2e0842a1 897 serial_port_out(port, s->overrun_reg, status);
d830fa45 898
d97fbbed
PM		 899 port->icount.overrun++;
900
92a19f9c 901 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 902 tty_flip_buffer_push(tport);
d830fa45 903
51b31f1c 904 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 905 copied++;
906 }
907
908 return copied;
909}
910
94c8b6db 911static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 912{
913 int copied = 0;
b12bb29f 914 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 915 struct tty_port *tport = &port->state->port;
a5660ada 916 struct sci_port *s = to_sci_port(port);
1da177e4 917
0b3d4ef6
PM		 918 if (uart_handle_break(port))
919 return 0;
920
b7a76e4b 921 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 922#if defined(CONFIG_CPU_SH3)
923 /* Debounce break */
924 s->break_flag = 1;
925#endif
d97fbbed
PM		 926
927 port->icount.brk++;
928
1da177e4 929 /* Notify of BREAK */
92a19f9c 930 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 931 copied++;
762c69e3
PM		 932
933 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 934 }
935
33f0f88f 936 if (copied)
2e124b4a 937 tty_flip_buffer_push(tport);
e108b2ca 938
d830fa45
PM		 939 copied += sci_handle_fifo_overrun(port);
940
1da177e4
LT		 941 return copied;
942}
943
73a19e4c 944static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 945{
73a19e4c
GL		 946#ifdef CONFIG_SERIAL_SH_SCI_DMA
947 struct uart_port *port = ptr;
948 struct sci_port *s = to_sci_port(port);
949
950 if (s->chan_rx) {
b12bb29f
PM		 951 u16 scr = serial_port_in(port, SCSCR);
952 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 953
954 /* Disable future Rx interrupts */
d1d4b10c 955 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 956 disable_irq_nosync(irq);
26de4f1b 957 scr |= SCSCR_RDRQE;
3089f381 958 } else {
f43dc23d 959 scr &= ~SCSCR_RIE;
3089f381 960 }
b12bb29f 961 serial_port_out(port, SCSCR, scr);
73a19e4c 962 /* Clear current interrupt */
54af5001
GU		 963 serial_port_out(port, SCxSR,
964 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
3089f381
GL		 965 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
966 jiffies, s->rx_timeout);
967 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 968
969 return IRQ_HANDLED;
970 }
971#endif
972
1da177e4
LT		 973 /* I think sci_receive_chars has to be called irrespective
974 * of whether the I_IXOFF is set, otherwise, how is the interrupt
975 * to be disabled?
976 */
73a19e4c 977 sci_receive_chars(ptr);
1da177e4
LT		 978
979 return IRQ_HANDLED;
980}
981
7d12e780 982static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 983{
984 struct uart_port *port = ptr;
fd78a76a 985 unsigned long flags;
1da177e4 986
fd78a76a 987 spin_lock_irqsave(&port->lock, flags);
1da177e4 988 sci_transmit_chars(port);
fd78a76a 989 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 990
991 return IRQ_HANDLED;
992}
993
7d12e780 994static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 995{
996 struct uart_port *port = ptr;
997
998 /* Handle errors */
999 if (port->type == PORT_SCI) {
1000 if (sci_handle_errors(port)) {
1001 /* discard character in rx buffer */
b12bb29f 1002 serial_port_in(port, SCxSR);
a1b5b43f 1003 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 1004 }
1005 } else {
d830fa45 1006 sci_handle_fifo_overrun(port);
7d12e780 1007 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 1008 }
1009
a1b5b43f 1010 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 1011
1012 /* Kick the transmission */
7d12e780 1013 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 1014
1015 return IRQ_HANDLED;
1016}
1017
7d12e780 1018static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 1019{
1020 struct uart_port *port = ptr;
1021
1022 /* Handle BREAKs */
1023 sci_handle_breaks(port);
a1b5b43f 1024 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 1025
1026 return IRQ_HANDLED;
1027}
1028
f43dc23d
PM		 1029static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1030{
1031 /*
1032 * Not all ports (such as SCIFA) will support REIE. Rather than
1033 * special-casing the port type, we check the port initialization
1034 * IRQ enable mask to see whether the IRQ is desired at all. If
1035 * it's unset, it's logically inferred that there's no point in
1036 * testing for it.
1037 */
ce6738b6 1038 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 1039}
1040
7d12e780 1041static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 1042{
cb772fe7 1043 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
a8884e34 1044 struct uart_port *port = ptr;
73a19e4c 1045 struct sci_port *s = to_sci_port(port);
a8884e34 1046 irqreturn_t ret = IRQ_NONE;
1da177e4 1047
b12bb29f
PM		 1048 ssr_status = serial_port_in(port, SCxSR);
1049 scr_status = serial_port_in(port, SCSCR);
2e0842a1 1050 if (s->overrun_reg == SCxSR)
cb772fe7 1051 orer_status = ssr_status;
2e0842a1
GU		 1052 else {
1053 if (sci_getreg(port, s->overrun_reg)->size)
1054 orer_status = serial_port_in(port, s->overrun_reg);
cb772fe7
NI		 1055 }
1056
f43dc23d 1057 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 1058
1059 /* Tx Interrupt */
f43dc23d 1060 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 1061 !s->chan_tx)
a8884e34 1062 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 1063
73a19e4c
GL		 1064 /*
1065 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1066 * DR flags
1067 */
1068 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
e0a12a27 1069 (scr_status & SCSCR_RIE))
a8884e34 1070 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1071
1da177e4 1072 /* Error Interrupt */
dd4da3a5 1073 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1074 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1075
1da177e4 1076 /* Break Interrupt */
dd4da3a5 1077 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1078 ret = sci_br_interrupt(irq, ptr);
1da177e4 1079
8b6ff84c 1080 /* Overrun Interrupt */
90803072 1081 if (orer_status & s->overrun_mask) {
cb772fe7 1082 sci_handle_fifo_overrun(port);
90803072
YS		 1083 ret = IRQ_HANDLED;
1084 }
8b6ff84c 1085
a8884e34 1086 return ret;
1da177e4
LT		 1087}
1088
1da177e4 1089/*
25985edc 1090 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1091 * ports' baud rate when the peripheral clock changes.
1092 */
e108b2ca
PM		 1093static int sci_notifier(struct notifier_block *self,
1094 unsigned long phase, void *p)
1da177e4 1095{
e552de24
MD		 1096 struct sci_port *sci_port;
1097 unsigned long flags;
1da177e4 1098
d535a230
PM		 1099 sci_port = container_of(self, struct sci_port, freq_transition);
1100
0b443ead 1101 if (phase == CPUFREQ_POSTCHANGE) {
d535a230 1102 struct uart_port *port = &sci_port->port;
073e84c9 1103
d535a230
PM		 1104 spin_lock_irqsave(&port->lock, flags);
1105 port->uartclk = clk_get_rate(sci_port->iclk);
1106 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1107 }
1da177e4 1108
1da177e4
LT		 1109 return NOTIFY_OK;
1110}
501b825d 1111
d56a91e8 1112static const struct sci_irq_desc {
9174fc8f
PM		 1113 const char *desc;
1114 irq_handler_t handler;
1115} sci_irq_desc[] = {
1116 /*
1117 * Split out handlers, the default case.
1118 */
1119 [SCIx_ERI_IRQ] = {
1120 .desc = "rx err",
1121 .handler = sci_er_interrupt,
1122 },
1123
1124 [SCIx_RXI_IRQ] = {
1125 .desc = "rx full",
1126 .handler = sci_rx_interrupt,
1127 },
1128
1129 [SCIx_TXI_IRQ] = {
1130 .desc = "tx empty",
1131 .handler = sci_tx_interrupt,
1132 },
1133
1134 [SCIx_BRI_IRQ] = {
1135 .desc = "break",
1136 .handler = sci_br_interrupt,
1137 },
1138
1139 /*
1140 * Special muxed handler.
1141 */
1142 [SCIx_MUX_IRQ] = {
1143 .desc = "mux",
1144 .handler = sci_mpxed_interrupt,
1145 },
1146};
1147
1da177e4
LT		 1148static int sci_request_irq(struct sci_port *port)
1149{
9174fc8f
PM		 1150 struct uart_port *up = &port->port;
1151 int i, j, ret = 0;
1152
1153 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
d56a91e8 1154 const struct sci_irq_desc *desc;
1fcc91a6 1155 int irq;
9174fc8f
PM		 1156
1157 if (SCIx_IRQ_IS_MUXED(port)) {
1158 i = SCIx_MUX_IRQ;
1159 irq = up->irq;
0e8963de 1160 } else {
1fcc91a6 1161 irq = port->irqs[i];
9174fc8f 1162
0e8963de
PM		 1163 /*
1164 * Certain port types won't support all of the
1165 * available interrupt sources.
1166 */
1fcc91a6 1167 if (unlikely(irq < 0))
0e8963de
PM		 1168 continue;
1169 }
1170
9174fc8f
PM		 1171 desc = sci_irq_desc + i;
1172 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1173 dev_name(up->dev), desc->desc);
4205463c 1174 if (!port->irqstr[j])
9174fc8f 1175 goto out_nomem;
9174fc8f
PM		 1176
1177 ret = request_irq(irq, desc->handler, up->irqflags,
1178 port->irqstr[j], port);
1179 if (unlikely(ret)) {
1180 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1181 goto out_noirq;
1da177e4
LT		 1182 }
1183 }
1184
1185 return 0;
9174fc8f
PM		 1186
1187out_noirq:
1188 while (--i >= 0)
1fcc91a6 1189 free_irq(port->irqs[i], port);
9174fc8f
PM		 1190
1191out_nomem:
1192 while (--j >= 0)
1193 kfree(port->irqstr[j]);
1194
1195 return ret;
1da177e4
LT		 1196}
1197
1198static void sci_free_irq(struct sci_port *port)
1199{
1200 int i;
1201
9174fc8f
PM		 1202 /*
1203 * Intentionally in reverse order so we iterate over the muxed
1204 * IRQ first.
1205 */
1206 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1207 int irq = port->irqs[i];
0e8963de
PM		 1208
1209 /*
1210 * Certain port types won't support all of the available
1211 * interrupt sources.
1212 */
1fcc91a6 1213 if (unlikely(irq < 0))
0e8963de
PM		 1214 continue;
1215
1fcc91a6 1216 free_irq(port->irqs[i], port);
9174fc8f 1217 kfree(port->irqstr[i]);
1da177e4 1218
9174fc8f
PM		 1219 if (SCIx_IRQ_IS_MUXED(port)) {
1220 /* If there's only one IRQ, we're done. */
1221 return;
1da177e4
LT		 1222 }
1223 }
1224}
1225
1226static unsigned int sci_tx_empty(struct uart_port *port)
1227{
b12bb29f 1228 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1229 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1230
1231 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1232}
1233
cdf7c42f
PM		 1234/*
1235 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1236 * CTS/RTS is supported in hardware by at least one port and controlled
1237 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1238 * handled via the ->init_pins() op, which is a bit of a one-way street,
1239 * lacking any ability to defer pin control -- this will later be
1240 * converted over to the GPIO framework).
dc7e3ef7
PM		 1241 *
1242 * Other modes (such as loopback) are supported generically on certain
1243 * port types, but not others. For these it's sufficient to test for the
1244 * existence of the support register and simply ignore the port type.
cdf7c42f 1245 */
1da177e4
LT		 1246static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1247{
dc7e3ef7 1248 if (mctrl & TIOCM_LOOP) {
d3184e68 1249 const struct plat_sci_reg *reg;
dc7e3ef7
PM		 1250
1251 /*
1252 * Standard loopback mode for SCFCR ports.
1253 */
1254 reg = sci_getreg(port, SCFCR);
1255 if (reg->size)
26de4f1b
GU		 1256 serial_port_out(port, SCFCR,
1257 serial_port_in(port, SCFCR) |
1258 SCFCR_LOOP);
dc7e3ef7 1259 }
1da177e4
LT		 1260}
1261
1262static unsigned int sci_get_mctrl(struct uart_port *port)
1263{
cdf7c42f
PM		 1264 /*
1265 * CTS/RTS is handled in hardware when supported, while nothing
1266 * else is wired up. Keep it simple and simply assert DSR/CAR.
1267 */
1268 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1269}
1270
73a19e4c
GL		 1271#ifdef CONFIG_SERIAL_SH_SCI_DMA
1272static void sci_dma_tx_complete(void *arg)
1273{
1274 struct sci_port *s = arg;
1275 struct uart_port *port = &s->port;
1276 struct circ_buf *xmit = &port->state->xmit;
1277 unsigned long flags;
1278
1279 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1280
1281 spin_lock_irqsave(&port->lock, flags);
1282
79904420 1283 xmit->tail += s->tx_dma_len;
73a19e4c
GL		 1284 xmit->tail &= UART_XMIT_SIZE - 1;
1285
79904420 1286 port->icount.tx += s->tx_dma_len;
73a19e4c
GL		 1287
1288 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1289 s->desc_tx = NULL;
1290
73a19e4c
GL		 1291 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1292 uart_write_wakeup(port);
1293
3089f381 1294 if (!uart_circ_empty(xmit)) {
49d4bcad 1295 s->cookie_tx = 0;
73a19e4c 1296 schedule_work(&s->work_tx);
49d4bcad
YT		 1297 } else {
1298 s->cookie_tx = -EINVAL;
1299 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1300 u16 ctrl = serial_port_in(port, SCSCR);
1301 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1302 }
3089f381
GL		 1303 }
1304
1305 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1306}
1307
1308/* Locking: called with port lock held */
92a19f9c 1309static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1310{
1311 struct uart_port *port = &s->port;
227434f8 1312 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1313 int i, active, room;
1314
227434f8 1315 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1316
1317 if (s->active_rx == s->cookie_rx[0]) {
1318 active = 0;
1319 } else if (s->active_rx == s->cookie_rx[1]) {
1320 active = 1;
1321 } else {
beb9487b
GU		 1322 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1323 s->active_rx);
73a19e4c
GL		 1324 return 0;
1325 }
1326
1327 if (room < count)
e2afca69 1328 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1329 count - room);
1330 if (!room)
1331 return room;
1332
1333 for (i = 0; i < room; i++)
92a19f9c 1334 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1335 TTY_NORMAL);
1336
1337 port->icount.rx += room;
1338
1339 return room;
1340}
1341
1342static void sci_dma_rx_complete(void *arg)
1343{
1344 struct sci_port *s = arg;
1345 struct uart_port *port = &s->port;
73a19e4c
GL		 1346 unsigned long flags;
1347 int count;
1348
beb9487b
GU		 1349 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1350 s->active_rx);
73a19e4c
GL		 1351
1352 spin_lock_irqsave(&port->lock, flags);
1353
92a19f9c 1354 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1355
3089f381 1356 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1357
1358 spin_unlock_irqrestore(&port->lock, flags);
1359
1360 if (count)
2e124b4a 1361 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1362
1363 schedule_work(&s->work_rx);
1364}
1365
73a19e4c
GL		 1366static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1367{
1368 struct dma_chan *chan = s->chan_rx;
1369 struct uart_port *port = &s->port;
73a19e4c
GL		 1370
1371 s->chan_rx = NULL;
1372 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
8e14ba8f 1373 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2,
b9258020 1374 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
8e14ba8f 1375 dma_release_channel(chan);
73a19e4c
GL		 1376 if (enable_pio)
1377 sci_start_rx(port);
1378}
1379
1380static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1381{
1382 struct dma_chan *chan = s->chan_tx;
1383 struct uart_port *port = &s->port;
73a19e4c
GL		 1384
1385 s->chan_tx = NULL;
1386 s->cookie_tx = -EINVAL;
2e301474
GU		 1387 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1388 DMA_TO_DEVICE);
73a19e4c
GL		 1389 dma_release_channel(chan);
1390 if (enable_pio)
1391 sci_start_tx(port);
1392}
1393
1394static void sci_submit_rx(struct sci_port *s)
1395{
1396 struct dma_chan *chan = s->chan_rx;
1397 int i;
1398
1399 for (i = 0; i < 2; i++) {
1400 struct scatterlist *sg = &s->sg_rx[i];
1401 struct dma_async_tx_descriptor *desc;
1402
16052827 1403 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1404 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1405
1406 if (desc) {
1407 s->desc_rx[i] = desc;
1408 desc->callback = sci_dma_rx_complete;
1409 desc->callback_param = s;
1410 s->cookie_rx[i] = desc->tx_submit(desc);
1411 }
1412
1413 if (!desc || s->cookie_rx[i] < 0) {
1414 if (i) {
1415 async_tx_ack(s->desc_rx[0]);
1416 s->cookie_rx[0] = -EINVAL;
1417 }
1418 if (desc) {
1419 async_tx_ack(desc);
1420 s->cookie_rx[i] = -EINVAL;
1421 }
1422 dev_warn(s->port.dev,
beb9487b 1423 "Failed to re-start Rx DMA, using PIO\n");
73a19e4c
GL		 1424 sci_rx_dma_release(s, true);
1425 return;
1426 }
beb9487b
GU		 1427 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1428 s->cookie_rx[i], i);
73a19e4c
GL		 1429 }
1430
1431 s->active_rx = s->cookie_rx[0];
1432
1433 dma_async_issue_pending(chan);
1434}
1435
1436static void work_fn_rx(struct work_struct *work)
1437{
1438 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1439 struct uart_port *port = &s->port;
1440 struct dma_async_tx_descriptor *desc;
1441 int new;
1442
1443 if (s->active_rx == s->cookie_rx[0]) {
1444 new = 0;
1445 } else if (s->active_rx == s->cookie_rx[1]) {
1446 new = 1;
1447 } else {
beb9487b
GU		 1448 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1449 s->active_rx);
73a19e4c
GL		 1450 return;
1451 }
1452 desc = s->desc_rx[new];
1453
1454 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1455 DMA_COMPLETE) {
73a19e4c 1456 /* Handle incomplete DMA receive */
73a19e4c 1457 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1458 struct shdma_desc *sh_desc = container_of(desc,
1459 struct shdma_desc, async_tx);
73a19e4c
GL		 1460 unsigned long flags;
1461 int count;
1462
2bcd90d5 1463 dmaengine_terminate_all(chan);
e2afca69 1464 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1465 sh_desc->partial, sh_desc->cookie);
1466
1467 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1468 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1469 spin_unlock_irqrestore(&port->lock, flags);
1470
1471 if (count)
2e124b4a 1472 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1473
1474 sci_submit_rx(s);
1475
1476 return;
1477 }
1478
1479 s->cookie_rx[new] = desc->tx_submit(desc);
1480 if (s->cookie_rx[new] < 0) {
1481 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1482 sci_rx_dma_release(s, true);
1483 return;
1484 }
1485
73a19e4c 1486 s->active_rx = s->cookie_rx[!new];
3089f381 1487
beb9487b 1488 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
9b971cd2 1489 __func__, s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1490}
1491
1492static void work_fn_tx(struct work_struct *work)
1493{
1494 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1495 struct dma_async_tx_descriptor *desc;
1496 struct dma_chan *chan = s->chan_tx;
1497 struct uart_port *port = &s->port;
1498 struct circ_buf *xmit = &port->state->xmit;
79904420 1499 dma_addr_t buf;
73a19e4c
GL		 1500
1501 /*
1502 * DMA is idle now.
1503 * Port xmit buffer is already mapped, and it is one page... Just adjust
1504 * offsets and lengths. Since it is a circular buffer, we have to
1505 * transmit till the end, and then the rest. Take the port lock to get a
1506 * consistent xmit buffer state.
1507 */
1508 spin_lock_irq(&port->lock);
79904420
GU		 1509 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1510 s->tx_dma_len = min_t(unsigned int,
092248aa 1511 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1512 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1513 spin_unlock_irq(&port->lock);
1514
79904420
GU		 1515 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1516 DMA_MEM_TO_DEV,
1517 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
73a19e4c 1518 if (!desc) {
beb9487b 1519 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
73a19e4c
GL		 1520 /* switch to PIO */
1521 sci_tx_dma_release(s, true);
1522 return;
1523 }
1524
79904420
GU		 1525 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1526 DMA_TO_DEVICE);
73a19e4c
GL		 1527
1528 spin_lock_irq(&port->lock);
1529 s->desc_tx = desc;
1530 desc->callback = sci_dma_tx_complete;
1531 desc->callback_param = s;
1532 spin_unlock_irq(&port->lock);
1533 s->cookie_tx = desc->tx_submit(desc);
1534 if (s->cookie_tx < 0) {
1535 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1536 /* switch to PIO */
1537 sci_tx_dma_release(s, true);
1538 return;
1539 }
1540
9b971cd2
JP		 1541 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1542 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c
GL		 1543
1544 dma_async_issue_pending(chan);
1545}
1546#endif
1547
b129a8cc 1548static void sci_start_tx(struct uart_port *port)
1da177e4 1549{
3089f381 1550 struct sci_port *s = to_sci_port(port);
e108b2ca 1551 unsigned short ctrl;
1da177e4 1552
73a19e4c 1553#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1554 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1555 u16 new, scr = serial_port_in(port, SCSCR);
3089f381 1556 if (s->chan_tx)
26de4f1b 1557 new = scr | SCSCR_TDRQE;
3089f381 1558 else
26de4f1b 1559 new = scr & ~SCSCR_TDRQE;
3089f381 1560 if (new != scr)
b12bb29f 1561 serial_port_out(port, SCSCR, new);
73a19e4c 1562 }
f43dc23d 1563
3089f381 1564 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1565 s->cookie_tx < 0) {
1566 s->cookie_tx = 0;
3089f381 1567 schedule_work(&s->work_tx);
49d4bcad 1568 }
73a19e4c 1569#endif
f43dc23d 1570
d1d4b10c 1571 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1572 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1573 ctrl = serial_port_in(port, SCSCR);
1574 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1575 }
1da177e4
LT		 1576}
1577
b129a8cc 1578static void sci_stop_tx(struct uart_port *port)
1da177e4 1579{
1da177e4
LT		 1580 unsigned short ctrl;
1581
1582 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1583 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1584
d1d4b10c 1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1586 ctrl &= ~SCSCR_TDRQE;
f43dc23d 1587
8e698614 1588 ctrl &= ~SCSCR_TIE;
f43dc23d 1589
b12bb29f 1590 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1591}
1592
73a19e4c 1593static void sci_start_rx(struct uart_port *port)
1da177e4 1594{
1da177e4
LT		 1595 unsigned short ctrl;
1596
b12bb29f 1597 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1598
d1d4b10c 1599 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1600 ctrl &= ~SCSCR_RDRQE;
f43dc23d 1601
b12bb29f 1602 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1603}
1604
1605static void sci_stop_rx(struct uart_port *port)
1606{
1da177e4
LT		 1607 unsigned short ctrl;
1608
b12bb29f 1609 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1610
d1d4b10c 1611 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1612 ctrl &= ~SCSCR_RDRQE;
f43dc23d
PM		 1613
1614 ctrl &= ~port_rx_irq_mask(port);
1615
b12bb29f 1616 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1617}
1618
1da177e4
LT		 1619static void sci_break_ctl(struct uart_port *port, int break_state)
1620{
bbb4ce50 1621 struct sci_port *s = to_sci_port(port);
d3184e68 1622 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1623 unsigned short scscr, scsptr;
1624
a4e02f6d
SY		 1625 /* check wheter the port has SCSPTR */
1626 if (!reg->size) {
bbb4ce50
SY		 1627 /*
1628 * Not supported by hardware. Most parts couple break and rx
1629 * interrupts together, with break detection always enabled.
1630 */
a4e02f6d 1631 return;
bbb4ce50 1632 }
a4e02f6d
SY		 1633
1634 scsptr = serial_port_in(port, SCSPTR);
1635 scscr = serial_port_in(port, SCSCR);
1636
1637 if (break_state == -1) {
1638 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1639 scscr &= ~SCSCR_TE;
1640 } else {
1641 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1642 scscr |= SCSCR_TE;
1643 }
1644
1645 serial_port_out(port, SCSPTR, scsptr);
1646 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1647}
1648
73a19e4c
GL		 1649#ifdef CONFIG_SERIAL_SH_SCI_DMA
1650static bool filter(struct dma_chan *chan, void *slave)
1651{
1652 struct sh_dmae_slave *param = slave;
1653
9b971cd2
JP		 1654 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1655 __func__, param->shdma_slave.slave_id);
73a19e4c 1656
d6fa5a4e 1657 chan->private = &param->shdma_slave;
937bb6e4 1658 return true;
73a19e4c
GL		 1659}
1660
1661static void rx_timer_fn(unsigned long arg)
1662{
1663 struct sci_port *s = (struct sci_port *)arg;
1664 struct uart_port *port = &s->port;
b12bb29f 1665 u16 scr = serial_port_in(port, SCSCR);
3089f381 1666
d1d4b10c 1667 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
26de4f1b 1668 scr &= ~SCSCR_RDRQE;
1fcc91a6 1669 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1670 }
b12bb29f 1671 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1672 dev_dbg(port->dev, "DMA Rx timed out\n");
1673 schedule_work(&s->work_rx);
1674}
1675
1676static void sci_request_dma(struct uart_port *port)
1677{
1678 struct sci_port *s = to_sci_port(port);
1679 struct sh_dmae_slave *param;
1680 struct dma_chan *chan;
1681 dma_cap_mask_t mask;
73a19e4c 1682
9b971cd2 1683 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1684
937bb6e4 1685 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1686 return;
1687
1688 dma_cap_zero(mask);
1689 dma_cap_set(DMA_SLAVE, mask);
1690
1691 param = &s->param_tx;
1692
1693 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1694 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1695
1696 s->cookie_tx = -EINVAL;
1697 chan = dma_request_channel(mask, filter, param);
1698 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1699 if (chan) {
1700 s->chan_tx = chan;
73a19e4c 1701 /* UART circular tx buffer is an aligned page. */
79904420
GU		 1702 s->tx_dma_addr = dma_map_single(chan->device->dev,
1703 port->state->xmit.buf,
1704 UART_XMIT_SIZE,
1705 DMA_TO_DEVICE);
1706 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
beb9487b 1707 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
b9258020
GU		 1708 dma_release_channel(chan);
1709 s->chan_tx = NULL;
beb9487b 1710 } else {
79904420
GU		 1711 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1712 __func__, UART_XMIT_SIZE,
1713 port->state->xmit.buf, &s->tx_dma_addr);
beb9487b 1714 }
73a19e4c 1715
73a19e4c
GL		 1716 INIT_WORK(&s->work_tx, work_fn_tx);
1717 }
1718
1719 param = &s->param_rx;
1720
1721 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1722 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1723
1724 chan = dma_request_channel(mask, filter, param);
1725 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1726 if (chan) {
1727 dma_addr_t dma[2];
1728 void *buf[2];
1729 int i;
1730
1731 s->chan_rx = chan;
1732
092248aa 1733 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
8e14ba8f
GU		 1734 buf[0] = dma_alloc_coherent(chan->device->dev,
1735 s->buf_len_rx * 2, &dma[0],
1736 GFP_KERNEL);
73a19e4c
GL		 1737
1738 if (!buf[0]) {
1739 dev_warn(port->dev,
beb9487b 1740 "Failed to allocate Rx dma buffer, using PIO\n");
b9258020
GU		 1741 dma_release_channel(chan);
1742 s->chan_rx = NULL;
1743 sci_start_rx(port);
73a19e4c
GL		 1744 return;
1745 }
1746
1747 buf[1] = buf[0] + s->buf_len_rx;
1748 dma[1] = dma[0] + s->buf_len_rx;
1749
1750 for (i = 0; i < 2; i++) {
1751 struct scatterlist *sg = &s->sg_rx[i];
1752
1753 sg_init_table(sg, 1);
1754 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1755 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1756 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1757 }
1758
1759 INIT_WORK(&s->work_rx, work_fn_rx);
1760 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1761
1762 sci_submit_rx(s);
1763 }
1764}
1765
1766static void sci_free_dma(struct uart_port *port)
1767{
1768 struct sci_port *s = to_sci_port(port);
1769
73a19e4c
GL		 1770 if (s->chan_tx)
1771 sci_tx_dma_release(s, false);
1772 if (s->chan_rx)
1773 sci_rx_dma_release(s, false);
1774}
27bd1075
PM		 1775#else
1776static inline void sci_request_dma(struct uart_port *port)
1777{
1778}
1779
1780static inline void sci_free_dma(struct uart_port *port)
1781{
1782}
73a19e4c
GL		 1783#endif
1784
1da177e4
LT		 1785static int sci_startup(struct uart_port *port)
1786{
a5660ada 1787 struct sci_port *s = to_sci_port(port);
33b48e16 1788 unsigned long flags;
073e84c9 1789 int ret;
1da177e4 1790
73a19e4c
GL		 1791 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1792
073e84c9
PM		 1793 ret = sci_request_irq(s);
1794 if (unlikely(ret < 0))
1795 return ret;
1796
73a19e4c 1797 sci_request_dma(port);
073e84c9 1798
33b48e16 1799 spin_lock_irqsave(&port->lock, flags);
d656901b 1800 sci_start_tx(port);
73a19e4c 1801 sci_start_rx(port);
33b48e16 1802 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1803
1804 return 0;
1805}
1806
1807static void sci_shutdown(struct uart_port *port)
1808{
a5660ada 1809 struct sci_port *s = to_sci_port(port);
33b48e16 1810 unsigned long flags;
1da177e4 1811
73a19e4c
GL		 1812 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1813
33b48e16 1814 spin_lock_irqsave(&port->lock, flags);
1da177e4 1815 sci_stop_rx(port);
b129a8cc 1816 sci_stop_tx(port);
33b48e16 1817 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1818
73a19e4c 1819 sci_free_dma(port);
1da177e4 1820 sci_free_irq(s);
1da177e4
LT		 1821}
1822
ec09c5eb 1823static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1824 unsigned long freq)
1825{
ec09c5eb
LP		 1826 if (s->sampling_rate)
1827 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1828
26c92f37
PM		 1829 /* Warn, but use a safe default */
1830 WARN_ON(1);
e8183a6c 1831
26c92f37
PM		 1832 return ((freq + 16 * bps) / (32 * bps) - 1);
1833}
1834
730c4e78
NI		 1835/* calculate frame length from SMR */
1836static int sci_baud_calc_frame_len(unsigned int smr_val)
1837{
1838 int len = 10;
1839
1840 if (smr_val & SCSMR_CHR)
1841 len--;
1842 if (smr_val & SCSMR_PE)
1843 len++;
1844 if (smr_val & SCSMR_STOP)
1845 len++;
1846
1847 return len;
1848}
1849
1850
f303b364
UH		 1851/* calculate sample rate, BRR, and clock select for HSCIF */
1852static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1853 int *brr, unsigned int *srr,
730c4e78 1854 unsigned int *cks, int frame_len)
f303b364 1855{
730c4e78 1856 int sr, c, br, err, recv_margin;
f303b364 1857 int min_err = 1000; /* 100% */
730c4e78 1858 int recv_max_margin = 0;
f303b364
UH		 1859
1860 /* Find the combination of sample rate and clock select with the
1861 smallest deviation from the desired baud rate. */
1862 for (sr = 8; sr <= 32; sr++) {
1863 for (c = 0; c <= 3; c++) {
1864 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1865 br = DIV_ROUND_CLOSEST(freq, (sr *
1866 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1867 br = clamp(br, 0, 255);
b7d66397
NI		 1868 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1869 (1 << (2 * c + 1)) / 1000)) -
1870 1000;
730c4e78
NI		 1871 /* Calc recv margin
1872 * M: Receive margin (%)
1873 * N: Ratio of bit rate to clock (N = sampling rate)
1874 * D: Clock duty (D = 0 to 1.0)
1875 * L: Frame length (L = 9 to 12)
1876 * F: Absolute value of clock frequency deviation
1877 *
1878 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1879 * (|D - 0.5| / N * (1 + F))|
1880 * NOTE: Usually, treat D for 0.5, F is 0 by this
1881 * calculation.
1882 */
1883 recv_margin = abs((500 -
1884 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1885 if (abs(min_err) > abs(err)) {
f303b364 1886 min_err = err;
730c4e78
NI		 1887 recv_max_margin = recv_margin;
1888 } else if ((min_err == err) &&
1889 (recv_margin > recv_max_margin))
1890 recv_max_margin = recv_margin;
1891 else
1892 continue;
1893
1894 *brr = br;
1895 *srr = sr - 1;
1896 *cks = c;
f303b364
UH		 1897 }
1898 }
1899
1900 if (min_err == 1000) {
1901 WARN_ON(1);
1902 /* use defaults */
1903 *brr = 255;
1904 *srr = 15;
1905 *cks = 0;
1906 }
1907}
1908
1ba76220
MD		 1909static void sci_reset(struct uart_port *port)
1910{
d3184e68 1911 const struct plat_sci_reg *reg;
1ba76220
MD		 1912 unsigned int status;
1913
1914 do {
b12bb29f 1915 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1916 } while (!(status & SCxSR_TEND(port)));
1917
b12bb29f 1918 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1919
0979e0e6
PM		 1920 reg = sci_getreg(port, SCFCR);
1921 if (reg->size)
b12bb29f 1922 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1923}
1924
606d099c
AC		 1925static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1926 struct ktermios *old)
1da177e4 1927{
00b9de9c 1928 struct sci_port *s = to_sci_port(port);
d3184e68 1929 const struct plat_sci_reg *reg;
730c4e78 1930 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1931 int t = -1;
d4759ded 1932 unsigned int srr = 15;
1da177e4 1933
730c4e78
NI		 1934 if ((termios->c_cflag & CSIZE) == CS7)
1935 smr_val |= SCSMR_CHR;
1936 if (termios->c_cflag & PARENB)
1937 smr_val |= SCSMR_PE;
1938 if (termios->c_cflag & PARODD)
1939 smr_val |= SCSMR_PE | SCSMR_ODD;
1940 if (termios->c_cflag & CSTOPB)
1941 smr_val |= SCSMR_STOP;
1942
154280fd
MD		 1943 /*
1944 * earlyprintk comes here early on with port->uartclk set to zero.
1945 * the clock framework is not up and running at this point so here
1946 * we assume that 115200 is the maximum baud rate. please note that
1947 * the baud rate is not programmed during earlyprintk - it is assumed
1948 * that the previous boot loader has enabled required clocks and
1949 * setup the baud rate generator hardware for us already.
1950 */
1951 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1952
154280fd 1953 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1954 if (likely(baud && port->uartclk)) {
ec09c5eb 1955 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1956 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1957 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1958 &cks, frame_len);
f303b364 1959 } else {
ec09c5eb 1960 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1961 for (cks = 0; t >= 256 && cks <= 3; cks++)
1962 t >>= 2;
1963 }
1964 }
e108b2ca 1965
23241d43 1966 sci_port_enable(s);
36003386 1967
1ba76220 1968 sci_reset(port);
1da177e4 1969
2944a331 1970 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 1971
1972 uart_update_timeout(port, termios->c_cflag, baud);
1973
9d482cc3
TY		 1974 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1975 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1976
4ffc3cdb 1977 if (t >= 0) {
26de4f1b 1978 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1979 serial_port_out(port, SCBRR, t);
f303b364
UH		 1980 reg = sci_getreg(port, HSSRR);
1981 if (reg->size)
1982 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1983 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1984 } else
1985 serial_port_out(port, SCSMR, smr_val);
1da177e4 1986
d5701647 1987 sci_init_pins(port, termios->c_cflag);
0979e0e6 1988
73c3d53f
PM		 1989 reg = sci_getreg(port, SCFCR);
1990 if (reg->size) {
b12bb29f 1991 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1992
73c3d53f 1993 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1994 if (termios->c_cflag & CRTSCTS)
1995 ctrl |= SCFCR_MCE;
1996 else
1997 ctrl &= ~SCFCR_MCE;
faf02f8f 1998 }
73c3d53f
PM		 1999
2000 /*
2001 * As we've done a sci_reset() above, ensure we don't
2002 * interfere with the FIFOs while toggling MCE. As the
2003 * reset values could still be set, simply mask them out.
2004 */
2005 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2006
b12bb29f 2007 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2008 }
b7a76e4b 2009
b12bb29f 2010 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2011
3089f381
GL		 2012#ifdef CONFIG_SERIAL_SH_SCI_DMA
2013 /*
5f6d8515 2014 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2015 * See serial_core.c::uart_update_timeout().
2016 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2017 * function calculates 1 jiffie for the data plus 5 jiffies for the
2018 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2019 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2020 * value obtained by this formula is too small. Therefore, if the value
2021 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2022 */
2023 if (s->chan_rx) {
5f6d8515
NI		 2024 unsigned int bits;
2025
2026 /* byte size and parity */
2027 switch (termios->c_cflag & CSIZE) {
2028 case CS5:
2029 bits = 7;
2030 break;
2031 case CS6:
2032 bits = 8;
2033 break;
2034 case CS7:
2035 bits = 9;
2036 break;
2037 default:
2038 bits = 10;
2039 break;
2040 }
2041
2042 if (termios->c_cflag & CSTOPB)
2043 bits++;
2044 if (termios->c_cflag & PARENB)
2045 bits++;
2046 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2047 (baud / 10), 10);
9b971cd2 2048 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2049 s->rx_timeout * 1000 / HZ, port->timeout);
2050 if (s->rx_timeout < msecs_to_jiffies(20))
2051 s->rx_timeout = msecs_to_jiffies(20);
2052 }
2053#endif
2054
1da177e4 2055 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2056 sci_start_rx(port);
36003386 2057
23241d43 2058 sci_port_disable(s);
1da177e4
LT		 2059}
2060
0174e5ca
TK		 2061static void sci_pm(struct uart_port *port, unsigned int state,
2062 unsigned int oldstate)
2063{
2064 struct sci_port *sci_port = to_sci_port(port);
2065
2066 switch (state) {
d3dfe5d9 2067 case UART_PM_STATE_OFF:
0174e5ca
TK		 2068 sci_port_disable(sci_port);
2069 break;
2070 default:
2071 sci_port_enable(sci_port);
2072 break;
2073 }
2074}
2075
1da177e4
LT		 2076static const char *sci_type(struct uart_port *port)
2077{
2078 switch (port->type) {
e7c98dc7
MT		 2079 case PORT_IRDA:
2080 return "irda";
2081 case PORT_SCI:
2082 return "sci";
2083 case PORT_SCIF:
2084 return "scif";
2085 case PORT_SCIFA:
2086 return "scifa";
d1d4b10c
GL		 2087 case PORT_SCIFB:
2088 return "scifb";
f303b364
UH		 2089 case PORT_HSCIF:
2090 return "hscif";
1da177e4
LT		 2091 }
2092
fa43972f 2093 return NULL;
1da177e4
LT		 2094}
2095
f6e9495d
PM		 2096static int sci_remap_port(struct uart_port *port)
2097{
e4d6f911 2098 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2099
2100 /*
2101 * Nothing to do if there's already an established membase.
2102 */
2103 if (port->membase)
2104 return 0;
2105
2106 if (port->flags & UPF_IOREMAP) {
e4d6f911 2107 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2108 if (unlikely(!port->membase)) {
2109 dev_err(port->dev, "can't remap port#%d\n", port->line);
2110 return -ENXIO;
2111 }
2112 } else {
2113 /*
2114 * For the simple (and majority of) cases where we don't
2115 * need to do any remapping, just cast the cookie
2116 * directly.
2117 */
3af4e960 2118 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2119 }
2120
2121 return 0;
2122}
2123
e2651647 2124static void sci_release_port(struct uart_port *port)
1da177e4 2125{
e4d6f911
YS		 2126 struct sci_port *sport = to_sci_port(port);
2127
e2651647
PM		 2128 if (port->flags & UPF_IOREMAP) {
2129 iounmap(port->membase);
2130 port->membase = NULL;
2131 }
2132
e4d6f911 2133 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2134}
2135
e2651647 2136static int sci_request_port(struct uart_port *port)
1da177e4 2137{
e2651647 2138 struct resource *res;
e4d6f911 2139 struct sci_port *sport = to_sci_port(port);
f6e9495d 2140 int ret;
1da177e4 2141
e4d6f911
YS		 2142 res = request_mem_region(port->mapbase, sport->reg_size,
2143 dev_name(port->dev));
2144 if (unlikely(res == NULL)) {
2145 dev_err(port->dev, "request_mem_region failed.");
e2651647 2146 return -EBUSY;
e4d6f911 2147 }
1da177e4 2148
f6e9495d
PM		 2149 ret = sci_remap_port(port);
2150 if (unlikely(ret != 0)) {
2151 release_resource(res);
2152 return ret;
7ff731ae 2153 }
e2651647
PM		 2154
2155 return 0;
2156}
2157
2158static void sci_config_port(struct uart_port *port, int flags)
2159{
2160 if (flags & UART_CONFIG_TYPE) {
2161 struct sci_port *sport = to_sci_port(port);
2162
2163 port->type = sport->cfg->type;
2164 sci_request_port(port);
2165 }
1da177e4
LT		 2166}
2167
2168static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2169{
1da177e4
LT		 2170 if (ser->baud_base < 2400)
2171 /* No paper tape reader for Mitch.. */
2172 return -EINVAL;
2173
2174 return 0;
2175}
2176
2177static struct uart_ops sci_uart_ops = {
2178 .tx_empty = sci_tx_empty,
2179 .set_mctrl = sci_set_mctrl,
2180 .get_mctrl = sci_get_mctrl,
2181 .start_tx = sci_start_tx,
2182 .stop_tx = sci_stop_tx,
2183 .stop_rx = sci_stop_rx,
1da177e4
LT		 2184 .break_ctl = sci_break_ctl,
2185 .startup = sci_startup,
2186 .shutdown = sci_shutdown,
2187 .set_termios = sci_set_termios,
0174e5ca 2188 .pm = sci_pm,
1da177e4
LT		 2189 .type = sci_type,
2190 .release_port = sci_release_port,
2191 .request_port = sci_request_port,
2192 .config_port = sci_config_port,
2193 .verify_port = sci_verify_port,
07d2a1a1
PM		 2194#ifdef CONFIG_CONSOLE_POLL
2195 .poll_get_char = sci_poll_get_char,
2196 .poll_put_char = sci_poll_put_char,
2197#endif
1da177e4
LT		 2198};
2199
9671f099 2200static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2201 struct sci_port *sci_port, unsigned int index,
2202 struct plat_sci_port *p, bool early)
e108b2ca 2203{
73a19e4c 2204 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2205 const struct resource *res;
2206 unsigned int i;
3127c6b2 2207 int ret;
e108b2ca 2208
50f0959a
PM		 2209 sci_port->cfg = p;
2210
73a19e4c
GL		 2211 port->ops = &sci_uart_ops;
2212 port->iotype = UPIO_MEM;
2213 port->line = index;
75136d48 2214
89b5c1ab
LP		 2215 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2216 if (res == NULL)
2217 return -ENOMEM;
1fcc91a6 2218
89b5c1ab 2219 port->mapbase = res->start;
e4d6f911 2220 sci_port->reg_size = resource_size(res);
1fcc91a6 2221
89b5c1ab
LP		 2222 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2223 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2224
89b5c1ab
LP		 2225 /* The SCI generates several interrupts. They can be muxed together or
2226 * connected to different interrupt lines. In the muxed case only one
2227 * interrupt resource is specified. In the non-muxed case three or four
2228 * interrupt resources are specified, as the BRI interrupt is optional.
2229 */
2230 if (sci_port->irqs[0] < 0)
2231 return -ENXIO;
1fcc91a6 2232
89b5c1ab
LP		 2233 if (sci_port->irqs[1] < 0) {
2234 sci_port->irqs[1] = sci_port->irqs[0];
2235 sci_port->irqs[2] = sci_port->irqs[0];
2236 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2237 }
2238
b545e4f4
LP		 2239 if (p->regtype == SCIx_PROBE_REGTYPE) {
2240 ret = sci_probe_regmap(p);
2241 if (unlikely(ret))
2242 return ret;
2243 }
2244
75136d48 2245 switch (p->type) {
d1d4b10c
GL		 2246 case PORT_SCIFB:
2247 port->fifosize = 256;
2e0842a1 2248 sci_port->overrun_reg = SCxSR;
75c249fd 2249 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2250 sci_port->sampling_rate = 16;
d1d4b10c 2251 break;
f303b364
UH		 2252 case PORT_HSCIF:
2253 port->fifosize = 128;
2e0842a1 2254 sci_port->overrun_reg = SCLSR;
75c249fd 2255 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2256 sci_port->sampling_rate = 0;
f303b364 2257 break;
75136d48 2258 case PORT_SCIFA:
73a19e4c 2259 port->fifosize = 64;
2e0842a1 2260 sci_port->overrun_reg = SCxSR;
75c249fd 2261 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2262 sci_port->sampling_rate = 16;
75136d48
MP		 2263 break;
2264 case PORT_SCIF:
73a19e4c 2265 port->fifosize = 16;
ec09c5eb 2266 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2267 sci_port->overrun_reg = SCxSR;
75c249fd 2268 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2269 sci_port->sampling_rate = 16;
ec09c5eb 2270 } else {
2e0842a1 2271 sci_port->overrun_reg = SCLSR;
75c249fd 2272 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2273 sci_port->sampling_rate = 32;
ec09c5eb 2274 }
75136d48
MP		 2275 break;
2276 default:
73a19e4c 2277 port->fifosize = 1;
2e0842a1 2278 sci_port->overrun_reg = SCxSR;
75c249fd 2279 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2280 sci_port->sampling_rate = 32;
75136d48
MP		 2281 break;
2282 }
7b6fd3bf 2283
878fbb91
LP		 2284 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2285 * match the SoC datasheet, this should be investigated. Let platform
2286 * data override the sampling rate for now.
ec09c5eb 2287 */
f84b6bdc
GU		 2288 if (p->sampling_rate)
2289 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2290
1fcc91a6 2291 if (!early) {
c7ed1ab3
PM		 2292 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2293 if (IS_ERR(sci_port->iclk)) {
2294 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2295 if (IS_ERR(sci_port->iclk)) {
2296 dev_err(&dev->dev, "can't get iclk\n");
2297 return PTR_ERR(sci_port->iclk);
2298 }
2299 }
2300
2301 /*
2302 * The function clock is optional, ignore it if we can't
2303 * find it.
2304 */
2305 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2306 if (IS_ERR(sci_port->fclk))
2307 sci_port->fclk = NULL;
2308
73a19e4c 2309 port->dev = &dev->dev;
5e50d2d6
MD		 2310
2311 pm_runtime_enable(&dev->dev);
7b6fd3bf 2312 }
e108b2ca 2313
7ed7e071
MD		 2314 sci_port->break_timer.data = (unsigned long)sci_port;
2315 sci_port->break_timer.function = sci_break_timer;
2316 init_timer(&sci_port->break_timer);
2317
debf9507
PM		 2318 /*
2319 * Establish some sensible defaults for the error detection.
2320 */
5da0f468
GU		 2321 if (p->type == PORT_SCI) {
2322 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2323 sci_port->error_clear = SCI_ERROR_CLEAR;
2324 } else {
2325 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2326 sci_port->error_clear = SCIF_ERROR_CLEAR;
2327 }
debf9507 2328
3ae988d9
LP		 2329 /*
2330 * Make the error mask inclusive of overrun detection, if
2331 * supported.
2332 */
5da0f468 2333 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2334 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2335 sci_port->error_clear &= ~sci_port->overrun_mask;
2336 }
debf9507 2337
ce6738b6 2338 port->type = p->type;
b6e4a3f1 2339 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2340 port->regshift = p->regshift;
73a19e4c 2341
ce6738b6 2342 /*
61a6976b 2343 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2344 * for the multi-IRQ ports, which is where we are primarily
2345 * concerned with the shutdown path synchronization.
2346 *
2347 * For the muxed case there's nothing more to do.
2348 */
1fcc91a6 2349 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2350 port->irqflags = 0;
73a19e4c 2351
61a6976b
PM		 2352 port->serial_in = sci_serial_in;
2353 port->serial_out = sci_serial_out;
2354
937bb6e4
GL		 2355 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2356 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2357 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2358
c7ed1ab3 2359 return 0;
e108b2ca
PM		 2360}
2361
6dae1421
LP		 2362static void sci_cleanup_single(struct sci_port *port)
2363{
6dae1421
LP		 2364 clk_put(port->iclk);
2365 clk_put(port->fclk);
2366
2367 pm_runtime_disable(port->port.dev);
2368}
2369
1da177e4 2370#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2371static void serial_console_putchar(struct uart_port *port, int ch)
2372{
2373 sci_poll_put_char(port, ch);
2374}
2375
1da177e4
LT		 2376/*
2377 * Print a string to the serial port trying not to disturb
2378 * any possible real use of the port...
2379 */
2380static void serial_console_write(struct console *co, const char *s,
2381 unsigned count)
2382{
906b17dc
PM		 2383 struct sci_port *sci_port = &sci_ports[co->index];
2384 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2385 unsigned short bits, ctrl;
2386 unsigned long flags;
2387 int locked = 1;
2388
2389 local_irq_save(flags);
2390 if (port->sysrq)
2391 locked = 0;
2392 else if (oops_in_progress)
2393 locked = spin_trylock(&port->lock);
2394 else
2395 spin_lock(&port->lock);
2396
2397 /* first save the SCSCR then disable the interrupts */
2398 ctrl = serial_port_in(port, SCSCR);
2399 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2400
501b825d 2401 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2402
2403 /* wait until fifo is empty and last bit has been transmitted */
2404 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2405 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2406 cpu_relax();
40f70c03
SK		 2407
2408 /* restore the SCSCR */
2409 serial_port_out(port, SCSCR, ctrl);
2410
2411 if (locked)
2412 spin_unlock(&port->lock);
2413 local_irq_restore(flags);
1da177e4
LT		 2414}
2415
9671f099 2416static int serial_console_setup(struct console *co, char *options)
1da177e4 2417{
dc8e6f5b 2418 struct sci_port *sci_port;
1da177e4
LT		 2419 struct uart_port *port;
2420 int baud = 115200;
2421 int bits = 8;
2422 int parity = 'n';
2423 int flow = 'n';
2424 int ret;
2425
e108b2ca 2426 /*
906b17dc 2427 * Refuse to handle any bogus ports.
1da177e4 2428 */
906b17dc 2429 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2430 return -ENODEV;
e108b2ca 2431
906b17dc
PM		 2432 sci_port = &sci_ports[co->index];
2433 port = &sci_port->port;
2434
b2267a6b
AC		 2435 /*
2436 * Refuse to handle uninitialized ports.
2437 */
2438 if (!port->ops)
2439 return -ENODEV;
2440
f6e9495d
PM		 2441 ret = sci_remap_port(port);
2442 if (unlikely(ret != 0))
2443 return ret;
e108b2ca 2444
1da177e4
LT		 2445 if (options)
2446 uart_parse_options(options, &baud, &parity, &bits, &flow);
2447
ab7cfb55 2448 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2449}
2450
2451static struct console serial_console = {
2452 .name = "ttySC",
906b17dc 2453 .device = uart_console_device,
1da177e4
LT		 2454 .write = serial_console_write,
2455 .setup = serial_console_setup,
fa5da2f7 2456 .flags = CON_PRINTBUFFER,
1da177e4 2457 .index = -1,
906b17dc 2458 .data = &sci_uart_driver,
1da177e4
LT		 2459};
2460
7b6fd3bf
MD		 2461static struct console early_serial_console = {
2462 .name = "early_ttySC",
2463 .write = serial_console_write,
2464 .flags = CON_PRINTBUFFER,
906b17dc 2465 .index = -1,
7b6fd3bf 2466};
ecdf8a46 2467
7b6fd3bf
MD		 2468static char early_serial_buf[32];
2469
9671f099 2470static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2471{
574de559 2472 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2473
2474 if (early_serial_console.data)
2475 return -EEXIST;
2476
2477 early_serial_console.index = pdev->id;
ecdf8a46 2478
1fcc91a6 2479 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2480
2481 serial_console_setup(&early_serial_console, early_serial_buf);
2482
2483 if (!strstr(early_serial_buf, "keep"))
2484 early_serial_console.flags |= CON_BOOT;
2485
2486 register_console(&early_serial_console);
2487 return 0;
2488}
6a8c9799
NI		 2489
2490#define SCI_CONSOLE (&serial_console)
2491
ecdf8a46 2492#else
9671f099 2493static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2494{
2495 return -EINVAL;
2496}
1da177e4 2497
6a8c9799
NI		 2498#define SCI_CONSOLE NULL
2499
2500#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2501
6c13d5d2 2502static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2503
2504static struct uart_driver sci_uart_driver = {
2505 .owner = THIS_MODULE,
2506 .driver_name = "sci",
1da177e4
LT		 2507 .dev_name = "ttySC",
2508 .major = SCI_MAJOR,
2509 .minor = SCI_MINOR_START,
e108b2ca 2510 .nr = SCI_NPORTS,
1da177e4
LT		 2511 .cons = SCI_CONSOLE,
2512};
2513
54507f6e 2514static int sci_remove(struct platform_device *dev)
e552de24 2515{
d535a230 2516 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2517
d535a230
PM		 2518 cpufreq_unregister_notifier(&port->freq_transition,
2519 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2520
d535a230
PM		 2521 uart_remove_one_port(&sci_uart_driver, &port->port);
2522
6dae1421 2523 sci_cleanup_single(port);
e552de24 2524
e552de24
MD		 2525 return 0;
2526}
2527
20bdcab8
BH		 2528struct sci_port_info {
2529 unsigned int type;
2530 unsigned int regtype;
2531};
2532
2533static const struct of_device_id of_sci_match[] = {
2534 {
2535 .compatible = "renesas,scif",
ff43da00 2536 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2537 .type = PORT_SCIF,
2538 .regtype = SCIx_SH4_SCIF_REGTYPE,
2539 },
2540 }, {
2541 .compatible = "renesas,scifa",
ff43da00 2542 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2543 .type = PORT_SCIFA,
2544 .regtype = SCIx_SCIFA_REGTYPE,
2545 },
2546 }, {
2547 .compatible = "renesas,scifb",
ff43da00 2548 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2549 .type = PORT_SCIFB,
2550 .regtype = SCIx_SCIFB_REGTYPE,
2551 },
2552 }, {
2553 .compatible = "renesas,hscif",
ff43da00 2554 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2555 .type = PORT_HSCIF,
2556 .regtype = SCIx_HSCIF_REGTYPE,
2557 },
e1d0be61
YS		 2558 }, {
2559 .compatible = "renesas,sci",
2560 .data = &(const struct sci_port_info) {
2561 .type = PORT_SCI,
2562 .regtype = SCIx_SCI_REGTYPE,
2563 },
20bdcab8
BH		 2564 }, {
2565 /* Terminator */
2566 },
2567};
2568MODULE_DEVICE_TABLE(of, of_sci_match);
2569
2570static struct plat_sci_port *
2571sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2572{
2573 struct device_node *np = pdev->dev.of_node;
2574 const struct of_device_id *match;
2575 const struct sci_port_info *info;
2576 struct plat_sci_port *p;
2577 int id;
2578
2579 if (!IS_ENABLED(CONFIG_OF) || !np)
2580 return NULL;
2581
2582 match = of_match_node(of_sci_match, pdev->dev.of_node);
2583 if (!match)
2584 return NULL;
2585
2586 info = match->data;
2587
2588 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2589 if (!p)
20bdcab8 2590 return NULL;
20bdcab8
BH		 2591
2592 /* Get the line number for the aliases node. */
2593 id = of_alias_get_id(np, "serial");
2594 if (id < 0) {
2595 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2596 return NULL;
2597 }
2598
2599 *dev_id = id;
2600
2601 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2602 p->type = info->type;
2603 p->regtype = info->regtype;
2604 p->scscr = SCSCR_RE | SCSCR_TE;
2605
2606 return p;
2607}
2608
9671f099 2609static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2610 unsigned int index,
2611 struct plat_sci_port *p,
2612 struct sci_port *sciport)
2613{
0ee70712
MD		 2614 int ret;
2615
2616 /* Sanity check */
2617 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2618 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2619 index+1, SCI_NPORTS);
9b971cd2 2620 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2621 return -EINVAL;
0ee70712
MD		 2622 }
2623
1fcc91a6 2624 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2625 if (ret)
2626 return ret;
0ee70712 2627
6dae1421
LP		 2628 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2629 if (ret) {
2630 sci_cleanup_single(sciport);
2631 return ret;
2632 }
2633
2634 return 0;
0ee70712
MD		 2635}
2636
9671f099 2637static int sci_probe(struct platform_device *dev)
1da177e4 2638{
20bdcab8
BH		 2639 struct plat_sci_port *p;
2640 struct sci_port *sp;
2641 unsigned int dev_id;
ecdf8a46 2642 int ret;
d535a230 2643
ecdf8a46
PM		 2644 /*
2645 * If we've come here via earlyprintk initialization, head off to
2646 * the special early probe. We don't have sufficient device state
2647 * to make it beyond this yet.
2648 */
2649 if (is_early_platform_device(dev))
2650 return sci_probe_earlyprintk(dev);
7b6fd3bf 2651
20bdcab8
BH		 2652 if (dev->dev.of_node) {
2653 p = sci_parse_dt(dev, &dev_id);
2654 if (p == NULL)
2655 return -EINVAL;
2656 } else {
2657 p = dev->dev.platform_data;
2658 if (p == NULL) {
2659 dev_err(&dev->dev, "no platform data supplied\n");
2660 return -EINVAL;
2661 }
2662
2663 dev_id = dev->id;
2664 }
2665
2666 sp = &sci_ports[dev_id];
d535a230 2667 platform_set_drvdata(dev, sp);
e552de24 2668
20bdcab8 2669 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2670 if (ret)
6dae1421 2671 return ret;
e552de24 2672
d535a230 2673 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2674
d535a230
PM		 2675 ret = cpufreq_register_notifier(&sp->freq_transition,
2676 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2677 if (unlikely(ret < 0)) {
bf13c9a8 2678 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2679 sci_cleanup_single(sp);
2680 return ret;
2681 }
1da177e4
LT		 2682
2683#ifdef CONFIG_SH_STANDARD_BIOS
2684 sh_bios_gdb_detach();
2685#endif
2686
e108b2ca 2687 return 0;
1da177e4
LT		 2688}
2689
cb876341 2690static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2691{
d535a230 2692 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2693
d535a230
PM		 2694 if (sport)
2695 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2696
e108b2ca
PM		 2697 return 0;
2698}
1da177e4 2699
cb876341 2700static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2701{
d535a230 2702 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2703
d535a230
PM		 2704 if (sport)
2705 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2706
2707 return 0;
2708}
2709
cb876341 2710static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2711
e108b2ca
PM		 2712static struct platform_driver sci_driver = {
2713 .probe = sci_probe,
b9e39c89 2714 .remove = sci_remove,
e108b2ca
PM		 2715 .driver = {
2716 .name = "sh-sci",
6daa79b3 2717 .pm = &sci_dev_pm_ops,
20bdcab8 2718 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2719 },
2720};
2721
2722static int __init sci_init(void)
2723{
2724 int ret;
2725
6c13d5d2 2726 pr_info("%s\n", banner);
e108b2ca 2727
e108b2ca
PM		 2728 ret = uart_register_driver(&sci_uart_driver);
2729 if (likely(ret == 0)) {
2730 ret = platform_driver_register(&sci_driver);
2731 if (unlikely(ret))
2732 uart_unregister_driver(&sci_uart_driver);
2733 }
2734
2735 return ret;
2736}
2737
2738static void __exit sci_exit(void)
2739{
2740 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2741 uart_unregister_driver(&sci_uart_driver);
2742}
2743
7b6fd3bf
MD		 2744#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2745early_platform_init_buffer("earlyprintk", &sci_driver,
2746 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2747#endif
1da177e4
LT		 2748module_init(sci_init);
2749module_exit(sci_exit);
2750
e108b2ca 2751MODULE_LICENSE("GPL");
e169c139 2752MODULE_ALIAS("platform:sh-sci");
7f405f9c 2753MODULE_AUTHOR("Paul Mundt");
f303b364 2754MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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