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serial: sh-sci: Add device tree support for r8a7795
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
79904420
GU		 110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
73a19e4c 112 struct scatterlist sg_rx[2];
7b39d901 113 void *rx_buf[2];
73a19e4c
GL		 114 size_t buf_len_rx;
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct work_struct work_rx;
119 struct timer_list rx_timer;
3089f381 120 unsigned int rx_timeout;
73a19e4c 121#endif
e552de24 122
d535a230 123 struct notifier_block freq_transition;
e108b2ca
PM		 124};
125
1da177e4 126/* Function prototypes */
d535a230 127static void sci_start_tx(struct uart_port *port);
b129a8cc 128static void sci_stop_tx(struct uart_port *port);
d535a230 129static void sci_start_rx(struct uart_port *port);
1da177e4 130
e108b2ca 131#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 132
e108b2ca
PM		 133static struct sci_port sci_ports[SCI_NPORTS];
134static struct uart_driver sci_uart_driver;
1da177e4 135
e7c98dc7
MT		 136static inline struct sci_port *
137to_sci_port(struct uart_port *uart)
138{
139 return container_of(uart, struct sci_port, port);
140}
141
61a6976b
PM		 142struct plat_sci_reg {
143 u8 offset, size;
144};
145
146/* Helper for invalidating specific entries of an inherited map. */
147#define sci_reg_invalid { .offset = 0, .size = 0 }
148
d3184e68 149static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 150 [SCIx_PROBE_REGTYPE] = {
151 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
152 },
153
154 /*
155 * Common SCI definitions, dependent on the port's regshift
156 * value.
157 */
158 [SCIx_SCI_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = sci_reg_invalid,
166 [SCFDR] = sci_reg_invalid,
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
f303b364 171 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 172 [SCPCR] = sci_reg_invalid,
173 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 174 },
175
176 /*
177 * Common definitions for legacy IrDA ports, dependent on
178 * regshift value.
179 */
180 [SCIx_IRDA_REGTYPE] = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 [SCFCR] = { 0x06, 8 },
188 [SCFDR] = { 0x07, 16 },
189 [SCTFDR] = sci_reg_invalid,
190 [SCRFDR] = sci_reg_invalid,
191 [SCSPTR] = sci_reg_invalid,
192 [SCLSR] = sci_reg_invalid,
f303b364 193 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 194 [SCPCR] = sci_reg_invalid,
195 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 196 },
197
198 /*
199 * Common SCIFA definitions.
200 */
201 [SCIx_SCIFA_REGTYPE] = {
202 [SCSMR] = { 0x00, 16 },
203 [SCBRR] = { 0x04, 8 },
204 [SCSCR] = { 0x08, 16 },
205 [SCxTDR] = { 0x20, 8 },
206 [SCxSR] = { 0x14, 16 },
207 [SCxRDR] = { 0x24, 8 },
208 [SCFCR] = { 0x18, 16 },
209 [SCFDR] = { 0x1c, 16 },
210 [SCTFDR] = sci_reg_invalid,
211 [SCRFDR] = sci_reg_invalid,
212 [SCSPTR] = sci_reg_invalid,
213 [SCLSR] = sci_reg_invalid,
f303b364 214 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 215 [SCPCR] = { 0x30, 16 },
216 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 217 },
218
219 /*
220 * Common SCIFB definitions.
221 */
222 [SCIx_SCIFB_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x40, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x60, 8 },
229 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 230 [SCFDR] = sci_reg_invalid,
231 [SCTFDR] = { 0x38, 16 },
232 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 233 [SCSPTR] = sci_reg_invalid,
234 [SCLSR] = sci_reg_invalid,
f303b364 235 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 236 [SCPCR] = { 0x30, 16 },
237 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 238 },
239
3af1f8a4
PE		 240 /*
241 * Common SH-2(A) SCIF definitions for ports with FIFO data
242 * count registers.
243 */
244 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
245 [SCSMR] = { 0x00, 16 },
246 [SCBRR] = { 0x04, 8 },
247 [SCSCR] = { 0x08, 16 },
248 [SCxTDR] = { 0x0c, 8 },
249 [SCxSR] = { 0x10, 16 },
250 [SCxRDR] = { 0x14, 8 },
251 [SCFCR] = { 0x18, 16 },
252 [SCFDR] = { 0x1c, 16 },
253 [SCTFDR] = sci_reg_invalid,
254 [SCRFDR] = sci_reg_invalid,
255 [SCSPTR] = { 0x20, 16 },
256 [SCLSR] = { 0x24, 16 },
f303b364 257 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 258 [SCPCR] = sci_reg_invalid,
259 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 260 },
261
61a6976b
PM		 262 /*
263 * Common SH-3 SCIF definitions.
264 */
265 [SCIx_SH3_SCIF_REGTYPE] = {
266 [SCSMR] = { 0x00, 8 },
267 [SCBRR] = { 0x02, 8 },
268 [SCSCR] = { 0x04, 8 },
269 [SCxTDR] = { 0x06, 8 },
270 [SCxSR] = { 0x08, 16 },
271 [SCxRDR] = { 0x0a, 8 },
272 [SCFCR] = { 0x0c, 8 },
273 [SCFDR] = { 0x0e, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = sci_reg_invalid,
f303b364 278 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 281 },
282
283 /*
284 * Common SH-4(A) SCIF(B) definitions.
285 */
286 [SCIx_SH4_SCIF_REGTYPE] = {
287 [SCSMR] = { 0x00, 16 },
288 [SCBRR] = { 0x04, 8 },
289 [SCSCR] = { 0x08, 16 },
290 [SCxTDR] = { 0x0c, 8 },
291 [SCxSR] = { 0x10, 16 },
292 [SCxRDR] = { 0x14, 8 },
293 [SCFCR] = { 0x18, 16 },
294 [SCFDR] = { 0x1c, 16 },
295 [SCTFDR] = sci_reg_invalid,
296 [SCRFDR] = sci_reg_invalid,
297 [SCSPTR] = { 0x20, 16 },
298 [SCLSR] = { 0x24, 16 },
f303b364 299 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 300 [SCPCR] = sci_reg_invalid,
301 [SCPDR] = sci_reg_invalid,
f303b364
UH		 302 },
303
304 /*
305 * Common HSCIF definitions.
306 */
307 [SCIx_HSCIF_REGTYPE] = {
308 [SCSMR] = { 0x00, 16 },
309 [SCBRR] = { 0x04, 8 },
310 [SCSCR] = { 0x08, 16 },
311 [SCxTDR] = { 0x0c, 8 },
312 [SCxSR] = { 0x10, 16 },
313 [SCxRDR] = { 0x14, 8 },
314 [SCFCR] = { 0x18, 16 },
315 [SCFDR] = { 0x1c, 16 },
316 [SCTFDR] = sci_reg_invalid,
317 [SCRFDR] = sci_reg_invalid,
318 [SCSPTR] = { 0x20, 16 },
319 [SCLSR] = { 0x24, 16 },
320 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 321 [SCPCR] = sci_reg_invalid,
322 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 323 },
324
325 /*
326 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
327 * register.
328 */
329 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
330 [SCSMR] = { 0x00, 16 },
331 [SCBRR] = { 0x04, 8 },
332 [SCSCR] = { 0x08, 16 },
333 [SCxTDR] = { 0x0c, 8 },
334 [SCxSR] = { 0x10, 16 },
335 [SCxRDR] = { 0x14, 8 },
336 [SCFCR] = { 0x18, 16 },
337 [SCFDR] = { 0x1c, 16 },
338 [SCTFDR] = sci_reg_invalid,
339 [SCRFDR] = sci_reg_invalid,
340 [SCSPTR] = sci_reg_invalid,
341 [SCLSR] = { 0x24, 16 },
f303b364 342 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 343 [SCPCR] = sci_reg_invalid,
344 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 345 },
346
347 /*
348 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
349 * count registers.
350 */
351 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
352 [SCSMR] = { 0x00, 16 },
353 [SCBRR] = { 0x04, 8 },
354 [SCSCR] = { 0x08, 16 },
355 [SCxTDR] = { 0x0c, 8 },
356 [SCxSR] = { 0x10, 16 },
357 [SCxRDR] = { 0x14, 8 },
358 [SCFCR] = { 0x18, 16 },
359 [SCFDR] = { 0x1c, 16 },
360 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
361 [SCRFDR] = { 0x20, 16 },
362 [SCSPTR] = { 0x24, 16 },
363 [SCLSR] = { 0x28, 16 },
f303b364 364 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 365 [SCPCR] = sci_reg_invalid,
366 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 367 },
368
369 /*
370 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
371 * registers.
372 */
373 [SCIx_SH7705_SCIF_REGTYPE] = {
374 [SCSMR] = { 0x00, 16 },
375 [SCBRR] = { 0x04, 8 },
376 [SCSCR] = { 0x08, 16 },
377 [SCxTDR] = { 0x20, 8 },
378 [SCxSR] = { 0x14, 16 },
379 [SCxRDR] = { 0x24, 8 },
380 [SCFCR] = { 0x18, 16 },
381 [SCFDR] = { 0x1c, 16 },
382 [SCTFDR] = sci_reg_invalid,
383 [SCRFDR] = sci_reg_invalid,
384 [SCSPTR] = sci_reg_invalid,
385 [SCLSR] = sci_reg_invalid,
f303b364 386 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 387 [SCPCR] = sci_reg_invalid,
388 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 389 },
390};
391
72b294cf
PM		 392#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
393
61a6976b
PM		 394/*
395 * The "offset" here is rather misleading, in that it refers to an enum
396 * value relative to the port mapping rather than the fixed offset
397 * itself, which needs to be manually retrieved from the platform's
398 * register map for the given port.
399 */
400static unsigned int sci_serial_in(struct uart_port *p, int offset)
401{
d3184e68 402 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 403
404 if (reg->size == 8)
405 return ioread8(p->membase + (reg->offset << p->regshift));
406 else if (reg->size == 16)
407 return ioread16(p->membase + (reg->offset << p->regshift));
408 else
409 WARN(1, "Invalid register access\n");
410
411 return 0;
412}
413
414static void sci_serial_out(struct uart_port *p, int offset, int value)
415{
d3184e68 416 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 417
418 if (reg->size == 8)
419 iowrite8(value, p->membase + (reg->offset << p->regshift));
420 else if (reg->size == 16)
421 iowrite16(value, p->membase + (reg->offset << p->regshift));
422 else
423 WARN(1, "Invalid register access\n");
424}
425
61a6976b
PM		 426static int sci_probe_regmap(struct plat_sci_port *cfg)
427{
428 switch (cfg->type) {
429 case PORT_SCI:
430 cfg->regtype = SCIx_SCI_REGTYPE;
431 break;
432 case PORT_IRDA:
433 cfg->regtype = SCIx_IRDA_REGTYPE;
434 break;
435 case PORT_SCIFA:
436 cfg->regtype = SCIx_SCIFA_REGTYPE;
437 break;
438 case PORT_SCIFB:
439 cfg->regtype = SCIx_SCIFB_REGTYPE;
440 break;
441 case PORT_SCIF:
442 /*
443 * The SH-4 is a bit of a misnomer here, although that's
444 * where this particular port layout originated. This
445 * configuration (or some slight variation thereof)
446 * remains the dominant model for all SCIFs.
447 */
448 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
449 break;
f303b364
UH		 450 case PORT_HSCIF:
451 cfg->regtype = SCIx_HSCIF_REGTYPE;
452 break;
61a6976b 453 default:
6c13d5d2 454 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 455 return -EINVAL;
456 }
457
458 return 0;
459}
460
23241d43
PM		 461static void sci_port_enable(struct sci_port *sci_port)
462{
463 if (!sci_port->port.dev)
464 return;
465
466 pm_runtime_get_sync(sci_port->port.dev);
467
b016b646 468 clk_prepare_enable(sci_port->iclk);
23241d43 469 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 470 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 471}
472
473static void sci_port_disable(struct sci_port *sci_port)
474{
475 if (!sci_port->port.dev)
476 return;
477
caec7038
LP		 478 /* Cancel the break timer to ensure that the timer handler will not try
479 * to access the hardware with clocks and power disabled. Reset the
480 * break flag to make the break debouncing state machine ready for the
481 * next break.
482 */
483 del_timer_sync(&sci_port->break_timer);
484 sci_port->break_flag = 0;
485
b016b646
LP		 486 clk_disable_unprepare(sci_port->fclk);
487 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 488
489 pm_runtime_put_sync(sci_port->port.dev);
490}
491
a1b5b43f
GU		 492static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
493{
494 if (port->type == PORT_SCI) {
495 /* Just store the mask */
496 serial_port_out(port, SCxSR, mask);
497 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
498 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
499 /* Only clear the status bits we want to clear */
500 serial_port_out(port, SCxSR,
501 serial_port_in(port, SCxSR) & mask);
502 } else {
503 /* Store the mask, clear parity/framing errors */
504 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
505 }
506}
507
07d2a1a1 508#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 509
510#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 511static int sci_poll_get_char(struct uart_port *port)
1da177e4 512{
1da177e4
LT		 513 unsigned short status;
514 int c;
515
e108b2ca 516 do {
b12bb29f 517 status = serial_port_in(port, SCxSR);
1da177e4 518 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 519 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 520 continue;
521 }
3f255eb3
JW		 522 break;
523 } while (1);
524
525 if (!(status & SCxSR_RDxF(port)))
526 return NO_POLL_CHAR;
07d2a1a1 527
b12bb29f 528 c = serial_port_in(port, SCxRDR);
07d2a1a1 529
e7c98dc7 530 /* Dummy read */
b12bb29f 531 serial_port_in(port, SCxSR);
a1b5b43f 532 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 533
534 return c;
535}
1f6fd5c9 536#endif
1da177e4 537
07d2a1a1 538static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 539{
1da177e4
LT		 540 unsigned short status;
541
1da177e4 542 do {
b12bb29f 543 status = serial_port_in(port, SCxSR);
1da177e4
LT		 544 } while (!(status & SCxSR_TDxE(port)));
545
b12bb29f 546 serial_port_out(port, SCxTDR, c);
a1b5b43f 547 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 548}
07d2a1a1 549#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 550
61a6976b 551static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 552{
61a6976b 553 struct sci_port *s = to_sci_port(port);
d3184e68 554 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 555
61a6976b
PM		 556 /*
557 * Use port-specific handler if provided.
558 */
559 if (s->cfg->ops && s->cfg->ops->init_pins) {
560 s->cfg->ops->init_pins(port, cflag);
561 return;
1da177e4 562 }
41504c39 563
61a6976b
PM		 564 /*
565 * For the generic path SCSPTR is necessary. Bail out if that's
566 * unavailable, too.
567 */
568 if (!reg->size)
569 return;
41504c39 570
faf02f8f
PM		 571 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
572 ((!(cflag & CRTSCTS)))) {
573 unsigned short status;
574
b12bb29f 575 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 576 status &= ~SCSPTR_CTSIO;
577 status |= SCSPTR_RTSIO;
b12bb29f 578 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 579 }
d5701647 580}
e108b2ca 581
72b294cf 582static int sci_txfill(struct uart_port *port)
e108b2ca 583{
d3184e68 584 const struct plat_sci_reg *reg;
e108b2ca 585
72b294cf
PM		 586 reg = sci_getreg(port, SCTFDR);
587 if (reg->size)
63f7ad11 588 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 589
72b294cf
PM		 590 reg = sci_getreg(port, SCFDR);
591 if (reg->size)
b12bb29f 592 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 593
b12bb29f 594 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 595}
596
73a19e4c
GL		 597static int sci_txroom(struct uart_port *port)
598{
72b294cf 599 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 600}
601
602static int sci_rxfill(struct uart_port *port)
e108b2ca 603{
d3184e68 604 const struct plat_sci_reg *reg;
72b294cf
PM		 605
606 reg = sci_getreg(port, SCRFDR);
607 if (reg->size)
63f7ad11 608 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 609
610 reg = sci_getreg(port, SCFDR);
611 if (reg->size)
b12bb29f 612 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 613
b12bb29f 614 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 615}
616
514820eb
PM		 617/*
618 * SCI helper for checking the state of the muxed port/RXD pins.
619 */
620static inline int sci_rxd_in(struct uart_port *port)
621{
622 struct sci_port *s = to_sci_port(port);
623
624 if (s->cfg->port_reg <= 0)
625 return 1;
626
0dd4d5cb 627 /* Cast for ARM damage */
e2afca69 628 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 629}
630
1da177e4
LT		 631/* ********************************************************************** *
632 * the interrupt related routines *
633 * ********************************************************************** */
634
635static void sci_transmit_chars(struct uart_port *port)
636{
ebd2c8f6 637 struct circ_buf *xmit = &port->state->xmit;
1da177e4 638 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 639 unsigned short status;
640 unsigned short ctrl;
e108b2ca 641 int count;
1da177e4 642
b12bb29f 643 status = serial_port_in(port, SCxSR);
1da177e4 644 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 645 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 646 if (uart_circ_empty(xmit))
8e698614 647 ctrl &= ~SCSCR_TIE;
e7c98dc7 648 else
8e698614 649 ctrl |= SCSCR_TIE;
b12bb29f 650 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 651 return;
652 }
653
72b294cf 654 count = sci_txroom(port);
1da177e4
LT		 655
656 do {
657 unsigned char c;
658
659 if (port->x_char) {
660 c = port->x_char;
661 port->x_char = 0;
662 } else if (!uart_circ_empty(xmit) && !stopped) {
663 c = xmit->buf[xmit->tail];
664 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
665 } else {
666 break;
667 }
668
b12bb29f 669 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 670
671 port->icount.tx++;
672 } while (--count > 0);
673
a1b5b43f 674 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 675
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(port);
678 if (uart_circ_empty(xmit)) {
b129a8cc 679 sci_stop_tx(port);
1da177e4 680 } else {
b12bb29f 681 ctrl = serial_port_in(port, SCSCR);
1da177e4 682
1a22f08d 683 if (port->type != PORT_SCI) {
b12bb29f 684 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 685 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 686 }
1da177e4 687
8e698614 688 ctrl |= SCSCR_TIE;
b12bb29f 689 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 690 }
691}
692
693/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 694#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 695
94c8b6db 696static void sci_receive_chars(struct uart_port *port)
1da177e4 697{
e7c98dc7 698 struct sci_port *sci_port = to_sci_port(port);
227434f8 699 struct tty_port *tport = &port->state->port;
1da177e4
LT		 700 int i, count, copied = 0;
701 unsigned short status;
33f0f88f 702 unsigned char flag;
1da177e4 703
b12bb29f 704 status = serial_port_in(port, SCxSR);
1da177e4
LT		 705 if (!(status & SCxSR_RDxF(port)))
706 return;
707
708 while (1) {
1da177e4 709 /* Don't copy more bytes than there is room for in the buffer */
227434f8 710 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 711
712 /* If for any reason we can't copy more data, we're done! */
713 if (count == 0)
714 break;
715
716 if (port->type == PORT_SCI) {
b12bb29f 717 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 718 if (uart_handle_sysrq_char(port, c) ||
719 sci_port->break_flag)
1da177e4 720 count = 0;
e7c98dc7 721 else
92a19f9c 722 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 723 } else {
e7c98dc7 724 for (i = 0; i < count; i++) {
b12bb29f 725 char c = serial_port_in(port, SCxRDR);
d97fbbed 726
b12bb29f 727 status = serial_port_in(port, SCxSR);
1da177e4
LT		 728#if defined(CONFIG_CPU_SH3)
729 /* Skip "chars" during break */
e108b2ca 730 if (sci_port->break_flag) {
1da177e4
LT		 731 if ((c == 0) &&
732 (status & SCxSR_FER(port))) {
733 count--; i--;
734 continue;
735 }
e108b2ca 736
1da177e4 737 /* Nonzero => end-of-break */
762c69e3 738 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 739 sci_port->break_flag = 0;
740
1da177e4
LT		 741 if (STEPFN(c)) {
742 count--; i--;
743 continue;
744 }
745 }
746#endif /* CONFIG_CPU_SH3 */
7d12e780 747 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 748 count--; i--;
749 continue;
750 }
751
752 /* Store data and status */
73a19e4c 753 if (status & SCxSR_FER(port)) {
33f0f88f 754 flag = TTY_FRAME;
d97fbbed 755 port->icount.frame++;
762c69e3 756 dev_notice(port->dev, "frame error\n");
73a19e4c 757 } else if (status & SCxSR_PER(port)) {
33f0f88f 758 flag = TTY_PARITY;
d97fbbed 759 port->icount.parity++;
762c69e3 760 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 761 } else
762 flag = TTY_NORMAL;
762c69e3 763
92a19f9c 764 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 765 }
766 }
767
b12bb29f 768 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 769 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 770
1da177e4
LT		 771 copied += count;
772 port->icount.rx += count;
773 }
774
775 if (copied) {
776 /* Tell the rest of the system the news. New characters! */
2e124b4a 777 tty_flip_buffer_push(tport);
1da177e4 778 } else {
b12bb29f 779 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 780 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 781 }
782}
783
784#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 785
786/*
787 * The sci generates interrupts during the break,
1da177e4
LT		 788 * 1 per millisecond or so during the break period, for 9600 baud.
789 * So dont bother disabling interrupts.
790 * But dont want more than 1 break event.
791 * Use a kernel timer to periodically poll the rx line until
792 * the break is finished.
793 */
94c8b6db 794static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 795{
bc9b3f5c 796 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 797}
94c8b6db 798
1da177e4
LT		 799/* Ensure that two consecutive samples find the break over. */
800static void sci_break_timer(unsigned long data)
801{
e108b2ca
PM		 802 struct sci_port *port = (struct sci_port *)data;
803
804 if (sci_rxd_in(&port->port) == 0) {
1da177e4 805 port->break_flag = 1;
e108b2ca
PM		 806 sci_schedule_break_timer(port);
807 } else if (port->break_flag == 1) {
1da177e4
LT		 808 /* break is over. */
809 port->break_flag = 2;
e108b2ca
PM		 810 sci_schedule_break_timer(port);
811 } else
812 port->break_flag = 0;
1da177e4
LT		 813}
814
94c8b6db 815static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 816{
817 int copied = 0;
b12bb29f 818 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 819 struct tty_port *tport = &port->state->port;
debf9507 820 struct sci_port *s = to_sci_port(port);
1da177e4 821
3ae988d9 822 /* Handle overruns */
75c249fd 823 if (status & s->overrun_mask) {
3ae988d9 824 port->icount.overrun++;
d97fbbed 825
3ae988d9
LP		 826 /* overrun error */
827 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
828 copied++;
762c69e3 829
9b971cd2 830 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 831 }
832
e108b2ca 833 if (status & SCxSR_FER(port)) {
1da177e4
LT		 834 if (sci_rxd_in(port) == 0) {
835 /* Notify of BREAK */
e7c98dc7 836 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 837
838 if (!sci_port->break_flag) {
d97fbbed
PM		 839 port->icount.brk++;
840
e108b2ca
PM		 841 sci_port->break_flag = 1;
842 sci_schedule_break_timer(sci_port);
843
1da177e4 844 /* Do sysrq handling. */
e108b2ca 845 if (uart_handle_break(port))
1da177e4 846 return 0;
762c69e3
PM		 847
848 dev_dbg(port->dev, "BREAK detected\n");
849
92a19f9c 850 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 851 copied++;
852 }
853
e108b2ca 854 } else {
1da177e4 855 /* frame error */
d97fbbed
PM		 856 port->icount.frame++;
857
92a19f9c 858 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 859 copied++;
762c69e3
PM		 860
861 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 862 }
863 }
864
e108b2ca 865 if (status & SCxSR_PER(port)) {
1da177e4 866 /* parity error */
d97fbbed
PM		 867 port->icount.parity++;
868
92a19f9c 869 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 870 copied++;
762c69e3 871
9b971cd2 872 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 873 }
874
33f0f88f 875 if (copied)
2e124b4a 876 tty_flip_buffer_push(tport);
1da177e4
LT		 877
878 return copied;
879}
880
94c8b6db 881static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 882{
92a19f9c 883 struct tty_port *tport = &port->state->port;
debf9507 884 struct sci_port *s = to_sci_port(port);
d3184e68 885 const struct plat_sci_reg *reg;
2e0842a1 886 int copied = 0;
75c249fd 887 u16 status;
d830fa45 888
2e0842a1 889 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 890 if (!reg->size)
d830fa45
PM		 891 return 0;
892
2e0842a1 893 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 894 if (status & s->overrun_mask) {
895 status &= ~s->overrun_mask;
2e0842a1 896 serial_port_out(port, s->overrun_reg, status);
d830fa45 897
d97fbbed
PM		 898 port->icount.overrun++;
899
92a19f9c 900 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 901 tty_flip_buffer_push(tport);
d830fa45 902
51b31f1c 903 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 904 copied++;
905 }
906
907 return copied;
908}
909
94c8b6db 910static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 911{
912 int copied = 0;
b12bb29f 913 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 914 struct tty_port *tport = &port->state->port;
a5660ada 915 struct sci_port *s = to_sci_port(port);
1da177e4 916
0b3d4ef6
PM		 917 if (uart_handle_break(port))
918 return 0;
919
b7a76e4b 920 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 921#if defined(CONFIG_CPU_SH3)
922 /* Debounce break */
923 s->break_flag = 1;
924#endif
d97fbbed
PM		 925
926 port->icount.brk++;
927
1da177e4 928 /* Notify of BREAK */
92a19f9c 929 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 930 copied++;
762c69e3
PM		 931
932 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 933 }
934
33f0f88f 935 if (copied)
2e124b4a 936 tty_flip_buffer_push(tport);
e108b2ca 937
d830fa45
PM		 938 copied += sci_handle_fifo_overrun(port);
939
1da177e4
LT		 940 return copied;
941}
942
73a19e4c 943static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 944{
73a19e4c
GL		 945#ifdef CONFIG_SERIAL_SH_SCI_DMA
946 struct uart_port *port = ptr;
947 struct sci_port *s = to_sci_port(port);
948
949 if (s->chan_rx) {
b12bb29f
PM		 950 u16 scr = serial_port_in(port, SCSCR);
951 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 952
953 /* Disable future Rx interrupts */
d1d4b10c 954 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 955 disable_irq_nosync(irq);
26de4f1b 956 scr |= SCSCR_RDRQE;
3089f381 957 } else {
f43dc23d 958 scr &= ~SCSCR_RIE;
3089f381 959 }
b12bb29f 960 serial_port_out(port, SCSCR, scr);
73a19e4c 961 /* Clear current interrupt */
54af5001
GU		 962 serial_port_out(port, SCxSR,
963 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
3089f381
GL		 964 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
965 jiffies, s->rx_timeout);
966 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 967
968 return IRQ_HANDLED;
969 }
970#endif
971
1da177e4
LT		 972 /* I think sci_receive_chars has to be called irrespective
973 * of whether the I_IXOFF is set, otherwise, how is the interrupt
974 * to be disabled?
975 */
73a19e4c 976 sci_receive_chars(ptr);
1da177e4
LT		 977
978 return IRQ_HANDLED;
979}
980
7d12e780 981static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 982{
983 struct uart_port *port = ptr;
fd78a76a 984 unsigned long flags;
1da177e4 985
fd78a76a 986 spin_lock_irqsave(&port->lock, flags);
1da177e4 987 sci_transmit_chars(port);
fd78a76a 988 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 989
990 return IRQ_HANDLED;
991}
992
7d12e780 993static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 994{
995 struct uart_port *port = ptr;
e6403c11 996 struct sci_port *s = to_sci_port(port);
1da177e4
LT		 997
998 /* Handle errors */
999 if (port->type == PORT_SCI) {
1000 if (sci_handle_errors(port)) {
1001 /* discard character in rx buffer */
b12bb29f 1002 serial_port_in(port, SCxSR);
a1b5b43f 1003 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 1004 }
1005 } else {
d830fa45 1006 sci_handle_fifo_overrun(port);
e6403c11
GU		 1007 if (!s->chan_rx)
1008 sci_receive_chars(ptr);
1da177e4
LT		 1009 }
1010
a1b5b43f 1011 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 1012
1013 /* Kick the transmission */
8eadb56d
YS		 1014 if (!s->chan_tx)
1015 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 1016
1017 return IRQ_HANDLED;
1018}
1019
7d12e780 1020static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 1021{
1022 struct uart_port *port = ptr;
1023
1024 /* Handle BREAKs */
1025 sci_handle_breaks(port);
a1b5b43f 1026 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 1027
1028 return IRQ_HANDLED;
1029}
1030
f43dc23d
PM		 1031static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1032{
1033 /*
1034 * Not all ports (such as SCIFA) will support REIE. Rather than
1035 * special-casing the port type, we check the port initialization
1036 * IRQ enable mask to see whether the IRQ is desired at all. If
1037 * it's unset, it's logically inferred that there's no point in
1038 * testing for it.
1039 */
ce6738b6 1040 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 1041}
1042
7d12e780 1043static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 1044{
cb772fe7 1045 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
a8884e34 1046 struct uart_port *port = ptr;
73a19e4c 1047 struct sci_port *s = to_sci_port(port);
a8884e34 1048 irqreturn_t ret = IRQ_NONE;
1da177e4 1049
b12bb29f
PM		 1050 ssr_status = serial_port_in(port, SCxSR);
1051 scr_status = serial_port_in(port, SCSCR);
2e0842a1 1052 if (s->overrun_reg == SCxSR)
cb772fe7 1053 orer_status = ssr_status;
2e0842a1
GU		 1054 else {
1055 if (sci_getreg(port, s->overrun_reg)->size)
1056 orer_status = serial_port_in(port, s->overrun_reg);
cb772fe7
NI		 1057 }
1058
f43dc23d 1059 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 1060
1061 /* Tx Interrupt */
f43dc23d 1062 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 1063 !s->chan_tx)
a8884e34 1064 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 1065
73a19e4c
GL		 1066 /*
1067 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1068 * DR flags
1069 */
1070 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
e0a12a27 1071 (scr_status & SCSCR_RIE))
a8884e34 1072 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1073
1da177e4 1074 /* Error Interrupt */
dd4da3a5 1075 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1076 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1077
1da177e4 1078 /* Break Interrupt */
dd4da3a5 1079 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1080 ret = sci_br_interrupt(irq, ptr);
1da177e4 1081
8b6ff84c 1082 /* Overrun Interrupt */
90803072 1083 if (orer_status & s->overrun_mask) {
cb772fe7 1084 sci_handle_fifo_overrun(port);
90803072
YS		 1085 ret = IRQ_HANDLED;
1086 }
8b6ff84c 1087
a8884e34 1088 return ret;
1da177e4
LT		 1089}
1090
1da177e4 1091/*
25985edc 1092 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1093 * ports' baud rate when the peripheral clock changes.
1094 */
e108b2ca
PM		 1095static int sci_notifier(struct notifier_block *self,
1096 unsigned long phase, void *p)
1da177e4 1097{
e552de24
MD		 1098 struct sci_port *sci_port;
1099 unsigned long flags;
1da177e4 1100
d535a230
PM		 1101 sci_port = container_of(self, struct sci_port, freq_transition);
1102
0b443ead 1103 if (phase == CPUFREQ_POSTCHANGE) {
d535a230 1104 struct uart_port *port = &sci_port->port;
073e84c9 1105
d535a230
PM		 1106 spin_lock_irqsave(&port->lock, flags);
1107 port->uartclk = clk_get_rate(sci_port->iclk);
1108 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1109 }
1da177e4 1110
1da177e4
LT		 1111 return NOTIFY_OK;
1112}
501b825d 1113
d56a91e8 1114static const struct sci_irq_desc {
9174fc8f
PM		 1115 const char *desc;
1116 irq_handler_t handler;
1117} sci_irq_desc[] = {
1118 /*
1119 * Split out handlers, the default case.
1120 */
1121 [SCIx_ERI_IRQ] = {
1122 .desc = "rx err",
1123 .handler = sci_er_interrupt,
1124 },
1125
1126 [SCIx_RXI_IRQ] = {
1127 .desc = "rx full",
1128 .handler = sci_rx_interrupt,
1129 },
1130
1131 [SCIx_TXI_IRQ] = {
1132 .desc = "tx empty",
1133 .handler = sci_tx_interrupt,
1134 },
1135
1136 [SCIx_BRI_IRQ] = {
1137 .desc = "break",
1138 .handler = sci_br_interrupt,
1139 },
1140
1141 /*
1142 * Special muxed handler.
1143 */
1144 [SCIx_MUX_IRQ] = {
1145 .desc = "mux",
1146 .handler = sci_mpxed_interrupt,
1147 },
1148};
1149
1da177e4
LT		 1150static int sci_request_irq(struct sci_port *port)
1151{
9174fc8f
PM		 1152 struct uart_port *up = &port->port;
1153 int i, j, ret = 0;
1154
1155 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
d56a91e8 1156 const struct sci_irq_desc *desc;
1fcc91a6 1157 int irq;
9174fc8f
PM		 1158
1159 if (SCIx_IRQ_IS_MUXED(port)) {
1160 i = SCIx_MUX_IRQ;
1161 irq = up->irq;
0e8963de 1162 } else {
1fcc91a6 1163 irq = port->irqs[i];
9174fc8f 1164
0e8963de
PM		 1165 /*
1166 * Certain port types won't support all of the
1167 * available interrupt sources.
1168 */
1fcc91a6 1169 if (unlikely(irq < 0))
0e8963de
PM		 1170 continue;
1171 }
1172
9174fc8f
PM		 1173 desc = sci_irq_desc + i;
1174 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1175 dev_name(up->dev), desc->desc);
4205463c 1176 if (!port->irqstr[j])
9174fc8f 1177 goto out_nomem;
9174fc8f
PM		 1178
1179 ret = request_irq(irq, desc->handler, up->irqflags,
1180 port->irqstr[j], port);
1181 if (unlikely(ret)) {
1182 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1183 goto out_noirq;
1da177e4
LT		 1184 }
1185 }
1186
1187 return 0;
9174fc8f
PM		 1188
1189out_noirq:
1190 while (--i >= 0)
1fcc91a6 1191 free_irq(port->irqs[i], port);
9174fc8f
PM		 1192
1193out_nomem:
1194 while (--j >= 0)
1195 kfree(port->irqstr[j]);
1196
1197 return ret;
1da177e4
LT		 1198}
1199
1200static void sci_free_irq(struct sci_port *port)
1201{
1202 int i;
1203
9174fc8f
PM		 1204 /*
1205 * Intentionally in reverse order so we iterate over the muxed
1206 * IRQ first.
1207 */
1208 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1209 int irq = port->irqs[i];
0e8963de
PM		 1210
1211 /*
1212 * Certain port types won't support all of the available
1213 * interrupt sources.
1214 */
1fcc91a6 1215 if (unlikely(irq < 0))
0e8963de
PM		 1216 continue;
1217
1fcc91a6 1218 free_irq(port->irqs[i], port);
9174fc8f 1219 kfree(port->irqstr[i]);
1da177e4 1220
9174fc8f
PM		 1221 if (SCIx_IRQ_IS_MUXED(port)) {
1222 /* If there's only one IRQ, we're done. */
1223 return;
1da177e4
LT		 1224 }
1225 }
1226}
1227
1228static unsigned int sci_tx_empty(struct uart_port *port)
1229{
b12bb29f 1230 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1231 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1232
1233 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1234}
1235
cdf7c42f
PM		 1236/*
1237 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1238 * CTS/RTS is supported in hardware by at least one port and controlled
1239 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1240 * handled via the ->init_pins() op, which is a bit of a one-way street,
1241 * lacking any ability to defer pin control -- this will later be
1242 * converted over to the GPIO framework).
dc7e3ef7
PM		 1243 *
1244 * Other modes (such as loopback) are supported generically on certain
1245 * port types, but not others. For these it's sufficient to test for the
1246 * existence of the support register and simply ignore the port type.
cdf7c42f 1247 */
1da177e4
LT		 1248static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1249{
dc7e3ef7 1250 if (mctrl & TIOCM_LOOP) {
d3184e68 1251 const struct plat_sci_reg *reg;
dc7e3ef7
PM		 1252
1253 /*
1254 * Standard loopback mode for SCFCR ports.
1255 */
1256 reg = sci_getreg(port, SCFCR);
1257 if (reg->size)
26de4f1b
GU		 1258 serial_port_out(port, SCFCR,
1259 serial_port_in(port, SCFCR) |
1260 SCFCR_LOOP);
dc7e3ef7 1261 }
1da177e4
LT		 1262}
1263
1264static unsigned int sci_get_mctrl(struct uart_port *port)
1265{
cdf7c42f
PM		 1266 /*
1267 * CTS/RTS is handled in hardware when supported, while nothing
1268 * else is wired up. Keep it simple and simply assert DSR/CAR.
1269 */
1270 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1271}
1272
73a19e4c
GL		 1273#ifdef CONFIG_SERIAL_SH_SCI_DMA
1274static void sci_dma_tx_complete(void *arg)
1275{
1276 struct sci_port *s = arg;
1277 struct uart_port *port = &s->port;
1278 struct circ_buf *xmit = &port->state->xmit;
1279 unsigned long flags;
1280
1281 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1282
1283 spin_lock_irqsave(&port->lock, flags);
1284
79904420 1285 xmit->tail += s->tx_dma_len;
73a19e4c
GL		 1286 xmit->tail &= UART_XMIT_SIZE - 1;
1287
79904420 1288 port->icount.tx += s->tx_dma_len;
73a19e4c 1289
73a19e4c
GL		 1290 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1291 uart_write_wakeup(port);
1292
3089f381 1293 if (!uart_circ_empty(xmit)) {
49d4bcad 1294 s->cookie_tx = 0;
73a19e4c 1295 schedule_work(&s->work_tx);
49d4bcad
YT		 1296 } else {
1297 s->cookie_tx = -EINVAL;
1298 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1299 u16 ctrl = serial_port_in(port, SCSCR);
1300 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1301 }
3089f381
GL		 1302 }
1303
1304 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1305}
1306
1307/* Locking: called with port lock held */
7b39d901 1308static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
73a19e4c
GL		 1309{
1310 struct uart_port *port = &s->port;
227434f8 1311 struct tty_port *tport = &port->state->port;
47b0e94a 1312 int copied;
73a19e4c 1313
7b39d901 1314 copied = tty_insert_flip_string(tport, buf, count);
47b0e94a 1315 if (copied < count) {
e2afca69 1316 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
47b0e94a
GU		 1317 count - copied);
1318 port->icount.buf_overrun++;
1319 }
73a19e4c 1320
47b0e94a 1321 port->icount.rx += copied;
73a19e4c 1322
47b0e94a 1323 return copied;
73a19e4c
GL		 1324}
1325
0533502d
GU		 1326static int sci_dma_rx_find_active(struct sci_port *s)
1327{
1328 unsigned int i;
1329
1330 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1331 if (s->active_rx == s->cookie_rx[i])
1332 return i;
1333
1334 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1335 s->active_rx);
1336 return -1;
1337}
1338
73a19e4c
GL		 1339static void sci_dma_rx_complete(void *arg)
1340{
1341 struct sci_port *s = arg;
1342 struct uart_port *port = &s->port;
73a19e4c 1343 unsigned long flags;
0533502d 1344 int active, count = 0;
73a19e4c 1345
beb9487b
GU		 1346 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1347 s->active_rx);
73a19e4c
GL		 1348
1349 spin_lock_irqsave(&port->lock, flags);
1350
0533502d
GU		 1351 active = sci_dma_rx_find_active(s);
1352 if (active >= 0)
7b39d901 1353 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
73a19e4c 1354
3089f381 1355 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1356
1357 spin_unlock_irqrestore(&port->lock, flags);
1358
1359 if (count)
2e124b4a 1360 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1361
1362 schedule_work(&s->work_rx);
1363}
1364
73a19e4c
GL		 1365static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1366{
1367 struct dma_chan *chan = s->chan_rx;
1368 struct uart_port *port = &s->port;
04928b79 1369 unsigned long flags;
73a19e4c 1370
04928b79 1371 spin_lock_irqsave(&port->lock, flags);
73a19e4c
GL		 1372 s->chan_rx = NULL;
1373 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
04928b79
GU		 1374 spin_unlock_irqrestore(&port->lock, flags);
1375 dmaengine_terminate_all(chan);
7b39d901
YS		 1376 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1377 sg_dma_address(&s->sg_rx[0]));
8e14ba8f 1378 dma_release_channel(chan);
73a19e4c
GL		 1379 if (enable_pio)
1380 sci_start_rx(port);
1381}
1382
1383static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1384{
1385 struct dma_chan *chan = s->chan_tx;
1386 struct uart_port *port = &s->port;
04928b79 1387 unsigned long flags;
73a19e4c 1388
04928b79 1389 spin_lock_irqsave(&port->lock, flags);
73a19e4c
GL		 1390 s->chan_tx = NULL;
1391 s->cookie_tx = -EINVAL;
04928b79
GU		 1392 spin_unlock_irqrestore(&port->lock, flags);
1393 dmaengine_terminate_all(chan);
2e301474
GU		 1394 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1395 DMA_TO_DEVICE);
73a19e4c
GL		 1396 dma_release_channel(chan);
1397 if (enable_pio)
1398 sci_start_tx(port);
1399}
1400
1401static void sci_submit_rx(struct sci_port *s)
1402{
1403 struct dma_chan *chan = s->chan_rx;
1404 int i;
1405
1406 for (i = 0; i < 2; i++) {
1407 struct scatterlist *sg = &s->sg_rx[i];
1408 struct dma_async_tx_descriptor *desc;
1409
16052827 1410 desc = dmaengine_prep_slave_sg(chan,
47aceb92
GU		 1411 sg, 1, DMA_DEV_TO_MEM,
1412 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
658daa95
GU		 1413 if (!desc)
1414 goto fail;
73a19e4c 1415
658daa95
GU		 1416 desc->callback = sci_dma_rx_complete;
1417 desc->callback_param = s;
1418 s->cookie_rx[i] = dmaengine_submit(desc);
1419 if (dma_submit_error(s->cookie_rx[i]))
1420 goto fail;
73a19e4c 1421
beb9487b
GU		 1422 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1423 s->cookie_rx[i], i);
73a19e4c
GL		 1424 }
1425
1426 s->active_rx = s->cookie_rx[0];
1427
1428 dma_async_issue_pending(chan);
658daa95
GU		 1429 return;
1430
1431fail:
1432 if (i)
1433 dmaengine_terminate_all(chan);
47aceb92 1434 for (i = 0; i < 2; i++)
658daa95 1435 s->cookie_rx[i] = -EINVAL;
658daa95
GU		 1436 s->active_rx = -EINVAL;
1437 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1438 sci_rx_dma_release(s, true);
73a19e4c
GL		 1439}
1440
1441static void work_fn_rx(struct work_struct *work)
1442{
1443 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1444 struct uart_port *port = &s->port;
1445 struct dma_async_tx_descriptor *desc;
565dd11a
GU		 1446 struct dma_tx_state state;
1447 enum dma_status status;
0907c100 1448 unsigned long flags;
73a19e4c
GL		 1449 int new;
1450
0907c100 1451 spin_lock_irqsave(&port->lock, flags);
0533502d
GU		 1452 new = sci_dma_rx_find_active(s);
1453 if (new < 0) {
04928b79
GU		 1454 spin_unlock_irqrestore(&port->lock, flags);
1455 return;
73a19e4c 1456 }
73a19e4c 1457
565dd11a
GU		 1458 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1459 if (status != DMA_COMPLETE) {
73a19e4c 1460 /* Handle incomplete DMA receive */
73a19e4c 1461 struct dma_chan *chan = s->chan_rx;
565dd11a 1462 unsigned int read;
73a19e4c
GL		 1463 int count;
1464
2bcd90d5 1465 dmaengine_terminate_all(chan);
565dd11a
GU		 1466 read = sg_dma_len(&s->sg_rx[new]) - state.residue;
1467 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1468 s->active_rx);
73a19e4c 1469
99dc8e40
GU		 1470 if (read) {
1471 count = sci_dma_rx_push(s, s->rx_buf[new], read);
1472 if (count)
1473 tty_flip_buffer_push(&port->state->port);
1474 }
73a19e4c 1475
04928b79 1476 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c 1477
04928b79
GU		 1478 sci_submit_rx(s);
1479 return;
73a19e4c
GL		 1480 }
1481
47aceb92
GU		 1482 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[new], 1,
1483 DMA_DEV_TO_MEM,
1484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1485 if (!desc)
1486 goto fail;
1487
1488 desc->callback = sci_dma_rx_complete;
1489 desc->callback_param = s;
3e14670c 1490 s->cookie_rx[new] = dmaengine_submit(desc);
47aceb92
GU		 1491 if (dma_submit_error(s->cookie_rx[new]))
1492 goto fail;
73a19e4c 1493
73a19e4c 1494 s->active_rx = s->cookie_rx[!new];
3089f381 1495
beb9487b 1496 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
9b971cd2 1497 __func__, s->cookie_rx[new], new, s->active_rx);
0907c100 1498 spin_unlock_irqrestore(&port->lock, flags);
47aceb92
GU		 1499 return;
1500
1501fail:
04928b79 1502 spin_unlock_irqrestore(&port->lock, flags);
47aceb92
GU		 1503 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1504 sci_rx_dma_release(s, true);
73a19e4c
GL		 1505}
1506
1507static void work_fn_tx(struct work_struct *work)
1508{
1509 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1510 struct dma_async_tx_descriptor *desc;
1511 struct dma_chan *chan = s->chan_tx;
1512 struct uart_port *port = &s->port;
1513 struct circ_buf *xmit = &port->state->xmit;
79904420 1514 dma_addr_t buf;
73a19e4c
GL		 1515
1516 /*
1517 * DMA is idle now.
1518 * Port xmit buffer is already mapped, and it is one page... Just adjust
1519 * offsets and lengths. Since it is a circular buffer, we have to
1520 * transmit till the end, and then the rest. Take the port lock to get a
1521 * consistent xmit buffer state.
1522 */
1523 spin_lock_irq(&port->lock);
79904420
GU		 1524 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1525 s->tx_dma_len = min_t(unsigned int,
092248aa 1526 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1527 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1528 spin_unlock_irq(&port->lock);
1529
79904420
GU		 1530 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1531 DMA_MEM_TO_DEV,
1532 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
73a19e4c 1533 if (!desc) {
beb9487b 1534 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
73a19e4c
GL		 1535 /* switch to PIO */
1536 sci_tx_dma_release(s, true);
1537 return;
1538 }
1539
79904420
GU		 1540 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1541 DMA_TO_DEVICE);
73a19e4c
GL		 1542
1543 spin_lock_irq(&port->lock);
73a19e4c
GL		 1544 desc->callback = sci_dma_tx_complete;
1545 desc->callback_param = s;
1546 spin_unlock_irq(&port->lock);
3e14670c
GU		 1547 s->cookie_tx = dmaengine_submit(desc);
1548 if (dma_submit_error(s->cookie_tx)) {
73a19e4c
GL		 1549 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1550 /* switch to PIO */
1551 sci_tx_dma_release(s, true);
1552 return;
1553 }
1554
9b971cd2
JP		 1555 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1556 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c
GL		 1557
1558 dma_async_issue_pending(chan);
1559}
1560#endif
1561
b129a8cc 1562static void sci_start_tx(struct uart_port *port)
1da177e4 1563{
3089f381 1564 struct sci_port *s = to_sci_port(port);
e108b2ca 1565 unsigned short ctrl;
1da177e4 1566
73a19e4c 1567#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1568 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1569 u16 new, scr = serial_port_in(port, SCSCR);
3089f381 1570 if (s->chan_tx)
26de4f1b 1571 new = scr | SCSCR_TDRQE;
3089f381 1572 else
26de4f1b 1573 new = scr & ~SCSCR_TDRQE;
3089f381 1574 if (new != scr)
b12bb29f 1575 serial_port_out(port, SCSCR, new);
73a19e4c 1576 }
f43dc23d 1577
3089f381 1578 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
3e14670c 1579 dma_submit_error(s->cookie_tx)) {
49d4bcad 1580 s->cookie_tx = 0;
3089f381 1581 schedule_work(&s->work_tx);
49d4bcad 1582 }
73a19e4c 1583#endif
f43dc23d 1584
d1d4b10c 1585 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1586 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1587 ctrl = serial_port_in(port, SCSCR);
1588 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1589 }
1da177e4
LT		 1590}
1591
b129a8cc 1592static void sci_stop_tx(struct uart_port *port)
1da177e4 1593{
1da177e4
LT		 1594 unsigned short ctrl;
1595
1596 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1597 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1598
d1d4b10c 1599 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1600 ctrl &= ~SCSCR_TDRQE;
f43dc23d 1601
8e698614 1602 ctrl &= ~SCSCR_TIE;
f43dc23d 1603
b12bb29f 1604 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1605}
1606
73a19e4c 1607static void sci_start_rx(struct uart_port *port)
1da177e4 1608{
1da177e4
LT		 1609 unsigned short ctrl;
1610
b12bb29f 1611 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1612
d1d4b10c 1613 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1614 ctrl &= ~SCSCR_RDRQE;
f43dc23d 1615
b12bb29f 1616 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1617}
1618
1619static void sci_stop_rx(struct uart_port *port)
1620{
1da177e4
LT		 1621 unsigned short ctrl;
1622
b12bb29f 1623 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1624
d1d4b10c 1625 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1626 ctrl &= ~SCSCR_RDRQE;
f43dc23d
PM		 1627
1628 ctrl &= ~port_rx_irq_mask(port);
1629
b12bb29f 1630 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1631}
1632
1da177e4
LT		 1633static void sci_break_ctl(struct uart_port *port, int break_state)
1634{
bbb4ce50 1635 struct sci_port *s = to_sci_port(port);
d3184e68 1636 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1637 unsigned short scscr, scsptr;
1638
a4e02f6d
SY		 1639 /* check wheter the port has SCSPTR */
1640 if (!reg->size) {
bbb4ce50
SY		 1641 /*
1642 * Not supported by hardware. Most parts couple break and rx
1643 * interrupts together, with break detection always enabled.
1644 */
a4e02f6d 1645 return;
bbb4ce50 1646 }
a4e02f6d
SY		 1647
1648 scsptr = serial_port_in(port, SCSPTR);
1649 scscr = serial_port_in(port, SCSCR);
1650
1651 if (break_state == -1) {
1652 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1653 scscr &= ~SCSCR_TE;
1654 } else {
1655 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1656 scscr |= SCSCR_TE;
1657 }
1658
1659 serial_port_out(port, SCSPTR, scsptr);
1660 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1661}
1662
73a19e4c
GL		 1663#ifdef CONFIG_SERIAL_SH_SCI_DMA
1664static bool filter(struct dma_chan *chan, void *slave)
1665{
1666 struct sh_dmae_slave *param = slave;
1667
9b971cd2
JP		 1668 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1669 __func__, param->shdma_slave.slave_id);
73a19e4c 1670
d6fa5a4e 1671 chan->private = &param->shdma_slave;
937bb6e4 1672 return true;
73a19e4c
GL		 1673}
1674
1675static void rx_timer_fn(unsigned long arg)
1676{
1677 struct sci_port *s = (struct sci_port *)arg;
1678 struct uart_port *port = &s->port;
b12bb29f 1679 u16 scr = serial_port_in(port, SCSCR);
3089f381 1680
d1d4b10c 1681 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
26de4f1b 1682 scr &= ~SCSCR_RDRQE;
1fcc91a6 1683 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1684 }
b12bb29f 1685 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1686 dev_dbg(port->dev, "DMA Rx timed out\n");
1687 schedule_work(&s->work_rx);
1688}
1689
1690static void sci_request_dma(struct uart_port *port)
1691{
1692 struct sci_port *s = to_sci_port(port);
1693 struct sh_dmae_slave *param;
1694 struct dma_chan *chan;
1695 dma_cap_mask_t mask;
73a19e4c 1696
9b971cd2 1697 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1698
937bb6e4 1699 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1700 return;
1701
1702 dma_cap_zero(mask);
1703 dma_cap_set(DMA_SLAVE, mask);
1704
1705 param = &s->param_tx;
1706
1707 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1708 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1709
1710 s->cookie_tx = -EINVAL;
1711 chan = dma_request_channel(mask, filter, param);
1712 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1713 if (chan) {
1714 s->chan_tx = chan;
73a19e4c 1715 /* UART circular tx buffer is an aligned page. */
79904420
GU		 1716 s->tx_dma_addr = dma_map_single(chan->device->dev,
1717 port->state->xmit.buf,
1718 UART_XMIT_SIZE,
1719 DMA_TO_DEVICE);
1720 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
beb9487b 1721 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
b9258020
GU		 1722 dma_release_channel(chan);
1723 s->chan_tx = NULL;
beb9487b 1724 } else {
79904420
GU		 1725 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1726 __func__, UART_XMIT_SIZE,
1727 port->state->xmit.buf, &s->tx_dma_addr);
beb9487b 1728 }
73a19e4c 1729
73a19e4c
GL		 1730 INIT_WORK(&s->work_tx, work_fn_tx);
1731 }
1732
1733 param = &s->param_rx;
1734
1735 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1736 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1737
1738 chan = dma_request_channel(mask, filter, param);
1739 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1740 if (chan) {
ba172c70
GU		 1741 unsigned int i;
1742 dma_addr_t dma;
1743 void *buf;
73a19e4c
GL		 1744
1745 s->chan_rx = chan;
1746
092248aa 1747 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
ba172c70
GU		 1748 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1749 &dma, GFP_KERNEL);
1750 if (!buf) {
73a19e4c 1751 dev_warn(port->dev,
beb9487b 1752 "Failed to allocate Rx dma buffer, using PIO\n");
b9258020
GU		 1753 dma_release_channel(chan);
1754 s->chan_rx = NULL;
1755 sci_start_rx(port);
73a19e4c
GL		 1756 return;
1757 }
1758
73a19e4c
GL		 1759 for (i = 0; i < 2; i++) {
1760 struct scatterlist *sg = &s->sg_rx[i];
1761
1762 sg_init_table(sg, 1);
7b39d901 1763 s->rx_buf[i] = buf;
ba172c70 1764 sg_dma_address(sg) = dma;
7b39d901 1765 sg->length = s->buf_len_rx;
ba172c70
GU		 1766
1767 buf += s->buf_len_rx;
1768 dma += s->buf_len_rx;
73a19e4c
GL		 1769 }
1770
1771 INIT_WORK(&s->work_rx, work_fn_rx);
1772 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1773
1774 sci_submit_rx(s);
1775 }
1776}
1777
1778static void sci_free_dma(struct uart_port *port)
1779{
1780 struct sci_port *s = to_sci_port(port);
1781
73a19e4c
GL		 1782 if (s->chan_tx)
1783 sci_tx_dma_release(s, false);
1784 if (s->chan_rx)
1785 sci_rx_dma_release(s, false);
1786}
27bd1075
PM		 1787#else
1788static inline void sci_request_dma(struct uart_port *port)
1789{
1790}
1791
1792static inline void sci_free_dma(struct uart_port *port)
1793{
1794}
73a19e4c
GL		 1795#endif
1796
1da177e4
LT		 1797static int sci_startup(struct uart_port *port)
1798{
a5660ada 1799 struct sci_port *s = to_sci_port(port);
33b48e16 1800 unsigned long flags;
073e84c9 1801 int ret;
1da177e4 1802
73a19e4c
GL		 1803 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1804
073e84c9
PM		 1805 ret = sci_request_irq(s);
1806 if (unlikely(ret < 0))
1807 return ret;
1808
73a19e4c 1809 sci_request_dma(port);
073e84c9 1810
33b48e16 1811 spin_lock_irqsave(&port->lock, flags);
d656901b 1812 sci_start_tx(port);
73a19e4c 1813 sci_start_rx(port);
33b48e16 1814 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1815
1816 return 0;
1817}
1818
1819static void sci_shutdown(struct uart_port *port)
1820{
a5660ada 1821 struct sci_port *s = to_sci_port(port);
33b48e16 1822 unsigned long flags;
1da177e4 1823
73a19e4c
GL		 1824 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1825
33b48e16 1826 spin_lock_irqsave(&port->lock, flags);
1da177e4 1827 sci_stop_rx(port);
b129a8cc 1828 sci_stop_tx(port);
33b48e16 1829 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1830
73a19e4c 1831 sci_free_dma(port);
1da177e4 1832 sci_free_irq(s);
1da177e4
LT		 1833}
1834
ec09c5eb 1835static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1836 unsigned long freq)
1837{
ec09c5eb
LP		 1838 if (s->sampling_rate)
1839 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1840
26c92f37
PM		 1841 /* Warn, but use a safe default */
1842 WARN_ON(1);
e8183a6c 1843
26c92f37
PM		 1844 return ((freq + 16 * bps) / (32 * bps) - 1);
1845}
1846
730c4e78
NI		 1847/* calculate frame length from SMR */
1848static int sci_baud_calc_frame_len(unsigned int smr_val)
1849{
1850 int len = 10;
1851
1852 if (smr_val & SCSMR_CHR)
1853 len--;
1854 if (smr_val & SCSMR_PE)
1855 len++;
1856 if (smr_val & SCSMR_STOP)
1857 len++;
1858
1859 return len;
1860}
1861
1862
f303b364
UH		 1863/* calculate sample rate, BRR, and clock select for HSCIF */
1864static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1865 int *brr, unsigned int *srr,
730c4e78 1866 unsigned int *cks, int frame_len)
f303b364 1867{
730c4e78 1868 int sr, c, br, err, recv_margin;
f303b364 1869 int min_err = 1000; /* 100% */
730c4e78 1870 int recv_max_margin = 0;
f303b364
UH		 1871
1872 /* Find the combination of sample rate and clock select with the
1873 smallest deviation from the desired baud rate. */
1874 for (sr = 8; sr <= 32; sr++) {
1875 for (c = 0; c <= 3; c++) {
1876 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1877 br = DIV_ROUND_CLOSEST(freq, (sr *
1878 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1879 br = clamp(br, 0, 255);
b7d66397
NI		 1880 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1881 (1 << (2 * c + 1)) / 1000)) -
1882 1000;
730c4e78
NI		 1883 /* Calc recv margin
1884 * M: Receive margin (%)
1885 * N: Ratio of bit rate to clock (N = sampling rate)
1886 * D: Clock duty (D = 0 to 1.0)
1887 * L: Frame length (L = 9 to 12)
1888 * F: Absolute value of clock frequency deviation
1889 *
1890 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1891 * (|D - 0.5| / N * (1 + F))|
1892 * NOTE: Usually, treat D for 0.5, F is 0 by this
1893 * calculation.
1894 */
1895 recv_margin = abs((500 -
1896 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1897 if (abs(min_err) > abs(err)) {
f303b364 1898 min_err = err;
730c4e78
NI		 1899 recv_max_margin = recv_margin;
1900 } else if ((min_err == err) &&
1901 (recv_margin > recv_max_margin))
1902 recv_max_margin = recv_margin;
1903 else
1904 continue;
1905
1906 *brr = br;
1907 *srr = sr - 1;
1908 *cks = c;
f303b364
UH		 1909 }
1910 }
1911
1912 if (min_err == 1000) {
1913 WARN_ON(1);
1914 /* use defaults */
1915 *brr = 255;
1916 *srr = 15;
1917 *cks = 0;
1918 }
1919}
1920
1ba76220
MD		 1921static void sci_reset(struct uart_port *port)
1922{
d3184e68 1923 const struct plat_sci_reg *reg;
1ba76220
MD		 1924 unsigned int status;
1925
1926 do {
b12bb29f 1927 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1928 } while (!(status & SCxSR_TEND(port)));
1929
b12bb29f 1930 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1931
0979e0e6
PM		 1932 reg = sci_getreg(port, SCFCR);
1933 if (reg->size)
b12bb29f 1934 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1935}
1936
606d099c
AC		 1937static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1938 struct ktermios *old)
1da177e4 1939{
00b9de9c 1940 struct sci_port *s = to_sci_port(port);
d3184e68 1941 const struct plat_sci_reg *reg;
730c4e78 1942 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1943 int t = -1;
d4759ded 1944 unsigned int srr = 15;
1da177e4 1945
730c4e78
NI		 1946 if ((termios->c_cflag & CSIZE) == CS7)
1947 smr_val |= SCSMR_CHR;
1948 if (termios->c_cflag & PARENB)
1949 smr_val |= SCSMR_PE;
1950 if (termios->c_cflag & PARODD)
1951 smr_val |= SCSMR_PE | SCSMR_ODD;
1952 if (termios->c_cflag & CSTOPB)
1953 smr_val |= SCSMR_STOP;
1954
154280fd
MD		 1955 /*
1956 * earlyprintk comes here early on with port->uartclk set to zero.
1957 * the clock framework is not up and running at this point so here
1958 * we assume that 115200 is the maximum baud rate. please note that
1959 * the baud rate is not programmed during earlyprintk - it is assumed
1960 * that the previous boot loader has enabled required clocks and
1961 * setup the baud rate generator hardware for us already.
1962 */
1963 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1964
154280fd 1965 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1966 if (likely(baud && port->uartclk)) {
ec09c5eb 1967 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1968 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1969 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1970 &cks, frame_len);
f303b364 1971 } else {
ec09c5eb 1972 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1973 for (cks = 0; t >= 256 && cks <= 3; cks++)
1974 t >>= 2;
1975 }
1976 }
e108b2ca 1977
23241d43 1978 sci_port_enable(s);
36003386 1979
1ba76220 1980 sci_reset(port);
1da177e4 1981
2944a331 1982 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 1983
1984 uart_update_timeout(port, termios->c_cflag, baud);
1985
9d482cc3
TY		 1986 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1987 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1988
4ffc3cdb 1989 if (t >= 0) {
26de4f1b 1990 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1991 serial_port_out(port, SCBRR, t);
f303b364
UH		 1992 reg = sci_getreg(port, HSSRR);
1993 if (reg->size)
1994 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1995 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1996 } else
1997 serial_port_out(port, SCSMR, smr_val);
1da177e4 1998
d5701647 1999 sci_init_pins(port, termios->c_cflag);
0979e0e6 2000
73c3d53f
PM		 2001 reg = sci_getreg(port, SCFCR);
2002 if (reg->size) {
b12bb29f 2003 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2004
73c3d53f 2005 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2006 if (termios->c_cflag & CRTSCTS)
2007 ctrl |= SCFCR_MCE;
2008 else
2009 ctrl &= ~SCFCR_MCE;
faf02f8f 2010 }
73c3d53f
PM		 2011
2012 /*
2013 * As we've done a sci_reset() above, ensure we don't
2014 * interfere with the FIFOs while toggling MCE. As the
2015 * reset values could still be set, simply mask them out.
2016 */
2017 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2018
b12bb29f 2019 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2020 }
b7a76e4b 2021
b12bb29f 2022 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2023
3089f381
GL		 2024#ifdef CONFIG_SERIAL_SH_SCI_DMA
2025 /*
5f6d8515 2026 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2027 * See serial_core.c::uart_update_timeout().
2028 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2029 * function calculates 1 jiffie for the data plus 5 jiffies for the
2030 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2031 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2032 * value obtained by this formula is too small. Therefore, if the value
2033 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2034 */
2035 if (s->chan_rx) {
5f6d8515
NI		 2036 unsigned int bits;
2037
2038 /* byte size and parity */
2039 switch (termios->c_cflag & CSIZE) {
2040 case CS5:
2041 bits = 7;
2042 break;
2043 case CS6:
2044 bits = 8;
2045 break;
2046 case CS7:
2047 bits = 9;
2048 break;
2049 default:
2050 bits = 10;
2051 break;
2052 }
2053
2054 if (termios->c_cflag & CSTOPB)
2055 bits++;
2056 if (termios->c_cflag & PARENB)
2057 bits++;
2058 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2059 (baud / 10), 10);
9b971cd2 2060 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2061 s->rx_timeout * 1000 / HZ, port->timeout);
2062 if (s->rx_timeout < msecs_to_jiffies(20))
2063 s->rx_timeout = msecs_to_jiffies(20);
2064 }
2065#endif
2066
1da177e4 2067 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2068 sci_start_rx(port);
36003386 2069
23241d43 2070 sci_port_disable(s);
1da177e4
LT		 2071}
2072
0174e5ca
TK		 2073static void sci_pm(struct uart_port *port, unsigned int state,
2074 unsigned int oldstate)
2075{
2076 struct sci_port *sci_port = to_sci_port(port);
2077
2078 switch (state) {
d3dfe5d9 2079 case UART_PM_STATE_OFF:
0174e5ca
TK		 2080 sci_port_disable(sci_port);
2081 break;
2082 default:
2083 sci_port_enable(sci_port);
2084 break;
2085 }
2086}
2087
1da177e4
LT		 2088static const char *sci_type(struct uart_port *port)
2089{
2090 switch (port->type) {
e7c98dc7
MT		 2091 case PORT_IRDA:
2092 return "irda";
2093 case PORT_SCI:
2094 return "sci";
2095 case PORT_SCIF:
2096 return "scif";
2097 case PORT_SCIFA:
2098 return "scifa";
d1d4b10c
GL		 2099 case PORT_SCIFB:
2100 return "scifb";
f303b364
UH		 2101 case PORT_HSCIF:
2102 return "hscif";
1da177e4
LT		 2103 }
2104
fa43972f 2105 return NULL;
1da177e4
LT		 2106}
2107
f6e9495d
PM		 2108static int sci_remap_port(struct uart_port *port)
2109{
e4d6f911 2110 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2111
2112 /*
2113 * Nothing to do if there's already an established membase.
2114 */
2115 if (port->membase)
2116 return 0;
2117
2118 if (port->flags & UPF_IOREMAP) {
e4d6f911 2119 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2120 if (unlikely(!port->membase)) {
2121 dev_err(port->dev, "can't remap port#%d\n", port->line);
2122 return -ENXIO;
2123 }
2124 } else {
2125 /*
2126 * For the simple (and majority of) cases where we don't
2127 * need to do any remapping, just cast the cookie
2128 * directly.
2129 */
3af4e960 2130 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2131 }
2132
2133 return 0;
2134}
2135
e2651647 2136static void sci_release_port(struct uart_port *port)
1da177e4 2137{
e4d6f911
YS		 2138 struct sci_port *sport = to_sci_port(port);
2139
e2651647
PM		 2140 if (port->flags & UPF_IOREMAP) {
2141 iounmap(port->membase);
2142 port->membase = NULL;
2143 }
2144
e4d6f911 2145 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2146}
2147
e2651647 2148static int sci_request_port(struct uart_port *port)
1da177e4 2149{
e2651647 2150 struct resource *res;
e4d6f911 2151 struct sci_port *sport = to_sci_port(port);
f6e9495d 2152 int ret;
1da177e4 2153
e4d6f911
YS		 2154 res = request_mem_region(port->mapbase, sport->reg_size,
2155 dev_name(port->dev));
2156 if (unlikely(res == NULL)) {
2157 dev_err(port->dev, "request_mem_region failed.");
e2651647 2158 return -EBUSY;
e4d6f911 2159 }
1da177e4 2160
f6e9495d
PM		 2161 ret = sci_remap_port(port);
2162 if (unlikely(ret != 0)) {
2163 release_resource(res);
2164 return ret;
7ff731ae 2165 }
e2651647
PM		 2166
2167 return 0;
2168}
2169
2170static void sci_config_port(struct uart_port *port, int flags)
2171{
2172 if (flags & UART_CONFIG_TYPE) {
2173 struct sci_port *sport = to_sci_port(port);
2174
2175 port->type = sport->cfg->type;
2176 sci_request_port(port);
2177 }
1da177e4
LT		 2178}
2179
2180static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2181{
1da177e4
LT		 2182 if (ser->baud_base < 2400)
2183 /* No paper tape reader for Mitch.. */
2184 return -EINVAL;
2185
2186 return 0;
2187}
2188
2189static struct uart_ops sci_uart_ops = {
2190 .tx_empty = sci_tx_empty,
2191 .set_mctrl = sci_set_mctrl,
2192 .get_mctrl = sci_get_mctrl,
2193 .start_tx = sci_start_tx,
2194 .stop_tx = sci_stop_tx,
2195 .stop_rx = sci_stop_rx,
1da177e4
LT		 2196 .break_ctl = sci_break_ctl,
2197 .startup = sci_startup,
2198 .shutdown = sci_shutdown,
2199 .set_termios = sci_set_termios,
0174e5ca 2200 .pm = sci_pm,
1da177e4
LT		 2201 .type = sci_type,
2202 .release_port = sci_release_port,
2203 .request_port = sci_request_port,
2204 .config_port = sci_config_port,
2205 .verify_port = sci_verify_port,
07d2a1a1
PM		 2206#ifdef CONFIG_CONSOLE_POLL
2207 .poll_get_char = sci_poll_get_char,
2208 .poll_put_char = sci_poll_put_char,
2209#endif
1da177e4
LT		 2210};
2211
9671f099 2212static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2213 struct sci_port *sci_port, unsigned int index,
2214 struct plat_sci_port *p, bool early)
e108b2ca 2215{
73a19e4c 2216 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2217 const struct resource *res;
2218 unsigned int i;
3127c6b2 2219 int ret;
e108b2ca 2220
50f0959a
PM		 2221 sci_port->cfg = p;
2222
73a19e4c
GL		 2223 port->ops = &sci_uart_ops;
2224 port->iotype = UPIO_MEM;
2225 port->line = index;
75136d48 2226
89b5c1ab
LP		 2227 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2228 if (res == NULL)
2229 return -ENOMEM;
1fcc91a6 2230
89b5c1ab 2231 port->mapbase = res->start;
e4d6f911 2232 sci_port->reg_size = resource_size(res);
1fcc91a6 2233
89b5c1ab
LP		 2234 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2235 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2236
89b5c1ab
LP		 2237 /* The SCI generates several interrupts. They can be muxed together or
2238 * connected to different interrupt lines. In the muxed case only one
2239 * interrupt resource is specified. In the non-muxed case three or four
2240 * interrupt resources are specified, as the BRI interrupt is optional.
2241 */
2242 if (sci_port->irqs[0] < 0)
2243 return -ENXIO;
1fcc91a6 2244
89b5c1ab
LP		 2245 if (sci_port->irqs[1] < 0) {
2246 sci_port->irqs[1] = sci_port->irqs[0];
2247 sci_port->irqs[2] = sci_port->irqs[0];
2248 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2249 }
2250
b545e4f4
LP		 2251 if (p->regtype == SCIx_PROBE_REGTYPE) {
2252 ret = sci_probe_regmap(p);
2253 if (unlikely(ret))
2254 return ret;
2255 }
2256
75136d48 2257 switch (p->type) {
d1d4b10c
GL		 2258 case PORT_SCIFB:
2259 port->fifosize = 256;
2e0842a1 2260 sci_port->overrun_reg = SCxSR;
75c249fd 2261 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2262 sci_port->sampling_rate = 16;
d1d4b10c 2263 break;
f303b364
UH		 2264 case PORT_HSCIF:
2265 port->fifosize = 128;
2e0842a1 2266 sci_port->overrun_reg = SCLSR;
75c249fd 2267 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2268 sci_port->sampling_rate = 0;
f303b364 2269 break;
75136d48 2270 case PORT_SCIFA:
73a19e4c 2271 port->fifosize = 64;
2e0842a1 2272 sci_port->overrun_reg = SCxSR;
75c249fd 2273 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2274 sci_port->sampling_rate = 16;
75136d48
MP		 2275 break;
2276 case PORT_SCIF:
73a19e4c 2277 port->fifosize = 16;
ec09c5eb 2278 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2279 sci_port->overrun_reg = SCxSR;
75c249fd 2280 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2281 sci_port->sampling_rate = 16;
ec09c5eb 2282 } else {
2e0842a1 2283 sci_port->overrun_reg = SCLSR;
75c249fd 2284 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2285 sci_port->sampling_rate = 32;
ec09c5eb 2286 }
75136d48
MP		 2287 break;
2288 default:
73a19e4c 2289 port->fifosize = 1;
2e0842a1 2290 sci_port->overrun_reg = SCxSR;
75c249fd 2291 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2292 sci_port->sampling_rate = 32;
75136d48
MP		 2293 break;
2294 }
7b6fd3bf 2295
878fbb91
LP		 2296 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2297 * match the SoC datasheet, this should be investigated. Let platform
2298 * data override the sampling rate for now.
ec09c5eb 2299 */
f84b6bdc
GU		 2300 if (p->sampling_rate)
2301 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2302
1fcc91a6 2303 if (!early) {
c7ed1ab3
PM		 2304 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2305 if (IS_ERR(sci_port->iclk)) {
2306 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2307 if (IS_ERR(sci_port->iclk)) {
2308 dev_err(&dev->dev, "can't get iclk\n");
2309 return PTR_ERR(sci_port->iclk);
2310 }
2311 }
2312
2313 /*
2314 * The function clock is optional, ignore it if we can't
2315 * find it.
2316 */
2317 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2318 if (IS_ERR(sci_port->fclk))
2319 sci_port->fclk = NULL;
2320
73a19e4c 2321 port->dev = &dev->dev;
5e50d2d6
MD		 2322
2323 pm_runtime_enable(&dev->dev);
7b6fd3bf 2324 }
e108b2ca 2325
7ed7e071
MD		 2326 sci_port->break_timer.data = (unsigned long)sci_port;
2327 sci_port->break_timer.function = sci_break_timer;
2328 init_timer(&sci_port->break_timer);
2329
debf9507
PM		 2330 /*
2331 * Establish some sensible defaults for the error detection.
2332 */
5da0f468
GU		 2333 if (p->type == PORT_SCI) {
2334 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2335 sci_port->error_clear = SCI_ERROR_CLEAR;
2336 } else {
2337 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2338 sci_port->error_clear = SCIF_ERROR_CLEAR;
2339 }
debf9507 2340
3ae988d9
LP		 2341 /*
2342 * Make the error mask inclusive of overrun detection, if
2343 * supported.
2344 */
5da0f468 2345 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2346 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2347 sci_port->error_clear &= ~sci_port->overrun_mask;
2348 }
debf9507 2349
ce6738b6 2350 port->type = p->type;
b6e4a3f1 2351 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2352 port->regshift = p->regshift;
73a19e4c 2353
ce6738b6 2354 /*
61a6976b 2355 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2356 * for the multi-IRQ ports, which is where we are primarily
2357 * concerned with the shutdown path synchronization.
2358 *
2359 * For the muxed case there's nothing more to do.
2360 */
1fcc91a6 2361 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2362 port->irqflags = 0;
73a19e4c 2363
61a6976b
PM		 2364 port->serial_in = sci_serial_in;
2365 port->serial_out = sci_serial_out;
2366
937bb6e4
GL		 2367 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2368 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2369 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2370
c7ed1ab3 2371 return 0;
e108b2ca
PM		 2372}
2373
6dae1421
LP		 2374static void sci_cleanup_single(struct sci_port *port)
2375{
6dae1421
LP		 2376 clk_put(port->iclk);
2377 clk_put(port->fclk);
2378
2379 pm_runtime_disable(port->port.dev);
2380}
2381
1da177e4 2382#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2383static void serial_console_putchar(struct uart_port *port, int ch)
2384{
2385 sci_poll_put_char(port, ch);
2386}
2387
1da177e4
LT		 2388/*
2389 * Print a string to the serial port trying not to disturb
2390 * any possible real use of the port...
2391 */
2392static void serial_console_write(struct console *co, const char *s,
2393 unsigned count)
2394{
906b17dc
PM		 2395 struct sci_port *sci_port = &sci_ports[co->index];
2396 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2397 unsigned short bits, ctrl;
2398 unsigned long flags;
2399 int locked = 1;
2400
2401 local_irq_save(flags);
2402 if (port->sysrq)
2403 locked = 0;
2404 else if (oops_in_progress)
2405 locked = spin_trylock(&port->lock);
2406 else
2407 spin_lock(&port->lock);
2408
2409 /* first save the SCSCR then disable the interrupts */
2410 ctrl = serial_port_in(port, SCSCR);
2411 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2412
501b825d 2413 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2414
2415 /* wait until fifo is empty and last bit has been transmitted */
2416 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2417 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2418 cpu_relax();
40f70c03
SK		 2419
2420 /* restore the SCSCR */
2421 serial_port_out(port, SCSCR, ctrl);
2422
2423 if (locked)
2424 spin_unlock(&port->lock);
2425 local_irq_restore(flags);
1da177e4
LT		 2426}
2427
9671f099 2428static int serial_console_setup(struct console *co, char *options)
1da177e4 2429{
dc8e6f5b 2430 struct sci_port *sci_port;
1da177e4
LT		 2431 struct uart_port *port;
2432 int baud = 115200;
2433 int bits = 8;
2434 int parity = 'n';
2435 int flow = 'n';
2436 int ret;
2437
e108b2ca 2438 /*
906b17dc 2439 * Refuse to handle any bogus ports.
1da177e4 2440 */
906b17dc 2441 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2442 return -ENODEV;
e108b2ca 2443
906b17dc
PM		 2444 sci_port = &sci_ports[co->index];
2445 port = &sci_port->port;
2446
b2267a6b
AC		 2447 /*
2448 * Refuse to handle uninitialized ports.
2449 */
2450 if (!port->ops)
2451 return -ENODEV;
2452
f6e9495d
PM		 2453 ret = sci_remap_port(port);
2454 if (unlikely(ret != 0))
2455 return ret;
e108b2ca 2456
1da177e4
LT		 2457 if (options)
2458 uart_parse_options(options, &baud, &parity, &bits, &flow);
2459
ab7cfb55 2460 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2461}
2462
2463static struct console serial_console = {
2464 .name = "ttySC",
906b17dc 2465 .device = uart_console_device,
1da177e4
LT		 2466 .write = serial_console_write,
2467 .setup = serial_console_setup,
fa5da2f7 2468 .flags = CON_PRINTBUFFER,
1da177e4 2469 .index = -1,
906b17dc 2470 .data = &sci_uart_driver,
1da177e4
LT		 2471};
2472
7b6fd3bf
MD		 2473static struct console early_serial_console = {
2474 .name = "early_ttySC",
2475 .write = serial_console_write,
2476 .flags = CON_PRINTBUFFER,
906b17dc 2477 .index = -1,
7b6fd3bf 2478};
ecdf8a46 2479
7b6fd3bf
MD		 2480static char early_serial_buf[32];
2481
9671f099 2482static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2483{
574de559 2484 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2485
2486 if (early_serial_console.data)
2487 return -EEXIST;
2488
2489 early_serial_console.index = pdev->id;
ecdf8a46 2490
1fcc91a6 2491 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2492
2493 serial_console_setup(&early_serial_console, early_serial_buf);
2494
2495 if (!strstr(early_serial_buf, "keep"))
2496 early_serial_console.flags |= CON_BOOT;
2497
2498 register_console(&early_serial_console);
2499 return 0;
2500}
6a8c9799
NI		 2501
2502#define SCI_CONSOLE (&serial_console)
2503
ecdf8a46 2504#else
9671f099 2505static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2506{
2507 return -EINVAL;
2508}
1da177e4 2509
6a8c9799
NI		 2510#define SCI_CONSOLE NULL
2511
2512#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2513
6c13d5d2 2514static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2515
2516static struct uart_driver sci_uart_driver = {
2517 .owner = THIS_MODULE,
2518 .driver_name = "sci",
1da177e4
LT		 2519 .dev_name = "ttySC",
2520 .major = SCI_MAJOR,
2521 .minor = SCI_MINOR_START,
e108b2ca 2522 .nr = SCI_NPORTS,
1da177e4
LT		 2523 .cons = SCI_CONSOLE,
2524};
2525
54507f6e 2526static int sci_remove(struct platform_device *dev)
e552de24 2527{
d535a230 2528 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2529
d535a230
PM		 2530 cpufreq_unregister_notifier(&port->freq_transition,
2531 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2532
d535a230
PM		 2533 uart_remove_one_port(&sci_uart_driver, &port->port);
2534
6dae1421 2535 sci_cleanup_single(port);
e552de24 2536
e552de24
MD		 2537 return 0;
2538}
2539
20bdcab8
BH		 2540struct sci_port_info {
2541 unsigned int type;
2542 unsigned int regtype;
2543};
2544
2545static const struct of_device_id of_sci_match[] = {
2546 {
2547 .compatible = "renesas,scif",
ff43da00 2548 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2549 .type = PORT_SCIF,
2550 .regtype = SCIx_SH4_SCIF_REGTYPE,
2551 },
2552 }, {
2553 .compatible = "renesas,scifa",
ff43da00 2554 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2555 .type = PORT_SCIFA,
2556 .regtype = SCIx_SCIFA_REGTYPE,
2557 },
2558 }, {
2559 .compatible = "renesas,scifb",
ff43da00 2560 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2561 .type = PORT_SCIFB,
2562 .regtype = SCIx_SCIFB_REGTYPE,
2563 },
2564 }, {
2565 .compatible = "renesas,hscif",
ff43da00 2566 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2567 .type = PORT_HSCIF,
2568 .regtype = SCIx_HSCIF_REGTYPE,
2569 },
e1d0be61
YS		 2570 }, {
2571 .compatible = "renesas,sci",
2572 .data = &(const struct sci_port_info) {
2573 .type = PORT_SCI,
2574 .regtype = SCIx_SCI_REGTYPE,
2575 },
20bdcab8
BH		 2576 }, {
2577 /* Terminator */
2578 },
2579};
2580MODULE_DEVICE_TABLE(of, of_sci_match);
2581
2582static struct plat_sci_port *
2583sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2584{
2585 struct device_node *np = pdev->dev.of_node;
2586 const struct of_device_id *match;
2587 const struct sci_port_info *info;
2588 struct plat_sci_port *p;
2589 int id;
2590
2591 if (!IS_ENABLED(CONFIG_OF) || !np)
2592 return NULL;
2593
2594 match = of_match_node(of_sci_match, pdev->dev.of_node);
2595 if (!match)
2596 return NULL;
2597
2598 info = match->data;
2599
2600 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2601 if (!p)
20bdcab8 2602 return NULL;
20bdcab8
BH		 2603
2604 /* Get the line number for the aliases node. */
2605 id = of_alias_get_id(np, "serial");
2606 if (id < 0) {
2607 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2608 return NULL;
2609 }
2610
2611 *dev_id = id;
2612
2613 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2614 p->type = info->type;
2615 p->regtype = info->regtype;
2616 p->scscr = SCSCR_RE | SCSCR_TE;
2617
2618 return p;
2619}
2620
9671f099 2621static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2622 unsigned int index,
2623 struct plat_sci_port *p,
2624 struct sci_port *sciport)
2625{
0ee70712
MD		 2626 int ret;
2627
2628 /* Sanity check */
2629 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2630 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2631 index+1, SCI_NPORTS);
9b971cd2 2632 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2633 return -EINVAL;
0ee70712
MD		 2634 }
2635
1fcc91a6 2636 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2637 if (ret)
2638 return ret;
0ee70712 2639
6dae1421
LP		 2640 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2641 if (ret) {
2642 sci_cleanup_single(sciport);
2643 return ret;
2644 }
2645
2646 return 0;
0ee70712
MD		 2647}
2648
9671f099 2649static int sci_probe(struct platform_device *dev)
1da177e4 2650{
20bdcab8
BH		 2651 struct plat_sci_port *p;
2652 struct sci_port *sp;
2653 unsigned int dev_id;
ecdf8a46 2654 int ret;
d535a230 2655
ecdf8a46
PM		 2656 /*
2657 * If we've come here via earlyprintk initialization, head off to
2658 * the special early probe. We don't have sufficient device state
2659 * to make it beyond this yet.
2660 */
2661 if (is_early_platform_device(dev))
2662 return sci_probe_earlyprintk(dev);
7b6fd3bf 2663
20bdcab8
BH		 2664 if (dev->dev.of_node) {
2665 p = sci_parse_dt(dev, &dev_id);
2666 if (p == NULL)
2667 return -EINVAL;
2668 } else {
2669 p = dev->dev.platform_data;
2670 if (p == NULL) {
2671 dev_err(&dev->dev, "no platform data supplied\n");
2672 return -EINVAL;
2673 }
2674
2675 dev_id = dev->id;
2676 }
2677
2678 sp = &sci_ports[dev_id];
d535a230 2679 platform_set_drvdata(dev, sp);
e552de24 2680
20bdcab8 2681 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2682 if (ret)
6dae1421 2683 return ret;
e552de24 2684
d535a230 2685 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2686
d535a230
PM		 2687 ret = cpufreq_register_notifier(&sp->freq_transition,
2688 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2689 if (unlikely(ret < 0)) {
bf13c9a8 2690 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2691 sci_cleanup_single(sp);
2692 return ret;
2693 }
1da177e4
LT		 2694
2695#ifdef CONFIG_SH_STANDARD_BIOS
2696 sh_bios_gdb_detach();
2697#endif
2698
e108b2ca 2699 return 0;
1da177e4
LT		 2700}
2701
cb876341 2702static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2703{
d535a230 2704 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2705
d535a230
PM		 2706 if (sport)
2707 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2708
e108b2ca
PM		 2709 return 0;
2710}
1da177e4 2711
cb876341 2712static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2713{
d535a230 2714 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2715
d535a230
PM		 2716 if (sport)
2717 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2718
2719 return 0;
2720}
2721
cb876341 2722static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2723
e108b2ca
PM		 2724static struct platform_driver sci_driver = {
2725 .probe = sci_probe,
b9e39c89 2726 .remove = sci_remove,
e108b2ca
PM		 2727 .driver = {
2728 .name = "sh-sci",
6daa79b3 2729 .pm = &sci_dev_pm_ops,
20bdcab8 2730 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2731 },
2732};
2733
2734static int __init sci_init(void)
2735{
2736 int ret;
2737
6c13d5d2 2738 pr_info("%s\n", banner);
e108b2ca 2739
e108b2ca
PM		 2740 ret = uart_register_driver(&sci_uart_driver);
2741 if (likely(ret == 0)) {
2742 ret = platform_driver_register(&sci_driver);
2743 if (unlikely(ret))
2744 uart_unregister_driver(&sci_uart_driver);
2745 }
2746
2747 return ret;
2748}
2749
2750static void __exit sci_exit(void)
2751{
2752 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2753 uart_unregister_driver(&sci_uart_driver);
2754}
2755
7b6fd3bf
MD		 2756#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2757early_platform_init_buffer("earlyprintk", &sci_driver,
2758 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2759#endif
1da177e4
LT		 2760module_init(sci_init);
2761module_exit(sci_exit);
2762
e108b2ca 2763MODULE_LICENSE("GPL");
e169c139 2764MODULE_ALIAS("platform:sh-sci");
7f405f9c 2765MODULE_AUTHOR("Paul Mundt");
f303b364 2766MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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