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serial: sh-sci: Use dev_dbg() to log an error message
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
3ae988d9
LP		 84 int overrun_bit;
85 unsigned int error_mask;
ec09c5eb 86 unsigned int sampling_rate;
3ae988d9 87
e108b2ca 88
e108b2ca
PM		 89 /* Break timer */
90 struct timer_list break_timer;
91 int break_flag;
1534a3b3 92
501b825d
MD		 93 /* Interface clock */
94 struct clk *iclk;
c7ed1ab3
PM		 95 /* Function clock */
96 struct clk *fclk;
edad1f20 97
1fcc91a6 98 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 99 char *irqstr[SCIx_NR_IRQS];
100
73a19e4c
GL		 101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
f43dc23d 103
73a19e4c 104#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 105 struct dma_async_tx_descriptor *desc_tx;
106 struct dma_async_tx_descriptor *desc_rx[2];
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 struct scatterlist sg_tx;
111 unsigned int sg_len_tx;
112 struct scatterlist sg_rx[2];
113 size_t buf_len_rx;
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
3089f381 119 unsigned int rx_timeout;
73a19e4c 120#endif
e552de24 121
d535a230 122 struct notifier_block freq_transition;
e108b2ca
PM		 123};
124
1da177e4 125/* Function prototypes */
d535a230 126static void sci_start_tx(struct uart_port *port);
b129a8cc 127static void sci_stop_tx(struct uart_port *port);
d535a230 128static void sci_start_rx(struct uart_port *port);
1da177e4 129
e108b2ca 130#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 131
e108b2ca
PM		 132static struct sci_port sci_ports[SCI_NPORTS];
133static struct uart_driver sci_uart_driver;
1da177e4 134
e7c98dc7
MT		 135static inline struct sci_port *
136to_sci_port(struct uart_port *uart)
137{
138 return container_of(uart, struct sci_port, port);
139}
140
61a6976b
PM		 141struct plat_sci_reg {
142 u8 offset, size;
143};
144
145/* Helper for invalidating specific entries of an inherited map. */
146#define sci_reg_invalid { .offset = 0, .size = 0 }
147
148static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151 },
152
153 /*
154 * Common SCI definitions, dependent on the port's regshift
155 * value.
156 */
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
f303b364 170 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 171 },
172
173 /*
174 * Common definitions for legacy IrDA ports, dependent on
175 * regshift value.
176 */
177 [SCIx_IRDA_REGTYPE] = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 [SCFCR] = { 0x06, 8 },
185 [SCFDR] = { 0x07, 16 },
186 [SCTFDR] = sci_reg_invalid,
187 [SCRFDR] = sci_reg_invalid,
188 [SCSPTR] = sci_reg_invalid,
189 [SCLSR] = sci_reg_invalid,
f303b364 190 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 191 },
192
193 /*
194 * Common SCIFA definitions.
195 */
196 [SCIx_SCIFA_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x20, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x24, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
f303b364 209 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 210 },
211
212 /*
213 * Common SCIFB definitions.
214 */
215 [SCIx_SCIFB_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x40, 8 },
220 [SCxSR] = { 0x14, 16 },
221 [SCxRDR] = { 0x60, 8 },
222 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 223 [SCFDR] = sci_reg_invalid,
224 [SCTFDR] = { 0x38, 16 },
225 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 226 [SCSPTR] = sci_reg_invalid,
227 [SCLSR] = sci_reg_invalid,
f303b364 228 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 229 },
230
3af1f8a4
PE		 231 /*
232 * Common SH-2(A) SCIF definitions for ports with FIFO data
233 * count registers.
234 */
235 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
236 [SCSMR] = { 0x00, 16 },
237 [SCBRR] = { 0x04, 8 },
238 [SCSCR] = { 0x08, 16 },
239 [SCxTDR] = { 0x0c, 8 },
240 [SCxSR] = { 0x10, 16 },
241 [SCxRDR] = { 0x14, 8 },
242 [SCFCR] = { 0x18, 16 },
243 [SCFDR] = { 0x1c, 16 },
244 [SCTFDR] = sci_reg_invalid,
245 [SCRFDR] = sci_reg_invalid,
246 [SCSPTR] = { 0x20, 16 },
247 [SCLSR] = { 0x24, 16 },
f303b364 248 [HSSRR] = sci_reg_invalid,
3af1f8a4
PE		 249 },
250
61a6976b
PM		 251 /*
252 * Common SH-3 SCIF definitions.
253 */
254 [SCIx_SH3_SCIF_REGTYPE] = {
255 [SCSMR] = { 0x00, 8 },
256 [SCBRR] = { 0x02, 8 },
257 [SCSCR] = { 0x04, 8 },
258 [SCxTDR] = { 0x06, 8 },
259 [SCxSR] = { 0x08, 16 },
260 [SCxRDR] = { 0x0a, 8 },
261 [SCFCR] = { 0x0c, 8 },
262 [SCFDR] = { 0x0e, 16 },
263 [SCTFDR] = sci_reg_invalid,
264 [SCRFDR] = sci_reg_invalid,
265 [SCSPTR] = sci_reg_invalid,
266 [SCLSR] = sci_reg_invalid,
f303b364 267 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 268 },
269
270 /*
271 * Common SH-4(A) SCIF(B) definitions.
272 */
273 [SCIx_SH4_SCIF_REGTYPE] = {
274 [SCSMR] = { 0x00, 16 },
275 [SCBRR] = { 0x04, 8 },
276 [SCSCR] = { 0x08, 16 },
277 [SCxTDR] = { 0x0c, 8 },
278 [SCxSR] = { 0x10, 16 },
279 [SCxRDR] = { 0x14, 8 },
280 [SCFCR] = { 0x18, 16 },
281 [SCFDR] = { 0x1c, 16 },
282 [SCTFDR] = sci_reg_invalid,
283 [SCRFDR] = sci_reg_invalid,
284 [SCSPTR] = { 0x20, 16 },
285 [SCLSR] = { 0x24, 16 },
f303b364
UH		 286 [HSSRR] = sci_reg_invalid,
287 },
288
289 /*
290 * Common HSCIF definitions.
291 */
292 [SCIx_HSCIF_REGTYPE] = {
293 [SCSMR] = { 0x00, 16 },
294 [SCBRR] = { 0x04, 8 },
295 [SCSCR] = { 0x08, 16 },
296 [SCxTDR] = { 0x0c, 8 },
297 [SCxSR] = { 0x10, 16 },
298 [SCxRDR] = { 0x14, 8 },
299 [SCFCR] = { 0x18, 16 },
300 [SCFDR] = { 0x1c, 16 },
301 [SCTFDR] = sci_reg_invalid,
302 [SCRFDR] = sci_reg_invalid,
303 [SCSPTR] = { 0x20, 16 },
304 [SCLSR] = { 0x24, 16 },
305 [HSSRR] = { 0x40, 16 },
61a6976b
PM		 306 },
307
308 /*
309 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
310 * register.
311 */
312 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
313 [SCSMR] = { 0x00, 16 },
314 [SCBRR] = { 0x04, 8 },
315 [SCSCR] = { 0x08, 16 },
316 [SCxTDR] = { 0x0c, 8 },
317 [SCxSR] = { 0x10, 16 },
318 [SCxRDR] = { 0x14, 8 },
319 [SCFCR] = { 0x18, 16 },
320 [SCFDR] = { 0x1c, 16 },
321 [SCTFDR] = sci_reg_invalid,
322 [SCRFDR] = sci_reg_invalid,
323 [SCSPTR] = sci_reg_invalid,
324 [SCLSR] = { 0x24, 16 },
f303b364 325 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 326 },
327
328 /*
329 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
330 * count registers.
331 */
332 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
333 [SCSMR] = { 0x00, 16 },
334 [SCBRR] = { 0x04, 8 },
335 [SCSCR] = { 0x08, 16 },
336 [SCxTDR] = { 0x0c, 8 },
337 [SCxSR] = { 0x10, 16 },
338 [SCxRDR] = { 0x14, 8 },
339 [SCFCR] = { 0x18, 16 },
340 [SCFDR] = { 0x1c, 16 },
341 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
342 [SCRFDR] = { 0x20, 16 },
343 [SCSPTR] = { 0x24, 16 },
344 [SCLSR] = { 0x28, 16 },
f303b364 345 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 346 },
347
348 /*
349 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
350 * registers.
351 */
352 [SCIx_SH7705_SCIF_REGTYPE] = {
353 [SCSMR] = { 0x00, 16 },
354 [SCBRR] = { 0x04, 8 },
355 [SCSCR] = { 0x08, 16 },
356 [SCxTDR] = { 0x20, 8 },
357 [SCxSR] = { 0x14, 16 },
358 [SCxRDR] = { 0x24, 8 },
359 [SCFCR] = { 0x18, 16 },
360 [SCFDR] = { 0x1c, 16 },
361 [SCTFDR] = sci_reg_invalid,
362 [SCRFDR] = sci_reg_invalid,
363 [SCSPTR] = sci_reg_invalid,
364 [SCLSR] = sci_reg_invalid,
f303b364 365 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 366 },
367};
368
72b294cf
PM		 369#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
370
61a6976b
PM		 371/*
372 * The "offset" here is rather misleading, in that it refers to an enum
373 * value relative to the port mapping rather than the fixed offset
374 * itself, which needs to be manually retrieved from the platform's
375 * register map for the given port.
376 */
377static unsigned int sci_serial_in(struct uart_port *p, int offset)
378{
72b294cf 379 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 380
381 if (reg->size == 8)
382 return ioread8(p->membase + (reg->offset << p->regshift));
383 else if (reg->size == 16)
384 return ioread16(p->membase + (reg->offset << p->regshift));
385 else
386 WARN(1, "Invalid register access\n");
387
388 return 0;
389}
390
391static void sci_serial_out(struct uart_port *p, int offset, int value)
392{
72b294cf 393 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 394
395 if (reg->size == 8)
396 iowrite8(value, p->membase + (reg->offset << p->regshift));
397 else if (reg->size == 16)
398 iowrite16(value, p->membase + (reg->offset << p->regshift));
399 else
400 WARN(1, "Invalid register access\n");
401}
402
61a6976b
PM		 403static int sci_probe_regmap(struct plat_sci_port *cfg)
404{
405 switch (cfg->type) {
406 case PORT_SCI:
407 cfg->regtype = SCIx_SCI_REGTYPE;
408 break;
409 case PORT_IRDA:
410 cfg->regtype = SCIx_IRDA_REGTYPE;
411 break;
412 case PORT_SCIFA:
413 cfg->regtype = SCIx_SCIFA_REGTYPE;
414 break;
415 case PORT_SCIFB:
416 cfg->regtype = SCIx_SCIFB_REGTYPE;
417 break;
418 case PORT_SCIF:
419 /*
420 * The SH-4 is a bit of a misnomer here, although that's
421 * where this particular port layout originated. This
422 * configuration (or some slight variation thereof)
423 * remains the dominant model for all SCIFs.
424 */
425 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
426 break;
f303b364
UH		 427 case PORT_HSCIF:
428 cfg->regtype = SCIx_HSCIF_REGTYPE;
429 break;
61a6976b 430 default:
6c13d5d2 431 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 432 return -EINVAL;
433 }
434
435 return 0;
436}
437
23241d43
PM		 438static void sci_port_enable(struct sci_port *sci_port)
439{
440 if (!sci_port->port.dev)
441 return;
442
443 pm_runtime_get_sync(sci_port->port.dev);
444
b016b646 445 clk_prepare_enable(sci_port->iclk);
23241d43 446 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 447 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 448}
449
450static void sci_port_disable(struct sci_port *sci_port)
451{
452 if (!sci_port->port.dev)
453 return;
454
caec7038
LP		 455 /* Cancel the break timer to ensure that the timer handler will not try
456 * to access the hardware with clocks and power disabled. Reset the
457 * break flag to make the break debouncing state machine ready for the
458 * next break.
459 */
460 del_timer_sync(&sci_port->break_timer);
461 sci_port->break_flag = 0;
462
b016b646
LP		 463 clk_disable_unprepare(sci_port->fclk);
464 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 465
466 pm_runtime_put_sync(sci_port->port.dev);
467}
468
07d2a1a1 469#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 470
471#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 472static int sci_poll_get_char(struct uart_port *port)
1da177e4 473{
1da177e4
LT		 474 unsigned short status;
475 int c;
476
e108b2ca 477 do {
b12bb29f 478 status = serial_port_in(port, SCxSR);
1da177e4 479 if (status & SCxSR_ERRORS(port)) {
b12bb29f 480 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 481 continue;
482 }
3f255eb3
JW		 483 break;
484 } while (1);
485
486 if (!(status & SCxSR_RDxF(port)))
487 return NO_POLL_CHAR;
07d2a1a1 488
b12bb29f 489 c = serial_port_in(port, SCxRDR);
07d2a1a1 490
e7c98dc7 491 /* Dummy read */
b12bb29f
PM		 492 serial_port_in(port, SCxSR);
493 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 494
495 return c;
496}
1f6fd5c9 497#endif
1da177e4 498
07d2a1a1 499static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 500{
1da177e4
LT		 501 unsigned short status;
502
1da177e4 503 do {
b12bb29f 504 status = serial_port_in(port, SCxSR);
1da177e4
LT		 505 } while (!(status & SCxSR_TDxE(port)));
506
b12bb29f
PM		 507 serial_port_out(port, SCxTDR, c);
508 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 509}
07d2a1a1 510#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 511
61a6976b 512static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 513{
61a6976b
PM		 514 struct sci_port *s = to_sci_port(port);
515 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 516
61a6976b
PM		 517 /*
518 * Use port-specific handler if provided.
519 */
520 if (s->cfg->ops && s->cfg->ops->init_pins) {
521 s->cfg->ops->init_pins(port, cflag);
522 return;
1da177e4 523 }
41504c39 524
61a6976b
PM		 525 /*
526 * For the generic path SCSPTR is necessary. Bail out if that's
527 * unavailable, too.
528 */
529 if (!reg->size)
530 return;
41504c39 531
faf02f8f
PM		 532 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
533 ((!(cflag & CRTSCTS)))) {
534 unsigned short status;
535
b12bb29f 536 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 537 status &= ~SCSPTR_CTSIO;
538 status |= SCSPTR_RTSIO;
b12bb29f 539 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 540 }
d5701647 541}
e108b2ca 542
72b294cf 543static int sci_txfill(struct uart_port *port)
e108b2ca 544{
72b294cf 545 struct plat_sci_reg *reg;
e108b2ca 546
72b294cf
PM		 547 reg = sci_getreg(port, SCTFDR);
548 if (reg->size)
63f7ad11 549 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 550
72b294cf
PM		 551 reg = sci_getreg(port, SCFDR);
552 if (reg->size)
b12bb29f 553 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 554
b12bb29f 555 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 556}
557
73a19e4c
GL		 558static int sci_txroom(struct uart_port *port)
559{
72b294cf 560 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 561}
562
563static int sci_rxfill(struct uart_port *port)
e108b2ca 564{
72b294cf
PM		 565 struct plat_sci_reg *reg;
566
567 reg = sci_getreg(port, SCRFDR);
568 if (reg->size)
63f7ad11 569 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 570
571 reg = sci_getreg(port, SCFDR);
572 if (reg->size)
b12bb29f 573 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 574
b12bb29f 575 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 576}
577
514820eb
PM		 578/*
579 * SCI helper for checking the state of the muxed port/RXD pins.
580 */
581static inline int sci_rxd_in(struct uart_port *port)
582{
583 struct sci_port *s = to_sci_port(port);
584
585 if (s->cfg->port_reg <= 0)
586 return 1;
587
0dd4d5cb 588 /* Cast for ARM damage */
e2afca69 589 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 590}
591
1da177e4
LT		 592/* ********************************************************************** *
593 * the interrupt related routines *
594 * ********************************************************************** */
595
596static void sci_transmit_chars(struct uart_port *port)
597{
ebd2c8f6 598 struct circ_buf *xmit = &port->state->xmit;
1da177e4 599 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 600 unsigned short status;
601 unsigned short ctrl;
e108b2ca 602 int count;
1da177e4 603
b12bb29f 604 status = serial_port_in(port, SCxSR);
1da177e4 605 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 606 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 607 if (uart_circ_empty(xmit))
8e698614 608 ctrl &= ~SCSCR_TIE;
e7c98dc7 609 else
8e698614 610 ctrl |= SCSCR_TIE;
b12bb29f 611 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 612 return;
613 }
614
72b294cf 615 count = sci_txroom(port);
1da177e4
LT		 616
617 do {
618 unsigned char c;
619
620 if (port->x_char) {
621 c = port->x_char;
622 port->x_char = 0;
623 } else if (!uart_circ_empty(xmit) && !stopped) {
624 c = xmit->buf[xmit->tail];
625 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
626 } else {
627 break;
628 }
629
b12bb29f 630 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 631
632 port->icount.tx++;
633 } while (--count > 0);
634
b12bb29f 635 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 636
637 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
638 uart_write_wakeup(port);
639 if (uart_circ_empty(xmit)) {
b129a8cc 640 sci_stop_tx(port);
1da177e4 641 } else {
b12bb29f 642 ctrl = serial_port_in(port, SCSCR);
1da177e4 643
1a22f08d 644 if (port->type != PORT_SCI) {
b12bb29f
PM		 645 serial_port_in(port, SCxSR); /* Dummy read */
646 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 647 }
1da177e4 648
8e698614 649 ctrl |= SCSCR_TIE;
b12bb29f 650 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 651 }
652}
653
654/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 655#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 656
94c8b6db 657static void sci_receive_chars(struct uart_port *port)
1da177e4 658{
e7c98dc7 659 struct sci_port *sci_port = to_sci_port(port);
227434f8 660 struct tty_port *tport = &port->state->port;
1da177e4
LT		 661 int i, count, copied = 0;
662 unsigned short status;
33f0f88f 663 unsigned char flag;
1da177e4 664
b12bb29f 665 status = serial_port_in(port, SCxSR);
1da177e4
LT		 666 if (!(status & SCxSR_RDxF(port)))
667 return;
668
669 while (1) {
1da177e4 670 /* Don't copy more bytes than there is room for in the buffer */
227434f8 671 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 672
673 /* If for any reason we can't copy more data, we're done! */
674 if (count == 0)
675 break;
676
677 if (port->type == PORT_SCI) {
b12bb29f 678 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 679 if (uart_handle_sysrq_char(port, c) ||
680 sci_port->break_flag)
1da177e4 681 count = 0;
e7c98dc7 682 else
92a19f9c 683 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 684 } else {
e7c98dc7 685 for (i = 0; i < count; i++) {
b12bb29f 686 char c = serial_port_in(port, SCxRDR);
d97fbbed 687
b12bb29f 688 status = serial_port_in(port, SCxSR);
1da177e4
LT		 689#if defined(CONFIG_CPU_SH3)
690 /* Skip "chars" during break */
e108b2ca 691 if (sci_port->break_flag) {
1da177e4
LT		 692 if ((c == 0) &&
693 (status & SCxSR_FER(port))) {
694 count--; i--;
695 continue;
696 }
e108b2ca 697
1da177e4 698 /* Nonzero => end-of-break */
762c69e3 699 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 700 sci_port->break_flag = 0;
701
1da177e4
LT		 702 if (STEPFN(c)) {
703 count--; i--;
704 continue;
705 }
706 }
707#endif /* CONFIG_CPU_SH3 */
7d12e780 708 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 709 count--; i--;
710 continue;
711 }
712
713 /* Store data and status */
73a19e4c 714 if (status & SCxSR_FER(port)) {
33f0f88f 715 flag = TTY_FRAME;
d97fbbed 716 port->icount.frame++;
762c69e3 717 dev_notice(port->dev, "frame error\n");
73a19e4c 718 } else if (status & SCxSR_PER(port)) {
33f0f88f 719 flag = TTY_PARITY;
d97fbbed 720 port->icount.parity++;
762c69e3 721 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 722 } else
723 flag = TTY_NORMAL;
762c69e3 724
92a19f9c 725 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 726 }
727 }
728
b12bb29f
PM		 729 serial_port_in(port, SCxSR); /* dummy read */
730 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 731
1da177e4
LT		 732 copied += count;
733 port->icount.rx += count;
734 }
735
736 if (copied) {
737 /* Tell the rest of the system the news. New characters! */
2e124b4a 738 tty_flip_buffer_push(tport);
1da177e4 739 } else {
b12bb29f
PM		 740 serial_port_in(port, SCxSR); /* dummy read */
741 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 742 }
743}
744
745#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 746
747/*
748 * The sci generates interrupts during the break,
1da177e4
LT		 749 * 1 per millisecond or so during the break period, for 9600 baud.
750 * So dont bother disabling interrupts.
751 * But dont want more than 1 break event.
752 * Use a kernel timer to periodically poll the rx line until
753 * the break is finished.
754 */
94c8b6db 755static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 756{
bc9b3f5c 757 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 758}
94c8b6db 759
1da177e4
LT		 760/* Ensure that two consecutive samples find the break over. */
761static void sci_break_timer(unsigned long data)
762{
e108b2ca
PM		 763 struct sci_port *port = (struct sci_port *)data;
764
765 if (sci_rxd_in(&port->port) == 0) {
1da177e4 766 port->break_flag = 1;
e108b2ca
PM		 767 sci_schedule_break_timer(port);
768 } else if (port->break_flag == 1) {
1da177e4
LT		 769 /* break is over. */
770 port->break_flag = 2;
e108b2ca
PM		 771 sci_schedule_break_timer(port);
772 } else
773 port->break_flag = 0;
1da177e4
LT		 774}
775
94c8b6db 776static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 777{
778 int copied = 0;
b12bb29f 779 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 780 struct tty_port *tport = &port->state->port;
debf9507 781 struct sci_port *s = to_sci_port(port);
1da177e4 782
3ae988d9
LP		 783 /* Handle overruns */
784 if (status & (1 << s->overrun_bit)) {
785 port->icount.overrun++;
d97fbbed 786
3ae988d9
LP		 787 /* overrun error */
788 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
789 copied++;
762c69e3 790
9b971cd2 791 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 792 }
793
e108b2ca 794 if (status & SCxSR_FER(port)) {
1da177e4
LT		 795 if (sci_rxd_in(port) == 0) {
796 /* Notify of BREAK */
e7c98dc7 797 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 798
799 if (!sci_port->break_flag) {
d97fbbed
PM		 800 port->icount.brk++;
801
e108b2ca
PM		 802 sci_port->break_flag = 1;
803 sci_schedule_break_timer(sci_port);
804
1da177e4 805 /* Do sysrq handling. */
e108b2ca 806 if (uart_handle_break(port))
1da177e4 807 return 0;
762c69e3
PM		 808
809 dev_dbg(port->dev, "BREAK detected\n");
810
92a19f9c 811 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 812 copied++;
813 }
814
e108b2ca 815 } else {
1da177e4 816 /* frame error */
d97fbbed
PM		 817 port->icount.frame++;
818
92a19f9c 819 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 820 copied++;
762c69e3
PM		 821
822 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 823 }
824 }
825
e108b2ca 826 if (status & SCxSR_PER(port)) {
1da177e4 827 /* parity error */
d97fbbed
PM		 828 port->icount.parity++;
829
92a19f9c 830 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 831 copied++;
762c69e3 832
9b971cd2 833 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 834 }
835
33f0f88f 836 if (copied)
2e124b4a 837 tty_flip_buffer_push(tport);
1da177e4
LT		 838
839 return copied;
840}
841
94c8b6db 842static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 843{
92a19f9c 844 struct tty_port *tport = &port->state->port;
debf9507 845 struct sci_port *s = to_sci_port(port);
4b8c59a3 846 struct plat_sci_reg *reg;
d830fa45
PM		 847 int copied = 0;
848
4b8c59a3
PM		 849 reg = sci_getreg(port, SCLSR);
850 if (!reg->size)
d830fa45
PM		 851 return 0;
852
3ae988d9 853 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
b12bb29f 854 serial_port_out(port, SCLSR, 0);
d830fa45 855
d97fbbed
PM		 856 port->icount.overrun++;
857
92a19f9c 858 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 859 tty_flip_buffer_push(tport);
d830fa45 860
51b31f1c 861 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 862 copied++;
863 }
864
865 return copied;
866}
867
94c8b6db 868static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 869{
870 int copied = 0;
b12bb29f 871 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 872 struct tty_port *tport = &port->state->port;
a5660ada 873 struct sci_port *s = to_sci_port(port);
1da177e4 874
0b3d4ef6
PM		 875 if (uart_handle_break(port))
876 return 0;
877
b7a76e4b 878 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 879#if defined(CONFIG_CPU_SH3)
880 /* Debounce break */
881 s->break_flag = 1;
882#endif
d97fbbed
PM		 883
884 port->icount.brk++;
885
1da177e4 886 /* Notify of BREAK */
92a19f9c 887 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 888 copied++;
762c69e3
PM		 889
890 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 891 }
892
33f0f88f 893 if (copied)
2e124b4a 894 tty_flip_buffer_push(tport);
e108b2ca 895
d830fa45
PM		 896 copied += sci_handle_fifo_overrun(port);
897
1da177e4
LT		 898 return copied;
899}
900
73a19e4c 901static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 902{
73a19e4c
GL		 903#ifdef CONFIG_SERIAL_SH_SCI_DMA
904 struct uart_port *port = ptr;
905 struct sci_port *s = to_sci_port(port);
906
907 if (s->chan_rx) {
b12bb29f
PM		 908 u16 scr = serial_port_in(port, SCSCR);
909 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 910
911 /* Disable future Rx interrupts */
d1d4b10c 912 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 913 disable_irq_nosync(irq);
26de4f1b 914 scr |= SCSCR_RDRQE;
3089f381 915 } else {
f43dc23d 916 scr &= ~SCSCR_RIE;
3089f381 917 }
b12bb29f 918 serial_port_out(port, SCSCR, scr);
73a19e4c 919 /* Clear current interrupt */
b12bb29f 920 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 921 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
922 jiffies, s->rx_timeout);
923 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 924
925 return IRQ_HANDLED;
926 }
927#endif
928
1da177e4
LT		 929 /* I think sci_receive_chars has to be called irrespective
930 * of whether the I_IXOFF is set, otherwise, how is the interrupt
931 * to be disabled?
932 */
73a19e4c 933 sci_receive_chars(ptr);
1da177e4
LT		 934
935 return IRQ_HANDLED;
936}
937
7d12e780 938static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 939{
940 struct uart_port *port = ptr;
fd78a76a 941 unsigned long flags;
1da177e4 942
fd78a76a 943 spin_lock_irqsave(&port->lock, flags);
1da177e4 944 sci_transmit_chars(port);
fd78a76a 945 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 946
947 return IRQ_HANDLED;
948}
949
7d12e780 950static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 951{
952 struct uart_port *port = ptr;
953
954 /* Handle errors */
955 if (port->type == PORT_SCI) {
956 if (sci_handle_errors(port)) {
957 /* discard character in rx buffer */
b12bb29f
PM		 958 serial_port_in(port, SCxSR);
959 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 960 }
961 } else {
d830fa45 962 sci_handle_fifo_overrun(port);
7d12e780 963 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 964 }
965
b12bb29f 966 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 967
968 /* Kick the transmission */
7d12e780 969 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 970
971 return IRQ_HANDLED;
972}
973
7d12e780 974static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 975{
976 struct uart_port *port = ptr;
977
978 /* Handle BREAKs */
979 sci_handle_breaks(port);
b12bb29f 980 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 981
982 return IRQ_HANDLED;
983}
984
f43dc23d
PM		 985static inline unsigned long port_rx_irq_mask(struct uart_port *port)
986{
987 /*
988 * Not all ports (such as SCIFA) will support REIE. Rather than
989 * special-casing the port type, we check the port initialization
990 * IRQ enable mask to see whether the IRQ is desired at all. If
991 * it's unset, it's logically inferred that there's no point in
992 * testing for it.
993 */
ce6738b6 994 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 995}
996
7d12e780 997static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 998{
44e18e9e 999 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 1000 struct uart_port *port = ptr;
73a19e4c 1001 struct sci_port *s = to_sci_port(port);
a8884e34 1002 irqreturn_t ret = IRQ_NONE;
1da177e4 1003
b12bb29f
PM		 1004 ssr_status = serial_port_in(port, SCxSR);
1005 scr_status = serial_port_in(port, SCSCR);
f43dc23d 1006 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 1007
1008 /* Tx Interrupt */
f43dc23d 1009 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 1010 !s->chan_tx)
a8884e34 1011 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 1012
73a19e4c
GL		 1013 /*
1014 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1015 * DR flags
1016 */
1017 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 1018 (scr_status & SCSCR_RIE))
a8884e34 1019 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1020
1da177e4 1021 /* Error Interrupt */
dd4da3a5 1022 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1023 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1024
1da177e4 1025 /* Break Interrupt */
dd4da3a5 1026 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1027 ret = sci_br_interrupt(irq, ptr);
1da177e4 1028
a8884e34 1029 return ret;
1da177e4
LT		 1030}
1031
1da177e4 1032/*
25985edc 1033 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1034 * ports' baud rate when the peripheral clock changes.
1035 */
e108b2ca
PM		 1036static int sci_notifier(struct notifier_block *self,
1037 unsigned long phase, void *p)
1da177e4 1038{
e552de24
MD		 1039 struct sci_port *sci_port;
1040 unsigned long flags;
1da177e4 1041
d535a230
PM		 1042 sci_port = container_of(self, struct sci_port, freq_transition);
1043
0b443ead 1044 if (phase == CPUFREQ_POSTCHANGE) {
d535a230 1045 struct uart_port *port = &sci_port->port;
073e84c9 1046
d535a230
PM		 1047 spin_lock_irqsave(&port->lock, flags);
1048 port->uartclk = clk_get_rate(sci_port->iclk);
1049 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1050 }
1da177e4 1051
1da177e4
LT		 1052 return NOTIFY_OK;
1053}
501b825d 1054
9174fc8f
PM		 1055static struct sci_irq_desc {
1056 const char *desc;
1057 irq_handler_t handler;
1058} sci_irq_desc[] = {
1059 /*
1060 * Split out handlers, the default case.
1061 */
1062 [SCIx_ERI_IRQ] = {
1063 .desc = "rx err",
1064 .handler = sci_er_interrupt,
1065 },
1066
1067 [SCIx_RXI_IRQ] = {
1068 .desc = "rx full",
1069 .handler = sci_rx_interrupt,
1070 },
1071
1072 [SCIx_TXI_IRQ] = {
1073 .desc = "tx empty",
1074 .handler = sci_tx_interrupt,
1075 },
1076
1077 [SCIx_BRI_IRQ] = {
1078 .desc = "break",
1079 .handler = sci_br_interrupt,
1080 },
1081
1082 /*
1083 * Special muxed handler.
1084 */
1085 [SCIx_MUX_IRQ] = {
1086 .desc = "mux",
1087 .handler = sci_mpxed_interrupt,
1088 },
1089};
1090
1da177e4
LT		 1091static int sci_request_irq(struct sci_port *port)
1092{
9174fc8f
PM		 1093 struct uart_port *up = &port->port;
1094 int i, j, ret = 0;
1095
1096 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1097 struct sci_irq_desc *desc;
1fcc91a6 1098 int irq;
9174fc8f
PM		 1099
1100 if (SCIx_IRQ_IS_MUXED(port)) {
1101 i = SCIx_MUX_IRQ;
1102 irq = up->irq;
0e8963de 1103 } else {
1fcc91a6 1104 irq = port->irqs[i];
9174fc8f 1105
0e8963de
PM		 1106 /*
1107 * Certain port types won't support all of the
1108 * available interrupt sources.
1109 */
1fcc91a6 1110 if (unlikely(irq < 0))
0e8963de
PM		 1111 continue;
1112 }
1113
9174fc8f
PM		 1114 desc = sci_irq_desc + i;
1115 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1116 dev_name(up->dev), desc->desc);
1117 if (!port->irqstr[j]) {
1118 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1119 desc->desc);
1120 goto out_nomem;
1da177e4 1121 }
9174fc8f
PM		 1122
1123 ret = request_irq(irq, desc->handler, up->irqflags,
1124 port->irqstr[j], port);
1125 if (unlikely(ret)) {
1126 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1127 goto out_noirq;
1da177e4
LT		 1128 }
1129 }
1130
1131 return 0;
9174fc8f
PM		 1132
1133out_noirq:
1134 while (--i >= 0)
1fcc91a6 1135 free_irq(port->irqs[i], port);
9174fc8f
PM		 1136
1137out_nomem:
1138 while (--j >= 0)
1139 kfree(port->irqstr[j]);
1140
1141 return ret;
1da177e4
LT		 1142}
1143
1144static void sci_free_irq(struct sci_port *port)
1145{
1146 int i;
1147
9174fc8f
PM		 1148 /*
1149 * Intentionally in reverse order so we iterate over the muxed
1150 * IRQ first.
1151 */
1152 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1153 int irq = port->irqs[i];
0e8963de
PM		 1154
1155 /*
1156 * Certain port types won't support all of the available
1157 * interrupt sources.
1158 */
1fcc91a6 1159 if (unlikely(irq < 0))
0e8963de
PM		 1160 continue;
1161
1fcc91a6 1162 free_irq(port->irqs[i], port);
9174fc8f 1163 kfree(port->irqstr[i]);
1da177e4 1164
9174fc8f
PM		 1165 if (SCIx_IRQ_IS_MUXED(port)) {
1166 /* If there's only one IRQ, we're done. */
1167 return;
1da177e4
LT		 1168 }
1169 }
1170}
1171
1172static unsigned int sci_tx_empty(struct uart_port *port)
1173{
b12bb29f 1174 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1175 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1176
1177 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1178}
1179
cdf7c42f
PM		 1180/*
1181 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1182 * CTS/RTS is supported in hardware by at least one port and controlled
1183 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1184 * handled via the ->init_pins() op, which is a bit of a one-way street,
1185 * lacking any ability to defer pin control -- this will later be
1186 * converted over to the GPIO framework).
dc7e3ef7
PM		 1187 *
1188 * Other modes (such as loopback) are supported generically on certain
1189 * port types, but not others. For these it's sufficient to test for the
1190 * existence of the support register and simply ignore the port type.
cdf7c42f 1191 */
1da177e4
LT		 1192static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1193{
dc7e3ef7
PM		 1194 if (mctrl & TIOCM_LOOP) {
1195 struct plat_sci_reg *reg;
1196
1197 /*
1198 * Standard loopback mode for SCFCR ports.
1199 */
1200 reg = sci_getreg(port, SCFCR);
1201 if (reg->size)
26de4f1b
GU		 1202 serial_port_out(port, SCFCR,
1203 serial_port_in(port, SCFCR) |
1204 SCFCR_LOOP);
dc7e3ef7 1205 }
1da177e4
LT		 1206}
1207
1208static unsigned int sci_get_mctrl(struct uart_port *port)
1209{
cdf7c42f
PM		 1210 /*
1211 * CTS/RTS is handled in hardware when supported, while nothing
1212 * else is wired up. Keep it simple and simply assert DSR/CAR.
1213 */
1214 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1215}
1216
73a19e4c
GL		 1217#ifdef CONFIG_SERIAL_SH_SCI_DMA
1218static void sci_dma_tx_complete(void *arg)
1219{
1220 struct sci_port *s = arg;
1221 struct uart_port *port = &s->port;
1222 struct circ_buf *xmit = &port->state->xmit;
1223 unsigned long flags;
1224
1225 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1226
1227 spin_lock_irqsave(&port->lock, flags);
1228
f354a381 1229 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1230 xmit->tail &= UART_XMIT_SIZE - 1;
1231
f354a381 1232 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1233
1234 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1235 s->desc_tx = NULL;
1236
73a19e4c
GL		 1237 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1238 uart_write_wakeup(port);
1239
3089f381 1240 if (!uart_circ_empty(xmit)) {
49d4bcad 1241 s->cookie_tx = 0;
73a19e4c 1242 schedule_work(&s->work_tx);
49d4bcad
YT		 1243 } else {
1244 s->cookie_tx = -EINVAL;
1245 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1246 u16 ctrl = serial_port_in(port, SCSCR);
1247 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1248 }
3089f381
GL		 1249 }
1250
1251 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1252}
1253
1254/* Locking: called with port lock held */
92a19f9c 1255static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1256{
1257 struct uart_port *port = &s->port;
227434f8 1258 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1259 int i, active, room;
1260
227434f8 1261 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1262
1263 if (s->active_rx == s->cookie_rx[0]) {
1264 active = 0;
1265 } else if (s->active_rx == s->cookie_rx[1]) {
1266 active = 1;
1267 } else {
1268 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1269 return 0;
1270 }
1271
1272 if (room < count)
e2afca69 1273 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1274 count - room);
1275 if (!room)
1276 return room;
1277
1278 for (i = 0; i < room; i++)
92a19f9c 1279 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1280 TTY_NORMAL);
1281
1282 port->icount.rx += room;
1283
1284 return room;
1285}
1286
1287static void sci_dma_rx_complete(void *arg)
1288{
1289 struct sci_port *s = arg;
1290 struct uart_port *port = &s->port;
73a19e4c
GL		 1291 unsigned long flags;
1292 int count;
1293
9b971cd2
JP		 1294 dev_dbg(port->dev, "%s(%d) active #%d\n",
1295 __func__, port->line, s->active_rx);
73a19e4c
GL		 1296
1297 spin_lock_irqsave(&port->lock, flags);
1298
92a19f9c 1299 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1300
3089f381 1301 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1302
1303 spin_unlock_irqrestore(&port->lock, flags);
1304
1305 if (count)
2e124b4a 1306 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1307
1308 schedule_work(&s->work_rx);
1309}
1310
73a19e4c
GL		 1311static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1312{
1313 struct dma_chan *chan = s->chan_rx;
1314 struct uart_port *port = &s->port;
73a19e4c
GL		 1315
1316 s->chan_rx = NULL;
1317 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1318 dma_release_channel(chan);
85b8e3ff
GL		 1319 if (sg_dma_address(&s->sg_rx[0]))
1320 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1321 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1322 if (enable_pio)
1323 sci_start_rx(port);
1324}
1325
1326static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1327{
1328 struct dma_chan *chan = s->chan_tx;
1329 struct uart_port *port = &s->port;
73a19e4c
GL		 1330
1331 s->chan_tx = NULL;
1332 s->cookie_tx = -EINVAL;
1333 dma_release_channel(chan);
1334 if (enable_pio)
1335 sci_start_tx(port);
1336}
1337
1338static void sci_submit_rx(struct sci_port *s)
1339{
1340 struct dma_chan *chan = s->chan_rx;
1341 int i;
1342
1343 for (i = 0; i < 2; i++) {
1344 struct scatterlist *sg = &s->sg_rx[i];
1345 struct dma_async_tx_descriptor *desc;
1346
16052827 1347 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1348 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1349
1350 if (desc) {
1351 s->desc_rx[i] = desc;
1352 desc->callback = sci_dma_rx_complete;
1353 desc->callback_param = s;
1354 s->cookie_rx[i] = desc->tx_submit(desc);
1355 }
1356
1357 if (!desc || s->cookie_rx[i] < 0) {
1358 if (i) {
1359 async_tx_ack(s->desc_rx[0]);
1360 s->cookie_rx[0] = -EINVAL;
1361 }
1362 if (desc) {
1363 async_tx_ack(desc);
1364 s->cookie_rx[i] = -EINVAL;
1365 }
1366 dev_warn(s->port.dev,
1367 "failed to re-start DMA, using PIO\n");
1368 sci_rx_dma_release(s, true);
1369 return;
1370 }
9b971cd2
JP		 1371 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1372 __func__, s->cookie_rx[i], i);
73a19e4c
GL		 1373 }
1374
1375 s->active_rx = s->cookie_rx[0];
1376
1377 dma_async_issue_pending(chan);
1378}
1379
1380static void work_fn_rx(struct work_struct *work)
1381{
1382 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1383 struct uart_port *port = &s->port;
1384 struct dma_async_tx_descriptor *desc;
1385 int new;
1386
1387 if (s->active_rx == s->cookie_rx[0]) {
1388 new = 0;
1389 } else if (s->active_rx == s->cookie_rx[1]) {
1390 new = 1;
1391 } else {
1392 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1393 return;
1394 }
1395 desc = s->desc_rx[new];
1396
1397 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1398 DMA_COMPLETE) {
73a19e4c 1399 /* Handle incomplete DMA receive */
73a19e4c 1400 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1401 struct shdma_desc *sh_desc = container_of(desc,
1402 struct shdma_desc, async_tx);
73a19e4c
GL		 1403 unsigned long flags;
1404 int count;
1405
2bcd90d5 1406 dmaengine_terminate_all(chan);
e2afca69 1407 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1408 sh_desc->partial, sh_desc->cookie);
1409
1410 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1411 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1412 spin_unlock_irqrestore(&port->lock, flags);
1413
1414 if (count)
2e124b4a 1415 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1416
1417 sci_submit_rx(s);
1418
1419 return;
1420 }
1421
1422 s->cookie_rx[new] = desc->tx_submit(desc);
1423 if (s->cookie_rx[new] < 0) {
1424 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1425 sci_rx_dma_release(s, true);
1426 return;
1427 }
1428
73a19e4c 1429 s->active_rx = s->cookie_rx[!new];
3089f381 1430
9b971cd2
JP		 1431 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1432 __func__, s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1433}
1434
1435static void work_fn_tx(struct work_struct *work)
1436{
1437 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1438 struct dma_async_tx_descriptor *desc;
1439 struct dma_chan *chan = s->chan_tx;
1440 struct uart_port *port = &s->port;
1441 struct circ_buf *xmit = &port->state->xmit;
1442 struct scatterlist *sg = &s->sg_tx;
1443
1444 /*
1445 * DMA is idle now.
1446 * Port xmit buffer is already mapped, and it is one page... Just adjust
1447 * offsets and lengths. Since it is a circular buffer, we have to
1448 * transmit till the end, and then the rest. Take the port lock to get a
1449 * consistent xmit buffer state.
1450 */
1451 spin_lock_irq(&port->lock);
1452 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1453 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1454 sg->offset;
f354a381 1455 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1456 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1457 spin_unlock_irq(&port->lock);
1458
f354a381 1459 BUG_ON(!sg_dma_len(sg));
73a19e4c 1460
16052827 1461 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1462 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1463 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1464 if (!desc) {
1465 /* switch to PIO */
1466 sci_tx_dma_release(s, true);
1467 return;
1468 }
1469
1470 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1471
1472 spin_lock_irq(&port->lock);
1473 s->desc_tx = desc;
1474 desc->callback = sci_dma_tx_complete;
1475 desc->callback_param = s;
1476 spin_unlock_irq(&port->lock);
1477 s->cookie_tx = desc->tx_submit(desc);
1478 if (s->cookie_tx < 0) {
1479 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1480 /* switch to PIO */
1481 sci_tx_dma_release(s, true);
1482 return;
1483 }
1484
9b971cd2
JP		 1485 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1486 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c
GL		 1487
1488 dma_async_issue_pending(chan);
1489}
1490#endif
1491
b129a8cc 1492static void sci_start_tx(struct uart_port *port)
1da177e4 1493{
3089f381 1494 struct sci_port *s = to_sci_port(port);
e108b2ca 1495 unsigned short ctrl;
1da177e4 1496
73a19e4c 1497#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1498 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1499 u16 new, scr = serial_port_in(port, SCSCR);
3089f381 1500 if (s->chan_tx)
26de4f1b 1501 new = scr | SCSCR_TDRQE;
3089f381 1502 else
26de4f1b 1503 new = scr & ~SCSCR_TDRQE;
3089f381 1504 if (new != scr)
b12bb29f 1505 serial_port_out(port, SCSCR, new);
73a19e4c 1506 }
f43dc23d 1507
3089f381 1508 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1509 s->cookie_tx < 0) {
1510 s->cookie_tx = 0;
3089f381 1511 schedule_work(&s->work_tx);
49d4bcad 1512 }
73a19e4c 1513#endif
f43dc23d 1514
d1d4b10c 1515 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1516 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1517 ctrl = serial_port_in(port, SCSCR);
1518 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1519 }
1da177e4
LT		 1520}
1521
b129a8cc 1522static void sci_stop_tx(struct uart_port *port)
1da177e4 1523{
1da177e4
LT		 1524 unsigned short ctrl;
1525
1526 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1527 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1528
d1d4b10c 1529 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1530 ctrl &= ~SCSCR_TDRQE;
f43dc23d 1531
8e698614 1532 ctrl &= ~SCSCR_TIE;
f43dc23d 1533
b12bb29f 1534 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1535}
1536
73a19e4c 1537static void sci_start_rx(struct uart_port *port)
1da177e4 1538{
1da177e4
LT		 1539 unsigned short ctrl;
1540
b12bb29f 1541 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1542
d1d4b10c 1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1544 ctrl &= ~SCSCR_RDRQE;
f43dc23d 1545
b12bb29f 1546 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1547}
1548
1549static void sci_stop_rx(struct uart_port *port)
1550{
1da177e4
LT		 1551 unsigned short ctrl;
1552
b12bb29f 1553 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1554
d1d4b10c 1555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1556 ctrl &= ~SCSCR_RDRQE;
f43dc23d
PM		 1557
1558 ctrl &= ~port_rx_irq_mask(port);
1559
b12bb29f 1560 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1561}
1562
1da177e4
LT		 1563static void sci_break_ctl(struct uart_port *port, int break_state)
1564{
bbb4ce50 1565 struct sci_port *s = to_sci_port(port);
a4e02f6d 1566 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1567 unsigned short scscr, scsptr;
1568
a4e02f6d
SY		 1569 /* check wheter the port has SCSPTR */
1570 if (!reg->size) {
bbb4ce50
SY		 1571 /*
1572 * Not supported by hardware. Most parts couple break and rx
1573 * interrupts together, with break detection always enabled.
1574 */
a4e02f6d 1575 return;
bbb4ce50 1576 }
a4e02f6d
SY		 1577
1578 scsptr = serial_port_in(port, SCSPTR);
1579 scscr = serial_port_in(port, SCSCR);
1580
1581 if (break_state == -1) {
1582 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1583 scscr &= ~SCSCR_TE;
1584 } else {
1585 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1586 scscr |= SCSCR_TE;
1587 }
1588
1589 serial_port_out(port, SCSPTR, scsptr);
1590 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1591}
1592
73a19e4c
GL		 1593#ifdef CONFIG_SERIAL_SH_SCI_DMA
1594static bool filter(struct dma_chan *chan, void *slave)
1595{
1596 struct sh_dmae_slave *param = slave;
1597
9b971cd2
JP		 1598 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1599 __func__, param->shdma_slave.slave_id);
73a19e4c 1600
d6fa5a4e 1601 chan->private = &param->shdma_slave;
937bb6e4 1602 return true;
73a19e4c
GL		 1603}
1604
1605static void rx_timer_fn(unsigned long arg)
1606{
1607 struct sci_port *s = (struct sci_port *)arg;
1608 struct uart_port *port = &s->port;
b12bb29f 1609 u16 scr = serial_port_in(port, SCSCR);
3089f381 1610
d1d4b10c 1611 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
26de4f1b 1612 scr &= ~SCSCR_RDRQE;
1fcc91a6 1613 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1614 }
b12bb29f 1615 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1616 dev_dbg(port->dev, "DMA Rx timed out\n");
1617 schedule_work(&s->work_rx);
1618}
1619
1620static void sci_request_dma(struct uart_port *port)
1621{
1622 struct sci_port *s = to_sci_port(port);
1623 struct sh_dmae_slave *param;
1624 struct dma_chan *chan;
1625 dma_cap_mask_t mask;
1626 int nent;
1627
9b971cd2 1628 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1629
937bb6e4 1630 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1631 return;
1632
1633 dma_cap_zero(mask);
1634 dma_cap_set(DMA_SLAVE, mask);
1635
1636 param = &s->param_tx;
1637
1638 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1639 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1640
1641 s->cookie_tx = -EINVAL;
1642 chan = dma_request_channel(mask, filter, param);
1643 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1644 if (chan) {
1645 s->chan_tx = chan;
1646 sg_init_table(&s->sg_tx, 1);
1647 /* UART circular tx buffer is an aligned page. */
e2afca69 1648 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1649 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1650 UART_XMIT_SIZE,
1651 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1652 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1653 if (!nent)
1654 sci_tx_dma_release(s, false);
1655 else
9b971cd2
JP		 1656 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1657 __func__,
e2afca69
LP		 1658 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1659 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1660
1661 s->sg_len_tx = nent;
1662
1663 INIT_WORK(&s->work_tx, work_fn_tx);
1664 }
1665
1666 param = &s->param_rx;
1667
1668 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1669 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1670
1671 chan = dma_request_channel(mask, filter, param);
1672 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1673 if (chan) {
1674 dma_addr_t dma[2];
1675 void *buf[2];
1676 int i;
1677
1678 s->chan_rx = chan;
1679
1680 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1681 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1682 &dma[0], GFP_KERNEL);
1683
1684 if (!buf[0]) {
1685 dev_warn(port->dev,
1686 "failed to allocate dma buffer, using PIO\n");
1687 sci_rx_dma_release(s, true);
1688 return;
1689 }
1690
1691 buf[1] = buf[0] + s->buf_len_rx;
1692 dma[1] = dma[0] + s->buf_len_rx;
1693
1694 for (i = 0; i < 2; i++) {
1695 struct scatterlist *sg = &s->sg_rx[i];
1696
1697 sg_init_table(sg, 1);
1698 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1699 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1700 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1701 }
1702
1703 INIT_WORK(&s->work_rx, work_fn_rx);
1704 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1705
1706 sci_submit_rx(s);
1707 }
1708}
1709
1710static void sci_free_dma(struct uart_port *port)
1711{
1712 struct sci_port *s = to_sci_port(port);
1713
73a19e4c
GL		 1714 if (s->chan_tx)
1715 sci_tx_dma_release(s, false);
1716 if (s->chan_rx)
1717 sci_rx_dma_release(s, false);
1718}
27bd1075
PM		 1719#else
1720static inline void sci_request_dma(struct uart_port *port)
1721{
1722}
1723
1724static inline void sci_free_dma(struct uart_port *port)
1725{
1726}
73a19e4c
GL		 1727#endif
1728
1da177e4
LT		 1729static int sci_startup(struct uart_port *port)
1730{
a5660ada 1731 struct sci_port *s = to_sci_port(port);
33b48e16 1732 unsigned long flags;
073e84c9 1733 int ret;
1da177e4 1734
73a19e4c
GL		 1735 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1736
073e84c9
PM		 1737 ret = sci_request_irq(s);
1738 if (unlikely(ret < 0))
1739 return ret;
1740
73a19e4c 1741 sci_request_dma(port);
073e84c9 1742
33b48e16 1743 spin_lock_irqsave(&port->lock, flags);
d656901b 1744 sci_start_tx(port);
73a19e4c 1745 sci_start_rx(port);
33b48e16 1746 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1747
1748 return 0;
1749}
1750
1751static void sci_shutdown(struct uart_port *port)
1752{
a5660ada 1753 struct sci_port *s = to_sci_port(port);
33b48e16 1754 unsigned long flags;
1da177e4 1755
73a19e4c
GL		 1756 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1757
33b48e16 1758 spin_lock_irqsave(&port->lock, flags);
1da177e4 1759 sci_stop_rx(port);
b129a8cc 1760 sci_stop_tx(port);
33b48e16 1761 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1762
73a19e4c 1763 sci_free_dma(port);
1da177e4 1764 sci_free_irq(s);
1da177e4
LT		 1765}
1766
ec09c5eb 1767static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1768 unsigned long freq)
1769{
ec09c5eb
LP		 1770 if (s->sampling_rate)
1771 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1772
26c92f37
PM		 1773 /* Warn, but use a safe default */
1774 WARN_ON(1);
e8183a6c 1775
26c92f37
PM		 1776 return ((freq + 16 * bps) / (32 * bps) - 1);
1777}
1778
730c4e78
NI		 1779/* calculate frame length from SMR */
1780static int sci_baud_calc_frame_len(unsigned int smr_val)
1781{
1782 int len = 10;
1783
1784 if (smr_val & SCSMR_CHR)
1785 len--;
1786 if (smr_val & SCSMR_PE)
1787 len++;
1788 if (smr_val & SCSMR_STOP)
1789 len++;
1790
1791 return len;
1792}
1793
1794
f303b364
UH		 1795/* calculate sample rate, BRR, and clock select for HSCIF */
1796static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1797 int *brr, unsigned int *srr,
730c4e78 1798 unsigned int *cks, int frame_len)
f303b364 1799{
730c4e78 1800 int sr, c, br, err, recv_margin;
f303b364 1801 int min_err = 1000; /* 100% */
730c4e78 1802 int recv_max_margin = 0;
f303b364
UH		 1803
1804 /* Find the combination of sample rate and clock select with the
1805 smallest deviation from the desired baud rate. */
1806 for (sr = 8; sr <= 32; sr++) {
1807 for (c = 0; c <= 3; c++) {
1808 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1809 br = DIV_ROUND_CLOSEST(freq, (sr *
1810 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1811 br = clamp(br, 0, 255);
b7d66397
NI		 1812 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1813 (1 << (2 * c + 1)) / 1000)) -
1814 1000;
730c4e78
NI		 1815 /* Calc recv margin
1816 * M: Receive margin (%)
1817 * N: Ratio of bit rate to clock (N = sampling rate)
1818 * D: Clock duty (D = 0 to 1.0)
1819 * L: Frame length (L = 9 to 12)
1820 * F: Absolute value of clock frequency deviation
1821 *
1822 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1823 * (|D - 0.5| / N * (1 + F))|
1824 * NOTE: Usually, treat D for 0.5, F is 0 by this
1825 * calculation.
1826 */
1827 recv_margin = abs((500 -
1828 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1829 if (abs(min_err) > abs(err)) {
f303b364 1830 min_err = err;
730c4e78
NI		 1831 recv_max_margin = recv_margin;
1832 } else if ((min_err == err) &&
1833 (recv_margin > recv_max_margin))
1834 recv_max_margin = recv_margin;
1835 else
1836 continue;
1837
1838 *brr = br;
1839 *srr = sr - 1;
1840 *cks = c;
f303b364
UH		 1841 }
1842 }
1843
1844 if (min_err == 1000) {
1845 WARN_ON(1);
1846 /* use defaults */
1847 *brr = 255;
1848 *srr = 15;
1849 *cks = 0;
1850 }
1851}
1852
1ba76220
MD		 1853static void sci_reset(struct uart_port *port)
1854{
0979e0e6 1855 struct plat_sci_reg *reg;
1ba76220
MD		 1856 unsigned int status;
1857
1858 do {
b12bb29f 1859 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1860 } while (!(status & SCxSR_TEND(port)));
1861
b12bb29f 1862 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1863
0979e0e6
PM		 1864 reg = sci_getreg(port, SCFCR);
1865 if (reg->size)
b12bb29f 1866 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1867}
1868
606d099c
AC		 1869static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1870 struct ktermios *old)
1da177e4 1871{
00b9de9c 1872 struct sci_port *s = to_sci_port(port);
0979e0e6 1873 struct plat_sci_reg *reg;
730c4e78 1874 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1875 int t = -1;
d4759ded 1876 unsigned int srr = 15;
1da177e4 1877
730c4e78
NI		 1878 if ((termios->c_cflag & CSIZE) == CS7)
1879 smr_val |= SCSMR_CHR;
1880 if (termios->c_cflag & PARENB)
1881 smr_val |= SCSMR_PE;
1882 if (termios->c_cflag & PARODD)
1883 smr_val |= SCSMR_PE | SCSMR_ODD;
1884 if (termios->c_cflag & CSTOPB)
1885 smr_val |= SCSMR_STOP;
1886
154280fd
MD		 1887 /*
1888 * earlyprintk comes here early on with port->uartclk set to zero.
1889 * the clock framework is not up and running at this point so here
1890 * we assume that 115200 is the maximum baud rate. please note that
1891 * the baud rate is not programmed during earlyprintk - it is assumed
1892 * that the previous boot loader has enabled required clocks and
1893 * setup the baud rate generator hardware for us already.
1894 */
1895 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1896
154280fd 1897 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1898 if (likely(baud && port->uartclk)) {
ec09c5eb 1899 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1900 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1901 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1902 &cks, frame_len);
f303b364 1903 } else {
ec09c5eb 1904 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1905 for (cks = 0; t >= 256 && cks <= 3; cks++)
1906 t >>= 2;
1907 }
1908 }
e108b2ca 1909
23241d43 1910 sci_port_enable(s);
36003386 1911
1ba76220 1912 sci_reset(port);
1da177e4 1913
730c4e78 1914 smr_val |= serial_port_in(port, SCSMR) & 3;
1da177e4
LT		 1915
1916 uart_update_timeout(port, termios->c_cflag, baud);
1917
9d482cc3
TY		 1918 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1919 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1920
4ffc3cdb 1921 if (t >= 0) {
26de4f1b 1922 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1923 serial_port_out(port, SCBRR, t);
f303b364
UH		 1924 reg = sci_getreg(port, HSSRR);
1925 if (reg->size)
1926 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1927 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1928 } else
1929 serial_port_out(port, SCSMR, smr_val);
1da177e4 1930
d5701647 1931 sci_init_pins(port, termios->c_cflag);
0979e0e6 1932
73c3d53f
PM		 1933 reg = sci_getreg(port, SCFCR);
1934 if (reg->size) {
b12bb29f 1935 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1936
73c3d53f 1937 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1938 if (termios->c_cflag & CRTSCTS)
1939 ctrl |= SCFCR_MCE;
1940 else
1941 ctrl &= ~SCFCR_MCE;
faf02f8f 1942 }
73c3d53f
PM		 1943
1944 /*
1945 * As we've done a sci_reset() above, ensure we don't
1946 * interfere with the FIFOs while toggling MCE. As the
1947 * reset values could still be set, simply mask them out.
1948 */
1949 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1950
b12bb29f 1951 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1952 }
b7a76e4b 1953
b12bb29f 1954 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1955
3089f381
GL		 1956#ifdef CONFIG_SERIAL_SH_SCI_DMA
1957 /*
1958 * Calculate delay for 1.5 DMA buffers: see
1959 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1960 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1961 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1962 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1963 * sizes), but it has been found out experimentally, that this is not
1964 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1965 * as a minimum seem to work perfectly.
1966 */
1967 if (s->chan_rx) {
1968 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1969 port->fifosize / 2;
9b971cd2 1970 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 1971 s->rx_timeout * 1000 / HZ, port->timeout);
1972 if (s->rx_timeout < msecs_to_jiffies(20))
1973 s->rx_timeout = msecs_to_jiffies(20);
1974 }
1975#endif
1976
1da177e4 1977 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1978 sci_start_rx(port);
36003386 1979
23241d43 1980 sci_port_disable(s);
1da177e4
LT		 1981}
1982
0174e5ca
TK		 1983static void sci_pm(struct uart_port *port, unsigned int state,
1984 unsigned int oldstate)
1985{
1986 struct sci_port *sci_port = to_sci_port(port);
1987
1988 switch (state) {
d3dfe5d9 1989 case UART_PM_STATE_OFF:
0174e5ca
TK		 1990 sci_port_disable(sci_port);
1991 break;
1992 default:
1993 sci_port_enable(sci_port);
1994 break;
1995 }
1996}
1997
1da177e4
LT		 1998static const char *sci_type(struct uart_port *port)
1999{
2000 switch (port->type) {
e7c98dc7
MT		 2001 case PORT_IRDA:
2002 return "irda";
2003 case PORT_SCI:
2004 return "sci";
2005 case PORT_SCIF:
2006 return "scif";
2007 case PORT_SCIFA:
2008 return "scifa";
d1d4b10c
GL		 2009 case PORT_SCIFB:
2010 return "scifb";
f303b364
UH		 2011 case PORT_HSCIF:
2012 return "hscif";
1da177e4
LT		 2013 }
2014
fa43972f 2015 return NULL;
1da177e4
LT		 2016}
2017
e2651647 2018static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 2019{
e2651647
PM		 2020 /*
2021 * Pick an arbitrary size that encapsulates all of the base
2022 * registers by default. This can be optimized later, or derived
2023 * from platform resource data at such a time that ports begin to
2024 * behave more erratically.
2025 */
f303b364
UH		 2026 if (port->type == PORT_HSCIF)
2027 return 96;
2028 else
2029 return 64;
1da177e4
LT		 2030}
2031
f6e9495d
PM		 2032static int sci_remap_port(struct uart_port *port)
2033{
2034 unsigned long size = sci_port_size(port);
2035
2036 /*
2037 * Nothing to do if there's already an established membase.
2038 */
2039 if (port->membase)
2040 return 0;
2041
2042 if (port->flags & UPF_IOREMAP) {
2043 port->membase = ioremap_nocache(port->mapbase, size);
2044 if (unlikely(!port->membase)) {
2045 dev_err(port->dev, "can't remap port#%d\n", port->line);
2046 return -ENXIO;
2047 }
2048 } else {
2049 /*
2050 * For the simple (and majority of) cases where we don't
2051 * need to do any remapping, just cast the cookie
2052 * directly.
2053 */
3af4e960 2054 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2055 }
2056
2057 return 0;
2058}
2059
e2651647 2060static void sci_release_port(struct uart_port *port)
1da177e4 2061{
e2651647
PM		 2062 if (port->flags & UPF_IOREMAP) {
2063 iounmap(port->membase);
2064 port->membase = NULL;
2065 }
2066
2067 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2068}
2069
e2651647 2070static int sci_request_port(struct uart_port *port)
1da177e4 2071{
e2651647
PM		 2072 unsigned long size = sci_port_size(port);
2073 struct resource *res;
f6e9495d 2074 int ret;
1da177e4 2075
1020520e 2076 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2077 if (unlikely(res == NULL))
2078 return -EBUSY;
1da177e4 2079
f6e9495d
PM		 2080 ret = sci_remap_port(port);
2081 if (unlikely(ret != 0)) {
2082 release_resource(res);
2083 return ret;
7ff731ae 2084 }
e2651647
PM		 2085
2086 return 0;
2087}
2088
2089static void sci_config_port(struct uart_port *port, int flags)
2090{
2091 if (flags & UART_CONFIG_TYPE) {
2092 struct sci_port *sport = to_sci_port(port);
2093
2094 port->type = sport->cfg->type;
2095 sci_request_port(port);
2096 }
1da177e4
LT		 2097}
2098
2099static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2100{
1da177e4
LT		 2101 if (ser->baud_base < 2400)
2102 /* No paper tape reader for Mitch.. */
2103 return -EINVAL;
2104
2105 return 0;
2106}
2107
2108static struct uart_ops sci_uart_ops = {
2109 .tx_empty = sci_tx_empty,
2110 .set_mctrl = sci_set_mctrl,
2111 .get_mctrl = sci_get_mctrl,
2112 .start_tx = sci_start_tx,
2113 .stop_tx = sci_stop_tx,
2114 .stop_rx = sci_stop_rx,
1da177e4
LT		 2115 .break_ctl = sci_break_ctl,
2116 .startup = sci_startup,
2117 .shutdown = sci_shutdown,
2118 .set_termios = sci_set_termios,
0174e5ca 2119 .pm = sci_pm,
1da177e4
LT		 2120 .type = sci_type,
2121 .release_port = sci_release_port,
2122 .request_port = sci_request_port,
2123 .config_port = sci_config_port,
2124 .verify_port = sci_verify_port,
07d2a1a1
PM		 2125#ifdef CONFIG_CONSOLE_POLL
2126 .poll_get_char = sci_poll_get_char,
2127 .poll_put_char = sci_poll_put_char,
2128#endif
1da177e4
LT		 2129};
2130
9671f099 2131static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2132 struct sci_port *sci_port, unsigned int index,
2133 struct plat_sci_port *p, bool early)
e108b2ca 2134{
73a19e4c 2135 struct uart_port *port = &sci_port->port;
1fcc91a6 2136 const struct resource *res;
ec09c5eb 2137 unsigned int sampling_rate;
1fcc91a6 2138 unsigned int i;
3127c6b2 2139 int ret;
e108b2ca 2140
50f0959a
PM		 2141 sci_port->cfg = p;
2142
73a19e4c
GL		 2143 port->ops = &sci_uart_ops;
2144 port->iotype = UPIO_MEM;
2145 port->line = index;
75136d48 2146
89b5c1ab
LP		 2147 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2148 if (res == NULL)
2149 return -ENOMEM;
1fcc91a6 2150
89b5c1ab 2151 port->mapbase = res->start;
1fcc91a6 2152
89b5c1ab
LP		 2153 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2154 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2155
89b5c1ab
LP		 2156 /* The SCI generates several interrupts. They can be muxed together or
2157 * connected to different interrupt lines. In the muxed case only one
2158 * interrupt resource is specified. In the non-muxed case three or four
2159 * interrupt resources are specified, as the BRI interrupt is optional.
2160 */
2161 if (sci_port->irqs[0] < 0)
2162 return -ENXIO;
1fcc91a6 2163
89b5c1ab
LP		 2164 if (sci_port->irqs[1] < 0) {
2165 sci_port->irqs[1] = sci_port->irqs[0];
2166 sci_port->irqs[2] = sci_port->irqs[0];
2167 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2168 }
2169
b545e4f4
LP		 2170 if (p->regtype == SCIx_PROBE_REGTYPE) {
2171 ret = sci_probe_regmap(p);
2172 if (unlikely(ret))
2173 return ret;
2174 }
2175
75136d48 2176 switch (p->type) {
d1d4b10c
GL		 2177 case PORT_SCIFB:
2178 port->fifosize = 256;
b545e4f4 2179 sci_port->overrun_bit = 9;
ec09c5eb 2180 sampling_rate = 16;
d1d4b10c 2181 break;
f303b364
UH		 2182 case PORT_HSCIF:
2183 port->fifosize = 128;
ec09c5eb 2184 sampling_rate = 0;
b545e4f4 2185 sci_port->overrun_bit = 0;
f303b364 2186 break;
75136d48 2187 case PORT_SCIFA:
73a19e4c 2188 port->fifosize = 64;
b545e4f4 2189 sci_port->overrun_bit = 9;
ec09c5eb 2190 sampling_rate = 16;
75136d48
MP		 2191 break;
2192 case PORT_SCIF:
73a19e4c 2193 port->fifosize = 16;
ec09c5eb 2194 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
b545e4f4 2195 sci_port->overrun_bit = 9;
ec09c5eb
LP		 2196 sampling_rate = 16;
2197 } else {
b545e4f4 2198 sci_port->overrun_bit = 0;
ec09c5eb
LP		 2199 sampling_rate = 32;
2200 }
75136d48
MP		 2201 break;
2202 default:
73a19e4c 2203 port->fifosize = 1;
b545e4f4 2204 sci_port->overrun_bit = 5;
ec09c5eb 2205 sampling_rate = 32;
75136d48
MP		 2206 break;
2207 }
7b6fd3bf 2208
878fbb91
LP		 2209 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2210 * match the SoC datasheet, this should be investigated. Let platform
2211 * data override the sampling rate for now.
ec09c5eb 2212 */
878fbb91
LP		 2213 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2214 : sampling_rate;
ec09c5eb 2215
1fcc91a6 2216 if (!early) {
c7ed1ab3
PM		 2217 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2218 if (IS_ERR(sci_port->iclk)) {
2219 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2220 if (IS_ERR(sci_port->iclk)) {
2221 dev_err(&dev->dev, "can't get iclk\n");
2222 return PTR_ERR(sci_port->iclk);
2223 }
2224 }
2225
2226 /*
2227 * The function clock is optional, ignore it if we can't
2228 * find it.
2229 */
2230 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2231 if (IS_ERR(sci_port->fclk))
2232 sci_port->fclk = NULL;
2233
73a19e4c 2234 port->dev = &dev->dev;
5e50d2d6
MD		 2235
2236 pm_runtime_enable(&dev->dev);
7b6fd3bf 2237 }
e108b2ca 2238
7ed7e071
MD		 2239 sci_port->break_timer.data = (unsigned long)sci_port;
2240 sci_port->break_timer.function = sci_break_timer;
2241 init_timer(&sci_port->break_timer);
2242
debf9507
PM		 2243 /*
2244 * Establish some sensible defaults for the error detection.
2245 */
3ae988d9 2246 sci_port->error_mask = (p->type == PORT_SCI) ?
debf9507
PM		 2247 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2248
2249 /*
2250 * Establish sensible defaults for the overrun detection, unless
2251 * the part has explicitly disabled support for it.
2252 */
debf9507 2253
3ae988d9
LP		 2254 /*
2255 * Make the error mask inclusive of overrun detection, if
2256 * supported.
2257 */
2258 sci_port->error_mask |= 1 << sci_port->overrun_bit;
debf9507 2259
ce6738b6 2260 port->type = p->type;
b6e4a3f1 2261 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2262 port->regshift = p->regshift;
73a19e4c 2263
ce6738b6 2264 /*
61a6976b 2265 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2266 * for the multi-IRQ ports, which is where we are primarily
2267 * concerned with the shutdown path synchronization.
2268 *
2269 * For the muxed case there's nothing more to do.
2270 */
1fcc91a6 2271 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2272 port->irqflags = 0;
73a19e4c 2273
61a6976b
PM		 2274 port->serial_in = sci_serial_in;
2275 port->serial_out = sci_serial_out;
2276
937bb6e4
GL		 2277 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2278 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2279 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2280
c7ed1ab3 2281 return 0;
e108b2ca
PM		 2282}
2283
6dae1421
LP		 2284static void sci_cleanup_single(struct sci_port *port)
2285{
6dae1421
LP		 2286 clk_put(port->iclk);
2287 clk_put(port->fclk);
2288
2289 pm_runtime_disable(port->port.dev);
2290}
2291
1da177e4 2292#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2293static void serial_console_putchar(struct uart_port *port, int ch)
2294{
2295 sci_poll_put_char(port, ch);
2296}
2297
1da177e4
LT		 2298/*
2299 * Print a string to the serial port trying not to disturb
2300 * any possible real use of the port...
2301 */
2302static void serial_console_write(struct console *co, const char *s,
2303 unsigned count)
2304{
906b17dc
PM		 2305 struct sci_port *sci_port = &sci_ports[co->index];
2306 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2307 unsigned short bits, ctrl;
2308 unsigned long flags;
2309 int locked = 1;
2310
2311 local_irq_save(flags);
2312 if (port->sysrq)
2313 locked = 0;
2314 else if (oops_in_progress)
2315 locked = spin_trylock(&port->lock);
2316 else
2317 spin_lock(&port->lock);
2318
2319 /* first save the SCSCR then disable the interrupts */
2320 ctrl = serial_port_in(port, SCSCR);
2321 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2322
501b825d 2323 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2324
2325 /* wait until fifo is empty and last bit has been transmitted */
2326 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2327 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2328 cpu_relax();
40f70c03
SK		 2329
2330 /* restore the SCSCR */
2331 serial_port_out(port, SCSCR, ctrl);
2332
2333 if (locked)
2334 spin_unlock(&port->lock);
2335 local_irq_restore(flags);
1da177e4
LT		 2336}
2337
9671f099 2338static int serial_console_setup(struct console *co, char *options)
1da177e4 2339{
dc8e6f5b 2340 struct sci_port *sci_port;
1da177e4
LT		 2341 struct uart_port *port;
2342 int baud = 115200;
2343 int bits = 8;
2344 int parity = 'n';
2345 int flow = 'n';
2346 int ret;
2347
e108b2ca 2348 /*
906b17dc 2349 * Refuse to handle any bogus ports.
1da177e4 2350 */
906b17dc 2351 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2352 return -ENODEV;
e108b2ca 2353
906b17dc
PM		 2354 sci_port = &sci_ports[co->index];
2355 port = &sci_port->port;
2356
b2267a6b
AC		 2357 /*
2358 * Refuse to handle uninitialized ports.
2359 */
2360 if (!port->ops)
2361 return -ENODEV;
2362
f6e9495d
PM		 2363 ret = sci_remap_port(port);
2364 if (unlikely(ret != 0))
2365 return ret;
e108b2ca 2366
1da177e4
LT		 2367 if (options)
2368 uart_parse_options(options, &baud, &parity, &bits, &flow);
2369
ab7cfb55 2370 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2371}
2372
2373static struct console serial_console = {
2374 .name = "ttySC",
906b17dc 2375 .device = uart_console_device,
1da177e4
LT		 2376 .write = serial_console_write,
2377 .setup = serial_console_setup,
fa5da2f7 2378 .flags = CON_PRINTBUFFER,
1da177e4 2379 .index = -1,
906b17dc 2380 .data = &sci_uart_driver,
1da177e4
LT		 2381};
2382
7b6fd3bf
MD		 2383static struct console early_serial_console = {
2384 .name = "early_ttySC",
2385 .write = serial_console_write,
2386 .flags = CON_PRINTBUFFER,
906b17dc 2387 .index = -1,
7b6fd3bf 2388};
ecdf8a46 2389
7b6fd3bf
MD		 2390static char early_serial_buf[32];
2391
9671f099 2392static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2393{
574de559 2394 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2395
2396 if (early_serial_console.data)
2397 return -EEXIST;
2398
2399 early_serial_console.index = pdev->id;
ecdf8a46 2400
1fcc91a6 2401 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2402
2403 serial_console_setup(&early_serial_console, early_serial_buf);
2404
2405 if (!strstr(early_serial_buf, "keep"))
2406 early_serial_console.flags |= CON_BOOT;
2407
2408 register_console(&early_serial_console);
2409 return 0;
2410}
6a8c9799
NI		 2411
2412#define SCI_CONSOLE (&serial_console)
2413
ecdf8a46 2414#else
9671f099 2415static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2416{
2417 return -EINVAL;
2418}
1da177e4 2419
6a8c9799
NI		 2420#define SCI_CONSOLE NULL
2421
2422#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2423
6c13d5d2 2424static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2425
2426static struct uart_driver sci_uart_driver = {
2427 .owner = THIS_MODULE,
2428 .driver_name = "sci",
1da177e4
LT		 2429 .dev_name = "ttySC",
2430 .major = SCI_MAJOR,
2431 .minor = SCI_MINOR_START,
e108b2ca 2432 .nr = SCI_NPORTS,
1da177e4
LT		 2433 .cons = SCI_CONSOLE,
2434};
2435
54507f6e 2436static int sci_remove(struct platform_device *dev)
e552de24 2437{
d535a230 2438 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2439
d535a230
PM		 2440 cpufreq_unregister_notifier(&port->freq_transition,
2441 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2442
d535a230
PM		 2443 uart_remove_one_port(&sci_uart_driver, &port->port);
2444
6dae1421 2445 sci_cleanup_single(port);
e552de24 2446
e552de24
MD		 2447 return 0;
2448}
2449
20bdcab8
BH		 2450struct sci_port_info {
2451 unsigned int type;
2452 unsigned int regtype;
2453};
2454
2455static const struct of_device_id of_sci_match[] = {
2456 {
2457 .compatible = "renesas,scif",
ff43da00 2458 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2459 .type = PORT_SCIF,
2460 .regtype = SCIx_SH4_SCIF_REGTYPE,
2461 },
2462 }, {
2463 .compatible = "renesas,scifa",
ff43da00 2464 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2465 .type = PORT_SCIFA,
2466 .regtype = SCIx_SCIFA_REGTYPE,
2467 },
2468 }, {
2469 .compatible = "renesas,scifb",
ff43da00 2470 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2471 .type = PORT_SCIFB,
2472 .regtype = SCIx_SCIFB_REGTYPE,
2473 },
2474 }, {
2475 .compatible = "renesas,hscif",
ff43da00 2476 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2477 .type = PORT_HSCIF,
2478 .regtype = SCIx_HSCIF_REGTYPE,
2479 },
2480 }, {
2481 /* Terminator */
2482 },
2483};
2484MODULE_DEVICE_TABLE(of, of_sci_match);
2485
2486static struct plat_sci_port *
2487sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2488{
2489 struct device_node *np = pdev->dev.of_node;
2490 const struct of_device_id *match;
2491 const struct sci_port_info *info;
2492 struct plat_sci_port *p;
2493 int id;
2494
2495 if (!IS_ENABLED(CONFIG_OF) || !np)
2496 return NULL;
2497
2498 match = of_match_node(of_sci_match, pdev->dev.of_node);
2499 if (!match)
2500 return NULL;
2501
2502 info = match->data;
2503
2504 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2505 if (!p) {
2506 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2507 return NULL;
2508 }
2509
2510 /* Get the line number for the aliases node. */
2511 id = of_alias_get_id(np, "serial");
2512 if (id < 0) {
2513 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2514 return NULL;
2515 }
2516
2517 *dev_id = id;
2518
2519 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2520 p->type = info->type;
2521 p->regtype = info->regtype;
2522 p->scscr = SCSCR_RE | SCSCR_TE;
2523
2524 return p;
2525}
2526
9671f099 2527static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2528 unsigned int index,
2529 struct plat_sci_port *p,
2530 struct sci_port *sciport)
2531{
0ee70712
MD		 2532 int ret;
2533
2534 /* Sanity check */
2535 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2536 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2537 index+1, SCI_NPORTS);
9b971cd2 2538 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2539 return -EINVAL;
0ee70712
MD		 2540 }
2541
1fcc91a6 2542 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2543 if (ret)
2544 return ret;
0ee70712 2545
6dae1421
LP		 2546 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2547 if (ret) {
2548 sci_cleanup_single(sciport);
2549 return ret;
2550 }
2551
2552 return 0;
0ee70712
MD		 2553}
2554
9671f099 2555static int sci_probe(struct platform_device *dev)
1da177e4 2556{
20bdcab8
BH		 2557 struct plat_sci_port *p;
2558 struct sci_port *sp;
2559 unsigned int dev_id;
ecdf8a46 2560 int ret;
d535a230 2561
ecdf8a46
PM		 2562 /*
2563 * If we've come here via earlyprintk initialization, head off to
2564 * the special early probe. We don't have sufficient device state
2565 * to make it beyond this yet.
2566 */
2567 if (is_early_platform_device(dev))
2568 return sci_probe_earlyprintk(dev);
7b6fd3bf 2569
20bdcab8
BH		 2570 if (dev->dev.of_node) {
2571 p = sci_parse_dt(dev, &dev_id);
2572 if (p == NULL)
2573 return -EINVAL;
2574 } else {
2575 p = dev->dev.platform_data;
2576 if (p == NULL) {
2577 dev_err(&dev->dev, "no platform data supplied\n");
2578 return -EINVAL;
2579 }
2580
2581 dev_id = dev->id;
2582 }
2583
2584 sp = &sci_ports[dev_id];
d535a230 2585 platform_set_drvdata(dev, sp);
e552de24 2586
20bdcab8 2587 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2588 if (ret)
6dae1421 2589 return ret;
e552de24 2590
d535a230 2591 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2592
d535a230
PM		 2593 ret = cpufreq_register_notifier(&sp->freq_transition,
2594 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2595 if (unlikely(ret < 0)) {
bf13c9a8 2596 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2597 sci_cleanup_single(sp);
2598 return ret;
2599 }
1da177e4
LT		 2600
2601#ifdef CONFIG_SH_STANDARD_BIOS
2602 sh_bios_gdb_detach();
2603#endif
2604
e108b2ca 2605 return 0;
1da177e4
LT		 2606}
2607
cb876341 2608static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2609{
d535a230 2610 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2611
d535a230
PM		 2612 if (sport)
2613 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2614
e108b2ca
PM		 2615 return 0;
2616}
1da177e4 2617
cb876341 2618static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2619{
d535a230 2620 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2621
d535a230
PM		 2622 if (sport)
2623 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2624
2625 return 0;
2626}
2627
cb876341 2628static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2629
e108b2ca
PM		 2630static struct platform_driver sci_driver = {
2631 .probe = sci_probe,
b9e39c89 2632 .remove = sci_remove,
e108b2ca
PM		 2633 .driver = {
2634 .name = "sh-sci",
6daa79b3 2635 .pm = &sci_dev_pm_ops,
20bdcab8 2636 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2637 },
2638};
2639
2640static int __init sci_init(void)
2641{
2642 int ret;
2643
6c13d5d2 2644 pr_info("%s\n", banner);
e108b2ca 2645
e108b2ca
PM		 2646 ret = uart_register_driver(&sci_uart_driver);
2647 if (likely(ret == 0)) {
2648 ret = platform_driver_register(&sci_driver);
2649 if (unlikely(ret))
2650 uart_unregister_driver(&sci_uart_driver);
2651 }
2652
2653 return ret;
2654}
2655
2656static void __exit sci_exit(void)
2657{
2658 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2659 uart_unregister_driver(&sci_uart_driver);
2660}
2661
7b6fd3bf
MD		 2662#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2663early_platform_init_buffer("earlyprintk", &sci_driver,
2664 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2665#endif
1da177e4
LT		 2666module_init(sci_init);
2667module_exit(sci_exit);
2668
e108b2ca 2669MODULE_LICENSE("GPL");
e169c139 2670MODULE_ALIAS("platform:sh-sci");
7f405f9c 2671MODULE_AUTHOR("Paul Mundt");
f303b364 2672MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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