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Linux 3.13-rc1
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
4dc4c516 28#include <linux/sh_dma.h>
1da177e4
LT		 29#include <linux/timer.h>
30#include <linux/interrupt.h>
31#include <linux/tty.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/sysrq.h>
1da177e4
LT		 37#include <linux/ioport.h>
38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/console.h>
e108b2ca 42#include <linux/platform_device.h>
96de1a8f 43#include <linux/serial_sci.h>
1da177e4 44#include <linux/notifier.h>
5e50d2d6 45#include <linux/pm_runtime.h>
1da177e4 46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
73a19e4c 50#include <linux/dmaengine.h>
5beabc7f 51#include <linux/dma-mapping.h>
73a19e4c 52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
50f0959a 54#include <linux/gpio.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
e108b2ca
PM		 62struct sci_port {
63 struct uart_port port;
64
ce6738b6
PM		 65 /* Platform configuration */
66 struct plat_sci_port *cfg;
e108b2ca 67
e108b2ca
PM		 68 /* Break timer */
69 struct timer_list break_timer;
70 int break_flag;
1534a3b3 71
501b825d
MD		 72 /* Interface clock */
73 struct clk *iclk;
c7ed1ab3
PM		 74 /* Function clock */
75 struct clk *fclk;
edad1f20 76
9174fc8f 77 char *irqstr[SCIx_NR_IRQS];
50f0959a 78 char *gpiostr[SCIx_NR_FNS];
9174fc8f 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
e108b2ca
PM		 102};
103
1da177e4 104/* Function prototypes */
d535a230 105static void sci_start_tx(struct uart_port *port);
b129a8cc 106static void sci_stop_tx(struct uart_port *port);
d535a230 107static void sci_start_rx(struct uart_port *port);
1da177e4 108
e108b2ca 109#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 110
e108b2ca
PM		 111static struct sci_port sci_ports[SCI_NPORTS];
112static struct uart_driver sci_uart_driver;
1da177e4 113
e7c98dc7
MT		 114static inline struct sci_port *
115to_sci_port(struct uart_port *uart)
116{
117 return container_of(uart, struct sci_port, port);
118}
119
61a6976b
PM		 120struct plat_sci_reg {
121 u8 offset, size;
122};
123
124/* Helper for invalidating specific entries of an inherited map. */
125#define sci_reg_invalid { .offset = 0, .size = 0 }
126
127static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
130 },
131
132 /*
133 * Common SCI definitions, dependent on the port's regshift
134 * value.
135 */
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
f303b364 149 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 150 },
151
152 /*
153 * Common definitions for legacy IrDA ports, dependent on
154 * regshift value.
155 */
156 [SCIx_IRDA_REGTYPE] = {
157 [SCSMR] = { 0x00, 8 },
158 [SCBRR] = { 0x01, 8 },
159 [SCSCR] = { 0x02, 8 },
160 [SCxTDR] = { 0x03, 8 },
161 [SCxSR] = { 0x04, 8 },
162 [SCxRDR] = { 0x05, 8 },
163 [SCFCR] = { 0x06, 8 },
164 [SCFDR] = { 0x07, 16 },
165 [SCTFDR] = sci_reg_invalid,
166 [SCRFDR] = sci_reg_invalid,
167 [SCSPTR] = sci_reg_invalid,
168 [SCLSR] = sci_reg_invalid,
f303b364 169 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 170 },
171
172 /*
173 * Common SCIFA definitions.
174 */
175 [SCIx_SCIFA_REGTYPE] = {
176 [SCSMR] = { 0x00, 16 },
177 [SCBRR] = { 0x04, 8 },
178 [SCSCR] = { 0x08, 16 },
179 [SCxTDR] = { 0x20, 8 },
180 [SCxSR] = { 0x14, 16 },
181 [SCxRDR] = { 0x24, 8 },
182 [SCFCR] = { 0x18, 16 },
183 [SCFDR] = { 0x1c, 16 },
184 [SCTFDR] = sci_reg_invalid,
185 [SCRFDR] = sci_reg_invalid,
186 [SCSPTR] = sci_reg_invalid,
187 [SCLSR] = sci_reg_invalid,
f303b364 188 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 189 },
190
191 /*
192 * Common SCIFB definitions.
193 */
194 [SCIx_SCIFB_REGTYPE] = {
195 [SCSMR] = { 0x00, 16 },
196 [SCBRR] = { 0x04, 8 },
197 [SCSCR] = { 0x08, 16 },
198 [SCxTDR] = { 0x40, 8 },
199 [SCxSR] = { 0x14, 16 },
200 [SCxRDR] = { 0x60, 8 },
201 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 202 [SCFDR] = sci_reg_invalid,
203 [SCTFDR] = { 0x38, 16 },
204 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 205 [SCSPTR] = sci_reg_invalid,
206 [SCLSR] = sci_reg_invalid,
f303b364 207 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 208 },
209
3af1f8a4
PE		 210 /*
211 * Common SH-2(A) SCIF definitions for ports with FIFO data
212 * count registers.
213 */
214 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x0c, 8 },
219 [SCxSR] = { 0x10, 16 },
220 [SCxRDR] = { 0x14, 8 },
221 [SCFCR] = { 0x18, 16 },
222 [SCFDR] = { 0x1c, 16 },
223 [SCTFDR] = sci_reg_invalid,
224 [SCRFDR] = sci_reg_invalid,
225 [SCSPTR] = { 0x20, 16 },
226 [SCLSR] = { 0x24, 16 },
f303b364 227 [HSSRR] = sci_reg_invalid,
3af1f8a4
PE		 228 },
229
61a6976b
PM		 230 /*
231 * Common SH-3 SCIF definitions.
232 */
233 [SCIx_SH3_SCIF_REGTYPE] = {
234 [SCSMR] = { 0x00, 8 },
235 [SCBRR] = { 0x02, 8 },
236 [SCSCR] = { 0x04, 8 },
237 [SCxTDR] = { 0x06, 8 },
238 [SCxSR] = { 0x08, 16 },
239 [SCxRDR] = { 0x0a, 8 },
240 [SCFCR] = { 0x0c, 8 },
241 [SCFDR] = { 0x0e, 16 },
242 [SCTFDR] = sci_reg_invalid,
243 [SCRFDR] = sci_reg_invalid,
244 [SCSPTR] = sci_reg_invalid,
245 [SCLSR] = sci_reg_invalid,
f303b364 246 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 247 },
248
249 /*
250 * Common SH-4(A) SCIF(B) definitions.
251 */
252 [SCIx_SH4_SCIF_REGTYPE] = {
253 [SCSMR] = { 0x00, 16 },
254 [SCBRR] = { 0x04, 8 },
255 [SCSCR] = { 0x08, 16 },
256 [SCxTDR] = { 0x0c, 8 },
257 [SCxSR] = { 0x10, 16 },
258 [SCxRDR] = { 0x14, 8 },
259 [SCFCR] = { 0x18, 16 },
260 [SCFDR] = { 0x1c, 16 },
261 [SCTFDR] = sci_reg_invalid,
262 [SCRFDR] = sci_reg_invalid,
263 [SCSPTR] = { 0x20, 16 },
264 [SCLSR] = { 0x24, 16 },
f303b364
UH		 265 [HSSRR] = sci_reg_invalid,
266 },
267
268 /*
269 * Common HSCIF definitions.
270 */
271 [SCIx_HSCIF_REGTYPE] = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCTFDR] = sci_reg_invalid,
281 [SCRFDR] = sci_reg_invalid,
282 [SCSPTR] = { 0x20, 16 },
283 [SCLSR] = { 0x24, 16 },
284 [HSSRR] = { 0x40, 16 },
61a6976b
PM		 285 },
286
287 /*
288 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
289 * register.
290 */
291 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
292 [SCSMR] = { 0x00, 16 },
293 [SCBRR] = { 0x04, 8 },
294 [SCSCR] = { 0x08, 16 },
295 [SCxTDR] = { 0x0c, 8 },
296 [SCxSR] = { 0x10, 16 },
297 [SCxRDR] = { 0x14, 8 },
298 [SCFCR] = { 0x18, 16 },
299 [SCFDR] = { 0x1c, 16 },
300 [SCTFDR] = sci_reg_invalid,
301 [SCRFDR] = sci_reg_invalid,
302 [SCSPTR] = sci_reg_invalid,
303 [SCLSR] = { 0x24, 16 },
f303b364 304 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 305 },
306
307 /*
308 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
309 * count registers.
310 */
311 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
312 [SCSMR] = { 0x00, 16 },
313 [SCBRR] = { 0x04, 8 },
314 [SCSCR] = { 0x08, 16 },
315 [SCxTDR] = { 0x0c, 8 },
316 [SCxSR] = { 0x10, 16 },
317 [SCxRDR] = { 0x14, 8 },
318 [SCFCR] = { 0x18, 16 },
319 [SCFDR] = { 0x1c, 16 },
320 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
321 [SCRFDR] = { 0x20, 16 },
322 [SCSPTR] = { 0x24, 16 },
323 [SCLSR] = { 0x28, 16 },
f303b364 324 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 325 },
326
327 /*
328 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
329 * registers.
330 */
331 [SCIx_SH7705_SCIF_REGTYPE] = {
332 [SCSMR] = { 0x00, 16 },
333 [SCBRR] = { 0x04, 8 },
334 [SCSCR] = { 0x08, 16 },
335 [SCxTDR] = { 0x20, 8 },
336 [SCxSR] = { 0x14, 16 },
337 [SCxRDR] = { 0x24, 8 },
338 [SCFCR] = { 0x18, 16 },
339 [SCFDR] = { 0x1c, 16 },
340 [SCTFDR] = sci_reg_invalid,
341 [SCRFDR] = sci_reg_invalid,
342 [SCSPTR] = sci_reg_invalid,
343 [SCLSR] = sci_reg_invalid,
f303b364 344 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 345 },
346};
347
72b294cf
PM		 348#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
349
61a6976b
PM		 350/*
351 * The "offset" here is rather misleading, in that it refers to an enum
352 * value relative to the port mapping rather than the fixed offset
353 * itself, which needs to be manually retrieved from the platform's
354 * register map for the given port.
355 */
356static unsigned int sci_serial_in(struct uart_port *p, int offset)
357{
72b294cf 358 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 359
360 if (reg->size == 8)
361 return ioread8(p->membase + (reg->offset << p->regshift));
362 else if (reg->size == 16)
363 return ioread16(p->membase + (reg->offset << p->regshift));
364 else
365 WARN(1, "Invalid register access\n");
366
367 return 0;
368}
369
370static void sci_serial_out(struct uart_port *p, int offset, int value)
371{
72b294cf 372 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 373
374 if (reg->size == 8)
375 iowrite8(value, p->membase + (reg->offset << p->regshift));
376 else if (reg->size == 16)
377 iowrite16(value, p->membase + (reg->offset << p->regshift));
378 else
379 WARN(1, "Invalid register access\n");
380}
381
61a6976b
PM		 382static int sci_probe_regmap(struct plat_sci_port *cfg)
383{
384 switch (cfg->type) {
385 case PORT_SCI:
386 cfg->regtype = SCIx_SCI_REGTYPE;
387 break;
388 case PORT_IRDA:
389 cfg->regtype = SCIx_IRDA_REGTYPE;
390 break;
391 case PORT_SCIFA:
392 cfg->regtype = SCIx_SCIFA_REGTYPE;
393 break;
394 case PORT_SCIFB:
395 cfg->regtype = SCIx_SCIFB_REGTYPE;
396 break;
397 case PORT_SCIF:
398 /*
399 * The SH-4 is a bit of a misnomer here, although that's
400 * where this particular port layout originated. This
401 * configuration (or some slight variation thereof)
402 * remains the dominant model for all SCIFs.
403 */
404 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
405 break;
f303b364
UH		 406 case PORT_HSCIF:
407 cfg->regtype = SCIx_HSCIF_REGTYPE;
408 break;
61a6976b
PM		 409 default:
410 printk(KERN_ERR "Can't probe register map for given port\n");
411 return -EINVAL;
412 }
413
414 return 0;
415}
416
23241d43
PM		 417static void sci_port_enable(struct sci_port *sci_port)
418{
419 if (!sci_port->port.dev)
420 return;
421
422 pm_runtime_get_sync(sci_port->port.dev);
423
424 clk_enable(sci_port->iclk);
425 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
426 clk_enable(sci_port->fclk);
427}
428
429static void sci_port_disable(struct sci_port *sci_port)
430{
431 if (!sci_port->port.dev)
432 return;
433
434 clk_disable(sci_port->fclk);
435 clk_disable(sci_port->iclk);
436
437 pm_runtime_put_sync(sci_port->port.dev);
438}
439
07d2a1a1 440#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 441
442#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 443static int sci_poll_get_char(struct uart_port *port)
1da177e4 444{
1da177e4
LT		 445 unsigned short status;
446 int c;
447
e108b2ca 448 do {
b12bb29f 449 status = serial_port_in(port, SCxSR);
1da177e4 450 if (status & SCxSR_ERRORS(port)) {
b12bb29f 451 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 452 continue;
453 }
3f255eb3
JW		 454 break;
455 } while (1);
456
457 if (!(status & SCxSR_RDxF(port)))
458 return NO_POLL_CHAR;
07d2a1a1 459
b12bb29f 460 c = serial_port_in(port, SCxRDR);
07d2a1a1 461
e7c98dc7 462 /* Dummy read */
b12bb29f
PM		 463 serial_port_in(port, SCxSR);
464 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 465
466 return c;
467}
1f6fd5c9 468#endif
1da177e4 469
07d2a1a1 470static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 471{
1da177e4
LT		 472 unsigned short status;
473
1da177e4 474 do {
b12bb29f 475 status = serial_port_in(port, SCxSR);
1da177e4
LT		 476 } while (!(status & SCxSR_TDxE(port)));
477
b12bb29f
PM		 478 serial_port_out(port, SCxTDR, c);
479 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 480}
07d2a1a1 481#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 482
61a6976b 483static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 484{
61a6976b
PM		 485 struct sci_port *s = to_sci_port(port);
486 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 487
61a6976b
PM		 488 /*
489 * Use port-specific handler if provided.
490 */
491 if (s->cfg->ops && s->cfg->ops->init_pins) {
492 s->cfg->ops->init_pins(port, cflag);
493 return;
1da177e4 494 }
41504c39 495
61a6976b
PM		 496 /*
497 * For the generic path SCSPTR is necessary. Bail out if that's
498 * unavailable, too.
499 */
500 if (!reg->size)
501 return;
41504c39 502
faf02f8f
PM		 503 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
504 ((!(cflag & CRTSCTS)))) {
505 unsigned short status;
506
b12bb29f 507 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 508 status &= ~SCSPTR_CTSIO;
509 status |= SCSPTR_RTSIO;
b12bb29f 510 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 511 }
d5701647 512}
e108b2ca 513
72b294cf 514static int sci_txfill(struct uart_port *port)
e108b2ca 515{
72b294cf 516 struct plat_sci_reg *reg;
e108b2ca 517
72b294cf
PM		 518 reg = sci_getreg(port, SCTFDR);
519 if (reg->size)
63f7ad11 520 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 521
72b294cf
PM		 522 reg = sci_getreg(port, SCFDR);
523 if (reg->size)
b12bb29f 524 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 525
b12bb29f 526 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 527}
528
73a19e4c
GL		 529static int sci_txroom(struct uart_port *port)
530{
72b294cf 531 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 532}
533
534static int sci_rxfill(struct uart_port *port)
e108b2ca 535{
72b294cf
PM		 536 struct plat_sci_reg *reg;
537
538 reg = sci_getreg(port, SCRFDR);
539 if (reg->size)
63f7ad11 540 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 541
542 reg = sci_getreg(port, SCFDR);
543 if (reg->size)
b12bb29f 544 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 545
b12bb29f 546 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 547}
548
514820eb
PM		 549/*
550 * SCI helper for checking the state of the muxed port/RXD pins.
551 */
552static inline int sci_rxd_in(struct uart_port *port)
553{
554 struct sci_port *s = to_sci_port(port);
555
556 if (s->cfg->port_reg <= 0)
557 return 1;
558
0dd4d5cb
PM		 559 /* Cast for ARM damage */
560 return !!__raw_readb((void __iomem *)s->cfg->port_reg);
514820eb
PM		 561}
562
1da177e4
LT		 563/* ********************************************************************** *
564 * the interrupt related routines *
565 * ********************************************************************** */
566
567static void sci_transmit_chars(struct uart_port *port)
568{
ebd2c8f6 569 struct circ_buf *xmit = &port->state->xmit;
1da177e4 570 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 571 unsigned short status;
572 unsigned short ctrl;
e108b2ca 573 int count;
1da177e4 574
b12bb29f 575 status = serial_port_in(port, SCxSR);
1da177e4 576 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 577 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 578 if (uart_circ_empty(xmit))
8e698614 579 ctrl &= ~SCSCR_TIE;
e7c98dc7 580 else
8e698614 581 ctrl |= SCSCR_TIE;
b12bb29f 582 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 583 return;
584 }
585
72b294cf 586 count = sci_txroom(port);
1da177e4
LT		 587
588 do {
589 unsigned char c;
590
591 if (port->x_char) {
592 c = port->x_char;
593 port->x_char = 0;
594 } else if (!uart_circ_empty(xmit) && !stopped) {
595 c = xmit->buf[xmit->tail];
596 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
597 } else {
598 break;
599 }
600
b12bb29f 601 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 602
603 port->icount.tx++;
604 } while (--count > 0);
605
b12bb29f 606 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 607
608 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
609 uart_write_wakeup(port);
610 if (uart_circ_empty(xmit)) {
b129a8cc 611 sci_stop_tx(port);
1da177e4 612 } else {
b12bb29f 613 ctrl = serial_port_in(port, SCSCR);
1da177e4 614
1a22f08d 615 if (port->type != PORT_SCI) {
b12bb29f
PM		 616 serial_port_in(port, SCxSR); /* Dummy read */
617 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 618 }
1da177e4 619
8e698614 620 ctrl |= SCSCR_TIE;
b12bb29f 621 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 622 }
623}
624
625/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 626#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 627
94c8b6db 628static void sci_receive_chars(struct uart_port *port)
1da177e4 629{
e7c98dc7 630 struct sci_port *sci_port = to_sci_port(port);
227434f8 631 struct tty_port *tport = &port->state->port;
1da177e4
LT		 632 int i, count, copied = 0;
633 unsigned short status;
33f0f88f 634 unsigned char flag;
1da177e4 635
b12bb29f 636 status = serial_port_in(port, SCxSR);
1da177e4
LT		 637 if (!(status & SCxSR_RDxF(port)))
638 return;
639
640 while (1) {
1da177e4 641 /* Don't copy more bytes than there is room for in the buffer */
227434f8 642 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 643
644 /* If for any reason we can't copy more data, we're done! */
645 if (count == 0)
646 break;
647
648 if (port->type == PORT_SCI) {
b12bb29f 649 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 650 if (uart_handle_sysrq_char(port, c) ||
651 sci_port->break_flag)
1da177e4 652 count = 0;
e7c98dc7 653 else
92a19f9c 654 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 655 } else {
e7c98dc7 656 for (i = 0; i < count; i++) {
b12bb29f 657 char c = serial_port_in(port, SCxRDR);
d97fbbed 658
b12bb29f 659 status = serial_port_in(port, SCxSR);
1da177e4
LT		 660#if defined(CONFIG_CPU_SH3)
661 /* Skip "chars" during break */
e108b2ca 662 if (sci_port->break_flag) {
1da177e4
LT		 663 if ((c == 0) &&
664 (status & SCxSR_FER(port))) {
665 count--; i--;
666 continue;
667 }
e108b2ca 668
1da177e4 669 /* Nonzero => end-of-break */
762c69e3 670 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 671 sci_port->break_flag = 0;
672
1da177e4
LT		 673 if (STEPFN(c)) {
674 count--; i--;
675 continue;
676 }
677 }
678#endif /* CONFIG_CPU_SH3 */
7d12e780 679 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 680 count--; i--;
681 continue;
682 }
683
684 /* Store data and status */
73a19e4c 685 if (status & SCxSR_FER(port)) {
33f0f88f 686 flag = TTY_FRAME;
d97fbbed 687 port->icount.frame++;
762c69e3 688 dev_notice(port->dev, "frame error\n");
73a19e4c 689 } else if (status & SCxSR_PER(port)) {
33f0f88f 690 flag = TTY_PARITY;
d97fbbed 691 port->icount.parity++;
762c69e3 692 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 693 } else
694 flag = TTY_NORMAL;
762c69e3 695
92a19f9c 696 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 697 }
698 }
699
b12bb29f
PM		 700 serial_port_in(port, SCxSR); /* dummy read */
701 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 702
1da177e4
LT		 703 copied += count;
704 port->icount.rx += count;
705 }
706
707 if (copied) {
708 /* Tell the rest of the system the news. New characters! */
2e124b4a 709 tty_flip_buffer_push(tport);
1da177e4 710 } else {
b12bb29f
PM		 711 serial_port_in(port, SCxSR); /* dummy read */
712 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 713 }
714}
715
716#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 717
718/*
719 * The sci generates interrupts during the break,
1da177e4
LT		 720 * 1 per millisecond or so during the break period, for 9600 baud.
721 * So dont bother disabling interrupts.
722 * But dont want more than 1 break event.
723 * Use a kernel timer to periodically poll the rx line until
724 * the break is finished.
725 */
94c8b6db 726static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 727{
bc9b3f5c 728 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 729}
94c8b6db 730
1da177e4
LT		 731/* Ensure that two consecutive samples find the break over. */
732static void sci_break_timer(unsigned long data)
733{
e108b2ca
PM		 734 struct sci_port *port = (struct sci_port *)data;
735
23241d43 736 sci_port_enable(port);
5e50d2d6 737
e108b2ca 738 if (sci_rxd_in(&port->port) == 0) {
1da177e4 739 port->break_flag = 1;
e108b2ca
PM		 740 sci_schedule_break_timer(port);
741 } else if (port->break_flag == 1) {
1da177e4
LT		 742 /* break is over. */
743 port->break_flag = 2;
e108b2ca
PM		 744 sci_schedule_break_timer(port);
745 } else
746 port->break_flag = 0;
5e50d2d6 747
23241d43 748 sci_port_disable(port);
1da177e4
LT		 749}
750
94c8b6db 751static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 752{
753 int copied = 0;
b12bb29f 754 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 755 struct tty_port *tport = &port->state->port;
debf9507 756 struct sci_port *s = to_sci_port(port);
1da177e4 757
debf9507
PM		 758 /*
759 * Handle overruns, if supported.
760 */
761 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
762 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 763 port->icount.overrun++;
764
debf9507 765 /* overrun error */
92a19f9c 766 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
debf9507 767 copied++;
762c69e3 768
debf9507
PM		 769 dev_notice(port->dev, "overrun error");
770 }
1da177e4
LT		 771 }
772
e108b2ca 773 if (status & SCxSR_FER(port)) {
1da177e4
LT		 774 if (sci_rxd_in(port) == 0) {
775 /* Notify of BREAK */
e7c98dc7 776 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 777
778 if (!sci_port->break_flag) {
d97fbbed
PM		 779 port->icount.brk++;
780
e108b2ca
PM		 781 sci_port->break_flag = 1;
782 sci_schedule_break_timer(sci_port);
783
1da177e4 784 /* Do sysrq handling. */
e108b2ca 785 if (uart_handle_break(port))
1da177e4 786 return 0;
762c69e3
PM		 787
788 dev_dbg(port->dev, "BREAK detected\n");
789
92a19f9c 790 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 791 copied++;
792 }
793
e108b2ca 794 } else {
1da177e4 795 /* frame error */
d97fbbed
PM		 796 port->icount.frame++;
797
92a19f9c 798 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 799 copied++;
762c69e3
PM		 800
801 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 802 }
803 }
804
e108b2ca 805 if (status & SCxSR_PER(port)) {
1da177e4 806 /* parity error */
d97fbbed
PM		 807 port->icount.parity++;
808
92a19f9c 809 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 810 copied++;
762c69e3
PM		 811
812 dev_notice(port->dev, "parity error");
1da177e4
LT		 813 }
814
33f0f88f 815 if (copied)
2e124b4a 816 tty_flip_buffer_push(tport);
1da177e4
LT		 817
818 return copied;
819}
820
94c8b6db 821static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 822{
92a19f9c 823 struct tty_port *tport = &port->state->port;
debf9507 824 struct sci_port *s = to_sci_port(port);
4b8c59a3 825 struct plat_sci_reg *reg;
d830fa45
PM		 826 int copied = 0;
827
4b8c59a3
PM		 828 reg = sci_getreg(port, SCLSR);
829 if (!reg->size)
d830fa45
PM		 830 return 0;
831
b12bb29f
PM		 832 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
833 serial_port_out(port, SCLSR, 0);
d830fa45 834
d97fbbed
PM		 835 port->icount.overrun++;
836
92a19f9c 837 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 838 tty_flip_buffer_push(tport);
d830fa45
PM		 839
840 dev_notice(port->dev, "overrun error\n");
841 copied++;
842 }
843
844 return copied;
845}
846
94c8b6db 847static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 848{
849 int copied = 0;
b12bb29f 850 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 851 struct tty_port *tport = &port->state->port;
a5660ada 852 struct sci_port *s = to_sci_port(port);
1da177e4 853
0b3d4ef6
PM		 854 if (uart_handle_break(port))
855 return 0;
856
b7a76e4b 857 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 858#if defined(CONFIG_CPU_SH3)
859 /* Debounce break */
860 s->break_flag = 1;
861#endif
d97fbbed
PM		 862
863 port->icount.brk++;
864
1da177e4 865 /* Notify of BREAK */
92a19f9c 866 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 867 copied++;
762c69e3
PM		 868
869 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 870 }
871
33f0f88f 872 if (copied)
2e124b4a 873 tty_flip_buffer_push(tport);
e108b2ca 874
d830fa45
PM		 875 copied += sci_handle_fifo_overrun(port);
876
1da177e4
LT		 877 return copied;
878}
879
73a19e4c 880static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 881{
73a19e4c
GL		 882#ifdef CONFIG_SERIAL_SH_SCI_DMA
883 struct uart_port *port = ptr;
884 struct sci_port *s = to_sci_port(port);
885
886 if (s->chan_rx) {
b12bb29f
PM		 887 u16 scr = serial_port_in(port, SCSCR);
888 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 889
890 /* Disable future Rx interrupts */
d1d4b10c 891 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 892 disable_irq_nosync(irq);
893 scr |= 0x4000;
894 } else {
f43dc23d 895 scr &= ~SCSCR_RIE;
3089f381 896 }
b12bb29f 897 serial_port_out(port, SCSCR, scr);
73a19e4c 898 /* Clear current interrupt */
b12bb29f 899 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 900 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
901 jiffies, s->rx_timeout);
902 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 903
904 return IRQ_HANDLED;
905 }
906#endif
907
1da177e4
LT		 908 /* I think sci_receive_chars has to be called irrespective
909 * of whether the I_IXOFF is set, otherwise, how is the interrupt
910 * to be disabled?
911 */
73a19e4c 912 sci_receive_chars(ptr);
1da177e4
LT		 913
914 return IRQ_HANDLED;
915}
916
7d12e780 917static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 918{
919 struct uart_port *port = ptr;
fd78a76a 920 unsigned long flags;
1da177e4 921
fd78a76a 922 spin_lock_irqsave(&port->lock, flags);
1da177e4 923 sci_transmit_chars(port);
fd78a76a 924 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 925
926 return IRQ_HANDLED;
927}
928
7d12e780 929static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 930{
931 struct uart_port *port = ptr;
932
933 /* Handle errors */
934 if (port->type == PORT_SCI) {
935 if (sci_handle_errors(port)) {
936 /* discard character in rx buffer */
b12bb29f
PM		 937 serial_port_in(port, SCxSR);
938 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 939 }
940 } else {
d830fa45 941 sci_handle_fifo_overrun(port);
7d12e780 942 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 943 }
944
b12bb29f 945 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 946
947 /* Kick the transmission */
7d12e780 948 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 949
950 return IRQ_HANDLED;
951}
952
7d12e780 953static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 954{
955 struct uart_port *port = ptr;
956
957 /* Handle BREAKs */
958 sci_handle_breaks(port);
b12bb29f 959 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 960
961 return IRQ_HANDLED;
962}
963
f43dc23d
PM		 964static inline unsigned long port_rx_irq_mask(struct uart_port *port)
965{
966 /*
967 * Not all ports (such as SCIFA) will support REIE. Rather than
968 * special-casing the port type, we check the port initialization
969 * IRQ enable mask to see whether the IRQ is desired at all. If
970 * it's unset, it's logically inferred that there's no point in
971 * testing for it.
972 */
ce6738b6 973 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 974}
975
7d12e780 976static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 977{
44e18e9e 978 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 979 struct uart_port *port = ptr;
73a19e4c 980 struct sci_port *s = to_sci_port(port);
a8884e34 981 irqreturn_t ret = IRQ_NONE;
1da177e4 982
b12bb29f
PM		 983 ssr_status = serial_port_in(port, SCxSR);
984 scr_status = serial_port_in(port, SCSCR);
f43dc23d 985 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 986
987 /* Tx Interrupt */
f43dc23d 988 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 989 !s->chan_tx)
a8884e34 990 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 991
73a19e4c
GL		 992 /*
993 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
994 * DR flags
995 */
996 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 997 (scr_status & SCSCR_RIE))
a8884e34 998 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 999
1da177e4 1000 /* Error Interrupt */
dd4da3a5 1001 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1002 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1003
1da177e4 1004 /* Break Interrupt */
dd4da3a5 1005 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1006 ret = sci_br_interrupt(irq, ptr);
1da177e4 1007
a8884e34 1008 return ret;
1da177e4
LT		 1009}
1010
1da177e4 1011/*
25985edc 1012 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1013 * ports' baud rate when the peripheral clock changes.
1014 */
e108b2ca
PM		 1015static int sci_notifier(struct notifier_block *self,
1016 unsigned long phase, void *p)
1da177e4 1017{
e552de24
MD		 1018 struct sci_port *sci_port;
1019 unsigned long flags;
1da177e4 1020
d535a230
PM		 1021 sci_port = container_of(self, struct sci_port, freq_transition);
1022
1da177e4 1023 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 1024 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 1025 struct uart_port *port = &sci_port->port;
073e84c9 1026
d535a230
PM		 1027 spin_lock_irqsave(&port->lock, flags);
1028 port->uartclk = clk_get_rate(sci_port->iclk);
1029 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1030 }
1da177e4 1031
1da177e4
LT		 1032 return NOTIFY_OK;
1033}
501b825d 1034
9174fc8f
PM		 1035static struct sci_irq_desc {
1036 const char *desc;
1037 irq_handler_t handler;
1038} sci_irq_desc[] = {
1039 /*
1040 * Split out handlers, the default case.
1041 */
1042 [SCIx_ERI_IRQ] = {
1043 .desc = "rx err",
1044 .handler = sci_er_interrupt,
1045 },
1046
1047 [SCIx_RXI_IRQ] = {
1048 .desc = "rx full",
1049 .handler = sci_rx_interrupt,
1050 },
1051
1052 [SCIx_TXI_IRQ] = {
1053 .desc = "tx empty",
1054 .handler = sci_tx_interrupt,
1055 },
1056
1057 [SCIx_BRI_IRQ] = {
1058 .desc = "break",
1059 .handler = sci_br_interrupt,
1060 },
1061
1062 /*
1063 * Special muxed handler.
1064 */
1065 [SCIx_MUX_IRQ] = {
1066 .desc = "mux",
1067 .handler = sci_mpxed_interrupt,
1068 },
1069};
1070
1da177e4
LT		 1071static int sci_request_irq(struct sci_port *port)
1072{
9174fc8f
PM		 1073 struct uart_port *up = &port->port;
1074 int i, j, ret = 0;
1075
1076 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1077 struct sci_irq_desc *desc;
1078 unsigned int irq;
1079
1080 if (SCIx_IRQ_IS_MUXED(port)) {
1081 i = SCIx_MUX_IRQ;
1082 irq = up->irq;
0e8963de 1083 } else {
9174fc8f
PM		 1084 irq = port->cfg->irqs[i];
1085
0e8963de
PM		 1086 /*
1087 * Certain port types won't support all of the
1088 * available interrupt sources.
1089 */
1090 if (unlikely(!irq))
1091 continue;
1092 }
1093
9174fc8f
PM		 1094 desc = sci_irq_desc + i;
1095 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1096 dev_name(up->dev), desc->desc);
1097 if (!port->irqstr[j]) {
1098 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1099 desc->desc);
1100 goto out_nomem;
1da177e4 1101 }
9174fc8f
PM		 1102
1103 ret = request_irq(irq, desc->handler, up->irqflags,
1104 port->irqstr[j], port);
1105 if (unlikely(ret)) {
1106 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1107 goto out_noirq;
1da177e4
LT		 1108 }
1109 }
1110
1111 return 0;
9174fc8f
PM		 1112
1113out_noirq:
1114 while (--i >= 0)
1115 free_irq(port->cfg->irqs[i], port);
1116
1117out_nomem:
1118 while (--j >= 0)
1119 kfree(port->irqstr[j]);
1120
1121 return ret;
1da177e4
LT		 1122}
1123
1124static void sci_free_irq(struct sci_port *port)
1125{
1126 int i;
1127
9174fc8f
PM		 1128 /*
1129 * Intentionally in reverse order so we iterate over the muxed
1130 * IRQ first.
1131 */
1132 for (i = 0; i < SCIx_NR_IRQS; i++) {
0e8963de
PM		 1133 unsigned int irq = port->cfg->irqs[i];
1134
1135 /*
1136 * Certain port types won't support all of the available
1137 * interrupt sources.
1138 */
1139 if (unlikely(!irq))
1140 continue;
1141
9174fc8f
PM		 1142 free_irq(port->cfg->irqs[i], port);
1143 kfree(port->irqstr[i]);
1da177e4 1144
9174fc8f
PM		 1145 if (SCIx_IRQ_IS_MUXED(port)) {
1146 /* If there's only one IRQ, we're done. */
1147 return;
1da177e4
LT		 1148 }
1149 }
1150}
1151
50f0959a
PM		 1152static const char *sci_gpio_names[SCIx_NR_FNS] = {
1153 "sck", "rxd", "txd", "cts", "rts",
1154};
1155
1156static const char *sci_gpio_str(unsigned int index)
1157{
1158 return sci_gpio_names[index];
1159}
1160
9671f099 1161static void sci_init_gpios(struct sci_port *port)
50f0959a
PM		 1162{
1163 struct uart_port *up = &port->port;
1164 int i;
1165
1166 if (!port->cfg)
1167 return;
1168
1169 for (i = 0; i < SCIx_NR_FNS; i++) {
1170 const char *desc;
1171 int ret;
1172
1173 if (!port->cfg->gpios[i])
1174 continue;
1175
1176 desc = sci_gpio_str(i);
1177
1178 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1179 dev_name(up->dev), desc);
1180
1181 /*
1182 * If we've failed the allocation, we can still continue
1183 * on with a NULL string.
1184 */
1185 if (!port->gpiostr[i])
1186 dev_notice(up->dev, "%s string allocation failure\n",
1187 desc);
1188
1189 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1190 if (unlikely(ret != 0)) {
1191 dev_notice(up->dev, "failed %s gpio request\n", desc);
1192
1193 /*
1194 * If we can't get the GPIO for whatever reason,
1195 * no point in keeping the verbose string around.
1196 */
1197 kfree(port->gpiostr[i]);
1198 }
1199 }
1200}
1201
1202static void sci_free_gpios(struct sci_port *port)
1203{
1204 int i;
1205
1206 for (i = 0; i < SCIx_NR_FNS; i++)
1207 if (port->cfg->gpios[i]) {
1208 gpio_free(port->cfg->gpios[i]);
1209 kfree(port->gpiostr[i]);
1210 }
1211}
1212
1da177e4
LT		 1213static unsigned int sci_tx_empty(struct uart_port *port)
1214{
b12bb29f 1215 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1216 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1217
1218 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1219}
1220
cdf7c42f
PM		 1221/*
1222 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1223 * CTS/RTS is supported in hardware by at least one port and controlled
1224 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1225 * handled via the ->init_pins() op, which is a bit of a one-way street,
1226 * lacking any ability to defer pin control -- this will later be
1227 * converted over to the GPIO framework).
dc7e3ef7
PM		 1228 *
1229 * Other modes (such as loopback) are supported generically on certain
1230 * port types, but not others. For these it's sufficient to test for the
1231 * existence of the support register and simply ignore the port type.
cdf7c42f 1232 */
1da177e4
LT		 1233static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1234{
dc7e3ef7
PM		 1235 if (mctrl & TIOCM_LOOP) {
1236 struct plat_sci_reg *reg;
1237
1238 /*
1239 * Standard loopback mode for SCFCR ports.
1240 */
1241 reg = sci_getreg(port, SCFCR);
1242 if (reg->size)
b12bb29f 1243 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1244 }
1da177e4
LT		 1245}
1246
1247static unsigned int sci_get_mctrl(struct uart_port *port)
1248{
cdf7c42f
PM		 1249 /*
1250 * CTS/RTS is handled in hardware when supported, while nothing
1251 * else is wired up. Keep it simple and simply assert DSR/CAR.
1252 */
1253 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1254}
1255
73a19e4c
GL		 1256#ifdef CONFIG_SERIAL_SH_SCI_DMA
1257static void sci_dma_tx_complete(void *arg)
1258{
1259 struct sci_port *s = arg;
1260 struct uart_port *port = &s->port;
1261 struct circ_buf *xmit = &port->state->xmit;
1262 unsigned long flags;
1263
1264 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1265
1266 spin_lock_irqsave(&port->lock, flags);
1267
f354a381 1268 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1269 xmit->tail &= UART_XMIT_SIZE - 1;
1270
f354a381 1271 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1272
1273 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1274 s->desc_tx = NULL;
1275
73a19e4c
GL		 1276 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1277 uart_write_wakeup(port);
1278
3089f381 1279 if (!uart_circ_empty(xmit)) {
49d4bcad 1280 s->cookie_tx = 0;
73a19e4c 1281 schedule_work(&s->work_tx);
49d4bcad
YT		 1282 } else {
1283 s->cookie_tx = -EINVAL;
1284 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1285 u16 ctrl = serial_port_in(port, SCSCR);
1286 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1287 }
3089f381
GL		 1288 }
1289
1290 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1291}
1292
1293/* Locking: called with port lock held */
92a19f9c 1294static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1295{
1296 struct uart_port *port = &s->port;
227434f8 1297 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1298 int i, active, room;
1299
227434f8 1300 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1301
1302 if (s->active_rx == s->cookie_rx[0]) {
1303 active = 0;
1304 } else if (s->active_rx == s->cookie_rx[1]) {
1305 active = 1;
1306 } else {
1307 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1308 return 0;
1309 }
1310
1311 if (room < count)
1312 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1313 count - room);
1314 if (!room)
1315 return room;
1316
1317 for (i = 0; i < room; i++)
92a19f9c 1318 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1319 TTY_NORMAL);
1320
1321 port->icount.rx += room;
1322
1323 return room;
1324}
1325
1326static void sci_dma_rx_complete(void *arg)
1327{
1328 struct sci_port *s = arg;
1329 struct uart_port *port = &s->port;
73a19e4c
GL		 1330 unsigned long flags;
1331 int count;
1332
3089f381 1333 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1334
1335 spin_lock_irqsave(&port->lock, flags);
1336
92a19f9c 1337 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1338
3089f381 1339 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1340
1341 spin_unlock_irqrestore(&port->lock, flags);
1342
1343 if (count)
2e124b4a 1344 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1345
1346 schedule_work(&s->work_rx);
1347}
1348
73a19e4c
GL		 1349static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1350{
1351 struct dma_chan *chan = s->chan_rx;
1352 struct uart_port *port = &s->port;
73a19e4c
GL		 1353
1354 s->chan_rx = NULL;
1355 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1356 dma_release_channel(chan);
85b8e3ff
GL		 1357 if (sg_dma_address(&s->sg_rx[0]))
1358 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1359 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1360 if (enable_pio)
1361 sci_start_rx(port);
1362}
1363
1364static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1365{
1366 struct dma_chan *chan = s->chan_tx;
1367 struct uart_port *port = &s->port;
73a19e4c
GL		 1368
1369 s->chan_tx = NULL;
1370 s->cookie_tx = -EINVAL;
1371 dma_release_channel(chan);
1372 if (enable_pio)
1373 sci_start_tx(port);
1374}
1375
1376static void sci_submit_rx(struct sci_port *s)
1377{
1378 struct dma_chan *chan = s->chan_rx;
1379 int i;
1380
1381 for (i = 0; i < 2; i++) {
1382 struct scatterlist *sg = &s->sg_rx[i];
1383 struct dma_async_tx_descriptor *desc;
1384
16052827 1385 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1386 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1387
1388 if (desc) {
1389 s->desc_rx[i] = desc;
1390 desc->callback = sci_dma_rx_complete;
1391 desc->callback_param = s;
1392 s->cookie_rx[i] = desc->tx_submit(desc);
1393 }
1394
1395 if (!desc || s->cookie_rx[i] < 0) {
1396 if (i) {
1397 async_tx_ack(s->desc_rx[0]);
1398 s->cookie_rx[0] = -EINVAL;
1399 }
1400 if (desc) {
1401 async_tx_ack(desc);
1402 s->cookie_rx[i] = -EINVAL;
1403 }
1404 dev_warn(s->port.dev,
1405 "failed to re-start DMA, using PIO\n");
1406 sci_rx_dma_release(s, true);
1407 return;
1408 }
3089f381
GL		 1409 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1410 s->cookie_rx[i], i);
73a19e4c
GL		 1411 }
1412
1413 s->active_rx = s->cookie_rx[0];
1414
1415 dma_async_issue_pending(chan);
1416}
1417
1418static void work_fn_rx(struct work_struct *work)
1419{
1420 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1421 struct uart_port *port = &s->port;
1422 struct dma_async_tx_descriptor *desc;
1423 int new;
1424
1425 if (s->active_rx == s->cookie_rx[0]) {
1426 new = 0;
1427 } else if (s->active_rx == s->cookie_rx[1]) {
1428 new = 1;
1429 } else {
1430 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1431 return;
1432 }
1433 desc = s->desc_rx[new];
1434
1435 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1436 DMA_COMPLETE) {
73a19e4c 1437 /* Handle incomplete DMA receive */
73a19e4c 1438 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1439 struct shdma_desc *sh_desc = container_of(desc,
1440 struct shdma_desc, async_tx);
73a19e4c
GL		 1441 unsigned long flags;
1442 int count;
1443
05827630 1444 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1445 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1446 sh_desc->partial, sh_desc->cookie);
1447
1448 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1449 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1450 spin_unlock_irqrestore(&port->lock, flags);
1451
1452 if (count)
2e124b4a 1453 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1454
1455 sci_submit_rx(s);
1456
1457 return;
1458 }
1459
1460 s->cookie_rx[new] = desc->tx_submit(desc);
1461 if (s->cookie_rx[new] < 0) {
1462 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1463 sci_rx_dma_release(s, true);
1464 return;
1465 }
1466
73a19e4c 1467 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1468
1469 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1470 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1471}
1472
1473static void work_fn_tx(struct work_struct *work)
1474{
1475 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1476 struct dma_async_tx_descriptor *desc;
1477 struct dma_chan *chan = s->chan_tx;
1478 struct uart_port *port = &s->port;
1479 struct circ_buf *xmit = &port->state->xmit;
1480 struct scatterlist *sg = &s->sg_tx;
1481
1482 /*
1483 * DMA is idle now.
1484 * Port xmit buffer is already mapped, and it is one page... Just adjust
1485 * offsets and lengths. Since it is a circular buffer, we have to
1486 * transmit till the end, and then the rest. Take the port lock to get a
1487 * consistent xmit buffer state.
1488 */
1489 spin_lock_irq(&port->lock);
1490 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1491 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1492 sg->offset;
f354a381 1493 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1494 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1495 spin_unlock_irq(&port->lock);
1496
f354a381 1497 BUG_ON(!sg_dma_len(sg));
73a19e4c 1498
16052827 1499 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1500 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1501 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1502 if (!desc) {
1503 /* switch to PIO */
1504 sci_tx_dma_release(s, true);
1505 return;
1506 }
1507
1508 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1509
1510 spin_lock_irq(&port->lock);
1511 s->desc_tx = desc;
1512 desc->callback = sci_dma_tx_complete;
1513 desc->callback_param = s;
1514 spin_unlock_irq(&port->lock);
1515 s->cookie_tx = desc->tx_submit(desc);
1516 if (s->cookie_tx < 0) {
1517 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1518 /* switch to PIO */
1519 sci_tx_dma_release(s, true);
1520 return;
1521 }
1522
1523 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1524 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1525
1526 dma_async_issue_pending(chan);
1527}
1528#endif
1529
b129a8cc 1530static void sci_start_tx(struct uart_port *port)
1da177e4 1531{
3089f381 1532 struct sci_port *s = to_sci_port(port);
e108b2ca 1533 unsigned short ctrl;
1da177e4 1534
73a19e4c 1535#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1536 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1537 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1538 if (s->chan_tx)
1539 new = scr | 0x8000;
1540 else
1541 new = scr & ~0x8000;
1542 if (new != scr)
b12bb29f 1543 serial_port_out(port, SCSCR, new);
73a19e4c 1544 }
f43dc23d 1545
3089f381 1546 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1547 s->cookie_tx < 0) {
1548 s->cookie_tx = 0;
3089f381 1549 schedule_work(&s->work_tx);
49d4bcad 1550 }
73a19e4c 1551#endif
f43dc23d 1552
d1d4b10c 1553 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1554 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1555 ctrl = serial_port_in(port, SCSCR);
1556 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1557 }
1da177e4
LT		 1558}
1559
b129a8cc 1560static void sci_stop_tx(struct uart_port *port)
1da177e4 1561{
1da177e4
LT		 1562 unsigned short ctrl;
1563
1564 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1565 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1566
d1d4b10c 1567 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1568 ctrl &= ~0x8000;
f43dc23d 1569
8e698614 1570 ctrl &= ~SCSCR_TIE;
f43dc23d 1571
b12bb29f 1572 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1573}
1574
73a19e4c 1575static void sci_start_rx(struct uart_port *port)
1da177e4 1576{
1da177e4
LT		 1577 unsigned short ctrl;
1578
b12bb29f 1579 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1580
d1d4b10c 1581 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1582 ctrl &= ~0x4000;
f43dc23d 1583
b12bb29f 1584 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1585}
1586
1587static void sci_stop_rx(struct uart_port *port)
1588{
1da177e4
LT		 1589 unsigned short ctrl;
1590
b12bb29f 1591 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1592
d1d4b10c 1593 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1594 ctrl &= ~0x4000;
f43dc23d
PM		 1595
1596 ctrl &= ~port_rx_irq_mask(port);
1597
b12bb29f 1598 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1599}
1600
1601static void sci_enable_ms(struct uart_port *port)
1602{
d39ec6ce
PM		 1603 /*
1604 * Not supported by hardware, always a nop.
1605 */
1da177e4
LT		 1606}
1607
1608static void sci_break_ctl(struct uart_port *port, int break_state)
1609{
bbb4ce50 1610 struct sci_port *s = to_sci_port(port);
a4e02f6d 1611 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1612 unsigned short scscr, scsptr;
1613
a4e02f6d
SY		 1614 /* check wheter the port has SCSPTR */
1615 if (!reg->size) {
bbb4ce50
SY		 1616 /*
1617 * Not supported by hardware. Most parts couple break and rx
1618 * interrupts together, with break detection always enabled.
1619 */
a4e02f6d 1620 return;
bbb4ce50 1621 }
a4e02f6d
SY		 1622
1623 scsptr = serial_port_in(port, SCSPTR);
1624 scscr = serial_port_in(port, SCSCR);
1625
1626 if (break_state == -1) {
1627 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1628 scscr &= ~SCSCR_TE;
1629 } else {
1630 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1631 scscr |= SCSCR_TE;
1632 }
1633
1634 serial_port_out(port, SCSPTR, scsptr);
1635 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1636}
1637
73a19e4c
GL		 1638#ifdef CONFIG_SERIAL_SH_SCI_DMA
1639static bool filter(struct dma_chan *chan, void *slave)
1640{
1641 struct sh_dmae_slave *param = slave;
1642
1643 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1644 param->shdma_slave.slave_id);
73a19e4c 1645
d6fa5a4e 1646 chan->private = &param->shdma_slave;
937bb6e4 1647 return true;
73a19e4c
GL		 1648}
1649
1650static void rx_timer_fn(unsigned long arg)
1651{
1652 struct sci_port *s = (struct sci_port *)arg;
1653 struct uart_port *port = &s->port;
b12bb29f 1654 u16 scr = serial_port_in(port, SCSCR);
3089f381 1655
d1d4b10c 1656 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1657 scr &= ~0x4000;
ce6738b6 1658 enable_irq(s->cfg->irqs[1]);
3089f381 1659 }
b12bb29f 1660 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1661 dev_dbg(port->dev, "DMA Rx timed out\n");
1662 schedule_work(&s->work_rx);
1663}
1664
1665static void sci_request_dma(struct uart_port *port)
1666{
1667 struct sci_port *s = to_sci_port(port);
1668 struct sh_dmae_slave *param;
1669 struct dma_chan *chan;
1670 dma_cap_mask_t mask;
1671 int nent;
1672
937bb6e4
GL		 1673 dev_dbg(port->dev, "%s: port %d\n", __func__,
1674 port->line);
73a19e4c 1675
937bb6e4 1676 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1677 return;
1678
1679 dma_cap_zero(mask);
1680 dma_cap_set(DMA_SLAVE, mask);
1681
1682 param = &s->param_tx;
1683
1684 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1685 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1686
1687 s->cookie_tx = -EINVAL;
1688 chan = dma_request_channel(mask, filter, param);
1689 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1690 if (chan) {
1691 s->chan_tx = chan;
1692 sg_init_table(&s->sg_tx, 1);
1693 /* UART circular tx buffer is an aligned page. */
1694 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1695 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1696 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1697 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1698 if (!nent)
1699 sci_tx_dma_release(s, false);
1700 else
1701 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1702 sg_dma_len(&s->sg_tx),
1703 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1704
1705 s->sg_len_tx = nent;
1706
1707 INIT_WORK(&s->work_tx, work_fn_tx);
1708 }
1709
1710 param = &s->param_rx;
1711
1712 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1713 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1714
1715 chan = dma_request_channel(mask, filter, param);
1716 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1717 if (chan) {
1718 dma_addr_t dma[2];
1719 void *buf[2];
1720 int i;
1721
1722 s->chan_rx = chan;
1723
1724 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1725 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1726 &dma[0], GFP_KERNEL);
1727
1728 if (!buf[0]) {
1729 dev_warn(port->dev,
1730 "failed to allocate dma buffer, using PIO\n");
1731 sci_rx_dma_release(s, true);
1732 return;
1733 }
1734
1735 buf[1] = buf[0] + s->buf_len_rx;
1736 dma[1] = dma[0] + s->buf_len_rx;
1737
1738 for (i = 0; i < 2; i++) {
1739 struct scatterlist *sg = &s->sg_rx[i];
1740
1741 sg_init_table(sg, 1);
1742 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1743 (int)buf[i] & ~PAGE_MASK);
f354a381 1744 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1745 }
1746
1747 INIT_WORK(&s->work_rx, work_fn_rx);
1748 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1749
1750 sci_submit_rx(s);
1751 }
1752}
1753
1754static void sci_free_dma(struct uart_port *port)
1755{
1756 struct sci_port *s = to_sci_port(port);
1757
73a19e4c
GL		 1758 if (s->chan_tx)
1759 sci_tx_dma_release(s, false);
1760 if (s->chan_rx)
1761 sci_rx_dma_release(s, false);
1762}
27bd1075
PM		 1763#else
1764static inline void sci_request_dma(struct uart_port *port)
1765{
1766}
1767
1768static inline void sci_free_dma(struct uart_port *port)
1769{
1770}
73a19e4c
GL		 1771#endif
1772
1da177e4
LT		 1773static int sci_startup(struct uart_port *port)
1774{
a5660ada 1775 struct sci_port *s = to_sci_port(port);
33b48e16 1776 unsigned long flags;
073e84c9 1777 int ret;
1da177e4 1778
73a19e4c
GL		 1779 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1780
073e84c9
PM		 1781 ret = sci_request_irq(s);
1782 if (unlikely(ret < 0))
1783 return ret;
1784
73a19e4c 1785 sci_request_dma(port);
073e84c9 1786
33b48e16 1787 spin_lock_irqsave(&port->lock, flags);
d656901b 1788 sci_start_tx(port);
73a19e4c 1789 sci_start_rx(port);
33b48e16 1790 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1791
1792 return 0;
1793}
1794
1795static void sci_shutdown(struct uart_port *port)
1796{
a5660ada 1797 struct sci_port *s = to_sci_port(port);
33b48e16 1798 unsigned long flags;
1da177e4 1799
73a19e4c
GL		 1800 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1801
33b48e16 1802 spin_lock_irqsave(&port->lock, flags);
1da177e4 1803 sci_stop_rx(port);
b129a8cc 1804 sci_stop_tx(port);
33b48e16 1805 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1806
73a19e4c 1807 sci_free_dma(port);
1da177e4 1808 sci_free_irq(s);
1da177e4
LT		 1809}
1810
26c92f37
PM		 1811static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1812 unsigned long freq)
1813{
1814 switch (algo_id) {
1815 case SCBRR_ALGO_1:
1816 return ((freq + 16 * bps) / (16 * bps) - 1);
1817 case SCBRR_ALGO_2:
1818 return ((freq + 16 * bps) / (32 * bps) - 1);
1819 case SCBRR_ALGO_3:
1820 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1821 case SCBRR_ALGO_4:
1822 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1823 case SCBRR_ALGO_5:
1824 return (((freq * 1000 / 32) / bps) - 1);
1825 }
1826
1827 /* Warn, but use a safe default */
1828 WARN_ON(1);
e8183a6c 1829
26c92f37
PM		 1830 return ((freq + 16 * bps) / (32 * bps) - 1);
1831}
1832
f303b364
UH		 1833/* calculate sample rate, BRR, and clock select for HSCIF */
1834static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1835 int *brr, unsigned int *srr,
1836 unsigned int *cks)
1837{
1838 int sr, c, br, err;
1839 int min_err = 1000; /* 100% */
1840
1841 /* Find the combination of sample rate and clock select with the
1842 smallest deviation from the desired baud rate. */
1843 for (sr = 8; sr <= 32; sr++) {
1844 for (c = 0; c <= 3; c++) {
1845 /* integerized formulas from HSCIF documentation */
1846 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1847 if (br < 0 || br > 255)
1848 continue;
1849 err = freq / ((br + 1) * bps * sr *
1850 (1 << (2 * c + 1)) / 1000) - 1000;
1851 if (min_err > err) {
1852 min_err = err;
1853 *brr = br;
1854 *srr = sr - 1;
1855 *cks = c;
1856 }
1857 }
1858 }
1859
1860 if (min_err == 1000) {
1861 WARN_ON(1);
1862 /* use defaults */
1863 *brr = 255;
1864 *srr = 15;
1865 *cks = 0;
1866 }
1867}
1868
1ba76220
MD		 1869static void sci_reset(struct uart_port *port)
1870{
0979e0e6 1871 struct plat_sci_reg *reg;
1ba76220
MD		 1872 unsigned int status;
1873
1874 do {
b12bb29f 1875 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1876 } while (!(status & SCxSR_TEND(port)));
1877
b12bb29f 1878 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1879
0979e0e6
PM		 1880 reg = sci_getreg(port, SCFCR);
1881 if (reg->size)
b12bb29f 1882 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1883}
1884
606d099c
AC		 1885static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1886 struct ktermios *old)
1da177e4 1887{
00b9de9c 1888 struct sci_port *s = to_sci_port(port);
0979e0e6 1889 struct plat_sci_reg *reg;
d4759ded 1890 unsigned int baud, smr_val, max_baud, cks = 0;
a2159b52 1891 int t = -1;
d4759ded 1892 unsigned int srr = 15;
1da177e4 1893
154280fd
MD		 1894 /*
1895 * earlyprintk comes here early on with port->uartclk set to zero.
1896 * the clock framework is not up and running at this point so here
1897 * we assume that 115200 is the maximum baud rate. please note that
1898 * the baud rate is not programmed during earlyprintk - it is assumed
1899 * that the previous boot loader has enabled required clocks and
1900 * setup the baud rate generator hardware for us already.
1901 */
1902 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1903
154280fd 1904 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364
UH		 1905 if (likely(baud && port->uartclk)) {
1906 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1907 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1908 &cks);
1909 } else {
1910 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1911 port->uartclk);
1912 for (cks = 0; t >= 256 && cks <= 3; cks++)
1913 t >>= 2;
1914 }
1915 }
e108b2ca 1916
23241d43 1917 sci_port_enable(s);
36003386 1918
1ba76220 1919 sci_reset(port);
1da177e4 1920
b12bb29f 1921 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1922
1da177e4
LT		 1923 if ((termios->c_cflag & CSIZE) == CS7)
1924 smr_val |= 0x40;
1925 if (termios->c_cflag & PARENB)
1926 smr_val |= 0x20;
1927 if (termios->c_cflag & PARODD)
1928 smr_val |= 0x30;
1929 if (termios->c_cflag & CSTOPB)
1930 smr_val |= 0x08;
1931
1932 uart_update_timeout(port, termios->c_cflag, baud);
1933
9d482cc3
TY		 1934 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1935 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1936
4ffc3cdb 1937 if (t >= 0) {
9d482cc3 1938 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1939 serial_port_out(port, SCBRR, t);
f303b364
UH		 1940 reg = sci_getreg(port, HSSRR);
1941 if (reg->size)
1942 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1943 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1944 } else
1945 serial_port_out(port, SCSMR, smr_val);
1da177e4 1946
d5701647 1947 sci_init_pins(port, termios->c_cflag);
0979e0e6 1948
73c3d53f
PM		 1949 reg = sci_getreg(port, SCFCR);
1950 if (reg->size) {
b12bb29f 1951 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1952
73c3d53f 1953 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1954 if (termios->c_cflag & CRTSCTS)
1955 ctrl |= SCFCR_MCE;
1956 else
1957 ctrl &= ~SCFCR_MCE;
faf02f8f 1958 }
73c3d53f
PM		 1959
1960 /*
1961 * As we've done a sci_reset() above, ensure we don't
1962 * interfere with the FIFOs while toggling MCE. As the
1963 * reset values could still be set, simply mask them out.
1964 */
1965 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1966
b12bb29f 1967 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1968 }
b7a76e4b 1969
b12bb29f 1970 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1971
3089f381
GL		 1972#ifdef CONFIG_SERIAL_SH_SCI_DMA
1973 /*
1974 * Calculate delay for 1.5 DMA buffers: see
1975 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1976 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1977 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1978 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1979 * sizes), but it has been found out experimentally, that this is not
1980 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1981 * as a minimum seem to work perfectly.
1982 */
1983 if (s->chan_rx) {
1984 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1985 port->fifosize / 2;
1986 dev_dbg(port->dev,
1987 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1988 s->rx_timeout * 1000 / HZ, port->timeout);
1989 if (s->rx_timeout < msecs_to_jiffies(20))
1990 s->rx_timeout = msecs_to_jiffies(20);
1991 }
1992#endif
1993
1da177e4 1994 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1995 sci_start_rx(port);
36003386 1996
23241d43 1997 sci_port_disable(s);
1da177e4
LT		 1998}
1999
0174e5ca
TK		 2000static void sci_pm(struct uart_port *port, unsigned int state,
2001 unsigned int oldstate)
2002{
2003 struct sci_port *sci_port = to_sci_port(port);
2004
2005 switch (state) {
2006 case 3:
2007 sci_port_disable(sci_port);
2008 break;
2009 default:
2010 sci_port_enable(sci_port);
2011 break;
2012 }
2013}
2014
1da177e4
LT		 2015static const char *sci_type(struct uart_port *port)
2016{
2017 switch (port->type) {
e7c98dc7
MT		 2018 case PORT_IRDA:
2019 return "irda";
2020 case PORT_SCI:
2021 return "sci";
2022 case PORT_SCIF:
2023 return "scif";
2024 case PORT_SCIFA:
2025 return "scifa";
d1d4b10c
GL		 2026 case PORT_SCIFB:
2027 return "scifb";
f303b364
UH		 2028 case PORT_HSCIF:
2029 return "hscif";
1da177e4
LT		 2030 }
2031
fa43972f 2032 return NULL;
1da177e4
LT		 2033}
2034
e2651647 2035static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 2036{
e2651647
PM		 2037 /*
2038 * Pick an arbitrary size that encapsulates all of the base
2039 * registers by default. This can be optimized later, or derived
2040 * from platform resource data at such a time that ports begin to
2041 * behave more erratically.
2042 */
f303b364
UH		 2043 if (port->type == PORT_HSCIF)
2044 return 96;
2045 else
2046 return 64;
1da177e4
LT		 2047}
2048
f6e9495d
PM		 2049static int sci_remap_port(struct uart_port *port)
2050{
2051 unsigned long size = sci_port_size(port);
2052
2053 /*
2054 * Nothing to do if there's already an established membase.
2055 */
2056 if (port->membase)
2057 return 0;
2058
2059 if (port->flags & UPF_IOREMAP) {
2060 port->membase = ioremap_nocache(port->mapbase, size);
2061 if (unlikely(!port->membase)) {
2062 dev_err(port->dev, "can't remap port#%d\n", port->line);
2063 return -ENXIO;
2064 }
2065 } else {
2066 /*
2067 * For the simple (and majority of) cases where we don't
2068 * need to do any remapping, just cast the cookie
2069 * directly.
2070 */
2071 port->membase = (void __iomem *)port->mapbase;
2072 }
2073
2074 return 0;
2075}
2076
e2651647 2077static void sci_release_port(struct uart_port *port)
1da177e4 2078{
e2651647
PM		 2079 if (port->flags & UPF_IOREMAP) {
2080 iounmap(port->membase);
2081 port->membase = NULL;
2082 }
2083
2084 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2085}
2086
e2651647 2087static int sci_request_port(struct uart_port *port)
1da177e4 2088{
e2651647
PM		 2089 unsigned long size = sci_port_size(port);
2090 struct resource *res;
f6e9495d 2091 int ret;
1da177e4 2092
1020520e 2093 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2094 if (unlikely(res == NULL))
2095 return -EBUSY;
1da177e4 2096
f6e9495d
PM		 2097 ret = sci_remap_port(port);
2098 if (unlikely(ret != 0)) {
2099 release_resource(res);
2100 return ret;
7ff731ae 2101 }
e2651647
PM		 2102
2103 return 0;
2104}
2105
2106static void sci_config_port(struct uart_port *port, int flags)
2107{
2108 if (flags & UART_CONFIG_TYPE) {
2109 struct sci_port *sport = to_sci_port(port);
2110
2111 port->type = sport->cfg->type;
2112 sci_request_port(port);
2113 }
1da177e4
LT		 2114}
2115
2116static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2117{
a5660ada 2118 struct sci_port *s = to_sci_port(port);
1da177e4 2119
ce6738b6 2120 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 2121 return -EINVAL;
2122 if (ser->baud_base < 2400)
2123 /* No paper tape reader for Mitch.. */
2124 return -EINVAL;
2125
2126 return 0;
2127}
2128
2129static struct uart_ops sci_uart_ops = {
2130 .tx_empty = sci_tx_empty,
2131 .set_mctrl = sci_set_mctrl,
2132 .get_mctrl = sci_get_mctrl,
2133 .start_tx = sci_start_tx,
2134 .stop_tx = sci_stop_tx,
2135 .stop_rx = sci_stop_rx,
2136 .enable_ms = sci_enable_ms,
2137 .break_ctl = sci_break_ctl,
2138 .startup = sci_startup,
2139 .shutdown = sci_shutdown,
2140 .set_termios = sci_set_termios,
0174e5ca 2141 .pm = sci_pm,
1da177e4
LT		 2142 .type = sci_type,
2143 .release_port = sci_release_port,
2144 .request_port = sci_request_port,
2145 .config_port = sci_config_port,
2146 .verify_port = sci_verify_port,
07d2a1a1
PM		 2147#ifdef CONFIG_CONSOLE_POLL
2148 .poll_get_char = sci_poll_get_char,
2149 .poll_put_char = sci_poll_put_char,
2150#endif
1da177e4
LT		 2151};
2152
9671f099 2153static int sci_init_single(struct platform_device *dev,
c7ed1ab3
PM		 2154 struct sci_port *sci_port,
2155 unsigned int index,
2156 struct plat_sci_port *p)
e108b2ca 2157{
73a19e4c 2158 struct uart_port *port = &sci_port->port;
3127c6b2 2159 int ret;
e108b2ca 2160
50f0959a
PM		 2161 sci_port->cfg = p;
2162
73a19e4c
GL		 2163 port->ops = &sci_uart_ops;
2164 port->iotype = UPIO_MEM;
2165 port->line = index;
75136d48
MP		 2166
2167 switch (p->type) {
d1d4b10c
GL		 2168 case PORT_SCIFB:
2169 port->fifosize = 256;
2170 break;
f303b364
UH		 2171 case PORT_HSCIF:
2172 port->fifosize = 128;
2173 break;
75136d48 2174 case PORT_SCIFA:
73a19e4c 2175 port->fifosize = 64;
75136d48
MP		 2176 break;
2177 case PORT_SCIF:
73a19e4c 2178 port->fifosize = 16;
75136d48
MP		 2179 break;
2180 default:
73a19e4c 2181 port->fifosize = 1;
75136d48
MP		 2182 break;
2183 }
7b6fd3bf 2184
3127c6b2
PM		 2185 if (p->regtype == SCIx_PROBE_REGTYPE) {
2186 ret = sci_probe_regmap(p);
fc97114b 2187 if (unlikely(ret))
3127c6b2
PM		 2188 return ret;
2189 }
61a6976b 2190
7b6fd3bf 2191 if (dev) {
c7ed1ab3
PM		 2192 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2193 if (IS_ERR(sci_port->iclk)) {
2194 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2195 if (IS_ERR(sci_port->iclk)) {
2196 dev_err(&dev->dev, "can't get iclk\n");
2197 return PTR_ERR(sci_port->iclk);
2198 }
2199 }
2200
2201 /*
2202 * The function clock is optional, ignore it if we can't
2203 * find it.
2204 */
2205 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2206 if (IS_ERR(sci_port->fclk))
2207 sci_port->fclk = NULL;
2208
73a19e4c 2209 port->dev = &dev->dev;
5e50d2d6 2210
50f0959a
PM		 2211 sci_init_gpios(sci_port);
2212
5e50d2d6 2213 pm_runtime_enable(&dev->dev);
7b6fd3bf 2214 }
e108b2ca 2215
7ed7e071
MD		 2216 sci_port->break_timer.data = (unsigned long)sci_port;
2217 sci_port->break_timer.function = sci_break_timer;
2218 init_timer(&sci_port->break_timer);
2219
debf9507
PM		 2220 /*
2221 * Establish some sensible defaults for the error detection.
2222 */
2223 if (!p->error_mask)
2224 p->error_mask = (p->type == PORT_SCI) ?
2225 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2226
2227 /*
2228 * Establish sensible defaults for the overrun detection, unless
2229 * the part has explicitly disabled support for it.
2230 */
2231 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2232 if (p->type == PORT_SCI)
2233 p->overrun_bit = 5;
2234 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2235 p->overrun_bit = 9;
2236 else
2237 p->overrun_bit = 0;
2238
2239 /*
2240 * Make the error mask inclusive of overrun detection, if
2241 * supported.
2242 */
2243 p->error_mask |= (1 << p->overrun_bit);
2244 }
2245
ce6738b6
PM		 2246 port->mapbase = p->mapbase;
2247 port->type = p->type;
f43dc23d 2248 port->flags = p->flags;
61a6976b 2249 port->regshift = p->regshift;
73a19e4c 2250
ce6738b6 2251 /*
61a6976b 2252 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2253 * for the multi-IRQ ports, which is where we are primarily
2254 * concerned with the shutdown path synchronization.
2255 *
2256 * For the muxed case there's nothing more to do.
2257 */
54aa89ea 2258 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2259 port->irqflags = 0;
73a19e4c 2260
61a6976b
PM		 2261 port->serial_in = sci_serial_in;
2262 port->serial_out = sci_serial_out;
2263
937bb6e4
GL		 2264 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2265 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2266 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2267
c7ed1ab3 2268 return 0;
e108b2ca
PM		 2269}
2270
6dae1421
LP		 2271static void sci_cleanup_single(struct sci_port *port)
2272{
2273 sci_free_gpios(port);
2274
2275 clk_put(port->iclk);
2276 clk_put(port->fclk);
2277
2278 pm_runtime_disable(port->port.dev);
2279}
2280
1da177e4 2281#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2282static void serial_console_putchar(struct uart_port *port, int ch)
2283{
2284 sci_poll_put_char(port, ch);
2285}
2286
1da177e4
LT		 2287/*
2288 * Print a string to the serial port trying not to disturb
2289 * any possible real use of the port...
2290 */
2291static void serial_console_write(struct console *co, const char *s,
2292 unsigned count)
2293{
906b17dc
PM		 2294 struct sci_port *sci_port = &sci_ports[co->index];
2295 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2296 unsigned short bits, ctrl;
2297 unsigned long flags;
2298 int locked = 1;
2299
2300 local_irq_save(flags);
2301 if (port->sysrq)
2302 locked = 0;
2303 else if (oops_in_progress)
2304 locked = spin_trylock(&port->lock);
2305 else
2306 spin_lock(&port->lock);
2307
2308 /* first save the SCSCR then disable the interrupts */
2309 ctrl = serial_port_in(port, SCSCR);
2310 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2311
501b825d 2312 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2313
2314 /* wait until fifo is empty and last bit has been transmitted */
2315 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2316 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2317 cpu_relax();
40f70c03
SK		 2318
2319 /* restore the SCSCR */
2320 serial_port_out(port, SCSCR, ctrl);
2321
2322 if (locked)
2323 spin_unlock(&port->lock);
2324 local_irq_restore(flags);
1da177e4
LT		 2325}
2326
9671f099 2327static int serial_console_setup(struct console *co, char *options)
1da177e4 2328{
dc8e6f5b 2329 struct sci_port *sci_port;
1da177e4
LT		 2330 struct uart_port *port;
2331 int baud = 115200;
2332 int bits = 8;
2333 int parity = 'n';
2334 int flow = 'n';
2335 int ret;
2336
e108b2ca 2337 /*
906b17dc 2338 * Refuse to handle any bogus ports.
1da177e4 2339 */
906b17dc 2340 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2341 return -ENODEV;
e108b2ca 2342
906b17dc
PM		 2343 sci_port = &sci_ports[co->index];
2344 port = &sci_port->port;
2345
b2267a6b
AC		 2346 /*
2347 * Refuse to handle uninitialized ports.
2348 */
2349 if (!port->ops)
2350 return -ENODEV;
2351
f6e9495d
PM		 2352 ret = sci_remap_port(port);
2353 if (unlikely(ret != 0))
2354 return ret;
e108b2ca 2355
1da177e4
LT		 2356 if (options)
2357 uart_parse_options(options, &baud, &parity, &bits, &flow);
2358
ab7cfb55 2359 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2360}
2361
2362static struct console serial_console = {
2363 .name = "ttySC",
906b17dc 2364 .device = uart_console_device,
1da177e4
LT		 2365 .write = serial_console_write,
2366 .setup = serial_console_setup,
fa5da2f7 2367 .flags = CON_PRINTBUFFER,
1da177e4 2368 .index = -1,
906b17dc 2369 .data = &sci_uart_driver,
1da177e4
LT		 2370};
2371
7b6fd3bf
MD		 2372static struct console early_serial_console = {
2373 .name = "early_ttySC",
2374 .write = serial_console_write,
2375 .flags = CON_PRINTBUFFER,
906b17dc 2376 .index = -1,
7b6fd3bf 2377};
ecdf8a46 2378
7b6fd3bf
MD		 2379static char early_serial_buf[32];
2380
9671f099 2381static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2382{
574de559 2383 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2384
2385 if (early_serial_console.data)
2386 return -EEXIST;
2387
2388 early_serial_console.index = pdev->id;
ecdf8a46 2389
906b17dc 2390 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2391
2392 serial_console_setup(&early_serial_console, early_serial_buf);
2393
2394 if (!strstr(early_serial_buf, "keep"))
2395 early_serial_console.flags |= CON_BOOT;
2396
2397 register_console(&early_serial_console);
2398 return 0;
2399}
6a8c9799
NI		 2400
2401#define SCI_CONSOLE (&serial_console)
2402
ecdf8a46 2403#else
9671f099 2404static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2405{
2406 return -EINVAL;
2407}
1da177e4 2408
6a8c9799
NI		 2409#define SCI_CONSOLE NULL
2410
2411#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2412
2413static char banner[] __initdata =
f303b364 2414 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
1da177e4
LT		 2415
2416static struct uart_driver sci_uart_driver = {
2417 .owner = THIS_MODULE,
2418 .driver_name = "sci",
1da177e4
LT		 2419 .dev_name = "ttySC",
2420 .major = SCI_MAJOR,
2421 .minor = SCI_MINOR_START,
e108b2ca 2422 .nr = SCI_NPORTS,
1da177e4
LT		 2423 .cons = SCI_CONSOLE,
2424};
2425
54507f6e 2426static int sci_remove(struct platform_device *dev)
e552de24 2427{
d535a230 2428 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2429
d535a230
PM		 2430 cpufreq_unregister_notifier(&port->freq_transition,
2431 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2432
d535a230
PM		 2433 uart_remove_one_port(&sci_uart_driver, &port->port);
2434
6dae1421 2435 sci_cleanup_single(port);
e552de24 2436
e552de24
MD		 2437 return 0;
2438}
2439
9671f099 2440static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2441 unsigned int index,
2442 struct plat_sci_port *p,
2443 struct sci_port *sciport)
2444{
0ee70712
MD		 2445 int ret;
2446
2447 /* Sanity check */
2448 if (unlikely(index >= SCI_NPORTS)) {
2449 dev_notice(&dev->dev, "Attempting to register port "
2450 "%d when only %d are available.\n",
2451 index+1, SCI_NPORTS);
2452 dev_notice(&dev->dev, "Consider bumping "
2453 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2454 return -EINVAL;
0ee70712
MD		 2455 }
2456
c7ed1ab3
PM		 2457 ret = sci_init_single(dev, sciport, index, p);
2458 if (ret)
2459 return ret;
0ee70712 2460
6dae1421
LP		 2461 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2462 if (ret) {
2463 sci_cleanup_single(sciport);
2464 return ret;
2465 }
2466
2467 return 0;
0ee70712
MD		 2468}
2469
9671f099 2470static int sci_probe(struct platform_device *dev)
1da177e4 2471{
3ba35baa 2472 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
d535a230 2473 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2474 int ret;
d535a230 2475
ecdf8a46
PM		 2476 /*
2477 * If we've come here via earlyprintk initialization, head off to
2478 * the special early probe. We don't have sufficient device state
2479 * to make it beyond this yet.
2480 */
2481 if (is_early_platform_device(dev))
2482 return sci_probe_earlyprintk(dev);
7b6fd3bf 2483
d535a230 2484 platform_set_drvdata(dev, sp);
e552de24 2485
906b17dc 2486 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2487 if (ret)
6dae1421 2488 return ret;
e552de24 2489
d535a230 2490 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2491
d535a230
PM		 2492 ret = cpufreq_register_notifier(&sp->freq_transition,
2493 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2494 if (unlikely(ret < 0)) {
2495 sci_cleanup_single(sp);
2496 return ret;
2497 }
1da177e4
LT		 2498
2499#ifdef CONFIG_SH_STANDARD_BIOS
2500 sh_bios_gdb_detach();
2501#endif
2502
e108b2ca 2503 return 0;
1da177e4
LT		 2504}
2505
6daa79b3 2506static int sci_suspend(struct device *dev)
1da177e4 2507{
d535a230 2508 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2509
d535a230
PM		 2510 if (sport)
2511 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2512
e108b2ca
PM		 2513 return 0;
2514}
1da177e4 2515
6daa79b3 2516static int sci_resume(struct device *dev)
e108b2ca 2517{
d535a230 2518 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2519
d535a230
PM		 2520 if (sport)
2521 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2522
2523 return 0;
2524}
2525
47145210 2526static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2527 .suspend = sci_suspend,
2528 .resume = sci_resume,
2529};
2530
e108b2ca
PM		 2531static struct platform_driver sci_driver = {
2532 .probe = sci_probe,
b9e39c89 2533 .remove = sci_remove,
e108b2ca
PM		 2534 .driver = {
2535 .name = "sh-sci",
2536 .owner = THIS_MODULE,
6daa79b3 2537 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2538 },
2539};
2540
2541static int __init sci_init(void)
2542{
2543 int ret;
2544
2545 printk(banner);
2546
e108b2ca
PM		 2547 ret = uart_register_driver(&sci_uart_driver);
2548 if (likely(ret == 0)) {
2549 ret = platform_driver_register(&sci_driver);
2550 if (unlikely(ret))
2551 uart_unregister_driver(&sci_uart_driver);
2552 }
2553
2554 return ret;
2555}
2556
2557static void __exit sci_exit(void)
2558{
2559 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2560 uart_unregister_driver(&sci_uart_driver);
2561}
2562
7b6fd3bf
MD		 2563#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2564early_platform_init_buffer("earlyprintk", &sci_driver,
2565 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2566#endif
1da177e4
LT		 2567module_init(sci_init);
2568module_exit(sci_exit);
2569
e108b2ca 2570MODULE_LICENSE("GPL");
e169c139 2571MODULE_ALIAS("platform:sh-sci");
7f405f9c 2572MODULE_AUTHOR("Paul Mundt");
f303b364 2573MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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