projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
serial: sh-sci: Fix probe error paths
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
1da177e4
LT		 28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
e108b2ca 41#include <linux/platform_device.h>
96de1a8f 42#include <linux/serial_sci.h>
1da177e4 43#include <linux/notifier.h>
5e50d2d6 44#include <linux/pm_runtime.h>
1da177e4 45#include <linux/cpufreq.h>
85f094ec 46#include <linux/clk.h>
fa5da2f7 47#include <linux/ctype.h>
7ff731ae 48#include <linux/err.h>
73a19e4c 49#include <linux/dmaengine.h>
5beabc7f 50#include <linux/dma-mapping.h>
73a19e4c 51#include <linux/scatterlist.h>
5a0e3ad6 52#include <linux/slab.h>
50f0959a 53#include <linux/gpio.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
1da177e4
LT		 59#include "sh-sci.h"
60
e108b2ca
PM		 61struct sci_port {
62 struct uart_port port;
63
ce6738b6
PM		 64 /* Platform configuration */
65 struct plat_sci_port *cfg;
e108b2ca 66
e108b2ca
PM		 67 /* Break timer */
68 struct timer_list break_timer;
69 int break_flag;
1534a3b3 70
501b825d
MD		 71 /* Interface clock */
72 struct clk *iclk;
c7ed1ab3
PM		 73 /* Function clock */
74 struct clk *fclk;
edad1f20 75
9174fc8f 76 char *irqstr[SCIx_NR_IRQS];
50f0959a 77 char *gpiostr[SCIx_NR_FNS];
9174fc8f 78
73a19e4c
GL		 79 struct dma_chan *chan_tx;
80 struct dma_chan *chan_rx;
f43dc23d 81
73a19e4c 82#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 83 struct dma_async_tx_descriptor *desc_tx;
84 struct dma_async_tx_descriptor *desc_rx[2];
85 dma_cookie_t cookie_tx;
86 dma_cookie_t cookie_rx[2];
87 dma_cookie_t active_rx;
88 struct scatterlist sg_tx;
89 unsigned int sg_len_tx;
90 struct scatterlist sg_rx[2];
91 size_t buf_len_rx;
92 struct sh_dmae_slave param_tx;
93 struct sh_dmae_slave param_rx;
94 struct work_struct work_tx;
95 struct work_struct work_rx;
96 struct timer_list rx_timer;
3089f381 97 unsigned int rx_timeout;
73a19e4c 98#endif
e552de24 99
d535a230 100 struct notifier_block freq_transition;
1ba76220
MD		 101
102#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
103 unsigned short saved_smr;
104 unsigned short saved_fcr;
105 unsigned char saved_brr;
106#endif
e108b2ca
PM		 107};
108
1da177e4 109/* Function prototypes */
d535a230 110static void sci_start_tx(struct uart_port *port);
b129a8cc 111static void sci_stop_tx(struct uart_port *port);
d535a230 112static void sci_start_rx(struct uart_port *port);
1da177e4 113
e108b2ca 114#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 115
e108b2ca
PM		 116static struct sci_port sci_ports[SCI_NPORTS];
117static struct uart_driver sci_uart_driver;
1da177e4 118
e7c98dc7
MT		 119static inline struct sci_port *
120to_sci_port(struct uart_port *uart)
121{
122 return container_of(uart, struct sci_port, port);
123}
124
61a6976b
PM		 125struct plat_sci_reg {
126 u8 offset, size;
127};
128
129/* Helper for invalidating specific entries of an inherited map. */
130#define sci_reg_invalid { .offset = 0, .size = 0 }
131
132static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
133 [SCIx_PROBE_REGTYPE] = {
134 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
135 },
136
137 /*
138 * Common SCI definitions, dependent on the port's regshift
139 * value.
140 */
141 [SCIx_SCI_REGTYPE] = {
142 [SCSMR] = { 0x00, 8 },
143 [SCBRR] = { 0x01, 8 },
144 [SCSCR] = { 0x02, 8 },
145 [SCxTDR] = { 0x03, 8 },
146 [SCxSR] = { 0x04, 8 },
147 [SCxRDR] = { 0x05, 8 },
148 [SCFCR] = sci_reg_invalid,
149 [SCFDR] = sci_reg_invalid,
150 [SCTFDR] = sci_reg_invalid,
151 [SCRFDR] = sci_reg_invalid,
152 [SCSPTR] = sci_reg_invalid,
153 [SCLSR] = sci_reg_invalid,
154 },
155
156 /*
157 * Common definitions for legacy IrDA ports, dependent on
158 * regshift value.
159 */
160 [SCIx_IRDA_REGTYPE] = {
161 [SCSMR] = { 0x00, 8 },
162 [SCBRR] = { 0x01, 8 },
163 [SCSCR] = { 0x02, 8 },
164 [SCxTDR] = { 0x03, 8 },
165 [SCxSR] = { 0x04, 8 },
166 [SCxRDR] = { 0x05, 8 },
167 [SCFCR] = { 0x06, 8 },
168 [SCFDR] = { 0x07, 16 },
169 [SCTFDR] = sci_reg_invalid,
170 [SCRFDR] = sci_reg_invalid,
171 [SCSPTR] = sci_reg_invalid,
172 [SCLSR] = sci_reg_invalid,
173 },
174
175 /*
176 * Common SCIFA definitions.
177 */
178 [SCIx_SCIFA_REGTYPE] = {
179 [SCSMR] = { 0x00, 16 },
180 [SCBRR] = { 0x04, 8 },
181 [SCSCR] = { 0x08, 16 },
182 [SCxTDR] = { 0x20, 8 },
183 [SCxSR] = { 0x14, 16 },
184 [SCxRDR] = { 0x24, 8 },
185 [SCFCR] = { 0x18, 16 },
186 [SCFDR] = { 0x1c, 16 },
187 [SCTFDR] = sci_reg_invalid,
188 [SCRFDR] = sci_reg_invalid,
189 [SCSPTR] = sci_reg_invalid,
190 [SCLSR] = sci_reg_invalid,
191 },
192
193 /*
194 * Common SCIFB definitions.
195 */
196 [SCIx_SCIFB_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x40, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x60, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
209 },
210
3af1f8a4
PE		 211 /*
212 * Common SH-2(A) SCIF definitions for ports with FIFO data
213 * count registers.
214 */
215 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x0c, 8 },
220 [SCxSR] = { 0x10, 16 },
221 [SCxRDR] = { 0x14, 8 },
222 [SCFCR] = { 0x18, 16 },
223 [SCFDR] = { 0x1c, 16 },
224 [SCTFDR] = sci_reg_invalid,
225 [SCRFDR] = sci_reg_invalid,
226 [SCSPTR] = { 0x20, 16 },
227 [SCLSR] = { 0x24, 16 },
228 },
229
61a6976b
PM		 230 /*
231 * Common SH-3 SCIF definitions.
232 */
233 [SCIx_SH3_SCIF_REGTYPE] = {
234 [SCSMR] = { 0x00, 8 },
235 [SCBRR] = { 0x02, 8 },
236 [SCSCR] = { 0x04, 8 },
237 [SCxTDR] = { 0x06, 8 },
238 [SCxSR] = { 0x08, 16 },
239 [SCxRDR] = { 0x0a, 8 },
240 [SCFCR] = { 0x0c, 8 },
241 [SCFDR] = { 0x0e, 16 },
242 [SCTFDR] = sci_reg_invalid,
243 [SCRFDR] = sci_reg_invalid,
244 [SCSPTR] = sci_reg_invalid,
245 [SCLSR] = sci_reg_invalid,
246 },
247
248 /*
249 * Common SH-4(A) SCIF(B) definitions.
250 */
251 [SCIx_SH4_SCIF_REGTYPE] = {
252 [SCSMR] = { 0x00, 16 },
253 [SCBRR] = { 0x04, 8 },
254 [SCSCR] = { 0x08, 16 },
255 [SCxTDR] = { 0x0c, 8 },
256 [SCxSR] = { 0x10, 16 },
257 [SCxRDR] = { 0x14, 8 },
258 [SCFCR] = { 0x18, 16 },
259 [SCFDR] = { 0x1c, 16 },
260 [SCTFDR] = sci_reg_invalid,
261 [SCRFDR] = sci_reg_invalid,
262 [SCSPTR] = { 0x20, 16 },
263 [SCLSR] = { 0x24, 16 },
264 },
265
266 /*
267 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
268 * register.
269 */
270 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
271 [SCSMR] = { 0x00, 16 },
272 [SCBRR] = { 0x04, 8 },
273 [SCSCR] = { 0x08, 16 },
274 [SCxTDR] = { 0x0c, 8 },
275 [SCxSR] = { 0x10, 16 },
276 [SCxRDR] = { 0x14, 8 },
277 [SCFCR] = { 0x18, 16 },
278 [SCFDR] = { 0x1c, 16 },
279 [SCTFDR] = sci_reg_invalid,
280 [SCRFDR] = sci_reg_invalid,
281 [SCSPTR] = sci_reg_invalid,
282 [SCLSR] = { 0x24, 16 },
283 },
284
285 /*
286 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
287 * count registers.
288 */
289 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
290 [SCSMR] = { 0x00, 16 },
291 [SCBRR] = { 0x04, 8 },
292 [SCSCR] = { 0x08, 16 },
293 [SCxTDR] = { 0x0c, 8 },
294 [SCxSR] = { 0x10, 16 },
295 [SCxRDR] = { 0x14, 8 },
296 [SCFCR] = { 0x18, 16 },
297 [SCFDR] = { 0x1c, 16 },
298 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
299 [SCRFDR] = { 0x20, 16 },
300 [SCSPTR] = { 0x24, 16 },
301 [SCLSR] = { 0x28, 16 },
302 },
303
304 /*
305 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
306 * registers.
307 */
308 [SCIx_SH7705_SCIF_REGTYPE] = {
309 [SCSMR] = { 0x00, 16 },
310 [SCBRR] = { 0x04, 8 },
311 [SCSCR] = { 0x08, 16 },
312 [SCxTDR] = { 0x20, 8 },
313 [SCxSR] = { 0x14, 16 },
314 [SCxRDR] = { 0x24, 8 },
315 [SCFCR] = { 0x18, 16 },
316 [SCFDR] = { 0x1c, 16 },
317 [SCTFDR] = sci_reg_invalid,
318 [SCRFDR] = sci_reg_invalid,
319 [SCSPTR] = sci_reg_invalid,
320 [SCLSR] = sci_reg_invalid,
321 },
322};
323
72b294cf
PM		 324#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
325
61a6976b
PM		 326/*
327 * The "offset" here is rather misleading, in that it refers to an enum
328 * value relative to the port mapping rather than the fixed offset
329 * itself, which needs to be manually retrieved from the platform's
330 * register map for the given port.
331 */
332static unsigned int sci_serial_in(struct uart_port *p, int offset)
333{
72b294cf 334 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 335
336 if (reg->size == 8)
337 return ioread8(p->membase + (reg->offset << p->regshift));
338 else if (reg->size == 16)
339 return ioread16(p->membase + (reg->offset << p->regshift));
340 else
341 WARN(1, "Invalid register access\n");
342
343 return 0;
344}
345
346static void sci_serial_out(struct uart_port *p, int offset, int value)
347{
72b294cf 348 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 349
350 if (reg->size == 8)
351 iowrite8(value, p->membase + (reg->offset << p->regshift));
352 else if (reg->size == 16)
353 iowrite16(value, p->membase + (reg->offset << p->regshift));
354 else
355 WARN(1, "Invalid register access\n");
356}
357
61a6976b
PM		 358static int sci_probe_regmap(struct plat_sci_port *cfg)
359{
360 switch (cfg->type) {
361 case PORT_SCI:
362 cfg->regtype = SCIx_SCI_REGTYPE;
363 break;
364 case PORT_IRDA:
365 cfg->regtype = SCIx_IRDA_REGTYPE;
366 break;
367 case PORT_SCIFA:
368 cfg->regtype = SCIx_SCIFA_REGTYPE;
369 break;
370 case PORT_SCIFB:
371 cfg->regtype = SCIx_SCIFB_REGTYPE;
372 break;
373 case PORT_SCIF:
374 /*
375 * The SH-4 is a bit of a misnomer here, although that's
376 * where this particular port layout originated. This
377 * configuration (or some slight variation thereof)
378 * remains the dominant model for all SCIFs.
379 */
380 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
381 break;
382 default:
383 printk(KERN_ERR "Can't probe register map for given port\n");
384 return -EINVAL;
385 }
386
387 return 0;
388}
389
23241d43
PM		 390static void sci_port_enable(struct sci_port *sci_port)
391{
392 if (!sci_port->port.dev)
393 return;
394
395 pm_runtime_get_sync(sci_port->port.dev);
396
397 clk_enable(sci_port->iclk);
398 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
399 clk_enable(sci_port->fclk);
400}
401
402static void sci_port_disable(struct sci_port *sci_port)
403{
404 if (!sci_port->port.dev)
405 return;
406
407 clk_disable(sci_port->fclk);
408 clk_disable(sci_port->iclk);
409
410 pm_runtime_put_sync(sci_port->port.dev);
411}
412
07d2a1a1 413#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 414
415#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 416static int sci_poll_get_char(struct uart_port *port)
1da177e4 417{
1da177e4
LT		 418 unsigned short status;
419 int c;
420
e108b2ca 421 do {
b12bb29f 422 status = serial_port_in(port, SCxSR);
1da177e4 423 if (status & SCxSR_ERRORS(port)) {
b12bb29f 424 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 425 continue;
426 }
3f255eb3
JW		 427 break;
428 } while (1);
429
430 if (!(status & SCxSR_RDxF(port)))
431 return NO_POLL_CHAR;
07d2a1a1 432
b12bb29f 433 c = serial_port_in(port, SCxRDR);
07d2a1a1 434
e7c98dc7 435 /* Dummy read */
b12bb29f
PM		 436 serial_port_in(port, SCxSR);
437 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 438
439 return c;
440}
1f6fd5c9 441#endif
1da177e4 442
07d2a1a1 443static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 444{
1da177e4
LT		 445 unsigned short status;
446
1da177e4 447 do {
b12bb29f 448 status = serial_port_in(port, SCxSR);
1da177e4
LT		 449 } while (!(status & SCxSR_TDxE(port)));
450
b12bb29f
PM		 451 serial_port_out(port, SCxTDR, c);
452 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 453}
07d2a1a1 454#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 455
61a6976b 456static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 457{
61a6976b
PM		 458 struct sci_port *s = to_sci_port(port);
459 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 460
61a6976b
PM		 461 /*
462 * Use port-specific handler if provided.
463 */
464 if (s->cfg->ops && s->cfg->ops->init_pins) {
465 s->cfg->ops->init_pins(port, cflag);
466 return;
1da177e4 467 }
41504c39 468
61a6976b
PM		 469 /*
470 * For the generic path SCSPTR is necessary. Bail out if that's
471 * unavailable, too.
472 */
473 if (!reg->size)
474 return;
41504c39 475
faf02f8f
PM		 476 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
477 ((!(cflag & CRTSCTS)))) {
478 unsigned short status;
479
b12bb29f 480 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 481 status &= ~SCSPTR_CTSIO;
482 status |= SCSPTR_RTSIO;
b12bb29f 483 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 484 }
d5701647 485}
e108b2ca 486
72b294cf 487static int sci_txfill(struct uart_port *port)
e108b2ca 488{
72b294cf 489 struct plat_sci_reg *reg;
e108b2ca 490
72b294cf
PM		 491 reg = sci_getreg(port, SCTFDR);
492 if (reg->size)
b12bb29f 493 return serial_port_in(port, SCTFDR) & 0xff;
c63847a3 494
72b294cf
PM		 495 reg = sci_getreg(port, SCFDR);
496 if (reg->size)
b12bb29f 497 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 498
b12bb29f 499 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 500}
501
73a19e4c
GL		 502static int sci_txroom(struct uart_port *port)
503{
72b294cf 504 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 505}
506
507static int sci_rxfill(struct uart_port *port)
e108b2ca 508{
72b294cf
PM		 509 struct plat_sci_reg *reg;
510
511 reg = sci_getreg(port, SCRFDR);
512 if (reg->size)
b12bb29f 513 return serial_port_in(port, SCRFDR) & 0xff;
72b294cf
PM		 514
515 reg = sci_getreg(port, SCFDR);
516 if (reg->size)
b12bb29f 517 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 518
b12bb29f 519 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 520}
521
514820eb
PM		 522/*
523 * SCI helper for checking the state of the muxed port/RXD pins.
524 */
525static inline int sci_rxd_in(struct uart_port *port)
526{
527 struct sci_port *s = to_sci_port(port);
528
529 if (s->cfg->port_reg <= 0)
530 return 1;
531
532 return !!__raw_readb(s->cfg->port_reg);
533}
534
1da177e4
LT		 535/* ********************************************************************** *
536 * the interrupt related routines *
537 * ********************************************************************** */
538
539static void sci_transmit_chars(struct uart_port *port)
540{
ebd2c8f6 541 struct circ_buf *xmit = &port->state->xmit;
1da177e4 542 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 543 unsigned short status;
544 unsigned short ctrl;
e108b2ca 545 int count;
1da177e4 546
b12bb29f 547 status = serial_port_in(port, SCxSR);
1da177e4 548 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 549 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 550 if (uart_circ_empty(xmit))
8e698614 551 ctrl &= ~SCSCR_TIE;
e7c98dc7 552 else
8e698614 553 ctrl |= SCSCR_TIE;
b12bb29f 554 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 555 return;
556 }
557
72b294cf 558 count = sci_txroom(port);
1da177e4
LT		 559
560 do {
561 unsigned char c;
562
563 if (port->x_char) {
564 c = port->x_char;
565 port->x_char = 0;
566 } else if (!uart_circ_empty(xmit) && !stopped) {
567 c = xmit->buf[xmit->tail];
568 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
569 } else {
570 break;
571 }
572
b12bb29f 573 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 574
575 port->icount.tx++;
576 } while (--count > 0);
577
b12bb29f 578 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 579
580 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
581 uart_write_wakeup(port);
582 if (uart_circ_empty(xmit)) {
b129a8cc 583 sci_stop_tx(port);
1da177e4 584 } else {
b12bb29f 585 ctrl = serial_port_in(port, SCSCR);
1da177e4 586
1a22f08d 587 if (port->type != PORT_SCI) {
b12bb29f
PM		 588 serial_port_in(port, SCxSR); /* Dummy read */
589 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 590 }
1da177e4 591
8e698614 592 ctrl |= SCSCR_TIE;
b12bb29f 593 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 594 }
595}
596
597/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 598#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 599
94c8b6db 600static void sci_receive_chars(struct uart_port *port)
1da177e4 601{
e7c98dc7 602 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 603 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 604 int i, count, copied = 0;
605 unsigned short status;
33f0f88f 606 unsigned char flag;
1da177e4 607
b12bb29f 608 status = serial_port_in(port, SCxSR);
1da177e4
LT		 609 if (!(status & SCxSR_RDxF(port)))
610 return;
611
612 while (1) {
1da177e4 613 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 614 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 615
616 /* If for any reason we can't copy more data, we're done! */
617 if (count == 0)
618 break;
619
620 if (port->type == PORT_SCI) {
b12bb29f 621 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 622 if (uart_handle_sysrq_char(port, c) ||
623 sci_port->break_flag)
1da177e4 624 count = 0;
e7c98dc7 625 else
e108b2ca 626 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 627 } else {
e7c98dc7 628 for (i = 0; i < count; i++) {
b12bb29f 629 char c = serial_port_in(port, SCxRDR);
d97fbbed 630
b12bb29f 631 status = serial_port_in(port, SCxSR);
1da177e4
LT		 632#if defined(CONFIG_CPU_SH3)
633 /* Skip "chars" during break */
e108b2ca 634 if (sci_port->break_flag) {
1da177e4
LT		 635 if ((c == 0) &&
636 (status & SCxSR_FER(port))) {
637 count--; i--;
638 continue;
639 }
e108b2ca 640
1da177e4 641 /* Nonzero => end-of-break */
762c69e3 642 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 643 sci_port->break_flag = 0;
644
1da177e4
LT		 645 if (STEPFN(c)) {
646 count--; i--;
647 continue;
648 }
649 }
650#endif /* CONFIG_CPU_SH3 */
7d12e780 651 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 652 count--; i--;
653 continue;
654 }
655
656 /* Store data and status */
73a19e4c 657 if (status & SCxSR_FER(port)) {
33f0f88f 658 flag = TTY_FRAME;
d97fbbed 659 port->icount.frame++;
762c69e3 660 dev_notice(port->dev, "frame error\n");
73a19e4c 661 } else if (status & SCxSR_PER(port)) {
33f0f88f 662 flag = TTY_PARITY;
d97fbbed 663 port->icount.parity++;
762c69e3 664 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 665 } else
666 flag = TTY_NORMAL;
762c69e3 667
33f0f88f 668 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 669 }
670 }
671
b12bb29f
PM		 672 serial_port_in(port, SCxSR); /* dummy read */
673 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 674
1da177e4
LT		 675 copied += count;
676 port->icount.rx += count;
677 }
678
679 if (copied) {
680 /* Tell the rest of the system the news. New characters! */
681 tty_flip_buffer_push(tty);
682 } else {
b12bb29f
PM		 683 serial_port_in(port, SCxSR); /* dummy read */
684 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 685 }
686}
687
688#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 689
690/*
691 * The sci generates interrupts during the break,
1da177e4
LT		 692 * 1 per millisecond or so during the break period, for 9600 baud.
693 * So dont bother disabling interrupts.
694 * But dont want more than 1 break event.
695 * Use a kernel timer to periodically poll the rx line until
696 * the break is finished.
697 */
94c8b6db 698static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 699{
bc9b3f5c 700 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 701}
94c8b6db 702
1da177e4
LT		 703/* Ensure that two consecutive samples find the break over. */
704static void sci_break_timer(unsigned long data)
705{
e108b2ca
PM		 706 struct sci_port *port = (struct sci_port *)data;
707
23241d43 708 sci_port_enable(port);
5e50d2d6 709
e108b2ca 710 if (sci_rxd_in(&port->port) == 0) {
1da177e4 711 port->break_flag = 1;
e108b2ca
PM		 712 sci_schedule_break_timer(port);
713 } else if (port->break_flag == 1) {
1da177e4
LT		 714 /* break is over. */
715 port->break_flag = 2;
e108b2ca
PM		 716 sci_schedule_break_timer(port);
717 } else
718 port->break_flag = 0;
5e50d2d6 719
23241d43 720 sci_port_disable(port);
1da177e4
LT		 721}
722
94c8b6db 723static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 724{
725 int copied = 0;
b12bb29f 726 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 727 struct tty_struct *tty = port->state->port.tty;
debf9507 728 struct sci_port *s = to_sci_port(port);
1da177e4 729
debf9507
PM		 730 /*
731 * Handle overruns, if supported.
732 */
733 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
734 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 735 port->icount.overrun++;
736
debf9507
PM		 737 /* overrun error */
738 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
739 copied++;
762c69e3 740
debf9507
PM		 741 dev_notice(port->dev, "overrun error");
742 }
1da177e4
LT		 743 }
744
e108b2ca 745 if (status & SCxSR_FER(port)) {
1da177e4
LT		 746 if (sci_rxd_in(port) == 0) {
747 /* Notify of BREAK */
e7c98dc7 748 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 749
750 if (!sci_port->break_flag) {
d97fbbed
PM		 751 port->icount.brk++;
752
e108b2ca
PM		 753 sci_port->break_flag = 1;
754 sci_schedule_break_timer(sci_port);
755
1da177e4 756 /* Do sysrq handling. */
e108b2ca 757 if (uart_handle_break(port))
1da177e4 758 return 0;
762c69e3
PM		 759
760 dev_dbg(port->dev, "BREAK detected\n");
761
e108b2ca 762 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 763 copied++;
764 }
765
e108b2ca 766 } else {
1da177e4 767 /* frame error */
d97fbbed
PM		 768 port->icount.frame++;
769
e108b2ca 770 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 771 copied++;
762c69e3
PM		 772
773 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 774 }
775 }
776
e108b2ca 777 if (status & SCxSR_PER(port)) {
1da177e4 778 /* parity error */
d97fbbed
PM		 779 port->icount.parity++;
780
e108b2ca
PM		 781 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
782 copied++;
762c69e3
PM		 783
784 dev_notice(port->dev, "parity error");
1da177e4
LT		 785 }
786
33f0f88f 787 if (copied)
1da177e4 788 tty_flip_buffer_push(tty);
1da177e4
LT		 789
790 return copied;
791}
792
94c8b6db 793static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 794{
ebd2c8f6 795 struct tty_struct *tty = port->state->port.tty;
debf9507 796 struct sci_port *s = to_sci_port(port);
4b8c59a3 797 struct plat_sci_reg *reg;
d830fa45
PM		 798 int copied = 0;
799
4b8c59a3
PM		 800 reg = sci_getreg(port, SCLSR);
801 if (!reg->size)
d830fa45
PM		 802 return 0;
803
b12bb29f
PM		 804 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
805 serial_port_out(port, SCLSR, 0);
d830fa45 806
d97fbbed
PM		 807 port->icount.overrun++;
808
d830fa45
PM		 809 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
810 tty_flip_buffer_push(tty);
811
812 dev_notice(port->dev, "overrun error\n");
813 copied++;
814 }
815
816 return copied;
817}
818
94c8b6db 819static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 820{
821 int copied = 0;
b12bb29f 822 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 823 struct tty_struct *tty = port->state->port.tty;
a5660ada 824 struct sci_port *s = to_sci_port(port);
1da177e4 825
0b3d4ef6
PM		 826 if (uart_handle_break(port))
827 return 0;
828
b7a76e4b 829 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 830#if defined(CONFIG_CPU_SH3)
831 /* Debounce break */
832 s->break_flag = 1;
833#endif
d97fbbed
PM		 834
835 port->icount.brk++;
836
1da177e4 837 /* Notify of BREAK */
e108b2ca 838 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 839 copied++;
762c69e3
PM		 840
841 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 842 }
843
33f0f88f 844 if (copied)
1da177e4 845 tty_flip_buffer_push(tty);
e108b2ca 846
d830fa45
PM		 847 copied += sci_handle_fifo_overrun(port);
848
1da177e4
LT		 849 return copied;
850}
851
73a19e4c 852static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 853{
73a19e4c
GL		 854#ifdef CONFIG_SERIAL_SH_SCI_DMA
855 struct uart_port *port = ptr;
856 struct sci_port *s = to_sci_port(port);
857
858 if (s->chan_rx) {
b12bb29f
PM		 859 u16 scr = serial_port_in(port, SCSCR);
860 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 861
862 /* Disable future Rx interrupts */
d1d4b10c 863 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 864 disable_irq_nosync(irq);
865 scr |= 0x4000;
866 } else {
f43dc23d 867 scr &= ~SCSCR_RIE;
3089f381 868 }
b12bb29f 869 serial_port_out(port, SCSCR, scr);
73a19e4c 870 /* Clear current interrupt */
b12bb29f 871 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 872 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
873 jiffies, s->rx_timeout);
874 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 875
876 return IRQ_HANDLED;
877 }
878#endif
879
1da177e4
LT		 880 /* I think sci_receive_chars has to be called irrespective
881 * of whether the I_IXOFF is set, otherwise, how is the interrupt
882 * to be disabled?
883 */
73a19e4c 884 sci_receive_chars(ptr);
1da177e4
LT		 885
886 return IRQ_HANDLED;
887}
888
7d12e780 889static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 890{
891 struct uart_port *port = ptr;
fd78a76a 892 unsigned long flags;
1da177e4 893
fd78a76a 894 spin_lock_irqsave(&port->lock, flags);
1da177e4 895 sci_transmit_chars(port);
fd78a76a 896 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 897
898 return IRQ_HANDLED;
899}
900
7d12e780 901static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 902{
903 struct uart_port *port = ptr;
904
905 /* Handle errors */
906 if (port->type == PORT_SCI) {
907 if (sci_handle_errors(port)) {
908 /* discard character in rx buffer */
b12bb29f
PM		 909 serial_port_in(port, SCxSR);
910 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 911 }
912 } else {
d830fa45 913 sci_handle_fifo_overrun(port);
7d12e780 914 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 915 }
916
b12bb29f 917 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 918
919 /* Kick the transmission */
7d12e780 920 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 921
922 return IRQ_HANDLED;
923}
924
7d12e780 925static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 926{
927 struct uart_port *port = ptr;
928
929 /* Handle BREAKs */
930 sci_handle_breaks(port);
b12bb29f 931 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 932
933 return IRQ_HANDLED;
934}
935
f43dc23d
PM		 936static inline unsigned long port_rx_irq_mask(struct uart_port *port)
937{
938 /*
939 * Not all ports (such as SCIFA) will support REIE. Rather than
940 * special-casing the port type, we check the port initialization
941 * IRQ enable mask to see whether the IRQ is desired at all. If
942 * it's unset, it's logically inferred that there's no point in
943 * testing for it.
944 */
ce6738b6 945 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 946}
947
7d12e780 948static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 949{
44e18e9e 950 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 951 struct uart_port *port = ptr;
73a19e4c 952 struct sci_port *s = to_sci_port(port);
a8884e34 953 irqreturn_t ret = IRQ_NONE;
1da177e4 954
b12bb29f
PM		 955 ssr_status = serial_port_in(port, SCxSR);
956 scr_status = serial_port_in(port, SCSCR);
f43dc23d 957 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 958
959 /* Tx Interrupt */
f43dc23d 960 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 961 !s->chan_tx)
a8884e34 962 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 963
73a19e4c
GL		 964 /*
965 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
966 * DR flags
967 */
968 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 969 (scr_status & SCSCR_RIE))
a8884e34 970 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 971
1da177e4 972 /* Error Interrupt */
dd4da3a5 973 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 974 ret = sci_er_interrupt(irq, ptr);
f43dc23d 975
1da177e4 976 /* Break Interrupt */
dd4da3a5 977 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 978 ret = sci_br_interrupt(irq, ptr);
1da177e4 979
a8884e34 980 return ret;
1da177e4
LT		 981}
982
1da177e4 983/*
25985edc 984 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 985 * ports' baud rate when the peripheral clock changes.
986 */
e108b2ca
PM		 987static int sci_notifier(struct notifier_block *self,
988 unsigned long phase, void *p)
1da177e4 989{
e552de24
MD		 990 struct sci_port *sci_port;
991 unsigned long flags;
1da177e4 992
d535a230
PM		 993 sci_port = container_of(self, struct sci_port, freq_transition);
994
1da177e4 995 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 996 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 997 struct uart_port *port = &sci_port->port;
073e84c9 998
d535a230
PM		 999 spin_lock_irqsave(&port->lock, flags);
1000 port->uartclk = clk_get_rate(sci_port->iclk);
1001 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1002 }
1da177e4 1003
1da177e4
LT		 1004 return NOTIFY_OK;
1005}
501b825d 1006
9174fc8f
PM		 1007static struct sci_irq_desc {
1008 const char *desc;
1009 irq_handler_t handler;
1010} sci_irq_desc[] = {
1011 /*
1012 * Split out handlers, the default case.
1013 */
1014 [SCIx_ERI_IRQ] = {
1015 .desc = "rx err",
1016 .handler = sci_er_interrupt,
1017 },
1018
1019 [SCIx_RXI_IRQ] = {
1020 .desc = "rx full",
1021 .handler = sci_rx_interrupt,
1022 },
1023
1024 [SCIx_TXI_IRQ] = {
1025 .desc = "tx empty",
1026 .handler = sci_tx_interrupt,
1027 },
1028
1029 [SCIx_BRI_IRQ] = {
1030 .desc = "break",
1031 .handler = sci_br_interrupt,
1032 },
1033
1034 /*
1035 * Special muxed handler.
1036 */
1037 [SCIx_MUX_IRQ] = {
1038 .desc = "mux",
1039 .handler = sci_mpxed_interrupt,
1040 },
1041};
1042
1da177e4
LT		 1043static int sci_request_irq(struct sci_port *port)
1044{
9174fc8f
PM		 1045 struct uart_port *up = &port->port;
1046 int i, j, ret = 0;
1047
1048 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1049 struct sci_irq_desc *desc;
1050 unsigned int irq;
1051
1052 if (SCIx_IRQ_IS_MUXED(port)) {
1053 i = SCIx_MUX_IRQ;
1054 irq = up->irq;
0e8963de 1055 } else {
9174fc8f
PM		 1056 irq = port->cfg->irqs[i];
1057
0e8963de
PM		 1058 /*
1059 * Certain port types won't support all of the
1060 * available interrupt sources.
1061 */
1062 if (unlikely(!irq))
1063 continue;
1064 }
1065
9174fc8f
PM		 1066 desc = sci_irq_desc + i;
1067 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1068 dev_name(up->dev), desc->desc);
1069 if (!port->irqstr[j]) {
1070 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1071 desc->desc);
1072 goto out_nomem;
1da177e4 1073 }
9174fc8f
PM		 1074
1075 ret = request_irq(irq, desc->handler, up->irqflags,
1076 port->irqstr[j], port);
1077 if (unlikely(ret)) {
1078 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1079 goto out_noirq;
1da177e4
LT		 1080 }
1081 }
1082
1083 return 0;
9174fc8f
PM		 1084
1085out_noirq:
1086 while (--i >= 0)
1087 free_irq(port->cfg->irqs[i], port);
1088
1089out_nomem:
1090 while (--j >= 0)
1091 kfree(port->irqstr[j]);
1092
1093 return ret;
1da177e4
LT		 1094}
1095
1096static void sci_free_irq(struct sci_port *port)
1097{
1098 int i;
1099
9174fc8f
PM		 1100 /*
1101 * Intentionally in reverse order so we iterate over the muxed
1102 * IRQ first.
1103 */
1104 for (i = 0; i < SCIx_NR_IRQS; i++) {
0e8963de
PM		 1105 unsigned int irq = port->cfg->irqs[i];
1106
1107 /*
1108 * Certain port types won't support all of the available
1109 * interrupt sources.
1110 */
1111 if (unlikely(!irq))
1112 continue;
1113
9174fc8f
PM		 1114 free_irq(port->cfg->irqs[i], port);
1115 kfree(port->irqstr[i]);
1da177e4 1116
9174fc8f
PM		 1117 if (SCIx_IRQ_IS_MUXED(port)) {
1118 /* If there's only one IRQ, we're done. */
1119 return;
1da177e4
LT		 1120 }
1121 }
1122}
1123
50f0959a
PM		 1124static const char *sci_gpio_names[SCIx_NR_FNS] = {
1125 "sck", "rxd", "txd", "cts", "rts",
1126};
1127
1128static const char *sci_gpio_str(unsigned int index)
1129{
1130 return sci_gpio_names[index];
1131}
1132
1133static void __devinit sci_init_gpios(struct sci_port *port)
1134{
1135 struct uart_port *up = &port->port;
1136 int i;
1137
1138 if (!port->cfg)
1139 return;
1140
1141 for (i = 0; i < SCIx_NR_FNS; i++) {
1142 const char *desc;
1143 int ret;
1144
1145 if (!port->cfg->gpios[i])
1146 continue;
1147
1148 desc = sci_gpio_str(i);
1149
1150 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1151 dev_name(up->dev), desc);
1152
1153 /*
1154 * If we've failed the allocation, we can still continue
1155 * on with a NULL string.
1156 */
1157 if (!port->gpiostr[i])
1158 dev_notice(up->dev, "%s string allocation failure\n",
1159 desc);
1160
1161 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1162 if (unlikely(ret != 0)) {
1163 dev_notice(up->dev, "failed %s gpio request\n", desc);
1164
1165 /*
1166 * If we can't get the GPIO for whatever reason,
1167 * no point in keeping the verbose string around.
1168 */
1169 kfree(port->gpiostr[i]);
1170 }
1171 }
1172}
1173
1174static void sci_free_gpios(struct sci_port *port)
1175{
1176 int i;
1177
1178 for (i = 0; i < SCIx_NR_FNS; i++)
1179 if (port->cfg->gpios[i]) {
1180 gpio_free(port->cfg->gpios[i]);
1181 kfree(port->gpiostr[i]);
1182 }
1183}
1184
1da177e4
LT		 1185static unsigned int sci_tx_empty(struct uart_port *port)
1186{
b12bb29f 1187 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1188 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1189
1190 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1191}
1192
cdf7c42f
PM		 1193/*
1194 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1195 * CTS/RTS is supported in hardware by at least one port and controlled
1196 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1197 * handled via the ->init_pins() op, which is a bit of a one-way street,
1198 * lacking any ability to defer pin control -- this will later be
1199 * converted over to the GPIO framework).
dc7e3ef7
PM		 1200 *
1201 * Other modes (such as loopback) are supported generically on certain
1202 * port types, but not others. For these it's sufficient to test for the
1203 * existence of the support register and simply ignore the port type.
cdf7c42f 1204 */
1da177e4
LT		 1205static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1206{
dc7e3ef7
PM		 1207 if (mctrl & TIOCM_LOOP) {
1208 struct plat_sci_reg *reg;
1209
1210 /*
1211 * Standard loopback mode for SCFCR ports.
1212 */
1213 reg = sci_getreg(port, SCFCR);
1214 if (reg->size)
b12bb29f 1215 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1216 }
1da177e4
LT		 1217}
1218
1219static unsigned int sci_get_mctrl(struct uart_port *port)
1220{
cdf7c42f
PM		 1221 /*
1222 * CTS/RTS is handled in hardware when supported, while nothing
1223 * else is wired up. Keep it simple and simply assert DSR/CAR.
1224 */
1225 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1226}
1227
73a19e4c
GL		 1228#ifdef CONFIG_SERIAL_SH_SCI_DMA
1229static void sci_dma_tx_complete(void *arg)
1230{
1231 struct sci_port *s = arg;
1232 struct uart_port *port = &s->port;
1233 struct circ_buf *xmit = &port->state->xmit;
1234 unsigned long flags;
1235
1236 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1237
1238 spin_lock_irqsave(&port->lock, flags);
1239
f354a381 1240 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1241 xmit->tail &= UART_XMIT_SIZE - 1;
1242
f354a381 1243 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1244
1245 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1246 s->desc_tx = NULL;
1247
73a19e4c
GL		 1248 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1249 uart_write_wakeup(port);
1250
3089f381 1251 if (!uart_circ_empty(xmit)) {
49d4bcad 1252 s->cookie_tx = 0;
73a19e4c 1253 schedule_work(&s->work_tx);
49d4bcad
YT		 1254 } else {
1255 s->cookie_tx = -EINVAL;
1256 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1257 u16 ctrl = serial_port_in(port, SCSCR);
1258 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1259 }
3089f381
GL		 1260 }
1261
1262 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1263}
1264
1265/* Locking: called with port lock held */
1266static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1267 size_t count)
1268{
1269 struct uart_port *port = &s->port;
1270 int i, active, room;
1271
1272 room = tty_buffer_request_room(tty, count);
1273
1274 if (s->active_rx == s->cookie_rx[0]) {
1275 active = 0;
1276 } else if (s->active_rx == s->cookie_rx[1]) {
1277 active = 1;
1278 } else {
1279 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1280 return 0;
1281 }
1282
1283 if (room < count)
1284 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1285 count - room);
1286 if (!room)
1287 return room;
1288
1289 for (i = 0; i < room; i++)
1290 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1291 TTY_NORMAL);
1292
1293 port->icount.rx += room;
1294
1295 return room;
1296}
1297
1298static void sci_dma_rx_complete(void *arg)
1299{
1300 struct sci_port *s = arg;
1301 struct uart_port *port = &s->port;
1302 struct tty_struct *tty = port->state->port.tty;
1303 unsigned long flags;
1304 int count;
1305
3089f381 1306 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1307
1308 spin_lock_irqsave(&port->lock, flags);
1309
1310 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1311
3089f381 1312 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1313
1314 spin_unlock_irqrestore(&port->lock, flags);
1315
1316 if (count)
1317 tty_flip_buffer_push(tty);
1318
1319 schedule_work(&s->work_rx);
1320}
1321
73a19e4c
GL		 1322static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1323{
1324 struct dma_chan *chan = s->chan_rx;
1325 struct uart_port *port = &s->port;
73a19e4c
GL		 1326
1327 s->chan_rx = NULL;
1328 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1329 dma_release_channel(chan);
85b8e3ff
GL		 1330 if (sg_dma_address(&s->sg_rx[0]))
1331 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1332 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1333 if (enable_pio)
1334 sci_start_rx(port);
1335}
1336
1337static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1338{
1339 struct dma_chan *chan = s->chan_tx;
1340 struct uart_port *port = &s->port;
73a19e4c
GL		 1341
1342 s->chan_tx = NULL;
1343 s->cookie_tx = -EINVAL;
1344 dma_release_channel(chan);
1345 if (enable_pio)
1346 sci_start_tx(port);
1347}
1348
1349static void sci_submit_rx(struct sci_port *s)
1350{
1351 struct dma_chan *chan = s->chan_rx;
1352 int i;
1353
1354 for (i = 0; i < 2; i++) {
1355 struct scatterlist *sg = &s->sg_rx[i];
1356 struct dma_async_tx_descriptor *desc;
1357
16052827 1358 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1359 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1360
1361 if (desc) {
1362 s->desc_rx[i] = desc;
1363 desc->callback = sci_dma_rx_complete;
1364 desc->callback_param = s;
1365 s->cookie_rx[i] = desc->tx_submit(desc);
1366 }
1367
1368 if (!desc || s->cookie_rx[i] < 0) {
1369 if (i) {
1370 async_tx_ack(s->desc_rx[0]);
1371 s->cookie_rx[0] = -EINVAL;
1372 }
1373 if (desc) {
1374 async_tx_ack(desc);
1375 s->cookie_rx[i] = -EINVAL;
1376 }
1377 dev_warn(s->port.dev,
1378 "failed to re-start DMA, using PIO\n");
1379 sci_rx_dma_release(s, true);
1380 return;
1381 }
3089f381
GL		 1382 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1383 s->cookie_rx[i], i);
73a19e4c
GL		 1384 }
1385
1386 s->active_rx = s->cookie_rx[0];
1387
1388 dma_async_issue_pending(chan);
1389}
1390
1391static void work_fn_rx(struct work_struct *work)
1392{
1393 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1394 struct uart_port *port = &s->port;
1395 struct dma_async_tx_descriptor *desc;
1396 int new;
1397
1398 if (s->active_rx == s->cookie_rx[0]) {
1399 new = 0;
1400 } else if (s->active_rx == s->cookie_rx[1]) {
1401 new = 1;
1402 } else {
1403 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1404 return;
1405 }
1406 desc = s->desc_rx[new];
1407
1408 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1409 DMA_SUCCESS) {
1410 /* Handle incomplete DMA receive */
1411 struct tty_struct *tty = port->state->port.tty;
1412 struct dma_chan *chan = s->chan_rx;
1413 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1414 async_tx);
1415 unsigned long flags;
1416 int count;
1417
05827630 1418 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1419 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1420 sh_desc->partial, sh_desc->cookie);
1421
1422 spin_lock_irqsave(&port->lock, flags);
1423 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1424 spin_unlock_irqrestore(&port->lock, flags);
1425
1426 if (count)
1427 tty_flip_buffer_push(tty);
1428
1429 sci_submit_rx(s);
1430
1431 return;
1432 }
1433
1434 s->cookie_rx[new] = desc->tx_submit(desc);
1435 if (s->cookie_rx[new] < 0) {
1436 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1437 sci_rx_dma_release(s, true);
1438 return;
1439 }
1440
73a19e4c 1441 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1442
1443 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1444 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1445}
1446
1447static void work_fn_tx(struct work_struct *work)
1448{
1449 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1450 struct dma_async_tx_descriptor *desc;
1451 struct dma_chan *chan = s->chan_tx;
1452 struct uart_port *port = &s->port;
1453 struct circ_buf *xmit = &port->state->xmit;
1454 struct scatterlist *sg = &s->sg_tx;
1455
1456 /*
1457 * DMA is idle now.
1458 * Port xmit buffer is already mapped, and it is one page... Just adjust
1459 * offsets and lengths. Since it is a circular buffer, we have to
1460 * transmit till the end, and then the rest. Take the port lock to get a
1461 * consistent xmit buffer state.
1462 */
1463 spin_lock_irq(&port->lock);
1464 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1465 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1466 sg->offset;
f354a381 1467 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1468 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1469 spin_unlock_irq(&port->lock);
1470
f354a381 1471 BUG_ON(!sg_dma_len(sg));
73a19e4c 1472
16052827 1473 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1474 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1475 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1476 if (!desc) {
1477 /* switch to PIO */
1478 sci_tx_dma_release(s, true);
1479 return;
1480 }
1481
1482 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1483
1484 spin_lock_irq(&port->lock);
1485 s->desc_tx = desc;
1486 desc->callback = sci_dma_tx_complete;
1487 desc->callback_param = s;
1488 spin_unlock_irq(&port->lock);
1489 s->cookie_tx = desc->tx_submit(desc);
1490 if (s->cookie_tx < 0) {
1491 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1492 /* switch to PIO */
1493 sci_tx_dma_release(s, true);
1494 return;
1495 }
1496
1497 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1498 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1499
1500 dma_async_issue_pending(chan);
1501}
1502#endif
1503
b129a8cc 1504static void sci_start_tx(struct uart_port *port)
1da177e4 1505{
3089f381 1506 struct sci_port *s = to_sci_port(port);
e108b2ca 1507 unsigned short ctrl;
1da177e4 1508
73a19e4c 1509#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1510 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1511 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1512 if (s->chan_tx)
1513 new = scr | 0x8000;
1514 else
1515 new = scr & ~0x8000;
1516 if (new != scr)
b12bb29f 1517 serial_port_out(port, SCSCR, new);
73a19e4c 1518 }
f43dc23d 1519
3089f381 1520 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1521 s->cookie_tx < 0) {
1522 s->cookie_tx = 0;
3089f381 1523 schedule_work(&s->work_tx);
49d4bcad 1524 }
73a19e4c 1525#endif
f43dc23d 1526
d1d4b10c 1527 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1528 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1529 ctrl = serial_port_in(port, SCSCR);
1530 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1531 }
1da177e4
LT		 1532}
1533
b129a8cc 1534static void sci_stop_tx(struct uart_port *port)
1da177e4 1535{
1da177e4
LT		 1536 unsigned short ctrl;
1537
1538 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1539 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1540
d1d4b10c 1541 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1542 ctrl &= ~0x8000;
f43dc23d 1543
8e698614 1544 ctrl &= ~SCSCR_TIE;
f43dc23d 1545
b12bb29f 1546 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1547}
1548
73a19e4c 1549static void sci_start_rx(struct uart_port *port)
1da177e4 1550{
1da177e4
LT		 1551 unsigned short ctrl;
1552
b12bb29f 1553 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1554
d1d4b10c 1555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1556 ctrl &= ~0x4000;
f43dc23d 1557
b12bb29f 1558 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1559}
1560
1561static void sci_stop_rx(struct uart_port *port)
1562{
1da177e4
LT		 1563 unsigned short ctrl;
1564
b12bb29f 1565 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1566
d1d4b10c 1567 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1568 ctrl &= ~0x4000;
f43dc23d
PM		 1569
1570 ctrl &= ~port_rx_irq_mask(port);
1571
b12bb29f 1572 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1573}
1574
1575static void sci_enable_ms(struct uart_port *port)
1576{
d39ec6ce
PM		 1577 /*
1578 * Not supported by hardware, always a nop.
1579 */
1da177e4
LT		 1580}
1581
1582static void sci_break_ctl(struct uart_port *port, int break_state)
1583{
bbb4ce50 1584 struct sci_port *s = to_sci_port(port);
a4e02f6d 1585 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1586 unsigned short scscr, scsptr;
1587
a4e02f6d
SY		 1588 /* check wheter the port has SCSPTR */
1589 if (!reg->size) {
bbb4ce50
SY		 1590 /*
1591 * Not supported by hardware. Most parts couple break and rx
1592 * interrupts together, with break detection always enabled.
1593 */
a4e02f6d 1594 return;
bbb4ce50 1595 }
a4e02f6d
SY		 1596
1597 scsptr = serial_port_in(port, SCSPTR);
1598 scscr = serial_port_in(port, SCSCR);
1599
1600 if (break_state == -1) {
1601 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1602 scscr &= ~SCSCR_TE;
1603 } else {
1604 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1605 scscr |= SCSCR_TE;
1606 }
1607
1608 serial_port_out(port, SCSPTR, scsptr);
1609 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1610}
1611
73a19e4c
GL		 1612#ifdef CONFIG_SERIAL_SH_SCI_DMA
1613static bool filter(struct dma_chan *chan, void *slave)
1614{
1615 struct sh_dmae_slave *param = slave;
1616
1617 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1618 param->slave_id);
1619
937bb6e4
GL		 1620 chan->private = param;
1621 return true;
73a19e4c
GL		 1622}
1623
1624static void rx_timer_fn(unsigned long arg)
1625{
1626 struct sci_port *s = (struct sci_port *)arg;
1627 struct uart_port *port = &s->port;
b12bb29f 1628 u16 scr = serial_port_in(port, SCSCR);
3089f381 1629
d1d4b10c 1630 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1631 scr &= ~0x4000;
ce6738b6 1632 enable_irq(s->cfg->irqs[1]);
3089f381 1633 }
b12bb29f 1634 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1635 dev_dbg(port->dev, "DMA Rx timed out\n");
1636 schedule_work(&s->work_rx);
1637}
1638
1639static void sci_request_dma(struct uart_port *port)
1640{
1641 struct sci_port *s = to_sci_port(port);
1642 struct sh_dmae_slave *param;
1643 struct dma_chan *chan;
1644 dma_cap_mask_t mask;
1645 int nent;
1646
937bb6e4
GL		 1647 dev_dbg(port->dev, "%s: port %d\n", __func__,
1648 port->line);
73a19e4c 1649
937bb6e4 1650 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1651 return;
1652
1653 dma_cap_zero(mask);
1654 dma_cap_set(DMA_SLAVE, mask);
1655
1656 param = &s->param_tx;
1657
1658 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6 1659 param->slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1660
1661 s->cookie_tx = -EINVAL;
1662 chan = dma_request_channel(mask, filter, param);
1663 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1664 if (chan) {
1665 s->chan_tx = chan;
1666 sg_init_table(&s->sg_tx, 1);
1667 /* UART circular tx buffer is an aligned page. */
1668 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1669 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1670 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1671 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1672 if (!nent)
1673 sci_tx_dma_release(s, false);
1674 else
1675 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1676 sg_dma_len(&s->sg_tx),
1677 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1678
1679 s->sg_len_tx = nent;
1680
1681 INIT_WORK(&s->work_tx, work_fn_tx);
1682 }
1683
1684 param = &s->param_rx;
1685
1686 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6 1687 param->slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1688
1689 chan = dma_request_channel(mask, filter, param);
1690 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1691 if (chan) {
1692 dma_addr_t dma[2];
1693 void *buf[2];
1694 int i;
1695
1696 s->chan_rx = chan;
1697
1698 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1699 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1700 &dma[0], GFP_KERNEL);
1701
1702 if (!buf[0]) {
1703 dev_warn(port->dev,
1704 "failed to allocate dma buffer, using PIO\n");
1705 sci_rx_dma_release(s, true);
1706 return;
1707 }
1708
1709 buf[1] = buf[0] + s->buf_len_rx;
1710 dma[1] = dma[0] + s->buf_len_rx;
1711
1712 for (i = 0; i < 2; i++) {
1713 struct scatterlist *sg = &s->sg_rx[i];
1714
1715 sg_init_table(sg, 1);
1716 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1717 (int)buf[i] & ~PAGE_MASK);
f354a381 1718 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1719 }
1720
1721 INIT_WORK(&s->work_rx, work_fn_rx);
1722 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1723
1724 sci_submit_rx(s);
1725 }
1726}
1727
1728static void sci_free_dma(struct uart_port *port)
1729{
1730 struct sci_port *s = to_sci_port(port);
1731
73a19e4c
GL		 1732 if (s->chan_tx)
1733 sci_tx_dma_release(s, false);
1734 if (s->chan_rx)
1735 sci_rx_dma_release(s, false);
1736}
27bd1075
PM		 1737#else
1738static inline void sci_request_dma(struct uart_port *port)
1739{
1740}
1741
1742static inline void sci_free_dma(struct uart_port *port)
1743{
1744}
73a19e4c
GL		 1745#endif
1746
1da177e4
LT		 1747static int sci_startup(struct uart_port *port)
1748{
a5660ada 1749 struct sci_port *s = to_sci_port(port);
073e84c9 1750 int ret;
1da177e4 1751
73a19e4c
GL		 1752 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1753
048be431
RW		 1754 pm_runtime_put_noidle(port->dev);
1755
23241d43 1756 sci_port_enable(s);
1da177e4 1757
073e84c9
PM		 1758 ret = sci_request_irq(s);
1759 if (unlikely(ret < 0))
1760 return ret;
1761
73a19e4c 1762 sci_request_dma(port);
073e84c9 1763
d656901b 1764 sci_start_tx(port);
73a19e4c 1765 sci_start_rx(port);
1da177e4
LT		 1766
1767 return 0;
1768}
1769
1770static void sci_shutdown(struct uart_port *port)
1771{
a5660ada 1772 struct sci_port *s = to_sci_port(port);
1da177e4 1773
73a19e4c
GL		 1774 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1775
1da177e4 1776 sci_stop_rx(port);
b129a8cc 1777 sci_stop_tx(port);
073e84c9 1778
73a19e4c 1779 sci_free_dma(port);
1da177e4
LT		 1780 sci_free_irq(s);
1781
23241d43 1782 sci_port_disable(s);
048be431
RW		 1783
1784 pm_runtime_get_noresume(port->dev);
1da177e4
LT		 1785}
1786
26c92f37
PM		 1787static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1788 unsigned long freq)
1789{
1790 switch (algo_id) {
1791 case SCBRR_ALGO_1:
1792 return ((freq + 16 * bps) / (16 * bps) - 1);
1793 case SCBRR_ALGO_2:
1794 return ((freq + 16 * bps) / (32 * bps) - 1);
1795 case SCBRR_ALGO_3:
1796 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1797 case SCBRR_ALGO_4:
1798 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1799 case SCBRR_ALGO_5:
1800 return (((freq * 1000 / 32) / bps) - 1);
1801 }
1802
1803 /* Warn, but use a safe default */
1804 WARN_ON(1);
e8183a6c 1805
26c92f37
PM		 1806 return ((freq + 16 * bps) / (32 * bps) - 1);
1807}
1808
1ba76220
MD		 1809static void sci_reset(struct uart_port *port)
1810{
0979e0e6 1811 struct plat_sci_reg *reg;
1ba76220
MD		 1812 unsigned int status;
1813
1814 do {
b12bb29f 1815 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1816 } while (!(status & SCxSR_TEND(port)));
1817
b12bb29f 1818 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1819
0979e0e6
PM		 1820 reg = sci_getreg(port, SCFCR);
1821 if (reg->size)
b12bb29f 1822 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1823}
1824
606d099c
AC		 1825static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1826 struct ktermios *old)
1da177e4 1827{
00b9de9c 1828 struct sci_port *s = to_sci_port(port);
0979e0e6 1829 struct plat_sci_reg *reg;
1ba76220 1830 unsigned int baud, smr_val, max_baud;
a2159b52 1831 int t = -1;
1da177e4 1832
154280fd
MD		 1833 /*
1834 * earlyprintk comes here early on with port->uartclk set to zero.
1835 * the clock framework is not up and running at this point so here
1836 * we assume that 115200 is the maximum baud rate. please note that
1837 * the baud rate is not programmed during earlyprintk - it is assumed
1838 * that the previous boot loader has enabled required clocks and
1839 * setup the baud rate generator hardware for us already.
1840 */
1841 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1842
154280fd
MD		 1843 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1844 if (likely(baud && port->uartclk))
ce6738b6 1845 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1846
23241d43 1847 sci_port_enable(s);
36003386 1848
1ba76220 1849 sci_reset(port);
1da177e4 1850
b12bb29f 1851 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1852
1da177e4
LT		 1853 if ((termios->c_cflag & CSIZE) == CS7)
1854 smr_val |= 0x40;
1855 if (termios->c_cflag & PARENB)
1856 smr_val |= 0x20;
1857 if (termios->c_cflag & PARODD)
1858 smr_val |= 0x30;
1859 if (termios->c_cflag & CSTOPB)
1860 smr_val |= 0x08;
1861
1862 uart_update_timeout(port, termios->c_cflag, baud);
1863
b12bb29f 1864 serial_port_out(port, SCSMR, smr_val);
1da177e4 1865
73a19e4c 1866 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1867 s->cfg->scscr);
73a19e4c 1868
1da177e4 1869 if (t > 0) {
e7c98dc7 1870 if (t >= 256) {
b12bb29f 1871 serial_port_out(port, SCSMR, (serial_port_in(port, SCSMR) & ~3) | 1);
1da177e4 1872 t >>= 2;
e7c98dc7 1873 } else
b12bb29f 1874 serial_port_out(port, SCSMR, serial_port_in(port, SCSMR) & ~3);
e7c98dc7 1875
b12bb29f 1876 serial_port_out(port, SCBRR, t);
1da177e4
LT		 1877 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1878 }
1879
d5701647 1880 sci_init_pins(port, termios->c_cflag);
0979e0e6 1881
73c3d53f
PM		 1882 reg = sci_getreg(port, SCFCR);
1883 if (reg->size) {
b12bb29f 1884 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1885
73c3d53f 1886 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1887 if (termios->c_cflag & CRTSCTS)
1888 ctrl |= SCFCR_MCE;
1889 else
1890 ctrl &= ~SCFCR_MCE;
faf02f8f 1891 }
73c3d53f
PM		 1892
1893 /*
1894 * As we've done a sci_reset() above, ensure we don't
1895 * interfere with the FIFOs while toggling MCE. As the
1896 * reset values could still be set, simply mask them out.
1897 */
1898 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1899
b12bb29f 1900 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1901 }
b7a76e4b 1902
b12bb29f 1903 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1904
3089f381
GL		 1905#ifdef CONFIG_SERIAL_SH_SCI_DMA
1906 /*
1907 * Calculate delay for 1.5 DMA buffers: see
1908 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1909 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1910 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1911 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1912 * sizes), but it has been found out experimentally, that this is not
1913 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1914 * as a minimum seem to work perfectly.
1915 */
1916 if (s->chan_rx) {
1917 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1918 port->fifosize / 2;
1919 dev_dbg(port->dev,
1920 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1921 s->rx_timeout * 1000 / HZ, port->timeout);
1922 if (s->rx_timeout < msecs_to_jiffies(20))
1923 s->rx_timeout = msecs_to_jiffies(20);
1924 }
1925#endif
1926
1da177e4 1927 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1928 sci_start_rx(port);
36003386 1929
23241d43 1930 sci_port_disable(s);
1da177e4
LT		 1931}
1932
1933static const char *sci_type(struct uart_port *port)
1934{
1935 switch (port->type) {
e7c98dc7
MT		 1936 case PORT_IRDA:
1937 return "irda";
1938 case PORT_SCI:
1939 return "sci";
1940 case PORT_SCIF:
1941 return "scif";
1942 case PORT_SCIFA:
1943 return "scifa";
d1d4b10c
GL		 1944 case PORT_SCIFB:
1945 return "scifb";
1da177e4
LT		 1946 }
1947
fa43972f 1948 return NULL;
1da177e4
LT		 1949}
1950
e2651647 1951static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1952{
e2651647
PM		 1953 /*
1954 * Pick an arbitrary size that encapsulates all of the base
1955 * registers by default. This can be optimized later, or derived
1956 * from platform resource data at such a time that ports begin to
1957 * behave more erratically.
1958 */
1959 return 64;
1da177e4
LT		 1960}
1961
f6e9495d
PM		 1962static int sci_remap_port(struct uart_port *port)
1963{
1964 unsigned long size = sci_port_size(port);
1965
1966 /*
1967 * Nothing to do if there's already an established membase.
1968 */
1969 if (port->membase)
1970 return 0;
1971
1972 if (port->flags & UPF_IOREMAP) {
1973 port->membase = ioremap_nocache(port->mapbase, size);
1974 if (unlikely(!port->membase)) {
1975 dev_err(port->dev, "can't remap port#%d\n", port->line);
1976 return -ENXIO;
1977 }
1978 } else {
1979 /*
1980 * For the simple (and majority of) cases where we don't
1981 * need to do any remapping, just cast the cookie
1982 * directly.
1983 */
1984 port->membase = (void __iomem *)port->mapbase;
1985 }
1986
1987 return 0;
1988}
1989
e2651647 1990static void sci_release_port(struct uart_port *port)
1da177e4 1991{
e2651647
PM		 1992 if (port->flags & UPF_IOREMAP) {
1993 iounmap(port->membase);
1994 port->membase = NULL;
1995 }
1996
1997 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1998}
1999
e2651647 2000static int sci_request_port(struct uart_port *port)
1da177e4 2001{
e2651647
PM		 2002 unsigned long size = sci_port_size(port);
2003 struct resource *res;
f6e9495d 2004 int ret;
1da177e4 2005
1020520e 2006 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2007 if (unlikely(res == NULL))
2008 return -EBUSY;
1da177e4 2009
f6e9495d
PM		 2010 ret = sci_remap_port(port);
2011 if (unlikely(ret != 0)) {
2012 release_resource(res);
2013 return ret;
7ff731ae 2014 }
e2651647
PM		 2015
2016 return 0;
2017}
2018
2019static void sci_config_port(struct uart_port *port, int flags)
2020{
2021 if (flags & UART_CONFIG_TYPE) {
2022 struct sci_port *sport = to_sci_port(port);
2023
2024 port->type = sport->cfg->type;
2025 sci_request_port(port);
2026 }
1da177e4
LT		 2027}
2028
2029static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2030{
a5660ada 2031 struct sci_port *s = to_sci_port(port);
1da177e4 2032
ce6738b6 2033 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 2034 return -EINVAL;
2035 if (ser->baud_base < 2400)
2036 /* No paper tape reader for Mitch.. */
2037 return -EINVAL;
2038
2039 return 0;
2040}
2041
2042static struct uart_ops sci_uart_ops = {
2043 .tx_empty = sci_tx_empty,
2044 .set_mctrl = sci_set_mctrl,
2045 .get_mctrl = sci_get_mctrl,
2046 .start_tx = sci_start_tx,
2047 .stop_tx = sci_stop_tx,
2048 .stop_rx = sci_stop_rx,
2049 .enable_ms = sci_enable_ms,
2050 .break_ctl = sci_break_ctl,
2051 .startup = sci_startup,
2052 .shutdown = sci_shutdown,
2053 .set_termios = sci_set_termios,
2054 .type = sci_type,
2055 .release_port = sci_release_port,
2056 .request_port = sci_request_port,
2057 .config_port = sci_config_port,
2058 .verify_port = sci_verify_port,
07d2a1a1
PM		 2059#ifdef CONFIG_CONSOLE_POLL
2060 .poll_get_char = sci_poll_get_char,
2061 .poll_put_char = sci_poll_put_char,
2062#endif
1da177e4
LT		 2063};
2064
c7ed1ab3
PM		 2065static int __devinit sci_init_single(struct platform_device *dev,
2066 struct sci_port *sci_port,
2067 unsigned int index,
2068 struct plat_sci_port *p)
e108b2ca 2069{
73a19e4c 2070 struct uart_port *port = &sci_port->port;
3127c6b2 2071 int ret;
e108b2ca 2072
50f0959a
PM		 2073 sci_port->cfg = p;
2074
73a19e4c
GL		 2075 port->ops = &sci_uart_ops;
2076 port->iotype = UPIO_MEM;
2077 port->line = index;
75136d48
MP		 2078
2079 switch (p->type) {
d1d4b10c
GL		 2080 case PORT_SCIFB:
2081 port->fifosize = 256;
2082 break;
75136d48 2083 case PORT_SCIFA:
73a19e4c 2084 port->fifosize = 64;
75136d48
MP		 2085 break;
2086 case PORT_SCIF:
73a19e4c 2087 port->fifosize = 16;
75136d48
MP		 2088 break;
2089 default:
73a19e4c 2090 port->fifosize = 1;
75136d48
MP		 2091 break;
2092 }
7b6fd3bf 2093
3127c6b2
PM		 2094 if (p->regtype == SCIx_PROBE_REGTYPE) {
2095 ret = sci_probe_regmap(p);
fc97114b 2096 if (unlikely(ret))
3127c6b2
PM		 2097 return ret;
2098 }
61a6976b 2099
7b6fd3bf 2100 if (dev) {
c7ed1ab3
PM		 2101 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2102 if (IS_ERR(sci_port->iclk)) {
2103 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2104 if (IS_ERR(sci_port->iclk)) {
2105 dev_err(&dev->dev, "can't get iclk\n");
2106 return PTR_ERR(sci_port->iclk);
2107 }
2108 }
2109
2110 /*
2111 * The function clock is optional, ignore it if we can't
2112 * find it.
2113 */
2114 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2115 if (IS_ERR(sci_port->fclk))
2116 sci_port->fclk = NULL;
2117
73a19e4c 2118 port->dev = &dev->dev;
5e50d2d6 2119
50f0959a
PM		 2120 sci_init_gpios(sci_port);
2121
5a50a01b 2122 pm_runtime_irq_safe(&dev->dev);
048be431 2123 pm_runtime_get_noresume(&dev->dev);
5e50d2d6 2124 pm_runtime_enable(&dev->dev);
7b6fd3bf 2125 }
e108b2ca 2126
7ed7e071
MD		 2127 sci_port->break_timer.data = (unsigned long)sci_port;
2128 sci_port->break_timer.function = sci_break_timer;
2129 init_timer(&sci_port->break_timer);
2130
debf9507
PM		 2131 /*
2132 * Establish some sensible defaults for the error detection.
2133 */
2134 if (!p->error_mask)
2135 p->error_mask = (p->type == PORT_SCI) ?
2136 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2137
2138 /*
2139 * Establish sensible defaults for the overrun detection, unless
2140 * the part has explicitly disabled support for it.
2141 */
2142 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2143 if (p->type == PORT_SCI)
2144 p->overrun_bit = 5;
2145 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2146 p->overrun_bit = 9;
2147 else
2148 p->overrun_bit = 0;
2149
2150 /*
2151 * Make the error mask inclusive of overrun detection, if
2152 * supported.
2153 */
2154 p->error_mask |= (1 << p->overrun_bit);
2155 }
2156
ce6738b6
PM		 2157 port->mapbase = p->mapbase;
2158 port->type = p->type;
f43dc23d 2159 port->flags = p->flags;
61a6976b 2160 port->regshift = p->regshift;
73a19e4c 2161
ce6738b6 2162 /*
61a6976b 2163 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2164 * for the multi-IRQ ports, which is where we are primarily
2165 * concerned with the shutdown path synchronization.
2166 *
2167 * For the muxed case there's nothing more to do.
2168 */
54aa89ea 2169 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2170 port->irqflags = 0;
73a19e4c 2171
61a6976b
PM		 2172 port->serial_in = sci_serial_in;
2173 port->serial_out = sci_serial_out;
2174
937bb6e4
GL		 2175 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2176 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2177 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2178
c7ed1ab3 2179 return 0;
e108b2ca
PM		 2180}
2181
6dae1421
LP		 2182static void sci_cleanup_single(struct sci_port *port)
2183{
2184 sci_free_gpios(port);
2185
2186 clk_put(port->iclk);
2187 clk_put(port->fclk);
2188
2189 pm_runtime_disable(port->port.dev);
2190}
2191
1da177e4 2192#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2193static void serial_console_putchar(struct uart_port *port, int ch)
2194{
2195 sci_poll_put_char(port, ch);
2196}
2197
1da177e4
LT		 2198/*
2199 * Print a string to the serial port trying not to disturb
2200 * any possible real use of the port...
2201 */
2202static void serial_console_write(struct console *co, const char *s,
2203 unsigned count)
2204{
906b17dc
PM		 2205 struct sci_port *sci_port = &sci_ports[co->index];
2206 struct uart_port *port = &sci_port->port;
973e5d52 2207 unsigned short bits;
07d2a1a1 2208
23241d43 2209 sci_port_enable(sci_port);
501b825d
MD		 2210
2211 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2212
2213 /* wait until fifo is empty and last bit has been transmitted */
2214 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2215 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2216 cpu_relax();
501b825d 2217
23241d43 2218 sci_port_disable(sci_port);
1da177e4
LT		 2219}
2220
7b6fd3bf 2221static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 2222{
dc8e6f5b 2223 struct sci_port *sci_port;
1da177e4
LT		 2224 struct uart_port *port;
2225 int baud = 115200;
2226 int bits = 8;
2227 int parity = 'n';
2228 int flow = 'n';
2229 int ret;
2230
e108b2ca 2231 /*
906b17dc 2232 * Refuse to handle any bogus ports.
1da177e4 2233 */
906b17dc 2234 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2235 return -ENODEV;
e108b2ca 2236
906b17dc
PM		 2237 sci_port = &sci_ports[co->index];
2238 port = &sci_port->port;
2239
b2267a6b
AC		 2240 /*
2241 * Refuse to handle uninitialized ports.
2242 */
2243 if (!port->ops)
2244 return -ENODEV;
2245
f6e9495d
PM		 2246 ret = sci_remap_port(port);
2247 if (unlikely(ret != 0))
2248 return ret;
e108b2ca 2249
23241d43 2250 sci_port_enable(sci_port);
b7a76e4b 2251
1da177e4
LT		 2252 if (options)
2253 uart_parse_options(options, &baud, &parity, &bits, &flow);
2254
1ba76220
MD		 2255 sci_port_disable(sci_port);
2256
ab7cfb55 2257 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2258}
2259
2260static struct console serial_console = {
2261 .name = "ttySC",
906b17dc 2262 .device = uart_console_device,
1da177e4
LT		 2263 .write = serial_console_write,
2264 .setup = serial_console_setup,
fa5da2f7 2265 .flags = CON_PRINTBUFFER,
1da177e4 2266 .index = -1,
906b17dc 2267 .data = &sci_uart_driver,
1da177e4
LT		 2268};
2269
7b6fd3bf
MD		 2270static struct console early_serial_console = {
2271 .name = "early_ttySC",
2272 .write = serial_console_write,
2273 .flags = CON_PRINTBUFFER,
906b17dc 2274 .index = -1,
7b6fd3bf 2275};
ecdf8a46 2276
7b6fd3bf
MD		 2277static char early_serial_buf[32];
2278
ecdf8a46
PM		 2279static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2280{
2281 struct plat_sci_port *cfg = pdev->dev.platform_data;
2282
2283 if (early_serial_console.data)
2284 return -EEXIST;
2285
2286 early_serial_console.index = pdev->id;
ecdf8a46 2287
906b17dc 2288 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2289
2290 serial_console_setup(&early_serial_console, early_serial_buf);
2291
2292 if (!strstr(early_serial_buf, "keep"))
2293 early_serial_console.flags |= CON_BOOT;
2294
2295 register_console(&early_serial_console);
2296 return 0;
2297}
6a8c9799 2298
1ba76220
MD		 2299#define uart_console(port) ((port)->cons->index == (port)->line)
2300
2301static int sci_runtime_suspend(struct device *dev)
2302{
2303 struct sci_port *sci_port = dev_get_drvdata(dev);
2304 struct uart_port *port = &sci_port->port;
2305
2306 if (uart_console(port)) {
0979e0e6
PM		 2307 struct plat_sci_reg *reg;
2308
b12bb29f
PM		 2309 sci_port->saved_smr = serial_port_in(port, SCSMR);
2310 sci_port->saved_brr = serial_port_in(port, SCBRR);
0979e0e6
PM		 2311
2312 reg = sci_getreg(port, SCFCR);
2313 if (reg->size)
b12bb29f 2314 sci_port->saved_fcr = serial_port_in(port, SCFCR);
0979e0e6
PM		 2315 else
2316 sci_port->saved_fcr = 0;
1ba76220
MD		 2317 }
2318 return 0;
2319}
2320
2321static int sci_runtime_resume(struct device *dev)
2322{
2323 struct sci_port *sci_port = dev_get_drvdata(dev);
2324 struct uart_port *port = &sci_port->port;
2325
2326 if (uart_console(port)) {
2327 sci_reset(port);
b12bb29f
PM		 2328 serial_port_out(port, SCSMR, sci_port->saved_smr);
2329 serial_port_out(port, SCBRR, sci_port->saved_brr);
0979e0e6
PM		 2330
2331 if (sci_port->saved_fcr)
b12bb29f 2332 serial_port_out(port, SCFCR, sci_port->saved_fcr);
0979e0e6 2333
b12bb29f 2334 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
1ba76220
MD		 2335 }
2336 return 0;
2337}
2338
6a8c9799
NI		 2339#define SCI_CONSOLE (&serial_console)
2340
ecdf8a46
PM		 2341#else
2342static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2343{
2344 return -EINVAL;
2345}
1da177e4 2346
6a8c9799 2347#define SCI_CONSOLE NULL
1ba76220
MD		 2348#define sci_runtime_suspend NULL
2349#define sci_runtime_resume NULL
6a8c9799
NI		 2350
2351#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2352
2353static char banner[] __initdata =
2354 KERN_INFO "SuperH SCI(F) driver initialized\n";
2355
2356static struct uart_driver sci_uart_driver = {
2357 .owner = THIS_MODULE,
2358 .driver_name = "sci",
1da177e4
LT		 2359 .dev_name = "ttySC",
2360 .major = SCI_MAJOR,
2361 .minor = SCI_MINOR_START,
e108b2ca 2362 .nr = SCI_NPORTS,
1da177e4
LT		 2363 .cons = SCI_CONSOLE,
2364};
2365
54507f6e 2366static int sci_remove(struct platform_device *dev)
e552de24 2367{
d535a230 2368 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2369
d535a230
PM		 2370 cpufreq_unregister_notifier(&port->freq_transition,
2371 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2372
d535a230
PM		 2373 uart_remove_one_port(&sci_uart_driver, &port->port);
2374
6dae1421 2375 sci_cleanup_single(port);
e552de24 2376
e552de24
MD		 2377 return 0;
2378}
2379
0ee70712
MD		 2380static int __devinit sci_probe_single(struct platform_device *dev,
2381 unsigned int index,
2382 struct plat_sci_port *p,
2383 struct sci_port *sciport)
2384{
0ee70712
MD		 2385 int ret;
2386
2387 /* Sanity check */
2388 if (unlikely(index >= SCI_NPORTS)) {
2389 dev_notice(&dev->dev, "Attempting to register port "
2390 "%d when only %d are available.\n",
2391 index+1, SCI_NPORTS);
2392 dev_notice(&dev->dev, "Consider bumping "
2393 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2394 return 0;
2395 }
2396
c7ed1ab3
PM		 2397 ret = sci_init_single(dev, sciport, index, p);
2398 if (ret)
2399 return ret;
0ee70712 2400
6dae1421
LP		 2401 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2402 if (ret) {
2403 sci_cleanup_single(sciport);
2404 return ret;
2405 }
2406
2407 return 0;
0ee70712
MD		 2408}
2409
e108b2ca 2410static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2411{
e108b2ca 2412 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2413 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2414 int ret;
d535a230 2415
ecdf8a46
PM		 2416 /*
2417 * If we've come here via earlyprintk initialization, head off to
2418 * the special early probe. We don't have sufficient device state
2419 * to make it beyond this yet.
2420 */
2421 if (is_early_platform_device(dev))
2422 return sci_probe_earlyprintk(dev);
7b6fd3bf 2423
d535a230 2424 platform_set_drvdata(dev, sp);
e552de24 2425
906b17dc 2426 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2427 if (ret)
6dae1421 2428 return ret;
e552de24 2429
d535a230 2430 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2431
d535a230
PM		 2432 ret = cpufreq_register_notifier(&sp->freq_transition,
2433 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2434 if (unlikely(ret < 0)) {
2435 sci_cleanup_single(sp);
2436 return ret;
2437 }
1da177e4
LT		 2438
2439#ifdef CONFIG_SH_STANDARD_BIOS
2440 sh_bios_gdb_detach();
2441#endif
2442
e108b2ca 2443 return 0;
1da177e4
LT		 2444}
2445
6daa79b3 2446static int sci_suspend(struct device *dev)
1da177e4 2447{
d535a230 2448 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2449
d535a230
PM		 2450 if (sport)
2451 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2452
e108b2ca
PM		 2453 return 0;
2454}
1da177e4 2455
6daa79b3 2456static int sci_resume(struct device *dev)
e108b2ca 2457{
d535a230 2458 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2459
d535a230
PM		 2460 if (sport)
2461 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2462
2463 return 0;
2464}
2465
47145210 2466static const struct dev_pm_ops sci_dev_pm_ops = {
1ba76220
MD		 2467 .runtime_suspend = sci_runtime_suspend,
2468 .runtime_resume = sci_runtime_resume,
6daa79b3
PM		 2469 .suspend = sci_suspend,
2470 .resume = sci_resume,
2471};
2472
e108b2ca
PM		 2473static struct platform_driver sci_driver = {
2474 .probe = sci_probe,
b9e39c89 2475 .remove = sci_remove,
e108b2ca
PM		 2476 .driver = {
2477 .name = "sh-sci",
2478 .owner = THIS_MODULE,
6daa79b3 2479 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2480 },
2481};
2482
2483static int __init sci_init(void)
2484{
2485 int ret;
2486
2487 printk(banner);
2488
e108b2ca
PM		 2489 ret = uart_register_driver(&sci_uart_driver);
2490 if (likely(ret == 0)) {
2491 ret = platform_driver_register(&sci_driver);
2492 if (unlikely(ret))
2493 uart_unregister_driver(&sci_uart_driver);
2494 }
2495
2496 return ret;
2497}
2498
2499static void __exit sci_exit(void)
2500{
2501 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2502 uart_unregister_driver(&sci_uart_driver);
2503}
2504
7b6fd3bf
MD		 2505#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2506early_platform_init_buffer("earlyprintk", &sci_driver,
2507 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2508#endif
1da177e4
LT		 2509module_init(sci_init);
2510module_exit(sci_exit);
2511
e108b2ca 2512MODULE_LICENSE("GPL");
e169c139 2513MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2514MODULE_AUTHOR("Paul Mundt");
2515MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux kernel - Deliverables
This page took 0.803771 seconds and 5 git commands to generate.