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serial: sh-sci: FIFO sizing helper consolidation.
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
1da177e4
LT		 28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
e108b2ca 41#include <linux/platform_device.h>
96de1a8f 42#include <linux/serial_sci.h>
1da177e4 43#include <linux/notifier.h>
5e50d2d6 44#include <linux/pm_runtime.h>
1da177e4 45#include <linux/cpufreq.h>
85f094ec 46#include <linux/clk.h>
fa5da2f7 47#include <linux/ctype.h>
7ff731ae 48#include <linux/err.h>
73a19e4c
GL		 49#include <linux/dmaengine.h>
50#include <linux/scatterlist.h>
5a0e3ad6 51#include <linux/slab.h>
85f094ec
PM		 52
53#ifdef CONFIG_SUPERH
1da177e4
LT		 54#include <asm/sh_bios.h>
55#endif
56
1da177e4
LT		 57#include "sh-sci.h"
58
e108b2ca
PM		 59struct sci_port {
60 struct uart_port port;
61
ce6738b6
PM		 62 /* Platform configuration */
63 struct plat_sci_port *cfg;
e108b2ca 64
e108b2ca
PM		 65 /* Port enable callback */
66 void (*enable)(struct uart_port *port);
67
68 /* Port disable callback */
69 void (*disable)(struct uart_port *port);
70
71 /* Break timer */
72 struct timer_list break_timer;
73 int break_flag;
1534a3b3 74
501b825d
MD		 75 /* Interface clock */
76 struct clk *iclk;
c7ed1ab3
PM		 77 /* Function clock */
78 struct clk *fclk;
edad1f20 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
e108b2ca
PM		 102};
103
1da177e4 104/* Function prototypes */
d535a230 105static void sci_start_tx(struct uart_port *port);
b129a8cc 106static void sci_stop_tx(struct uart_port *port);
d535a230 107static void sci_start_rx(struct uart_port *port);
1da177e4 108
e108b2ca 109#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 110
e108b2ca
PM		 111static struct sci_port sci_ports[SCI_NPORTS];
112static struct uart_driver sci_uart_driver;
1da177e4 113
e7c98dc7
MT		 114static inline struct sci_port *
115to_sci_port(struct uart_port *uart)
116{
117 return container_of(uart, struct sci_port, port);
118}
119
61a6976b
PM		 120struct plat_sci_reg {
121 u8 offset, size;
122};
123
124/* Helper for invalidating specific entries of an inherited map. */
125#define sci_reg_invalid { .offset = 0, .size = 0 }
126
127static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
130 },
131
132 /*
133 * Common SCI definitions, dependent on the port's regshift
134 * value.
135 */
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
149 },
150
151 /*
152 * Common definitions for legacy IrDA ports, dependent on
153 * regshift value.
154 */
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
168 },
169
170 /*
171 * Common SCIFA definitions.
172 */
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 },
187
188 /*
189 * Common SCIFB definitions.
190 */
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
199 [SCFDR] = { 0x1c, 16 },
200 [SCTFDR] = sci_reg_invalid,
201 [SCRFDR] = sci_reg_invalid,
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
204 },
205
206 /*
207 * Common SH-3 SCIF definitions.
208 */
209 [SCIx_SH3_SCIF_REGTYPE] = {
210 [SCSMR] = { 0x00, 8 },
211 [SCBRR] = { 0x02, 8 },
212 [SCSCR] = { 0x04, 8 },
213 [SCxTDR] = { 0x06, 8 },
214 [SCxSR] = { 0x08, 16 },
215 [SCxRDR] = { 0x0a, 8 },
216 [SCFCR] = { 0x0c, 8 },
217 [SCFDR] = { 0x0e, 16 },
218 [SCTFDR] = sci_reg_invalid,
219 [SCRFDR] = sci_reg_invalid,
220 [SCSPTR] = sci_reg_invalid,
221 [SCLSR] = sci_reg_invalid,
222 },
223
224 /*
225 * Common SH-4(A) SCIF(B) definitions.
226 */
227 [SCIx_SH4_SCIF_REGTYPE] = {
228 [SCSMR] = { 0x00, 16 },
229 [SCBRR] = { 0x04, 8 },
230 [SCSCR] = { 0x08, 16 },
231 [SCxTDR] = { 0x0c, 8 },
232 [SCxSR] = { 0x10, 16 },
233 [SCxRDR] = { 0x14, 8 },
234 [SCFCR] = { 0x18, 16 },
235 [SCFDR] = { 0x1c, 16 },
236 [SCTFDR] = sci_reg_invalid,
237 [SCRFDR] = sci_reg_invalid,
238 [SCSPTR] = { 0x20, 16 },
239 [SCLSR] = { 0x24, 16 },
240 },
241
242 /*
243 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
244 * register.
245 */
246 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = sci_reg_invalid,
258 [SCLSR] = { 0x24, 16 },
259 },
260
261 /*
262 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
263 * count registers.
264 */
265 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
275 [SCRFDR] = { 0x20, 16 },
276 [SCSPTR] = { 0x24, 16 },
277 [SCLSR] = { 0x28, 16 },
278 },
279
280 /*
281 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
282 * registers.
283 */
284 [SCIx_SH7705_SCIF_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x20, 8 },
289 [SCxSR] = { 0x14, 16 },
290 [SCxRDR] = { 0x24, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = sci_reg_invalid,
294 [SCRFDR] = sci_reg_invalid,
295 [SCSPTR] = sci_reg_invalid,
296 [SCLSR] = sci_reg_invalid,
297 },
298};
299
72b294cf
PM		 300#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
301
61a6976b
PM		 302/*
303 * The "offset" here is rather misleading, in that it refers to an enum
304 * value relative to the port mapping rather than the fixed offset
305 * itself, which needs to be manually retrieved from the platform's
306 * register map for the given port.
307 */
308static unsigned int sci_serial_in(struct uart_port *p, int offset)
309{
72b294cf 310 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 311
312 if (reg->size == 8)
313 return ioread8(p->membase + (reg->offset << p->regshift));
314 else if (reg->size == 16)
315 return ioread16(p->membase + (reg->offset << p->regshift));
316 else
317 WARN(1, "Invalid register access\n");
318
319 return 0;
320}
321
322static void sci_serial_out(struct uart_port *p, int offset, int value)
323{
72b294cf 324 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 325
326 if (reg->size == 8)
327 iowrite8(value, p->membase + (reg->offset << p->regshift));
328 else if (reg->size == 16)
329 iowrite16(value, p->membase + (reg->offset << p->regshift));
330 else
331 WARN(1, "Invalid register access\n");
332}
333
334#define sci_in(up, offset) (up->serial_in(up, offset))
335#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
336
337static int sci_probe_regmap(struct plat_sci_port *cfg)
338{
339 switch (cfg->type) {
340 case PORT_SCI:
341 cfg->regtype = SCIx_SCI_REGTYPE;
342 break;
343 case PORT_IRDA:
344 cfg->regtype = SCIx_IRDA_REGTYPE;
345 break;
346 case PORT_SCIFA:
347 cfg->regtype = SCIx_SCIFA_REGTYPE;
348 break;
349 case PORT_SCIFB:
350 cfg->regtype = SCIx_SCIFB_REGTYPE;
351 break;
352 case PORT_SCIF:
353 /*
354 * The SH-4 is a bit of a misnomer here, although that's
355 * where this particular port layout originated. This
356 * configuration (or some slight variation thereof)
357 * remains the dominant model for all SCIFs.
358 */
359 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
360 break;
361 default:
362 printk(KERN_ERR "Can't probe register map for given port\n");
363 return -EINVAL;
364 }
365
366 return 0;
367}
368
07d2a1a1 369#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 370
371#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 372static int sci_poll_get_char(struct uart_port *port)
1da177e4 373{
1da177e4
LT		 374 unsigned short status;
375 int c;
376
e108b2ca 377 do {
1da177e4
LT		 378 status = sci_in(port, SCxSR);
379 if (status & SCxSR_ERRORS(port)) {
94c8b6db 380 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 381 continue;
382 }
3f255eb3
JW		 383 break;
384 } while (1);
385
386 if (!(status & SCxSR_RDxF(port)))
387 return NO_POLL_CHAR;
07d2a1a1 388
1da177e4 389 c = sci_in(port, SCxRDR);
07d2a1a1 390
e7c98dc7
MT		 391 /* Dummy read */
392 sci_in(port, SCxSR);
1da177e4 393 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 394
395 return c;
396}
1f6fd5c9 397#endif
1da177e4 398
07d2a1a1 399static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 400{
1da177e4
LT		 401 unsigned short status;
402
1da177e4
LT		 403 do {
404 status = sci_in(port, SCxSR);
405 } while (!(status & SCxSR_TDxE(port)));
406
272966c0 407 sci_out(port, SCxTDR, c);
dd0a3e77 408 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 409}
07d2a1a1 410#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 411
61a6976b 412static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 413{
61a6976b
PM		 414 struct sci_port *s = to_sci_port(port);
415 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 416
61a6976b
PM		 417 /*
418 * Use port-specific handler if provided.
419 */
420 if (s->cfg->ops && s->cfg->ops->init_pins) {
421 s->cfg->ops->init_pins(port, cflag);
422 return;
1da177e4 423 }
41504c39 424
61a6976b
PM		 425 /*
426 * For the generic path SCSPTR is necessary. Bail out if that's
427 * unavailable, too.
428 */
429 if (!reg->size)
430 return;
41504c39 431
d5701647 432 if (!(cflag & CRTSCTS))
61a6976b 433 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
d5701647 434}
e108b2ca 435
72b294cf 436static int sci_txfill(struct uart_port *port)
e108b2ca 437{
72b294cf 438 struct plat_sci_reg *reg;
e108b2ca 439
72b294cf
PM		 440 reg = sci_getreg(port, SCTFDR);
441 if (reg->size)
73a19e4c 442 return sci_in(port, SCTFDR) & 0xff;
c63847a3 443
72b294cf
PM		 444 reg = sci_getreg(port, SCFDR);
445 if (reg->size)
d1d4b10c 446 return sci_in(port, SCFDR) >> 8;
d1d4b10c 447
73a19e4c 448 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 449}
450
73a19e4c
GL		 451static int sci_txroom(struct uart_port *port)
452{
72b294cf 453 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 454}
455
456static int sci_rxfill(struct uart_port *port)
e108b2ca 457{
72b294cf
PM		 458 struct plat_sci_reg *reg;
459
460 reg = sci_getreg(port, SCRFDR);
461 if (reg->size)
462 return sci_in(port, SCRFDR) & 0xff;
463
464 reg = sci_getreg(port, SCFDR);
465 if (reg->size)
466 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
467
e7c98dc7 468 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 469}
470
514820eb
PM		 471/*
472 * SCI helper for checking the state of the muxed port/RXD pins.
473 */
474static inline int sci_rxd_in(struct uart_port *port)
475{
476 struct sci_port *s = to_sci_port(port);
477
478 if (s->cfg->port_reg <= 0)
479 return 1;
480
481 return !!__raw_readb(s->cfg->port_reg);
482}
483
1da177e4
LT		 484/* ********************************************************************** *
485 * the interrupt related routines *
486 * ********************************************************************** */
487
488static void sci_transmit_chars(struct uart_port *port)
489{
ebd2c8f6 490 struct circ_buf *xmit = &port->state->xmit;
1da177e4 491 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 492 unsigned short status;
493 unsigned short ctrl;
e108b2ca 494 int count;
1da177e4
LT		 495
496 status = sci_in(port, SCxSR);
497 if (!(status & SCxSR_TDxE(port))) {
1da177e4 498 ctrl = sci_in(port, SCSCR);
e7c98dc7 499 if (uart_circ_empty(xmit))
8e698614 500 ctrl &= ~SCSCR_TIE;
e7c98dc7 501 else
8e698614 502 ctrl |= SCSCR_TIE;
1da177e4 503 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 504 return;
505 }
506
72b294cf 507 count = sci_txroom(port);
1da177e4
LT		 508
509 do {
510 unsigned char c;
511
512 if (port->x_char) {
513 c = port->x_char;
514 port->x_char = 0;
515 } else if (!uart_circ_empty(xmit) && !stopped) {
516 c = xmit->buf[xmit->tail];
517 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
518 } else {
519 break;
520 }
521
522 sci_out(port, SCxTDR, c);
523
524 port->icount.tx++;
525 } while (--count > 0);
526
527 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
528
529 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
530 uart_write_wakeup(port);
531 if (uart_circ_empty(xmit)) {
b129a8cc 532 sci_stop_tx(port);
1da177e4 533 } else {
1da177e4
LT		 534 ctrl = sci_in(port, SCSCR);
535
1a22f08d 536 if (port->type != PORT_SCI) {
1da177e4
LT		 537 sci_in(port, SCxSR); /* Dummy read */
538 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
539 }
1da177e4 540
8e698614 541 ctrl |= SCSCR_TIE;
1da177e4 542 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 543 }
544}
545
546/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 547#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 548
94c8b6db 549static void sci_receive_chars(struct uart_port *port)
1da177e4 550{
e7c98dc7 551 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 552 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 553 int i, count, copied = 0;
554 unsigned short status;
33f0f88f 555 unsigned char flag;
1da177e4
LT		 556
557 status = sci_in(port, SCxSR);
558 if (!(status & SCxSR_RDxF(port)))
559 return;
560
561 while (1) {
1da177e4 562 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 563 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 564
565 /* If for any reason we can't copy more data, we're done! */
566 if (count == 0)
567 break;
568
569 if (port->type == PORT_SCI) {
570 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 571 if (uart_handle_sysrq_char(port, c) ||
572 sci_port->break_flag)
1da177e4 573 count = 0;
e7c98dc7 574 else
e108b2ca 575 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 576 } else {
e7c98dc7 577 for (i = 0; i < count; i++) {
1da177e4
LT		 578 char c = sci_in(port, SCxRDR);
579 status = sci_in(port, SCxSR);
580#if defined(CONFIG_CPU_SH3)
581 /* Skip "chars" during break */
e108b2ca 582 if (sci_port->break_flag) {
1da177e4
LT		 583 if ((c == 0) &&
584 (status & SCxSR_FER(port))) {
585 count--; i--;
586 continue;
587 }
e108b2ca 588
1da177e4 589 /* Nonzero => end-of-break */
762c69e3 590 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 591 sci_port->break_flag = 0;
592
1da177e4
LT		 593 if (STEPFN(c)) {
594 count--; i--;
595 continue;
596 }
597 }
598#endif /* CONFIG_CPU_SH3 */
7d12e780 599 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 600 count--; i--;
601 continue;
602 }
603
604 /* Store data and status */
73a19e4c 605 if (status & SCxSR_FER(port)) {
33f0f88f 606 flag = TTY_FRAME;
762c69e3 607 dev_notice(port->dev, "frame error\n");
73a19e4c 608 } else if (status & SCxSR_PER(port)) {
33f0f88f 609 flag = TTY_PARITY;
762c69e3 610 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 611 } else
612 flag = TTY_NORMAL;
762c69e3 613
33f0f88f 614 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 615 }
616 }
617
618 sci_in(port, SCxSR); /* dummy read */
619 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
620
1da177e4
LT		 621 copied += count;
622 port->icount.rx += count;
623 }
624
625 if (copied) {
626 /* Tell the rest of the system the news. New characters! */
627 tty_flip_buffer_push(tty);
628 } else {
629 sci_in(port, SCxSR); /* dummy read */
630 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
631 }
632}
633
634#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 635
636/*
637 * The sci generates interrupts during the break,
1da177e4
LT		 638 * 1 per millisecond or so during the break period, for 9600 baud.
639 * So dont bother disabling interrupts.
640 * But dont want more than 1 break event.
641 * Use a kernel timer to periodically poll the rx line until
642 * the break is finished.
643 */
94c8b6db 644static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 645{
bc9b3f5c 646 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 647}
94c8b6db 648
1da177e4
LT		 649/* Ensure that two consecutive samples find the break over. */
650static void sci_break_timer(unsigned long data)
651{
e108b2ca
PM		 652 struct sci_port *port = (struct sci_port *)data;
653
5e50d2d6
MD		 654 if (port->enable)
655 port->enable(&port->port);
656
e108b2ca 657 if (sci_rxd_in(&port->port) == 0) {
1da177e4 658 port->break_flag = 1;
e108b2ca
PM		 659 sci_schedule_break_timer(port);
660 } else if (port->break_flag == 1) {
1da177e4
LT		 661 /* break is over. */
662 port->break_flag = 2;
e108b2ca
PM		 663 sci_schedule_break_timer(port);
664 } else
665 port->break_flag = 0;
5e50d2d6
MD		 666
667 if (port->disable)
668 port->disable(&port->port);
1da177e4
LT		 669}
670
94c8b6db 671static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 672{
673 int copied = 0;
674 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 675 struct tty_struct *tty = port->state->port.tty;
debf9507 676 struct sci_port *s = to_sci_port(port);
1da177e4 677
debf9507
PM		 678 /*
679 * Handle overruns, if supported.
680 */
681 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
682 if (status & (1 << s->cfg->overrun_bit)) {
683 /* overrun error */
684 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
685 copied++;
762c69e3 686
debf9507
PM		 687 dev_notice(port->dev, "overrun error");
688 }
1da177e4
LT		 689 }
690
e108b2ca 691 if (status & SCxSR_FER(port)) {
1da177e4
LT		 692 if (sci_rxd_in(port) == 0) {
693 /* Notify of BREAK */
e7c98dc7 694 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 695
696 if (!sci_port->break_flag) {
697 sci_port->break_flag = 1;
698 sci_schedule_break_timer(sci_port);
699
1da177e4 700 /* Do sysrq handling. */
e108b2ca 701 if (uart_handle_break(port))
1da177e4 702 return 0;
762c69e3
PM		 703
704 dev_dbg(port->dev, "BREAK detected\n");
705
e108b2ca 706 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 707 copied++;
708 }
709
e108b2ca 710 } else {
1da177e4 711 /* frame error */
e108b2ca 712 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 713 copied++;
762c69e3
PM		 714
715 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 716 }
717 }
718
e108b2ca 719 if (status & SCxSR_PER(port)) {
1da177e4 720 /* parity error */
e108b2ca
PM		 721 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
722 copied++;
762c69e3
PM		 723
724 dev_notice(port->dev, "parity error");
1da177e4
LT		 725 }
726
33f0f88f 727 if (copied)
1da177e4 728 tty_flip_buffer_push(tty);
1da177e4
LT		 729
730 return copied;
731}
732
94c8b6db 733static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 734{
ebd2c8f6 735 struct tty_struct *tty = port->state->port.tty;
debf9507 736 struct sci_port *s = to_sci_port(port);
d830fa45
PM		 737 int copied = 0;
738
debf9507
PM		 739 /*
740 * XXX: Technically not limited to non-SCIFs, it's simply the
741 * SCLSR check that is for the moment SCIF-specific. This
742 * probably wants to be revisited for SCIFA/B as well as for
743 * factoring in SCI overrun detection.
744 */
d830fa45
PM		 745 if (port->type != PORT_SCIF)
746 return 0;
747
debf9507 748 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
d830fa45
PM		 749 sci_out(port, SCLSR, 0);
750
751 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
752 tty_flip_buffer_push(tty);
753
754 dev_notice(port->dev, "overrun error\n");
755 copied++;
756 }
757
758 return copied;
759}
760
94c8b6db 761static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 762{
763 int copied = 0;
764 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 765 struct tty_struct *tty = port->state->port.tty;
a5660ada 766 struct sci_port *s = to_sci_port(port);
1da177e4 767
0b3d4ef6
PM		 768 if (uart_handle_break(port))
769 return 0;
770
b7a76e4b 771 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 772#if defined(CONFIG_CPU_SH3)
773 /* Debounce break */
774 s->break_flag = 1;
775#endif
776 /* Notify of BREAK */
e108b2ca 777 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 778 copied++;
762c69e3
PM		 779
780 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 781 }
782
33f0f88f 783 if (copied)
1da177e4 784 tty_flip_buffer_push(tty);
e108b2ca 785
d830fa45
PM		 786 copied += sci_handle_fifo_overrun(port);
787
1da177e4
LT		 788 return copied;
789}
790
73a19e4c 791static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 792{
73a19e4c
GL		 793#ifdef CONFIG_SERIAL_SH_SCI_DMA
794 struct uart_port *port = ptr;
795 struct sci_port *s = to_sci_port(port);
796
797 if (s->chan_rx) {
73a19e4c
GL		 798 u16 scr = sci_in(port, SCSCR);
799 u16 ssr = sci_in(port, SCxSR);
800
801 /* Disable future Rx interrupts */
d1d4b10c 802 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 803 disable_irq_nosync(irq);
804 scr |= 0x4000;
805 } else {
f43dc23d 806 scr &= ~SCSCR_RIE;
3089f381
GL		 807 }
808 sci_out(port, SCSCR, scr);
73a19e4c
GL		 809 /* Clear current interrupt */
810 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 811 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
812 jiffies, s->rx_timeout);
813 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 814
815 return IRQ_HANDLED;
816 }
817#endif
818
1da177e4
LT		 819 /* I think sci_receive_chars has to be called irrespective
820 * of whether the I_IXOFF is set, otherwise, how is the interrupt
821 * to be disabled?
822 */
73a19e4c 823 sci_receive_chars(ptr);
1da177e4
LT		 824
825 return IRQ_HANDLED;
826}
827
7d12e780 828static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 829{
830 struct uart_port *port = ptr;
fd78a76a 831 unsigned long flags;
1da177e4 832
fd78a76a 833 spin_lock_irqsave(&port->lock, flags);
1da177e4 834 sci_transmit_chars(port);
fd78a76a 835 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 836
837 return IRQ_HANDLED;
838}
839
7d12e780 840static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 841{
842 struct uart_port *port = ptr;
843
844 /* Handle errors */
845 if (port->type == PORT_SCI) {
846 if (sci_handle_errors(port)) {
847 /* discard character in rx buffer */
848 sci_in(port, SCxSR);
849 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
850 }
851 } else {
d830fa45 852 sci_handle_fifo_overrun(port);
7d12e780 853 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 854 }
855
856 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
857
858 /* Kick the transmission */
7d12e780 859 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 860
861 return IRQ_HANDLED;
862}
863
7d12e780 864static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 865{
866 struct uart_port *port = ptr;
867
868 /* Handle BREAKs */
869 sci_handle_breaks(port);
870 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
871
872 return IRQ_HANDLED;
873}
874
f43dc23d
PM		 875static inline unsigned long port_rx_irq_mask(struct uart_port *port)
876{
877 /*
878 * Not all ports (such as SCIFA) will support REIE. Rather than
879 * special-casing the port type, we check the port initialization
880 * IRQ enable mask to see whether the IRQ is desired at all. If
881 * it's unset, it's logically inferred that there's no point in
882 * testing for it.
883 */
ce6738b6 884 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 885}
886
7d12e780 887static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 888{
44e18e9e 889 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 890 struct uart_port *port = ptr;
73a19e4c 891 struct sci_port *s = to_sci_port(port);
a8884e34 892 irqreturn_t ret = IRQ_NONE;
1da177e4 893
e7c98dc7
MT		 894 ssr_status = sci_in(port, SCxSR);
895 scr_status = sci_in(port, SCSCR);
f43dc23d 896 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 897
898 /* Tx Interrupt */
f43dc23d 899 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 900 !s->chan_tx)
a8884e34 901 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 902
73a19e4c
GL		 903 /*
904 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
905 * DR flags
906 */
907 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 908 (scr_status & SCSCR_RIE))
a8884e34 909 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 910
1da177e4 911 /* Error Interrupt */
dd4da3a5 912 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 913 ret = sci_er_interrupt(irq, ptr);
f43dc23d 914
1da177e4 915 /* Break Interrupt */
dd4da3a5 916 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 917 ret = sci_br_interrupt(irq, ptr);
1da177e4 918
a8884e34 919 return ret;
1da177e4
LT		 920}
921
1da177e4 922/*
25985edc 923 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 924 * ports' baud rate when the peripheral clock changes.
925 */
e108b2ca
PM		 926static int sci_notifier(struct notifier_block *self,
927 unsigned long phase, void *p)
1da177e4 928{
e552de24
MD		 929 struct sci_port *sci_port;
930 unsigned long flags;
1da177e4 931
d535a230
PM		 932 sci_port = container_of(self, struct sci_port, freq_transition);
933
1da177e4 934 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 935 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 936 struct uart_port *port = &sci_port->port;
073e84c9 937
d535a230
PM		 938 spin_lock_irqsave(&port->lock, flags);
939 port->uartclk = clk_get_rate(sci_port->iclk);
940 spin_unlock_irqrestore(&port->lock, flags);
e552de24 941 }
1da177e4 942
1da177e4
LT		 943 return NOTIFY_OK;
944}
501b825d
MD		 945
946static void sci_clk_enable(struct uart_port *port)
947{
948 struct sci_port *sci_port = to_sci_port(port);
949
5e50d2d6
MD		 950 pm_runtime_get_sync(port->dev);
951
c7ed1ab3
PM		 952 clk_enable(sci_port->iclk);
953 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
954 clk_enable(sci_port->fclk);
501b825d
MD		 955}
956
957static void sci_clk_disable(struct uart_port *port)
958{
959 struct sci_port *sci_port = to_sci_port(port);
960
c7ed1ab3
PM		 961 clk_disable(sci_port->fclk);
962 clk_disable(sci_port->iclk);
5e50d2d6
MD		 963
964 pm_runtime_put_sync(port->dev);
501b825d 965}
1da177e4
LT		 966
967static int sci_request_irq(struct sci_port *port)
968{
969 int i;
7d12e780 970 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 971 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
972 sci_br_interrupt,
973 };
974 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
975 "SCI Transmit Data Empty", "SCI Break" };
976
ce6738b6
PM		 977 if (port->cfg->irqs[0] == port->cfg->irqs[1]) {
978 if (unlikely(!port->cfg->irqs[0]))
1da177e4 979 return -ENODEV;
e108b2ca 980
ce6738b6 981 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt,
35f3c518 982 IRQF_DISABLED, "sci", port)) {
762c69e3 983 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 984 return -ENODEV;
985 }
986 } else {
987 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
ce6738b6 988 if (unlikely(!port->cfg->irqs[i]))
1da177e4 989 continue;
762c69e3 990
ce6738b6 991 if (request_irq(port->cfg->irqs[i], handlers[i],
35f3c518 992 IRQF_DISABLED, desc[i], port)) {
762c69e3 993 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 994 return -ENODEV;
995 }
996 }
997 }
998
999 return 0;
1000}
1001
1002static void sci_free_irq(struct sci_port *port)
1003{
1004 int i;
1005
ce6738b6
PM		 1006 if (port->cfg->irqs[0] == port->cfg->irqs[1])
1007 free_irq(port->cfg->irqs[0], port);
762c69e3 1008 else {
ce6738b6
PM		 1009 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) {
1010 if (!port->cfg->irqs[i])
1da177e4
LT		 1011 continue;
1012
ce6738b6 1013 free_irq(port->cfg->irqs[i], port);
1da177e4
LT		 1014 }
1015 }
1016}
1017
1018static unsigned int sci_tx_empty(struct uart_port *port)
1019{
b1516803 1020 unsigned short status = sci_in(port, SCxSR);
72b294cf 1021 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1022
1023 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1024}
1025
1026static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1027{
1028 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
1029 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
1030 /* If you have signals for DTR and DCD, please implement here. */
1031}
1032
1033static unsigned int sci_get_mctrl(struct uart_port *port)
1034{
73a19e4c 1035 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 1036 and CTS/RTS */
1037
1038 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
1039}
1040
73a19e4c
GL		 1041#ifdef CONFIG_SERIAL_SH_SCI_DMA
1042static void sci_dma_tx_complete(void *arg)
1043{
1044 struct sci_port *s = arg;
1045 struct uart_port *port = &s->port;
1046 struct circ_buf *xmit = &port->state->xmit;
1047 unsigned long flags;
1048
1049 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1050
1051 spin_lock_irqsave(&port->lock, flags);
1052
f354a381 1053 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1054 xmit->tail &= UART_XMIT_SIZE - 1;
1055
f354a381 1056 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1057
1058 async_tx_ack(s->desc_tx);
1059 s->cookie_tx = -EINVAL;
1060 s->desc_tx = NULL;
1061
73a19e4c
GL		 1062 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1063 uart_write_wakeup(port);
1064
3089f381 1065 if (!uart_circ_empty(xmit)) {
73a19e4c 1066 schedule_work(&s->work_tx);
d1d4b10c 1067 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1068 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 1069 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 1070 }
1071
1072 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1073}
1074
1075/* Locking: called with port lock held */
1076static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1077 size_t count)
1078{
1079 struct uart_port *port = &s->port;
1080 int i, active, room;
1081
1082 room = tty_buffer_request_room(tty, count);
1083
1084 if (s->active_rx == s->cookie_rx[0]) {
1085 active = 0;
1086 } else if (s->active_rx == s->cookie_rx[1]) {
1087 active = 1;
1088 } else {
1089 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1090 return 0;
1091 }
1092
1093 if (room < count)
1094 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1095 count - room);
1096 if (!room)
1097 return room;
1098
1099 for (i = 0; i < room; i++)
1100 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1101 TTY_NORMAL);
1102
1103 port->icount.rx += room;
1104
1105 return room;
1106}
1107
1108static void sci_dma_rx_complete(void *arg)
1109{
1110 struct sci_port *s = arg;
1111 struct uart_port *port = &s->port;
1112 struct tty_struct *tty = port->state->port.tty;
1113 unsigned long flags;
1114 int count;
1115
3089f381 1116 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1117
1118 spin_lock_irqsave(&port->lock, flags);
1119
1120 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1121
3089f381 1122 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1123
1124 spin_unlock_irqrestore(&port->lock, flags);
1125
1126 if (count)
1127 tty_flip_buffer_push(tty);
1128
1129 schedule_work(&s->work_rx);
1130}
1131
73a19e4c
GL		 1132static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1133{
1134 struct dma_chan *chan = s->chan_rx;
1135 struct uart_port *port = &s->port;
73a19e4c
GL		 1136
1137 s->chan_rx = NULL;
1138 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1139 dma_release_channel(chan);
85b8e3ff
GL		 1140 if (sg_dma_address(&s->sg_rx[0]))
1141 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1142 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1143 if (enable_pio)
1144 sci_start_rx(port);
1145}
1146
1147static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1148{
1149 struct dma_chan *chan = s->chan_tx;
1150 struct uart_port *port = &s->port;
73a19e4c
GL		 1151
1152 s->chan_tx = NULL;
1153 s->cookie_tx = -EINVAL;
1154 dma_release_channel(chan);
1155 if (enable_pio)
1156 sci_start_tx(port);
1157}
1158
1159static void sci_submit_rx(struct sci_port *s)
1160{
1161 struct dma_chan *chan = s->chan_rx;
1162 int i;
1163
1164 for (i = 0; i < 2; i++) {
1165 struct scatterlist *sg = &s->sg_rx[i];
1166 struct dma_async_tx_descriptor *desc;
1167
1168 desc = chan->device->device_prep_slave_sg(chan,
1169 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1170
1171 if (desc) {
1172 s->desc_rx[i] = desc;
1173 desc->callback = sci_dma_rx_complete;
1174 desc->callback_param = s;
1175 s->cookie_rx[i] = desc->tx_submit(desc);
1176 }
1177
1178 if (!desc || s->cookie_rx[i] < 0) {
1179 if (i) {
1180 async_tx_ack(s->desc_rx[0]);
1181 s->cookie_rx[0] = -EINVAL;
1182 }
1183 if (desc) {
1184 async_tx_ack(desc);
1185 s->cookie_rx[i] = -EINVAL;
1186 }
1187 dev_warn(s->port.dev,
1188 "failed to re-start DMA, using PIO\n");
1189 sci_rx_dma_release(s, true);
1190 return;
1191 }
3089f381
GL		 1192 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1193 s->cookie_rx[i], i);
73a19e4c
GL		 1194 }
1195
1196 s->active_rx = s->cookie_rx[0];
1197
1198 dma_async_issue_pending(chan);
1199}
1200
1201static void work_fn_rx(struct work_struct *work)
1202{
1203 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1204 struct uart_port *port = &s->port;
1205 struct dma_async_tx_descriptor *desc;
1206 int new;
1207
1208 if (s->active_rx == s->cookie_rx[0]) {
1209 new = 0;
1210 } else if (s->active_rx == s->cookie_rx[1]) {
1211 new = 1;
1212 } else {
1213 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1214 return;
1215 }
1216 desc = s->desc_rx[new];
1217
1218 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1219 DMA_SUCCESS) {
1220 /* Handle incomplete DMA receive */
1221 struct tty_struct *tty = port->state->port.tty;
1222 struct dma_chan *chan = s->chan_rx;
1223 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1224 async_tx);
1225 unsigned long flags;
1226 int count;
1227
05827630 1228 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1229 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1230 sh_desc->partial, sh_desc->cookie);
1231
1232 spin_lock_irqsave(&port->lock, flags);
1233 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1234 spin_unlock_irqrestore(&port->lock, flags);
1235
1236 if (count)
1237 tty_flip_buffer_push(tty);
1238
1239 sci_submit_rx(s);
1240
1241 return;
1242 }
1243
1244 s->cookie_rx[new] = desc->tx_submit(desc);
1245 if (s->cookie_rx[new] < 0) {
1246 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1247 sci_rx_dma_release(s, true);
1248 return;
1249 }
1250
73a19e4c 1251 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1252
1253 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1254 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1255}
1256
1257static void work_fn_tx(struct work_struct *work)
1258{
1259 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1260 struct dma_async_tx_descriptor *desc;
1261 struct dma_chan *chan = s->chan_tx;
1262 struct uart_port *port = &s->port;
1263 struct circ_buf *xmit = &port->state->xmit;
1264 struct scatterlist *sg = &s->sg_tx;
1265
1266 /*
1267 * DMA is idle now.
1268 * Port xmit buffer is already mapped, and it is one page... Just adjust
1269 * offsets and lengths. Since it is a circular buffer, we have to
1270 * transmit till the end, and then the rest. Take the port lock to get a
1271 * consistent xmit buffer state.
1272 */
1273 spin_lock_irq(&port->lock);
1274 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1275 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1276 sg->offset;
f354a381 1277 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1278 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1279 spin_unlock_irq(&port->lock);
1280
f354a381 1281 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1282
1283 desc = chan->device->device_prep_slave_sg(chan,
1284 sg, s->sg_len_tx, DMA_TO_DEVICE,
1285 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1286 if (!desc) {
1287 /* switch to PIO */
1288 sci_tx_dma_release(s, true);
1289 return;
1290 }
1291
1292 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1293
1294 spin_lock_irq(&port->lock);
1295 s->desc_tx = desc;
1296 desc->callback = sci_dma_tx_complete;
1297 desc->callback_param = s;
1298 spin_unlock_irq(&port->lock);
1299 s->cookie_tx = desc->tx_submit(desc);
1300 if (s->cookie_tx < 0) {
1301 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1302 /* switch to PIO */
1303 sci_tx_dma_release(s, true);
1304 return;
1305 }
1306
1307 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1308 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1309
1310 dma_async_issue_pending(chan);
1311}
1312#endif
1313
b129a8cc 1314static void sci_start_tx(struct uart_port *port)
1da177e4 1315{
3089f381 1316 struct sci_port *s = to_sci_port(port);
e108b2ca 1317 unsigned short ctrl;
1da177e4 1318
73a19e4c 1319#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1320 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1321 u16 new, scr = sci_in(port, SCSCR);
1322 if (s->chan_tx)
1323 new = scr | 0x8000;
1324 else
1325 new = scr & ~0x8000;
1326 if (new != scr)
1327 sci_out(port, SCSCR, new);
73a19e4c 1328 }
f43dc23d 1329
3089f381
GL		 1330 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1331 s->cookie_tx < 0)
1332 schedule_work(&s->work_tx);
73a19e4c 1333#endif
f43dc23d 1334
d1d4b10c 1335 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1336 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1337 ctrl = sci_in(port, SCSCR);
f43dc23d 1338 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1339 }
1da177e4
LT		 1340}
1341
b129a8cc 1342static void sci_stop_tx(struct uart_port *port)
1da177e4 1343{
1da177e4
LT		 1344 unsigned short ctrl;
1345
1346 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1347 ctrl = sci_in(port, SCSCR);
f43dc23d 1348
d1d4b10c 1349 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1350 ctrl &= ~0x8000;
f43dc23d 1351
8e698614 1352 ctrl &= ~SCSCR_TIE;
f43dc23d 1353
1da177e4 1354 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1355}
1356
73a19e4c 1357static void sci_start_rx(struct uart_port *port)
1da177e4 1358{
1da177e4
LT		 1359 unsigned short ctrl;
1360
f43dc23d 1361 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1362
d1d4b10c 1363 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1364 ctrl &= ~0x4000;
f43dc23d 1365
1da177e4 1366 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1367}
1368
1369static void sci_stop_rx(struct uart_port *port)
1370{
1da177e4
LT		 1371 unsigned short ctrl;
1372
1da177e4 1373 ctrl = sci_in(port, SCSCR);
f43dc23d 1374
d1d4b10c 1375 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1376 ctrl &= ~0x4000;
f43dc23d
PM		 1377
1378 ctrl &= ~port_rx_irq_mask(port);
1379
1da177e4 1380 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1381}
1382
1383static void sci_enable_ms(struct uart_port *port)
1384{
1385 /* Nothing here yet .. */
1386}
1387
1388static void sci_break_ctl(struct uart_port *port, int break_state)
1389{
1390 /* Nothing here yet .. */
1391}
1392
73a19e4c
GL		 1393#ifdef CONFIG_SERIAL_SH_SCI_DMA
1394static bool filter(struct dma_chan *chan, void *slave)
1395{
1396 struct sh_dmae_slave *param = slave;
1397
1398 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1399 param->slave_id);
1400
1401 if (param->dma_dev == chan->device->dev) {
1402 chan->private = param;
1403 return true;
1404 } else {
1405 return false;
1406 }
1407}
1408
1409static void rx_timer_fn(unsigned long arg)
1410{
1411 struct sci_port *s = (struct sci_port *)arg;
1412 struct uart_port *port = &s->port;
73a19e4c 1413 u16 scr = sci_in(port, SCSCR);
3089f381 1414
d1d4b10c 1415 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1416 scr &= ~0x4000;
ce6738b6 1417 enable_irq(s->cfg->irqs[1]);
3089f381 1418 }
f43dc23d 1419 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1420 dev_dbg(port->dev, "DMA Rx timed out\n");
1421 schedule_work(&s->work_rx);
1422}
1423
1424static void sci_request_dma(struct uart_port *port)
1425{
1426 struct sci_port *s = to_sci_port(port);
1427 struct sh_dmae_slave *param;
1428 struct dma_chan *chan;
1429 dma_cap_mask_t mask;
1430 int nent;
1431
1432 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
ce6738b6 1433 port->line, s->cfg->dma_dev);
73a19e4c 1434
ce6738b6 1435 if (!s->cfg->dma_dev)
73a19e4c
GL		 1436 return;
1437
1438 dma_cap_zero(mask);
1439 dma_cap_set(DMA_SLAVE, mask);
1440
1441 param = &s->param_tx;
1442
1443 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6
PM		 1444 param->slave_id = s->cfg->dma_slave_tx;
1445 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1446
1447 s->cookie_tx = -EINVAL;
1448 chan = dma_request_channel(mask, filter, param);
1449 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1450 if (chan) {
1451 s->chan_tx = chan;
1452 sg_init_table(&s->sg_tx, 1);
1453 /* UART circular tx buffer is an aligned page. */
1454 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1455 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1456 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1457 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1458 if (!nent)
1459 sci_tx_dma_release(s, false);
1460 else
1461 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1462 sg_dma_len(&s->sg_tx),
1463 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1464
1465 s->sg_len_tx = nent;
1466
1467 INIT_WORK(&s->work_tx, work_fn_tx);
1468 }
1469
1470 param = &s->param_rx;
1471
1472 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6
PM		 1473 param->slave_id = s->cfg->dma_slave_rx;
1474 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1475
1476 chan = dma_request_channel(mask, filter, param);
1477 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1478 if (chan) {
1479 dma_addr_t dma[2];
1480 void *buf[2];
1481 int i;
1482
1483 s->chan_rx = chan;
1484
1485 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1486 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1487 &dma[0], GFP_KERNEL);
1488
1489 if (!buf[0]) {
1490 dev_warn(port->dev,
1491 "failed to allocate dma buffer, using PIO\n");
1492 sci_rx_dma_release(s, true);
1493 return;
1494 }
1495
1496 buf[1] = buf[0] + s->buf_len_rx;
1497 dma[1] = dma[0] + s->buf_len_rx;
1498
1499 for (i = 0; i < 2; i++) {
1500 struct scatterlist *sg = &s->sg_rx[i];
1501
1502 sg_init_table(sg, 1);
1503 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1504 (int)buf[i] & ~PAGE_MASK);
f354a381 1505 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1506 }
1507
1508 INIT_WORK(&s->work_rx, work_fn_rx);
1509 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1510
1511 sci_submit_rx(s);
1512 }
1513}
1514
1515static void sci_free_dma(struct uart_port *port)
1516{
1517 struct sci_port *s = to_sci_port(port);
1518
ce6738b6 1519 if (!s->cfg->dma_dev)
73a19e4c
GL		 1520 return;
1521
1522 if (s->chan_tx)
1523 sci_tx_dma_release(s, false);
1524 if (s->chan_rx)
1525 sci_rx_dma_release(s, false);
1526}
27bd1075
PM		 1527#else
1528static inline void sci_request_dma(struct uart_port *port)
1529{
1530}
1531
1532static inline void sci_free_dma(struct uart_port *port)
1533{
1534}
73a19e4c
GL		 1535#endif
1536
1da177e4
LT		 1537static int sci_startup(struct uart_port *port)
1538{
a5660ada 1539 struct sci_port *s = to_sci_port(port);
073e84c9 1540 int ret;
1da177e4 1541
73a19e4c
GL		 1542 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1543
e108b2ca
PM		 1544 if (s->enable)
1545 s->enable(port);
1da177e4 1546
073e84c9
PM		 1547 ret = sci_request_irq(s);
1548 if (unlikely(ret < 0))
1549 return ret;
1550
73a19e4c 1551 sci_request_dma(port);
073e84c9 1552
d656901b 1553 sci_start_tx(port);
73a19e4c 1554 sci_start_rx(port);
1da177e4
LT		 1555
1556 return 0;
1557}
1558
1559static void sci_shutdown(struct uart_port *port)
1560{
a5660ada 1561 struct sci_port *s = to_sci_port(port);
1da177e4 1562
73a19e4c
GL		 1563 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1564
1da177e4 1565 sci_stop_rx(port);
b129a8cc 1566 sci_stop_tx(port);
073e84c9 1567
73a19e4c 1568 sci_free_dma(port);
1da177e4
LT		 1569 sci_free_irq(s);
1570
e108b2ca
PM		 1571 if (s->disable)
1572 s->disable(port);
1da177e4
LT		 1573}
1574
26c92f37
PM		 1575static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1576 unsigned long freq)
1577{
1578 switch (algo_id) {
1579 case SCBRR_ALGO_1:
1580 return ((freq + 16 * bps) / (16 * bps) - 1);
1581 case SCBRR_ALGO_2:
1582 return ((freq + 16 * bps) / (32 * bps) - 1);
1583 case SCBRR_ALGO_3:
1584 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1585 case SCBRR_ALGO_4:
1586 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1587 case SCBRR_ALGO_5:
1588 return (((freq * 1000 / 32) / bps) - 1);
1589 }
1590
1591 /* Warn, but use a safe default */
1592 WARN_ON(1);
e8183a6c 1593
26c92f37
PM		 1594 return ((freq + 16 * bps) / (32 * bps) - 1);
1595}
1596
606d099c
AC		 1597static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1598 struct ktermios *old)
1da177e4 1599{
00b9de9c 1600 struct sci_port *s = to_sci_port(port);
154280fd 1601 unsigned int status, baud, smr_val, max_baud;
a2159b52 1602 int t = -1;
3089f381 1603 u16 scfcr = 0;
1da177e4 1604
154280fd
MD		 1605 /*
1606 * earlyprintk comes here early on with port->uartclk set to zero.
1607 * the clock framework is not up and running at this point so here
1608 * we assume that 115200 is the maximum baud rate. please note that
1609 * the baud rate is not programmed during earlyprintk - it is assumed
1610 * that the previous boot loader has enabled required clocks and
1611 * setup the baud rate generator hardware for us already.
1612 */
1613 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1614
154280fd
MD		 1615 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1616 if (likely(baud && port->uartclk))
ce6738b6 1617 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1618
36003386
AC		 1619 if (s->enable)
1620 s->enable(port);
1621
1da177e4
LT		 1622 do {
1623 status = sci_in(port, SCxSR);
1624 } while (!(status & SCxSR_TEND(port)));
1625
1626 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1627
1a22f08d 1628 if (port->type != PORT_SCI)
3089f381 1629 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1630
1631 smr_val = sci_in(port, SCSMR) & 3;
e8183a6c 1632
1da177e4
LT		 1633 if ((termios->c_cflag & CSIZE) == CS7)
1634 smr_val |= 0x40;
1635 if (termios->c_cflag & PARENB)
1636 smr_val |= 0x20;
1637 if (termios->c_cflag & PARODD)
1638 smr_val |= 0x30;
1639 if (termios->c_cflag & CSTOPB)
1640 smr_val |= 0x08;
1641
1642 uart_update_timeout(port, termios->c_cflag, baud);
1643
1644 sci_out(port, SCSMR, smr_val);
1645
73a19e4c 1646 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1647 s->cfg->scscr);
73a19e4c 1648
1da177e4 1649 if (t > 0) {
e7c98dc7 1650 if (t >= 256) {
1da177e4
LT		 1651 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1652 t >>= 2;
e7c98dc7 1653 } else
1da177e4 1654 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1655
1da177e4
LT		 1656 sci_out(port, SCBRR, t);
1657 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1658 }
1659
d5701647 1660 sci_init_pins(port, termios->c_cflag);
3089f381 1661 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
b7a76e4b 1662
ce6738b6 1663 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1664
3089f381
GL		 1665#ifdef CONFIG_SERIAL_SH_SCI_DMA
1666 /*
1667 * Calculate delay for 1.5 DMA buffers: see
1668 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1669 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1670 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1671 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1672 * sizes), but it has been found out experimentally, that this is not
1673 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1674 * as a minimum seem to work perfectly.
1675 */
1676 if (s->chan_rx) {
1677 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1678 port->fifosize / 2;
1679 dev_dbg(port->dev,
1680 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1681 s->rx_timeout * 1000 / HZ, port->timeout);
1682 if (s->rx_timeout < msecs_to_jiffies(20))
1683 s->rx_timeout = msecs_to_jiffies(20);
1684 }
1685#endif
1686
1da177e4 1687 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1688 sci_start_rx(port);
36003386
AC		 1689
1690 if (s->disable)
1691 s->disable(port);
1da177e4
LT		 1692}
1693
1694static const char *sci_type(struct uart_port *port)
1695{
1696 switch (port->type) {
e7c98dc7
MT		 1697 case PORT_IRDA:
1698 return "irda";
1699 case PORT_SCI:
1700 return "sci";
1701 case PORT_SCIF:
1702 return "scif";
1703 case PORT_SCIFA:
1704 return "scifa";
d1d4b10c
GL		 1705 case PORT_SCIFB:
1706 return "scifb";
1da177e4
LT		 1707 }
1708
fa43972f 1709 return NULL;
1da177e4
LT		 1710}
1711
e2651647 1712static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1713{
e2651647
PM		 1714 /*
1715 * Pick an arbitrary size that encapsulates all of the base
1716 * registers by default. This can be optimized later, or derived
1717 * from platform resource data at such a time that ports begin to
1718 * behave more erratically.
1719 */
1720 return 64;
1da177e4
LT		 1721}
1722
f6e9495d
PM		 1723static int sci_remap_port(struct uart_port *port)
1724{
1725 unsigned long size = sci_port_size(port);
1726
1727 /*
1728 * Nothing to do if there's already an established membase.
1729 */
1730 if (port->membase)
1731 return 0;
1732
1733 if (port->flags & UPF_IOREMAP) {
1734 port->membase = ioremap_nocache(port->mapbase, size);
1735 if (unlikely(!port->membase)) {
1736 dev_err(port->dev, "can't remap port#%d\n", port->line);
1737 return -ENXIO;
1738 }
1739 } else {
1740 /*
1741 * For the simple (and majority of) cases where we don't
1742 * need to do any remapping, just cast the cookie
1743 * directly.
1744 */
1745 port->membase = (void __iomem *)port->mapbase;
1746 }
1747
1748 return 0;
1749}
1750
e2651647 1751static void sci_release_port(struct uart_port *port)
1da177e4 1752{
e2651647
PM		 1753 if (port->flags & UPF_IOREMAP) {
1754 iounmap(port->membase);
1755 port->membase = NULL;
1756 }
1757
1758 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1759}
1760
e2651647 1761static int sci_request_port(struct uart_port *port)
1da177e4 1762{
e2651647
PM		 1763 unsigned long size = sci_port_size(port);
1764 struct resource *res;
f6e9495d 1765 int ret;
1da177e4 1766
1020520e 1767 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 1768 if (unlikely(res == NULL))
1769 return -EBUSY;
1da177e4 1770
f6e9495d
PM		 1771 ret = sci_remap_port(port);
1772 if (unlikely(ret != 0)) {
1773 release_resource(res);
1774 return ret;
7ff731ae 1775 }
e2651647
PM		 1776
1777 return 0;
1778}
1779
1780static void sci_config_port(struct uart_port *port, int flags)
1781{
1782 if (flags & UART_CONFIG_TYPE) {
1783 struct sci_port *sport = to_sci_port(port);
1784
1785 port->type = sport->cfg->type;
1786 sci_request_port(port);
1787 }
1da177e4
LT		 1788}
1789
1790static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1791{
a5660ada 1792 struct sci_port *s = to_sci_port(port);
1da177e4 1793
ce6738b6 1794 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1795 return -EINVAL;
1796 if (ser->baud_base < 2400)
1797 /* No paper tape reader for Mitch.. */
1798 return -EINVAL;
1799
1800 return 0;
1801}
1802
1803static struct uart_ops sci_uart_ops = {
1804 .tx_empty = sci_tx_empty,
1805 .set_mctrl = sci_set_mctrl,
1806 .get_mctrl = sci_get_mctrl,
1807 .start_tx = sci_start_tx,
1808 .stop_tx = sci_stop_tx,
1809 .stop_rx = sci_stop_rx,
1810 .enable_ms = sci_enable_ms,
1811 .break_ctl = sci_break_ctl,
1812 .startup = sci_startup,
1813 .shutdown = sci_shutdown,
1814 .set_termios = sci_set_termios,
1815 .type = sci_type,
1816 .release_port = sci_release_port,
1817 .request_port = sci_request_port,
1818 .config_port = sci_config_port,
1819 .verify_port = sci_verify_port,
07d2a1a1
PM		 1820#ifdef CONFIG_CONSOLE_POLL
1821 .poll_get_char = sci_poll_get_char,
1822 .poll_put_char = sci_poll_put_char,
1823#endif
1da177e4
LT		 1824};
1825
c7ed1ab3
PM		 1826static int __devinit sci_init_single(struct platform_device *dev,
1827 struct sci_port *sci_port,
1828 unsigned int index,
1829 struct plat_sci_port *p)
e108b2ca 1830{
73a19e4c 1831 struct uart_port *port = &sci_port->port;
e108b2ca 1832
73a19e4c
GL		 1833 port->ops = &sci_uart_ops;
1834 port->iotype = UPIO_MEM;
1835 port->line = index;
75136d48
MP		 1836
1837 switch (p->type) {
d1d4b10c
GL		 1838 case PORT_SCIFB:
1839 port->fifosize = 256;
1840 break;
75136d48 1841 case PORT_SCIFA:
73a19e4c 1842 port->fifosize = 64;
75136d48
MP		 1843 break;
1844 case PORT_SCIF:
73a19e4c 1845 port->fifosize = 16;
75136d48
MP		 1846 break;
1847 default:
73a19e4c 1848 port->fifosize = 1;
75136d48
MP		 1849 break;
1850 }
7b6fd3bf 1851
61a6976b
PM		 1852 if (p->regtype == SCIx_PROBE_REGTYPE)
1853 BUG_ON(sci_probe_regmap(p) != 0);
1854
7b6fd3bf 1855 if (dev) {
c7ed1ab3
PM		 1856 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1857 if (IS_ERR(sci_port->iclk)) {
1858 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1859 if (IS_ERR(sci_port->iclk)) {
1860 dev_err(&dev->dev, "can't get iclk\n");
1861 return PTR_ERR(sci_port->iclk);
1862 }
1863 }
1864
1865 /*
1866 * The function clock is optional, ignore it if we can't
1867 * find it.
1868 */
1869 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1870 if (IS_ERR(sci_port->fclk))
1871 sci_port->fclk = NULL;
1872
7b6fd3bf
MD		 1873 sci_port->enable = sci_clk_enable;
1874 sci_port->disable = sci_clk_disable;
73a19e4c 1875 port->dev = &dev->dev;
5e50d2d6
MD		 1876
1877 pm_runtime_enable(&dev->dev);
7b6fd3bf 1878 }
e108b2ca 1879
7ed7e071
MD		 1880 sci_port->break_timer.data = (unsigned long)sci_port;
1881 sci_port->break_timer.function = sci_break_timer;
1882 init_timer(&sci_port->break_timer);
1883
debf9507
PM		 1884 /*
1885 * Establish some sensible defaults for the error detection.
1886 */
1887 if (!p->error_mask)
1888 p->error_mask = (p->type == PORT_SCI) ?
1889 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1890
1891 /*
1892 * Establish sensible defaults for the overrun detection, unless
1893 * the part has explicitly disabled support for it.
1894 */
1895 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1896 if (p->type == PORT_SCI)
1897 p->overrun_bit = 5;
1898 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1899 p->overrun_bit = 9;
1900 else
1901 p->overrun_bit = 0;
1902
1903 /*
1904 * Make the error mask inclusive of overrun detection, if
1905 * supported.
1906 */
1907 p->error_mask |= (1 << p->overrun_bit);
1908 }
1909
ce6738b6 1910 sci_port->cfg = p;
7ed7e071 1911
ce6738b6
PM		 1912 port->mapbase = p->mapbase;
1913 port->type = p->type;
f43dc23d 1914 port->flags = p->flags;
61a6976b 1915 port->regshift = p->regshift;
73a19e4c 1916
ce6738b6 1917 /*
61a6976b 1918 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 1919 * for the multi-IRQ ports, which is where we are primarily
1920 * concerned with the shutdown path synchronization.
1921 *
1922 * For the muxed case there's nothing more to do.
1923 */
54aa89ea 1924 port->irq = p->irqs[SCIx_RXI_IRQ];
73a19e4c 1925
61a6976b
PM		 1926 port->serial_in = sci_serial_in;
1927 port->serial_out = sci_serial_out;
1928
ce6738b6
PM		 1929 if (p->dma_dev)
1930 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1931 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 1932
c7ed1ab3 1933 return 0;
e108b2ca
PM		 1934}
1935
1da177e4 1936#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1937static void serial_console_putchar(struct uart_port *port, int ch)
1938{
1939 sci_poll_put_char(port, ch);
1940}
1941
1da177e4
LT		 1942/*
1943 * Print a string to the serial port trying not to disturb
1944 * any possible real use of the port...
1945 */
1946static void serial_console_write(struct console *co, const char *s,
1947 unsigned count)
1948{
906b17dc
PM		 1949 struct sci_port *sci_port = &sci_ports[co->index];
1950 struct uart_port *port = &sci_port->port;
973e5d52 1951 unsigned short bits;
07d2a1a1 1952
501b825d
MD		 1953 if (sci_port->enable)
1954 sci_port->enable(port);
1955
1956 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1957
1958 /* wait until fifo is empty and last bit has been transmitted */
1959 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1960 while ((sci_in(port, SCxSR) & bits) != bits)
1961 cpu_relax();
501b825d 1962
345e5a76 1963 if (sci_port->disable)
501b825d 1964 sci_port->disable(port);
1da177e4
LT		 1965}
1966
7b6fd3bf 1967static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1968{
dc8e6f5b 1969 struct sci_port *sci_port;
1da177e4
LT		 1970 struct uart_port *port;
1971 int baud = 115200;
1972 int bits = 8;
1973 int parity = 'n';
1974 int flow = 'n';
1975 int ret;
1976
e108b2ca 1977 /*
906b17dc 1978 * Refuse to handle any bogus ports.
1da177e4 1979 */
906b17dc 1980 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 1981 return -ENODEV;
e108b2ca 1982
906b17dc
PM		 1983 sci_port = &sci_ports[co->index];
1984 port = &sci_port->port;
1985
b2267a6b
AC		 1986 /*
1987 * Refuse to handle uninitialized ports.
1988 */
1989 if (!port->ops)
1990 return -ENODEV;
1991
f6e9495d
PM		 1992 ret = sci_remap_port(port);
1993 if (unlikely(ret != 0))
1994 return ret;
e108b2ca 1995
dc8e6f5b
MD		 1996 if (sci_port->enable)
1997 sci_port->enable(port);
b7a76e4b 1998
1da177e4
LT		 1999 if (options)
2000 uart_parse_options(options, &baud, &parity, &bits, &flow);
2001
501b825d 2002 /* TODO: disable clock */
ab7cfb55 2003 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2004}
2005
2006static struct console serial_console = {
2007 .name = "ttySC",
906b17dc 2008 .device = uart_console_device,
1da177e4
LT		 2009 .write = serial_console_write,
2010 .setup = serial_console_setup,
fa5da2f7 2011 .flags = CON_PRINTBUFFER,
1da177e4 2012 .index = -1,
906b17dc 2013 .data = &sci_uart_driver,
1da177e4
LT		 2014};
2015
7b6fd3bf
MD		 2016static struct console early_serial_console = {
2017 .name = "early_ttySC",
2018 .write = serial_console_write,
2019 .flags = CON_PRINTBUFFER,
906b17dc 2020 .index = -1,
7b6fd3bf 2021};
ecdf8a46 2022
7b6fd3bf
MD		 2023static char early_serial_buf[32];
2024
ecdf8a46
PM		 2025static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2026{
2027 struct plat_sci_port *cfg = pdev->dev.platform_data;
2028
2029 if (early_serial_console.data)
2030 return -EEXIST;
2031
2032 early_serial_console.index = pdev->id;
ecdf8a46 2033
906b17dc 2034 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2035
2036 serial_console_setup(&early_serial_console, early_serial_buf);
2037
2038 if (!strstr(early_serial_buf, "keep"))
2039 early_serial_console.flags |= CON_BOOT;
2040
2041 register_console(&early_serial_console);
2042 return 0;
2043}
6a8c9799
NI		 2044
2045#define SCI_CONSOLE (&serial_console)
2046
ecdf8a46
PM		 2047#else
2048static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2049{
2050 return -EINVAL;
2051}
1da177e4 2052
6a8c9799
NI		 2053#define SCI_CONSOLE NULL
2054
2055#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2056
2057static char banner[] __initdata =
2058 KERN_INFO "SuperH SCI(F) driver initialized\n";
2059
2060static struct uart_driver sci_uart_driver = {
2061 .owner = THIS_MODULE,
2062 .driver_name = "sci",
1da177e4
LT		 2063 .dev_name = "ttySC",
2064 .major = SCI_MAJOR,
2065 .minor = SCI_MINOR_START,
e108b2ca 2066 .nr = SCI_NPORTS,
1da177e4
LT		 2067 .cons = SCI_CONSOLE,
2068};
2069
54507f6e 2070static int sci_remove(struct platform_device *dev)
e552de24 2071{
d535a230 2072 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2073
d535a230
PM		 2074 cpufreq_unregister_notifier(&port->freq_transition,
2075 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2076
d535a230
PM		 2077 uart_remove_one_port(&sci_uart_driver, &port->port);
2078
2079 clk_put(port->iclk);
2080 clk_put(port->fclk);
e552de24 2081
5e50d2d6 2082 pm_runtime_disable(&dev->dev);
e552de24
MD		 2083 return 0;
2084}
2085
0ee70712
MD		 2086static int __devinit sci_probe_single(struct platform_device *dev,
2087 unsigned int index,
2088 struct plat_sci_port *p,
2089 struct sci_port *sciport)
2090{
0ee70712
MD		 2091 int ret;
2092
2093 /* Sanity check */
2094 if (unlikely(index >= SCI_NPORTS)) {
2095 dev_notice(&dev->dev, "Attempting to register port "
2096 "%d when only %d are available.\n",
2097 index+1, SCI_NPORTS);
2098 dev_notice(&dev->dev, "Consider bumping "
2099 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2100 return 0;
2101 }
2102
c7ed1ab3
PM		 2103 ret = sci_init_single(dev, sciport, index, p);
2104 if (ret)
2105 return ret;
0ee70712 2106
d535a230 2107 return uart_add_one_port(&sci_uart_driver, &sciport->port);
0ee70712
MD		 2108}
2109
e108b2ca 2110static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2111{
e108b2ca 2112 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2113 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2114 int ret;
d535a230 2115
ecdf8a46
PM		 2116 /*
2117 * If we've come here via earlyprintk initialization, head off to
2118 * the special early probe. We don't have sufficient device state
2119 * to make it beyond this yet.
2120 */
2121 if (is_early_platform_device(dev))
2122 return sci_probe_earlyprintk(dev);
7b6fd3bf 2123
d535a230 2124 platform_set_drvdata(dev, sp);
e552de24 2125
906b17dc 2126 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230
PM		 2127 if (ret)
2128 goto err_unreg;
e552de24 2129
d535a230 2130 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2131
d535a230
PM		 2132 ret = cpufreq_register_notifier(&sp->freq_transition,
2133 CPUFREQ_TRANSITION_NOTIFIER);
2134 if (unlikely(ret < 0))
2135 goto err_unreg;
1da177e4
LT		 2136
2137#ifdef CONFIG_SH_STANDARD_BIOS
2138 sh_bios_gdb_detach();
2139#endif
2140
e108b2ca 2141 return 0;
7ff731ae
PM		 2142
2143err_unreg:
e552de24 2144 sci_remove(dev);
7ff731ae 2145 return ret;
1da177e4
LT		 2146}
2147
6daa79b3 2148static int sci_suspend(struct device *dev)
1da177e4 2149{
d535a230 2150 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2151
d535a230
PM		 2152 if (sport)
2153 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2154
e108b2ca
PM		 2155 return 0;
2156}
1da177e4 2157
6daa79b3 2158static int sci_resume(struct device *dev)
e108b2ca 2159{
d535a230 2160 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2161
d535a230
PM		 2162 if (sport)
2163 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2164
2165 return 0;
2166}
2167
47145210 2168static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2169 .suspend = sci_suspend,
2170 .resume = sci_resume,
2171};
2172
e108b2ca
PM		 2173static struct platform_driver sci_driver = {
2174 .probe = sci_probe,
b9e39c89 2175 .remove = sci_remove,
e108b2ca
PM		 2176 .driver = {
2177 .name = "sh-sci",
2178 .owner = THIS_MODULE,
6daa79b3 2179 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2180 },
2181};
2182
2183static int __init sci_init(void)
2184{
2185 int ret;
2186
2187 printk(banner);
2188
e108b2ca
PM		 2189 ret = uart_register_driver(&sci_uart_driver);
2190 if (likely(ret == 0)) {
2191 ret = platform_driver_register(&sci_driver);
2192 if (unlikely(ret))
2193 uart_unregister_driver(&sci_uart_driver);
2194 }
2195
2196 return ret;
2197}
2198
2199static void __exit sci_exit(void)
2200{
2201 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2202 uart_unregister_driver(&sci_uart_driver);
2203}
2204
7b6fd3bf
MD		 2205#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2206early_platform_init_buffer("earlyprintk", &sci_driver,
2207 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2208#endif
1da177e4
LT		 2209module_init(sci_init);
2210module_exit(sci_exit);
2211
e108b2ca 2212MODULE_LICENSE("GPL");
e169c139 2213MODULE_ALIAS("platform:sh-sci");
Linux kernel - Deliverables
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