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Linux 4.4-rc1
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
79904420
GU		 110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
73a19e4c 112 struct scatterlist sg_rx[2];
7b39d901 113 void *rx_buf[2];
73a19e4c 114 size_t buf_len_rx;
73a19e4c 115 struct work_struct work_tx;
73a19e4c 116 struct timer_list rx_timer;
3089f381 117 unsigned int rx_timeout;
73a19e4c 118#endif
e552de24 119
d535a230 120 struct notifier_block freq_transition;
e108b2ca
PM		 121};
122
e108b2ca 123#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 124
e108b2ca
PM		 125static struct sci_port sci_ports[SCI_NPORTS];
126static struct uart_driver sci_uart_driver;
1da177e4 127
e7c98dc7
MT		 128static inline struct sci_port *
129to_sci_port(struct uart_port *uart)
130{
131 return container_of(uart, struct sci_port, port);
132}
133
61a6976b
PM		 134struct plat_sci_reg {
135 u8 offset, size;
136};
137
138/* Helper for invalidating specific entries of an inherited map. */
139#define sci_reg_invalid { .offset = 0, .size = 0 }
140
d3184e68 141static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 142 [SCIx_PROBE_REGTYPE] = {
143 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
144 },
145
146 /*
147 * Common SCI definitions, dependent on the port's regshift
148 * value.
149 */
150 [SCIx_SCI_REGTYPE] = {
151 [SCSMR] = { 0x00, 8 },
152 [SCBRR] = { 0x01, 8 },
153 [SCSCR] = { 0x02, 8 },
154 [SCxTDR] = { 0x03, 8 },
155 [SCxSR] = { 0x04, 8 },
156 [SCxRDR] = { 0x05, 8 },
157 [SCFCR] = sci_reg_invalid,
158 [SCFDR] = sci_reg_invalid,
159 [SCTFDR] = sci_reg_invalid,
160 [SCRFDR] = sci_reg_invalid,
161 [SCSPTR] = sci_reg_invalid,
162 [SCLSR] = sci_reg_invalid,
f303b364 163 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 164 [SCPCR] = sci_reg_invalid,
165 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 166 },
167
168 /*
169 * Common definitions for legacy IrDA ports, dependent on
170 * regshift value.
171 */
172 [SCIx_IRDA_REGTYPE] = {
173 [SCSMR] = { 0x00, 8 },
174 [SCBRR] = { 0x01, 8 },
175 [SCSCR] = { 0x02, 8 },
176 [SCxTDR] = { 0x03, 8 },
177 [SCxSR] = { 0x04, 8 },
178 [SCxRDR] = { 0x05, 8 },
179 [SCFCR] = { 0x06, 8 },
180 [SCFDR] = { 0x07, 16 },
181 [SCTFDR] = sci_reg_invalid,
182 [SCRFDR] = sci_reg_invalid,
183 [SCSPTR] = sci_reg_invalid,
184 [SCLSR] = sci_reg_invalid,
f303b364 185 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 186 [SCPCR] = sci_reg_invalid,
187 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 188 },
189
190 /*
191 * Common SCIFA definitions.
192 */
193 [SCIx_SCIFA_REGTYPE] = {
194 [SCSMR] = { 0x00, 16 },
195 [SCBRR] = { 0x04, 8 },
196 [SCSCR] = { 0x08, 16 },
197 [SCxTDR] = { 0x20, 8 },
198 [SCxSR] = { 0x14, 16 },
199 [SCxRDR] = { 0x24, 8 },
200 [SCFCR] = { 0x18, 16 },
201 [SCFDR] = { 0x1c, 16 },
202 [SCTFDR] = sci_reg_invalid,
203 [SCRFDR] = sci_reg_invalid,
204 [SCSPTR] = sci_reg_invalid,
205 [SCLSR] = sci_reg_invalid,
f303b364 206 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 207 [SCPCR] = { 0x30, 16 },
208 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 209 },
210
211 /*
212 * Common SCIFB definitions.
213 */
214 [SCIx_SCIFB_REGTYPE] = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x40, 8 },
219 [SCxSR] = { 0x14, 16 },
220 [SCxRDR] = { 0x60, 8 },
221 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 222 [SCFDR] = sci_reg_invalid,
223 [SCTFDR] = { 0x38, 16 },
224 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 225 [SCSPTR] = sci_reg_invalid,
226 [SCLSR] = sci_reg_invalid,
f303b364 227 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 230 },
231
3af1f8a4
PE		 232 /*
233 * Common SH-2(A) SCIF definitions for ports with FIFO data
234 * count registers.
235 */
236 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
237 [SCSMR] = { 0x00, 16 },
238 [SCBRR] = { 0x04, 8 },
239 [SCSCR] = { 0x08, 16 },
240 [SCxTDR] = { 0x0c, 8 },
241 [SCxSR] = { 0x10, 16 },
242 [SCxRDR] = { 0x14, 8 },
243 [SCFCR] = { 0x18, 16 },
244 [SCFDR] = { 0x1c, 16 },
245 [SCTFDR] = sci_reg_invalid,
246 [SCRFDR] = sci_reg_invalid,
247 [SCSPTR] = { 0x20, 16 },
248 [SCLSR] = { 0x24, 16 },
f303b364 249 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 250 [SCPCR] = sci_reg_invalid,
251 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 252 },
253
61a6976b
PM		 254 /*
255 * Common SH-3 SCIF definitions.
256 */
257 [SCIx_SH3_SCIF_REGTYPE] = {
258 [SCSMR] = { 0x00, 8 },
259 [SCBRR] = { 0x02, 8 },
260 [SCSCR] = { 0x04, 8 },
261 [SCxTDR] = { 0x06, 8 },
262 [SCxSR] = { 0x08, 16 },
263 [SCxRDR] = { 0x0a, 8 },
264 [SCFCR] = { 0x0c, 8 },
265 [SCFDR] = { 0x0e, 16 },
266 [SCTFDR] = sci_reg_invalid,
267 [SCRFDR] = sci_reg_invalid,
268 [SCSPTR] = sci_reg_invalid,
269 [SCLSR] = sci_reg_invalid,
f303b364 270 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 271 [SCPCR] = sci_reg_invalid,
272 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 273 },
274
275 /*
276 * Common SH-4(A) SCIF(B) definitions.
277 */
278 [SCIx_SH4_SCIF_REGTYPE] = {
279 [SCSMR] = { 0x00, 16 },
280 [SCBRR] = { 0x04, 8 },
281 [SCSCR] = { 0x08, 16 },
282 [SCxTDR] = { 0x0c, 8 },
283 [SCxSR] = { 0x10, 16 },
284 [SCxRDR] = { 0x14, 8 },
285 [SCFCR] = { 0x18, 16 },
286 [SCFDR] = { 0x1c, 16 },
287 [SCTFDR] = sci_reg_invalid,
288 [SCRFDR] = sci_reg_invalid,
289 [SCSPTR] = { 0x20, 16 },
290 [SCLSR] = { 0x24, 16 },
f303b364 291 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 292 [SCPCR] = sci_reg_invalid,
293 [SCPDR] = sci_reg_invalid,
f303b364
UH		 294 },
295
296 /*
297 * Common HSCIF definitions.
298 */
299 [SCIx_HSCIF_REGTYPE] = {
300 [SCSMR] = { 0x00, 16 },
301 [SCBRR] = { 0x04, 8 },
302 [SCSCR] = { 0x08, 16 },
303 [SCxTDR] = { 0x0c, 8 },
304 [SCxSR] = { 0x10, 16 },
305 [SCxRDR] = { 0x14, 8 },
306 [SCFCR] = { 0x18, 16 },
307 [SCFDR] = { 0x1c, 16 },
308 [SCTFDR] = sci_reg_invalid,
309 [SCRFDR] = sci_reg_invalid,
310 [SCSPTR] = { 0x20, 16 },
311 [SCLSR] = { 0x24, 16 },
312 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 313 [SCPCR] = sci_reg_invalid,
314 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 315 },
316
317 /*
318 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
319 * register.
320 */
321 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
322 [SCSMR] = { 0x00, 16 },
323 [SCBRR] = { 0x04, 8 },
324 [SCSCR] = { 0x08, 16 },
325 [SCxTDR] = { 0x0c, 8 },
326 [SCxSR] = { 0x10, 16 },
327 [SCxRDR] = { 0x14, 8 },
328 [SCFCR] = { 0x18, 16 },
329 [SCFDR] = { 0x1c, 16 },
330 [SCTFDR] = sci_reg_invalid,
331 [SCRFDR] = sci_reg_invalid,
332 [SCSPTR] = sci_reg_invalid,
333 [SCLSR] = { 0x24, 16 },
f303b364 334 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 335 [SCPCR] = sci_reg_invalid,
336 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 337 },
338
339 /*
340 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
341 * count registers.
342 */
343 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
344 [SCSMR] = { 0x00, 16 },
345 [SCBRR] = { 0x04, 8 },
346 [SCSCR] = { 0x08, 16 },
347 [SCxTDR] = { 0x0c, 8 },
348 [SCxSR] = { 0x10, 16 },
349 [SCxRDR] = { 0x14, 8 },
350 [SCFCR] = { 0x18, 16 },
351 [SCFDR] = { 0x1c, 16 },
352 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
353 [SCRFDR] = { 0x20, 16 },
354 [SCSPTR] = { 0x24, 16 },
355 [SCLSR] = { 0x28, 16 },
f303b364 356 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 357 [SCPCR] = sci_reg_invalid,
358 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 359 },
360
361 /*
362 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
363 * registers.
364 */
365 [SCIx_SH7705_SCIF_REGTYPE] = {
366 [SCSMR] = { 0x00, 16 },
367 [SCBRR] = { 0x04, 8 },
368 [SCSCR] = { 0x08, 16 },
369 [SCxTDR] = { 0x20, 8 },
370 [SCxSR] = { 0x14, 16 },
371 [SCxRDR] = { 0x24, 8 },
372 [SCFCR] = { 0x18, 16 },
373 [SCFDR] = { 0x1c, 16 },
374 [SCTFDR] = sci_reg_invalid,
375 [SCRFDR] = sci_reg_invalid,
376 [SCSPTR] = sci_reg_invalid,
377 [SCLSR] = sci_reg_invalid,
f303b364 378 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 379 [SCPCR] = sci_reg_invalid,
380 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 381 },
382};
383
72b294cf
PM		 384#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
385
61a6976b
PM		 386/*
387 * The "offset" here is rather misleading, in that it refers to an enum
388 * value relative to the port mapping rather than the fixed offset
389 * itself, which needs to be manually retrieved from the platform's
390 * register map for the given port.
391 */
392static unsigned int sci_serial_in(struct uart_port *p, int offset)
393{
d3184e68 394 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 395
396 if (reg->size == 8)
397 return ioread8(p->membase + (reg->offset << p->regshift));
398 else if (reg->size == 16)
399 return ioread16(p->membase + (reg->offset << p->regshift));
400 else
401 WARN(1, "Invalid register access\n");
402
403 return 0;
404}
405
406static void sci_serial_out(struct uart_port *p, int offset, int value)
407{
d3184e68 408 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 409
410 if (reg->size == 8)
411 iowrite8(value, p->membase + (reg->offset << p->regshift));
412 else if (reg->size == 16)
413 iowrite16(value, p->membase + (reg->offset << p->regshift));
414 else
415 WARN(1, "Invalid register access\n");
416}
417
61a6976b
PM		 418static int sci_probe_regmap(struct plat_sci_port *cfg)
419{
420 switch (cfg->type) {
421 case PORT_SCI:
422 cfg->regtype = SCIx_SCI_REGTYPE;
423 break;
424 case PORT_IRDA:
425 cfg->regtype = SCIx_IRDA_REGTYPE;
426 break;
427 case PORT_SCIFA:
428 cfg->regtype = SCIx_SCIFA_REGTYPE;
429 break;
430 case PORT_SCIFB:
431 cfg->regtype = SCIx_SCIFB_REGTYPE;
432 break;
433 case PORT_SCIF:
434 /*
435 * The SH-4 is a bit of a misnomer here, although that's
436 * where this particular port layout originated. This
437 * configuration (or some slight variation thereof)
438 * remains the dominant model for all SCIFs.
439 */
440 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
441 break;
f303b364
UH		 442 case PORT_HSCIF:
443 cfg->regtype = SCIx_HSCIF_REGTYPE;
444 break;
61a6976b 445 default:
6c13d5d2 446 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 447 return -EINVAL;
448 }
449
450 return 0;
451}
452
23241d43
PM		 453static void sci_port_enable(struct sci_port *sci_port)
454{
455 if (!sci_port->port.dev)
456 return;
457
458 pm_runtime_get_sync(sci_port->port.dev);
459
b016b646 460 clk_prepare_enable(sci_port->iclk);
23241d43 461 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 462 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 463}
464
465static void sci_port_disable(struct sci_port *sci_port)
466{
467 if (!sci_port->port.dev)
468 return;
469
caec7038
LP		 470 /* Cancel the break timer to ensure that the timer handler will not try
471 * to access the hardware with clocks and power disabled. Reset the
472 * break flag to make the break debouncing state machine ready for the
473 * next break.
474 */
475 del_timer_sync(&sci_port->break_timer);
476 sci_port->break_flag = 0;
477
b016b646
LP		 478 clk_disable_unprepare(sci_port->fclk);
479 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 480
481 pm_runtime_put_sync(sci_port->port.dev);
482}
483
e1910fcd
GU		 484static inline unsigned long port_rx_irq_mask(struct uart_port *port)
485{
486 /*
487 * Not all ports (such as SCIFA) will support REIE. Rather than
488 * special-casing the port type, we check the port initialization
489 * IRQ enable mask to see whether the IRQ is desired at all. If
490 * it's unset, it's logically inferred that there's no point in
491 * testing for it.
492 */
493 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
494}
495
496static void sci_start_tx(struct uart_port *port)
497{
498 struct sci_port *s = to_sci_port(port);
499 unsigned short ctrl;
500
501#ifdef CONFIG_SERIAL_SH_SCI_DMA
502 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
503 u16 new, scr = serial_port_in(port, SCSCR);
504 if (s->chan_tx)
505 new = scr | SCSCR_TDRQE;
506 else
507 new = scr & ~SCSCR_TDRQE;
508 if (new != scr)
509 serial_port_out(port, SCSCR, new);
510 }
511
512 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
513 dma_submit_error(s->cookie_tx)) {
514 s->cookie_tx = 0;
515 schedule_work(&s->work_tx);
516 }
517#endif
518
519 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
520 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
521 ctrl = serial_port_in(port, SCSCR);
522 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
523 }
524}
525
526static void sci_stop_tx(struct uart_port *port)
527{
528 unsigned short ctrl;
529
530 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
531 ctrl = serial_port_in(port, SCSCR);
532
533 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
534 ctrl &= ~SCSCR_TDRQE;
535
536 ctrl &= ~SCSCR_TIE;
537
538 serial_port_out(port, SCSCR, ctrl);
539}
540
541static void sci_start_rx(struct uart_port *port)
542{
543 unsigned short ctrl;
544
545 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
546
547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
548 ctrl &= ~SCSCR_RDRQE;
549
550 serial_port_out(port, SCSCR, ctrl);
551}
552
553static void sci_stop_rx(struct uart_port *port)
554{
555 unsigned short ctrl;
556
557 ctrl = serial_port_in(port, SCSCR);
558
559 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
560 ctrl &= ~SCSCR_RDRQE;
561
562 ctrl &= ~port_rx_irq_mask(port);
563
564 serial_port_out(port, SCSCR, ctrl);
565}
566
a1b5b43f
GU		 567static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
568{
569 if (port->type == PORT_SCI) {
570 /* Just store the mask */
571 serial_port_out(port, SCxSR, mask);
572 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
573 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
574 /* Only clear the status bits we want to clear */
575 serial_port_out(port, SCxSR,
576 serial_port_in(port, SCxSR) & mask);
577 } else {
578 /* Store the mask, clear parity/framing errors */
579 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
580 }
581}
582
07d2a1a1 583#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 584
585#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 586static int sci_poll_get_char(struct uart_port *port)
1da177e4 587{
1da177e4
LT		 588 unsigned short status;
589 int c;
590
e108b2ca 591 do {
b12bb29f 592 status = serial_port_in(port, SCxSR);
1da177e4 593 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 594 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 595 continue;
596 }
3f255eb3
JW		 597 break;
598 } while (1);
599
600 if (!(status & SCxSR_RDxF(port)))
601 return NO_POLL_CHAR;
07d2a1a1 602
b12bb29f 603 c = serial_port_in(port, SCxRDR);
07d2a1a1 604
e7c98dc7 605 /* Dummy read */
b12bb29f 606 serial_port_in(port, SCxSR);
a1b5b43f 607 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 608
609 return c;
610}
1f6fd5c9 611#endif
1da177e4 612
07d2a1a1 613static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 614{
1da177e4
LT		 615 unsigned short status;
616
1da177e4 617 do {
b12bb29f 618 status = serial_port_in(port, SCxSR);
1da177e4
LT		 619 } while (!(status & SCxSR_TDxE(port)));
620
b12bb29f 621 serial_port_out(port, SCxTDR, c);
a1b5b43f 622 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 623}
07d2a1a1 624#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 625
61a6976b 626static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 627{
61a6976b 628 struct sci_port *s = to_sci_port(port);
d3184e68 629 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 630
61a6976b
PM		 631 /*
632 * Use port-specific handler if provided.
633 */
634 if (s->cfg->ops && s->cfg->ops->init_pins) {
635 s->cfg->ops->init_pins(port, cflag);
636 return;
1da177e4 637 }
41504c39 638
61a6976b
PM		 639 /*
640 * For the generic path SCSPTR is necessary. Bail out if that's
641 * unavailable, too.
642 */
643 if (!reg->size)
644 return;
41504c39 645
faf02f8f
PM		 646 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
647 ((!(cflag & CRTSCTS)))) {
648 unsigned short status;
649
b12bb29f 650 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 651 status &= ~SCSPTR_CTSIO;
652 status |= SCSPTR_RTSIO;
b12bb29f 653 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 654 }
d5701647 655}
e108b2ca 656
72b294cf 657static int sci_txfill(struct uart_port *port)
e108b2ca 658{
d3184e68 659 const struct plat_sci_reg *reg;
e108b2ca 660
72b294cf
PM		 661 reg = sci_getreg(port, SCTFDR);
662 if (reg->size)
63f7ad11 663 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 664
72b294cf
PM		 665 reg = sci_getreg(port, SCFDR);
666 if (reg->size)
b12bb29f 667 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 668
b12bb29f 669 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 670}
671
73a19e4c
GL		 672static int sci_txroom(struct uart_port *port)
673{
72b294cf 674 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 675}
676
677static int sci_rxfill(struct uart_port *port)
e108b2ca 678{
d3184e68 679 const struct plat_sci_reg *reg;
72b294cf
PM		 680
681 reg = sci_getreg(port, SCRFDR);
682 if (reg->size)
63f7ad11 683 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 684
685 reg = sci_getreg(port, SCFDR);
686 if (reg->size)
b12bb29f 687 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 688
b12bb29f 689 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 690}
691
514820eb
PM		 692/*
693 * SCI helper for checking the state of the muxed port/RXD pins.
694 */
695static inline int sci_rxd_in(struct uart_port *port)
696{
697 struct sci_port *s = to_sci_port(port);
698
699 if (s->cfg->port_reg <= 0)
700 return 1;
701
0dd4d5cb 702 /* Cast for ARM damage */
e2afca69 703 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 704}
705
1da177e4
LT		 706/* ********************************************************************** *
707 * the interrupt related routines *
708 * ********************************************************************** */
709
710static void sci_transmit_chars(struct uart_port *port)
711{
ebd2c8f6 712 struct circ_buf *xmit = &port->state->xmit;
1da177e4 713 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 714 unsigned short status;
715 unsigned short ctrl;
e108b2ca 716 int count;
1da177e4 717
b12bb29f 718 status = serial_port_in(port, SCxSR);
1da177e4 719 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 720 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 721 if (uart_circ_empty(xmit))
8e698614 722 ctrl &= ~SCSCR_TIE;
e7c98dc7 723 else
8e698614 724 ctrl |= SCSCR_TIE;
b12bb29f 725 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 726 return;
727 }
728
72b294cf 729 count = sci_txroom(port);
1da177e4
LT		 730
731 do {
732 unsigned char c;
733
734 if (port->x_char) {
735 c = port->x_char;
736 port->x_char = 0;
737 } else if (!uart_circ_empty(xmit) && !stopped) {
738 c = xmit->buf[xmit->tail];
739 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
740 } else {
741 break;
742 }
743
b12bb29f 744 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 745
746 port->icount.tx++;
747 } while (--count > 0);
748
a1b5b43f 749 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 750
751 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
752 uart_write_wakeup(port);
753 if (uart_circ_empty(xmit)) {
b129a8cc 754 sci_stop_tx(port);
1da177e4 755 } else {
b12bb29f 756 ctrl = serial_port_in(port, SCSCR);
1da177e4 757
1a22f08d 758 if (port->type != PORT_SCI) {
b12bb29f 759 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 760 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 761 }
1da177e4 762
8e698614 763 ctrl |= SCSCR_TIE;
b12bb29f 764 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 765 }
766}
767
768/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 769#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 770
94c8b6db 771static void sci_receive_chars(struct uart_port *port)
1da177e4 772{
e7c98dc7 773 struct sci_port *sci_port = to_sci_port(port);
227434f8 774 struct tty_port *tport = &port->state->port;
1da177e4
LT		 775 int i, count, copied = 0;
776 unsigned short status;
33f0f88f 777 unsigned char flag;
1da177e4 778
b12bb29f 779 status = serial_port_in(port, SCxSR);
1da177e4
LT		 780 if (!(status & SCxSR_RDxF(port)))
781 return;
782
783 while (1) {
1da177e4 784 /* Don't copy more bytes than there is room for in the buffer */
227434f8 785 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 786
787 /* If for any reason we can't copy more data, we're done! */
788 if (count == 0)
789 break;
790
791 if (port->type == PORT_SCI) {
b12bb29f 792 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 793 if (uart_handle_sysrq_char(port, c) ||
794 sci_port->break_flag)
1da177e4 795 count = 0;
e7c98dc7 796 else
92a19f9c 797 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 798 } else {
e7c98dc7 799 for (i = 0; i < count; i++) {
b12bb29f 800 char c = serial_port_in(port, SCxRDR);
d97fbbed 801
b12bb29f 802 status = serial_port_in(port, SCxSR);
1da177e4
LT		 803#if defined(CONFIG_CPU_SH3)
804 /* Skip "chars" during break */
e108b2ca 805 if (sci_port->break_flag) {
1da177e4
LT		 806 if ((c == 0) &&
807 (status & SCxSR_FER(port))) {
808 count--; i--;
809 continue;
810 }
e108b2ca 811
1da177e4 812 /* Nonzero => end-of-break */
762c69e3 813 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 814 sci_port->break_flag = 0;
815
1da177e4
LT		 816 if (STEPFN(c)) {
817 count--; i--;
818 continue;
819 }
820 }
821#endif /* CONFIG_CPU_SH3 */
7d12e780 822 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 823 count--; i--;
824 continue;
825 }
826
827 /* Store data and status */
73a19e4c 828 if (status & SCxSR_FER(port)) {
33f0f88f 829 flag = TTY_FRAME;
d97fbbed 830 port->icount.frame++;
762c69e3 831 dev_notice(port->dev, "frame error\n");
73a19e4c 832 } else if (status & SCxSR_PER(port)) {
33f0f88f 833 flag = TTY_PARITY;
d97fbbed 834 port->icount.parity++;
762c69e3 835 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 836 } else
837 flag = TTY_NORMAL;
762c69e3 838
92a19f9c 839 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 840 }
841 }
842
b12bb29f 843 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 844 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 845
1da177e4
LT		 846 copied += count;
847 port->icount.rx += count;
848 }
849
850 if (copied) {
851 /* Tell the rest of the system the news. New characters! */
2e124b4a 852 tty_flip_buffer_push(tport);
1da177e4 853 } else {
b12bb29f 854 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 855 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 856 }
857}
858
859#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 860
861/*
862 * The sci generates interrupts during the break,
1da177e4
LT		 863 * 1 per millisecond or so during the break period, for 9600 baud.
864 * So dont bother disabling interrupts.
865 * But dont want more than 1 break event.
866 * Use a kernel timer to periodically poll the rx line until
867 * the break is finished.
868 */
94c8b6db 869static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 870{
bc9b3f5c 871 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 872}
94c8b6db 873
1da177e4
LT		 874/* Ensure that two consecutive samples find the break over. */
875static void sci_break_timer(unsigned long data)
876{
e108b2ca
PM		 877 struct sci_port *port = (struct sci_port *)data;
878
879 if (sci_rxd_in(&port->port) == 0) {
1da177e4 880 port->break_flag = 1;
e108b2ca
PM		 881 sci_schedule_break_timer(port);
882 } else if (port->break_flag == 1) {
1da177e4
LT		 883 /* break is over. */
884 port->break_flag = 2;
e108b2ca
PM		 885 sci_schedule_break_timer(port);
886 } else
887 port->break_flag = 0;
1da177e4
LT		 888}
889
94c8b6db 890static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 891{
892 int copied = 0;
b12bb29f 893 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 894 struct tty_port *tport = &port->state->port;
debf9507 895 struct sci_port *s = to_sci_port(port);
1da177e4 896
3ae988d9 897 /* Handle overruns */
75c249fd 898 if (status & s->overrun_mask) {
3ae988d9 899 port->icount.overrun++;
d97fbbed 900
3ae988d9
LP		 901 /* overrun error */
902 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
903 copied++;
762c69e3 904
9b971cd2 905 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 906 }
907
e108b2ca 908 if (status & SCxSR_FER(port)) {
1da177e4
LT		 909 if (sci_rxd_in(port) == 0) {
910 /* Notify of BREAK */
e7c98dc7 911 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 912
913 if (!sci_port->break_flag) {
d97fbbed
PM		 914 port->icount.brk++;
915
e108b2ca
PM		 916 sci_port->break_flag = 1;
917 sci_schedule_break_timer(sci_port);
918
1da177e4 919 /* Do sysrq handling. */
e108b2ca 920 if (uart_handle_break(port))
1da177e4 921 return 0;
762c69e3
PM		 922
923 dev_dbg(port->dev, "BREAK detected\n");
924
92a19f9c 925 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 926 copied++;
927 }
928
e108b2ca 929 } else {
1da177e4 930 /* frame error */
d97fbbed
PM		 931 port->icount.frame++;
932
92a19f9c 933 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 934 copied++;
762c69e3
PM		 935
936 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 937 }
938 }
939
e108b2ca 940 if (status & SCxSR_PER(port)) {
1da177e4 941 /* parity error */
d97fbbed
PM		 942 port->icount.parity++;
943
92a19f9c 944 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 945 copied++;
762c69e3 946
9b971cd2 947 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 948 }
949
33f0f88f 950 if (copied)
2e124b4a 951 tty_flip_buffer_push(tport);
1da177e4
LT		 952
953 return copied;
954}
955
94c8b6db 956static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 957{
92a19f9c 958 struct tty_port *tport = &port->state->port;
debf9507 959 struct sci_port *s = to_sci_port(port);
d3184e68 960 const struct plat_sci_reg *reg;
2e0842a1 961 int copied = 0;
75c249fd 962 u16 status;
d830fa45 963
2e0842a1 964 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 965 if (!reg->size)
d830fa45
PM		 966 return 0;
967
2e0842a1 968 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 969 if (status & s->overrun_mask) {
970 status &= ~s->overrun_mask;
2e0842a1 971 serial_port_out(port, s->overrun_reg, status);
d830fa45 972
d97fbbed
PM		 973 port->icount.overrun++;
974
92a19f9c 975 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 976 tty_flip_buffer_push(tport);
d830fa45 977
51b31f1c 978 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 979 copied++;
980 }
981
982 return copied;
983}
984
94c8b6db 985static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 986{
987 int copied = 0;
b12bb29f 988 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 989 struct tty_port *tport = &port->state->port;
a5660ada 990 struct sci_port *s = to_sci_port(port);
1da177e4 991
0b3d4ef6
PM		 992 if (uart_handle_break(port))
993 return 0;
994
b7a76e4b 995 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 996#if defined(CONFIG_CPU_SH3)
997 /* Debounce break */
998 s->break_flag = 1;
999#endif
d97fbbed
PM		 1000
1001 port->icount.brk++;
1002
1da177e4 1003 /* Notify of BREAK */
92a19f9c 1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1005 copied++;
762c69e3
PM		 1006
1007 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1008 }
1009
33f0f88f 1010 if (copied)
2e124b4a 1011 tty_flip_buffer_push(tport);
e108b2ca 1012
d830fa45
PM		 1013 copied += sci_handle_fifo_overrun(port);
1014
1da177e4
LT		 1015 return copied;
1016}
1017
73a19e4c 1018#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1019static void sci_dma_tx_complete(void *arg)
1020{
1021 struct sci_port *s = arg;
1022 struct uart_port *port = &s->port;
1023 struct circ_buf *xmit = &port->state->xmit;
1024 unsigned long flags;
73a19e4c 1025
e1910fcd 1026 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1027
e1910fcd 1028 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1029
e1910fcd
GU		 1030 xmit->tail += s->tx_dma_len;
1031 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1032
e1910fcd 1033 port->icount.tx += s->tx_dma_len;
1da177e4 1034
e1910fcd
GU		 1035 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1036 uart_write_wakeup(port);
1da177e4 1037
e1910fcd
GU		 1038 if (!uart_circ_empty(xmit)) {
1039 s->cookie_tx = 0;
1040 schedule_work(&s->work_tx);
1041 } else {
1042 s->cookie_tx = -EINVAL;
1043 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1044 u16 ctrl = serial_port_in(port, SCSCR);
1045 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1046 }
1047 }
1da177e4 1048
fd78a76a 1049 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1050}
1051
e1910fcd
GU		 1052/* Locking: called with port lock held */
1053static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1054{
e1910fcd
GU		 1055 struct uart_port *port = &s->port;
1056 struct tty_port *tport = &port->state->port;
1057 int copied;
1da177e4 1058
e1910fcd
GU		 1059 copied = tty_insert_flip_string(tport, buf, count);
1060 if (copied < count) {
1061 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1062 count - copied);
1063 port->icount.buf_overrun++;
1da177e4
LT		 1064 }
1065
e1910fcd 1066 port->icount.rx += copied;
1da177e4 1067
e1910fcd 1068 return copied;
1da177e4
LT		 1069}
1070
e1910fcd 1071static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1072{
e1910fcd 1073 unsigned int i;
1da177e4 1074
e1910fcd
GU		 1075 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1076 if (s->active_rx == s->cookie_rx[i])
1077 return i;
1da177e4 1078
e1910fcd
GU		 1079 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1080 s->active_rx);
1081 return -1;
1da177e4
LT		 1082}
1083
e1910fcd 1084static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1085{
e1910fcd
GU		 1086 struct dma_chan *chan = s->chan_rx;
1087 struct uart_port *port = &s->port;
1088 unsigned long flags;
1089
1090 spin_lock_irqsave(&port->lock, flags);
1091 s->chan_rx = NULL;
1092 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1093 spin_unlock_irqrestore(&port->lock, flags);
1094 dmaengine_terminate_all(chan);
1095 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1096 sg_dma_address(&s->sg_rx[0]));
1097 dma_release_channel(chan);
1098 if (enable_pio)
1099 sci_start_rx(port);
f43dc23d
PM		 1100}
1101
e1910fcd 1102static void sci_dma_rx_complete(void *arg)
1da177e4 1103{
e1910fcd 1104 struct sci_port *s = arg;
1d3db608 1105 struct dma_chan *chan = s->chan_rx;
e1910fcd 1106 struct uart_port *port = &s->port;
67f462b0 1107 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1108 unsigned long flags;
1109 int active, count = 0;
1da177e4 1110
e1910fcd
GU		 1111 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1112 s->active_rx);
cb772fe7 1113
e1910fcd 1114 spin_lock_irqsave(&port->lock, flags);
1da177e4 1115
e1910fcd
GU		 1116 active = sci_dma_rx_find_active(s);
1117 if (active >= 0)
1118 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1119
e1910fcd 1120 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1121
e1910fcd
GU		 1122 if (count)
1123 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1124
67f462b0
GU		 1125 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1126 DMA_DEV_TO_MEM,
1127 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1128 if (!desc)
1129 goto fail;
1130
1131 desc->callback = sci_dma_rx_complete;
1132 desc->callback_param = s;
1133 s->cookie_rx[active] = dmaengine_submit(desc);
1134 if (dma_submit_error(s->cookie_rx[active]))
1135 goto fail;
1136
1137 s->active_rx = s->cookie_rx[!active];
1138
1d3db608
MHF		 1139 dma_async_issue_pending(chan);
1140
67f462b0
GU		 1141 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1142 __func__, s->cookie_rx[active], active, s->active_rx);
1143 spin_unlock_irqrestore(&port->lock, flags);
1144 return;
1145
1146fail:
1147 spin_unlock_irqrestore(&port->lock, flags);
1148 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1149 sci_rx_dma_release(s, true);
1da177e4
LT		 1150}
1151
e1910fcd 1152static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1153{
e1910fcd
GU		 1154 struct dma_chan *chan = s->chan_tx;
1155 struct uart_port *port = &s->port;
e552de24 1156 unsigned long flags;
1da177e4 1157
e1910fcd
GU		 1158 spin_lock_irqsave(&port->lock, flags);
1159 s->chan_tx = NULL;
1160 s->cookie_tx = -EINVAL;
1161 spin_unlock_irqrestore(&port->lock, flags);
1162 dmaengine_terminate_all(chan);
1163 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1164 DMA_TO_DEVICE);
1165 dma_release_channel(chan);
1166 if (enable_pio)
1167 sci_start_tx(port);
1168}
d535a230 1169
e1910fcd
GU		 1170static void sci_submit_rx(struct sci_port *s)
1171{
1172 struct dma_chan *chan = s->chan_rx;
1173 int i;
073e84c9 1174
e1910fcd
GU		 1175 for (i = 0; i < 2; i++) {
1176 struct scatterlist *sg = &s->sg_rx[i];
1177 struct dma_async_tx_descriptor *desc;
1da177e4 1178
e1910fcd
GU		 1179 desc = dmaengine_prep_slave_sg(chan,
1180 sg, 1, DMA_DEV_TO_MEM,
1181 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1182 if (!desc)
1183 goto fail;
501b825d 1184
e1910fcd
GU		 1185 desc->callback = sci_dma_rx_complete;
1186 desc->callback_param = s;
1187 s->cookie_rx[i] = dmaengine_submit(desc);
1188 if (dma_submit_error(s->cookie_rx[i]))
1189 goto fail;
9174fc8f 1190
e1910fcd
GU		 1191 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1192 s->cookie_rx[i], i);
1193 }
9174fc8f 1194
e1910fcd 1195 s->active_rx = s->cookie_rx[0];
9174fc8f 1196
e1910fcd
GU		 1197 dma_async_issue_pending(chan);
1198 return;
9174fc8f 1199
e1910fcd
GU		 1200fail:
1201 if (i)
1202 dmaengine_terminate_all(chan);
1203 for (i = 0; i < 2; i++)
1204 s->cookie_rx[i] = -EINVAL;
1205 s->active_rx = -EINVAL;
1206 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1207 sci_rx_dma_release(s, true);
1208}
9174fc8f 1209
e1910fcd 1210static void work_fn_tx(struct work_struct *work)
1da177e4 1211{
e1910fcd
GU		 1212 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1213 struct dma_async_tx_descriptor *desc;
1214 struct dma_chan *chan = s->chan_tx;
1215 struct uart_port *port = &s->port;
1216 struct circ_buf *xmit = &port->state->xmit;
1217 dma_addr_t buf;
1da177e4 1218
9174fc8f 1219 /*
e1910fcd
GU		 1220 * DMA is idle now.
1221 * Port xmit buffer is already mapped, and it is one page... Just adjust
1222 * offsets and lengths. Since it is a circular buffer, we have to
1223 * transmit till the end, and then the rest. Take the port lock to get a
1224 * consistent xmit buffer state.
9174fc8f 1225 */
e1910fcd
GU		 1226 spin_lock_irq(&port->lock);
1227 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1228 s->tx_dma_len = min_t(unsigned int,
1229 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1230 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1231 spin_unlock_irq(&port->lock);
0e8963de 1232
e1910fcd
GU		 1233 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1234 DMA_MEM_TO_DEV,
1235 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1236 if (!desc) {
1237 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1238 /* switch to PIO */
1239 sci_tx_dma_release(s, true);
1240 return;
1241 }
0e8963de 1242
e1910fcd
GU		 1243 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1244 DMA_TO_DEVICE);
1da177e4 1245
e1910fcd
GU		 1246 spin_lock_irq(&port->lock);
1247 desc->callback = sci_dma_tx_complete;
1248 desc->callback_param = s;
1249 spin_unlock_irq(&port->lock);
1250 s->cookie_tx = dmaengine_submit(desc);
1251 if (dma_submit_error(s->cookie_tx)) {
1252 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1253 /* switch to PIO */
1254 sci_tx_dma_release(s, true);
1255 return;
1da177e4 1256 }
1da177e4 1257
e1910fcd
GU		 1258 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1259 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1260
e1910fcd 1261 dma_async_issue_pending(chan);
1da177e4
LT		 1262}
1263
e1910fcd 1264static void rx_timer_fn(unsigned long arg)
1da177e4 1265{
e1910fcd 1266 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1267 struct dma_chan *chan = s->chan_rx;
e1910fcd 1268 struct uart_port *port = &s->port;
67f462b0
GU		 1269 struct dma_tx_state state;
1270 enum dma_status status;
1271 unsigned long flags;
1272 unsigned int read;
1273 int active, count;
1274 u16 scr;
1275
1276 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1277
67f462b0 1278 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0
GU		 1279
1280 active = sci_dma_rx_find_active(s);
1281 if (active < 0) {
1282 spin_unlock_irqrestore(&port->lock, flags);
1283 return;
1284 }
1285
1286 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1287 if (status == DMA_COMPLETE) {
67f462b0
GU		 1288 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1289 s->active_rx, active);
3b963042
MHF		 1290 spin_unlock_irqrestore(&port->lock, flags);
1291
1292 /* Let packet complete handler take care of the packet */
1293 return;
1294 }
67f462b0 1295
e7327c09
MHF		 1296 dmaengine_pause(chan);
1297
1298 /*
1299 * sometimes DMA transfer doesn't stop even if it is stopped and
1300 * data keeps on coming until transaction is complete so check
1301 * for DMA_COMPLETE again
1302 * Let packet complete handler take care of the packet
1303 */
1304 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1305 if (status == DMA_COMPLETE) {
1306 spin_unlock_irqrestore(&port->lock, flags);
1307 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1308 return;
1309 }
1310
67f462b0
GU		 1311 /* Handle incomplete DMA receive */
1312 dmaengine_terminate_all(s->chan_rx);
1313 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1314 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1315 s->active_rx);
1316
1317 if (read) {
1318 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1319 if (count)
1320 tty_flip_buffer_push(&port->state->port);
1321 }
1322
756981be
GU		 1323 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1324 sci_submit_rx(s);
371cfed3
MHF		 1325
1326 /* Direct new serial port interrupts back to CPU */
1327 scr = serial_port_in(port, SCSCR);
1328 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1329 scr &= ~SCSCR_RDRQE;
1330 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1331 }
1332 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1333
1334 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1335}
1336
ff441129
GU		 1337static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1338 enum dma_transfer_direction dir,
1339 unsigned int id)
1340{
1341 dma_cap_mask_t mask;
1342 struct dma_chan *chan;
1343 struct dma_slave_config cfg;
1344 int ret;
1345
1346 dma_cap_zero(mask);
1347 dma_cap_set(DMA_SLAVE, mask);
1348
1349 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1350 (void *)(unsigned long)id, port->dev,
1351 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1352 if (!chan) {
1353 dev_warn(port->dev,
1354 "dma_request_slave_channel_compat failed\n");
1355 return NULL;
1356 }
1357
1358 memset(&cfg, 0, sizeof(cfg));
1359 cfg.direction = dir;
1360 if (dir == DMA_MEM_TO_DEV) {
1361 cfg.dst_addr = port->mapbase +
1362 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1363 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1364 } else {
1365 cfg.src_addr = port->mapbase +
1366 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1367 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1368 }
1369
1370 ret = dmaengine_slave_config(chan, &cfg);
1371 if (ret) {
1372 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1373 dma_release_channel(chan);
1374 return NULL;
1375 }
1376
1377 return chan;
1378}
1379
e1910fcd 1380static void sci_request_dma(struct uart_port *port)
73a19e4c 1381{
e1910fcd 1382 struct sci_port *s = to_sci_port(port);
e1910fcd 1383 struct dma_chan *chan;
73a19e4c 1384
e1910fcd 1385 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1386
ff441129
GU		 1387 if (!port->dev->of_node &&
1388 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
e1910fcd 1389 return;
73a19e4c 1390
e1910fcd 1391 s->cookie_tx = -EINVAL;
ff441129 1392 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
e1910fcd
GU		 1393 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1394 if (chan) {
1395 s->chan_tx = chan;
1396 /* UART circular tx buffer is an aligned page. */
1397 s->tx_dma_addr = dma_map_single(chan->device->dev,
1398 port->state->xmit.buf,
1399 UART_XMIT_SIZE,
1400 DMA_TO_DEVICE);
1401 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1402 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1403 dma_release_channel(chan);
1404 s->chan_tx = NULL;
1405 } else {
1406 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1407 __func__, UART_XMIT_SIZE,
1408 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1409 }
e1910fcd
GU		 1410
1411 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1412 }
1413
ff441129 1414 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
e1910fcd
GU		 1415 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1416 if (chan) {
1417 unsigned int i;
1418 dma_addr_t dma;
1419 void *buf;
73a19e4c 1420
e1910fcd 1421 s->chan_rx = chan;
73a19e4c 1422
e1910fcd
GU		 1423 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1424 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1425 &dma, GFP_KERNEL);
1426 if (!buf) {
1427 dev_warn(port->dev,
1428 "Failed to allocate Rx dma buffer, using PIO\n");
1429 dma_release_channel(chan);
1430 s->chan_rx = NULL;
e1910fcd
GU		 1431 return;
1432 }
73a19e4c 1433
e1910fcd
GU		 1434 for (i = 0; i < 2; i++) {
1435 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1436
e1910fcd
GU		 1437 sg_init_table(sg, 1);
1438 s->rx_buf[i] = buf;
1439 sg_dma_address(sg) = dma;
1440 sg->length = s->buf_len_rx;
0533502d 1441
e1910fcd
GU		 1442 buf += s->buf_len_rx;
1443 dma += s->buf_len_rx;
1444 }
1445
e1910fcd
GU		 1446 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1447
756981be
GU		 1448 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1449 sci_submit_rx(s);
e1910fcd 1450 }
0533502d
GU		 1451}
1452
e1910fcd 1453static void sci_free_dma(struct uart_port *port)
73a19e4c 1454{
e1910fcd 1455 struct sci_port *s = to_sci_port(port);
73a19e4c 1456
e1910fcd
GU		 1457 if (s->chan_tx)
1458 sci_tx_dma_release(s, false);
1459 if (s->chan_rx)
1460 sci_rx_dma_release(s, false);
1461}
1462#else
1463static inline void sci_request_dma(struct uart_port *port)
1464{
1465}
73a19e4c 1466
e1910fcd
GU		 1467static inline void sci_free_dma(struct uart_port *port)
1468{
1469}
1470#endif
73a19e4c 1471
e1910fcd
GU		 1472static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1473{
1474#ifdef CONFIG_SERIAL_SH_SCI_DMA
1475 struct uart_port *port = ptr;
1476 struct sci_port *s = to_sci_port(port);
73a19e4c 1477
e1910fcd
GU		 1478 if (s->chan_rx) {
1479 u16 scr = serial_port_in(port, SCSCR);
1480 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1481
e1910fcd
GU		 1482 /* Disable future Rx interrupts */
1483 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1484 disable_irq_nosync(irq);
1485 scr |= SCSCR_RDRQE;
1486 } else {
1487 scr &= ~SCSCR_RIE;
756981be 1488 sci_submit_rx(s);
e1910fcd
GU		 1489 }
1490 serial_port_out(port, SCSCR, scr);
1491 /* Clear current interrupt */
1492 serial_port_out(port, SCxSR,
1493 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1494 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1495 jiffies, s->rx_timeout);
1496 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1497
e1910fcd
GU		 1498 return IRQ_HANDLED;
1499 }
1500#endif
73a19e4c 1501
e1910fcd
GU		 1502 /* I think sci_receive_chars has to be called irrespective
1503 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1504 * to be disabled?
1505 */
1506 sci_receive_chars(ptr);
1507
1508 return IRQ_HANDLED;
73a19e4c
GL		 1509}
1510
e1910fcd 1511static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1512{
e1910fcd 1513 struct uart_port *port = ptr;
04928b79 1514 unsigned long flags;
73a19e4c 1515
04928b79 1516 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1517 sci_transmit_chars(port);
04928b79 1518 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1519
1520 return IRQ_HANDLED;
73a19e4c
GL		 1521}
1522
e1910fcd 1523static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1524{
e1910fcd
GU		 1525 struct uart_port *port = ptr;
1526 struct sci_port *s = to_sci_port(port);
73a19e4c 1527
e1910fcd
GU		 1528 /* Handle errors */
1529 if (port->type == PORT_SCI) {
1530 if (sci_handle_errors(port)) {
1531 /* discard character in rx buffer */
1532 serial_port_in(port, SCxSR);
1533 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1534 }
1535 } else {
1536 sci_handle_fifo_overrun(port);
1537 if (!s->chan_rx)
1538 sci_receive_chars(ptr);
1539 }
1540
1541 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1542
1543 /* Kick the transmission */
1544 if (!s->chan_tx)
1545 sci_tx_interrupt(irq, ptr);
1546
1547 return IRQ_HANDLED;
73a19e4c
GL		 1548}
1549
e1910fcd 1550static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1551{
e1910fcd 1552 struct uart_port *port = ptr;
73a19e4c 1553
e1910fcd
GU		 1554 /* Handle BREAKs */
1555 sci_handle_breaks(port);
1556 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1557
e1910fcd
GU		 1558 return IRQ_HANDLED;
1559}
73a19e4c 1560
e1910fcd
GU		 1561static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1562{
1563 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1564 struct uart_port *port = ptr;
1565 struct sci_port *s = to_sci_port(port);
1566 irqreturn_t ret = IRQ_NONE;
73a19e4c 1567
e1910fcd
GU		 1568 ssr_status = serial_port_in(port, SCxSR);
1569 scr_status = serial_port_in(port, SCSCR);
1570 if (s->overrun_reg == SCxSR)
1571 orer_status = ssr_status;
1572 else {
1573 if (sci_getreg(port, s->overrun_reg)->size)
1574 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1575 }
1576
e1910fcd 1577 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1578
e1910fcd
GU		 1579 /* Tx Interrupt */
1580 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1581 !s->chan_tx)
1582 ret = sci_tx_interrupt(irq, ptr);
658daa95 1583
e1910fcd
GU		 1584 /*
1585 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1586 * DR flags
1587 */
1588 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1589 (scr_status & SCSCR_RIE))
1590 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1591
e1910fcd
GU		 1592 /* Error Interrupt */
1593 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1594 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1595
e1910fcd
GU		 1596 /* Break Interrupt */
1597 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1598 ret = sci_br_interrupt(irq, ptr);
1599
1600 /* Overrun Interrupt */
1601 if (orer_status & s->overrun_mask) {
1602 sci_handle_fifo_overrun(port);
1603 ret = IRQ_HANDLED;
73a19e4c 1604 }
73a19e4c 1605
e1910fcd
GU		 1606 return ret;
1607}
73a19e4c 1608
e1910fcd
GU		 1609/*
1610 * Here we define a transition notifier so that we can update all of our
1611 * ports' baud rate when the peripheral clock changes.
1612 */
1613static int sci_notifier(struct notifier_block *self,
1614 unsigned long phase, void *p)
1615{
1616 struct sci_port *sci_port;
1617 unsigned long flags;
73a19e4c 1618
e1910fcd 1619 sci_port = container_of(self, struct sci_port, freq_transition);
73a19e4c 1620
e1910fcd
GU		 1621 if (phase == CPUFREQ_POSTCHANGE) {
1622 struct uart_port *port = &sci_port->port;
73a19e4c 1623
e1910fcd
GU		 1624 spin_lock_irqsave(&port->lock, flags);
1625 port->uartclk = clk_get_rate(sci_port->iclk);
1626 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1627 }
1628
e1910fcd
GU		 1629 return NOTIFY_OK;
1630}
73a19e4c 1631
e1910fcd
GU		 1632static const struct sci_irq_desc {
1633 const char *desc;
1634 irq_handler_t handler;
1635} sci_irq_desc[] = {
1636 /*
1637 * Split out handlers, the default case.
1638 */
1639 [SCIx_ERI_IRQ] = {
1640 .desc = "rx err",
1641 .handler = sci_er_interrupt,
1642 },
3089f381 1643
e1910fcd
GU		 1644 [SCIx_RXI_IRQ] = {
1645 .desc = "rx full",
1646 .handler = sci_rx_interrupt,
1647 },
47aceb92 1648
e1910fcd
GU		 1649 [SCIx_TXI_IRQ] = {
1650 .desc = "tx empty",
1651 .handler = sci_tx_interrupt,
1652 },
73a19e4c 1653
e1910fcd
GU		 1654 [SCIx_BRI_IRQ] = {
1655 .desc = "break",
1656 .handler = sci_br_interrupt,
1657 },
73a19e4c
GL		 1658
1659 /*
e1910fcd 1660 * Special muxed handler.
73a19e4c 1661 */
e1910fcd
GU		 1662 [SCIx_MUX_IRQ] = {
1663 .desc = "mux",
1664 .handler = sci_mpxed_interrupt,
1665 },
1666};
73a19e4c 1667
e1910fcd
GU		 1668static int sci_request_irq(struct sci_port *port)
1669{
1670 struct uart_port *up = &port->port;
1671 int i, j, ret = 0;
73a19e4c 1672
e1910fcd
GU		 1673 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1674 const struct sci_irq_desc *desc;
1675 int irq;
73a19e4c 1676
e1910fcd
GU		 1677 if (SCIx_IRQ_IS_MUXED(port)) {
1678 i = SCIx_MUX_IRQ;
1679 irq = up->irq;
1680 } else {
1681 irq = port->irqs[i];
1682
1683 /*
1684 * Certain port types won't support all of the
1685 * available interrupt sources.
1686 */
1687 if (unlikely(irq < 0))
1688 continue;
1689 }
1690
1691 desc = sci_irq_desc + i;
1692 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1693 dev_name(up->dev), desc->desc);
1694 if (!port->irqstr[j])
1695 goto out_nomem;
1696
1697 ret = request_irq(irq, desc->handler, up->irqflags,
1698 port->irqstr[j], port);
1699 if (unlikely(ret)) {
1700 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1701 goto out_noirq;
1702 }
73a19e4c
GL		 1703 }
1704
e1910fcd 1705 return 0;
1da177e4 1706
e1910fcd
GU		 1707out_noirq:
1708 while (--i >= 0)
1709 free_irq(port->irqs[i], port);
f43dc23d 1710
e1910fcd
GU		 1711out_nomem:
1712 while (--j >= 0)
1713 kfree(port->irqstr[j]);
f43dc23d 1714
e1910fcd 1715 return ret;
1da177e4
LT		 1716}
1717
e1910fcd 1718static void sci_free_irq(struct sci_port *port)
1da177e4 1719{
e1910fcd 1720 int i;
1da177e4 1721
e1910fcd
GU		 1722 /*
1723 * Intentionally in reverse order so we iterate over the muxed
1724 * IRQ first.
1725 */
1726 for (i = 0; i < SCIx_NR_IRQS; i++) {
1727 int irq = port->irqs[i];
f43dc23d 1728
e1910fcd
GU		 1729 /*
1730 * Certain port types won't support all of the available
1731 * interrupt sources.
1732 */
1733 if (unlikely(irq < 0))
1734 continue;
f43dc23d 1735
e1910fcd
GU		 1736 free_irq(port->irqs[i], port);
1737 kfree(port->irqstr[i]);
f43dc23d 1738
e1910fcd
GU		 1739 if (SCIx_IRQ_IS_MUXED(port)) {
1740 /* If there's only one IRQ, we're done. */
1741 return;
1742 }
1743 }
1da177e4
LT		 1744}
1745
e1910fcd 1746static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1747{
e1910fcd
GU		 1748 unsigned short status = serial_port_in(port, SCxSR);
1749 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1750
e1910fcd 1751 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1752}
1753
e1910fcd
GU		 1754/*
1755 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1756 * CTS/RTS is supported in hardware by at least one port and controlled
1757 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1758 * handled via the ->init_pins() op, which is a bit of a one-way street,
1759 * lacking any ability to defer pin control -- this will later be
1760 * converted over to the GPIO framework).
1761 *
1762 * Other modes (such as loopback) are supported generically on certain
1763 * port types, but not others. For these it's sufficient to test for the
1764 * existence of the support register and simply ignore the port type.
1765 */
1766static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1767{
e1910fcd
GU		 1768 if (mctrl & TIOCM_LOOP) {
1769 const struct plat_sci_reg *reg;
f43dc23d 1770
e1910fcd
GU		 1771 /*
1772 * Standard loopback mode for SCFCR ports.
1773 */
1774 reg = sci_getreg(port, SCFCR);
1775 if (reg->size)
1776 serial_port_out(port, SCFCR,
1777 serial_port_in(port, SCFCR) |
1778 SCFCR_LOOP);
1779 }
1780}
f43dc23d 1781
e1910fcd
GU		 1782static unsigned int sci_get_mctrl(struct uart_port *port)
1783{
1784 /*
1785 * CTS/RTS is handled in hardware when supported, while nothing
1786 * else is wired up. Keep it simple and simply assert DSR/CAR.
1787 */
1788 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1789}
1790
1da177e4
LT		 1791static void sci_break_ctl(struct uart_port *port, int break_state)
1792{
bbb4ce50 1793 struct sci_port *s = to_sci_port(port);
d3184e68 1794 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1795 unsigned short scscr, scsptr;
1796
a4e02f6d
SY		 1797 /* check wheter the port has SCSPTR */
1798 if (!reg->size) {
bbb4ce50
SY		 1799 /*
1800 * Not supported by hardware. Most parts couple break and rx
1801 * interrupts together, with break detection always enabled.
1802 */
a4e02f6d 1803 return;
bbb4ce50 1804 }
a4e02f6d
SY		 1805
1806 scsptr = serial_port_in(port, SCSPTR);
1807 scscr = serial_port_in(port, SCSCR);
1808
1809 if (break_state == -1) {
1810 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1811 scscr &= ~SCSCR_TE;
1812 } else {
1813 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1814 scscr |= SCSCR_TE;
1815 }
1816
1817 serial_port_out(port, SCSPTR, scsptr);
1818 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1819}
1820
1821static int sci_startup(struct uart_port *port)
1822{
a5660ada 1823 struct sci_port *s = to_sci_port(port);
33b48e16 1824 unsigned long flags;
073e84c9 1825 int ret;
1da177e4 1826
73a19e4c
GL		 1827 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1828
073e84c9
PM		 1829 ret = sci_request_irq(s);
1830 if (unlikely(ret < 0))
1831 return ret;
1832
73a19e4c 1833 sci_request_dma(port);
073e84c9 1834
33b48e16 1835 spin_lock_irqsave(&port->lock, flags);
d656901b 1836 sci_start_tx(port);
73a19e4c 1837 sci_start_rx(port);
33b48e16 1838 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1839
1840 return 0;
1841}
1842
1843static void sci_shutdown(struct uart_port *port)
1844{
a5660ada 1845 struct sci_port *s = to_sci_port(port);
33b48e16 1846 unsigned long flags;
1da177e4 1847
73a19e4c
GL		 1848 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1849
33b48e16 1850 spin_lock_irqsave(&port->lock, flags);
1da177e4 1851 sci_stop_rx(port);
b129a8cc 1852 sci_stop_tx(port);
33b48e16 1853 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1854
9ab76556
AM		 1855#ifdef CONFIG_SERIAL_SH_SCI_DMA
1856 if (s->chan_rx) {
1857 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1858 port->line);
1859 del_timer_sync(&s->rx_timer);
1860 }
1861#endif
1862
73a19e4c 1863 sci_free_dma(port);
1da177e4 1864 sci_free_irq(s);
1da177e4
LT		 1865}
1866
ec09c5eb 1867static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1868 unsigned long freq)
1869{
ec09c5eb
LP		 1870 if (s->sampling_rate)
1871 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1872
26c92f37
PM		 1873 /* Warn, but use a safe default */
1874 WARN_ON(1);
e8183a6c 1875
26c92f37
PM		 1876 return ((freq + 16 * bps) / (32 * bps) - 1);
1877}
1878
730c4e78
NI		 1879/* calculate frame length from SMR */
1880static int sci_baud_calc_frame_len(unsigned int smr_val)
1881{
1882 int len = 10;
1883
1884 if (smr_val & SCSMR_CHR)
1885 len--;
1886 if (smr_val & SCSMR_PE)
1887 len++;
1888 if (smr_val & SCSMR_STOP)
1889 len++;
1890
1891 return len;
1892}
1893
1894
f303b364
UH		 1895/* calculate sample rate, BRR, and clock select for HSCIF */
1896static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1897 int *brr, unsigned int *srr,
730c4e78 1898 unsigned int *cks, int frame_len)
f303b364 1899{
730c4e78 1900 int sr, c, br, err, recv_margin;
f303b364 1901 int min_err = 1000; /* 100% */
730c4e78 1902 int recv_max_margin = 0;
f303b364
UH		 1903
1904 /* Find the combination of sample rate and clock select with the
1905 smallest deviation from the desired baud rate. */
1906 for (sr = 8; sr <= 32; sr++) {
1907 for (c = 0; c <= 3; c++) {
1908 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1909 br = DIV_ROUND_CLOSEST(freq, (sr *
1910 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1911 br = clamp(br, 0, 255);
b7d66397
NI		 1912 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1913 (1 << (2 * c + 1)) / 1000)) -
1914 1000;
730c4e78
NI		 1915 /* Calc recv margin
1916 * M: Receive margin (%)
1917 * N: Ratio of bit rate to clock (N = sampling rate)
1918 * D: Clock duty (D = 0 to 1.0)
1919 * L: Frame length (L = 9 to 12)
1920 * F: Absolute value of clock frequency deviation
1921 *
1922 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1923 * (|D - 0.5| / N * (1 + F))|
1924 * NOTE: Usually, treat D for 0.5, F is 0 by this
1925 * calculation.
1926 */
1927 recv_margin = abs((500 -
1928 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1929 if (abs(min_err) > abs(err)) {
f303b364 1930 min_err = err;
730c4e78
NI		 1931 recv_max_margin = recv_margin;
1932 } else if ((min_err == err) &&
1933 (recv_margin > recv_max_margin))
1934 recv_max_margin = recv_margin;
1935 else
1936 continue;
1937
1938 *brr = br;
1939 *srr = sr - 1;
1940 *cks = c;
f303b364
UH		 1941 }
1942 }
1943
1944 if (min_err == 1000) {
1945 WARN_ON(1);
1946 /* use defaults */
1947 *brr = 255;
1948 *srr = 15;
1949 *cks = 0;
1950 }
1951}
1952
1ba76220
MD		 1953static void sci_reset(struct uart_port *port)
1954{
d3184e68 1955 const struct plat_sci_reg *reg;
1ba76220
MD		 1956 unsigned int status;
1957
1958 do {
b12bb29f 1959 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1960 } while (!(status & SCxSR_TEND(port)));
1961
b12bb29f 1962 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1963
0979e0e6
PM		 1964 reg = sci_getreg(port, SCFCR);
1965 if (reg->size)
b12bb29f 1966 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1967}
1968
606d099c
AC		 1969static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1970 struct ktermios *old)
1da177e4 1971{
00b9de9c 1972 struct sci_port *s = to_sci_port(port);
d3184e68 1973 const struct plat_sci_reg *reg;
730c4e78 1974 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1975 int t = -1;
d4759ded 1976 unsigned int srr = 15;
1da177e4 1977
730c4e78
NI		 1978 if ((termios->c_cflag & CSIZE) == CS7)
1979 smr_val |= SCSMR_CHR;
1980 if (termios->c_cflag & PARENB)
1981 smr_val |= SCSMR_PE;
1982 if (termios->c_cflag & PARODD)
1983 smr_val |= SCSMR_PE | SCSMR_ODD;
1984 if (termios->c_cflag & CSTOPB)
1985 smr_val |= SCSMR_STOP;
1986
154280fd
MD		 1987 /*
1988 * earlyprintk comes here early on with port->uartclk set to zero.
1989 * the clock framework is not up and running at this point so here
1990 * we assume that 115200 is the maximum baud rate. please note that
1991 * the baud rate is not programmed during earlyprintk - it is assumed
1992 * that the previous boot loader has enabled required clocks and
1993 * setup the baud rate generator hardware for us already.
1994 */
1995 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1996
154280fd 1997 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1998 if (likely(baud && port->uartclk)) {
ec09c5eb 1999 if (s->cfg->type == PORT_HSCIF) {
730c4e78 2000 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 2001 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 2002 &cks, frame_len);
f303b364 2003 } else {
ec09c5eb 2004 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 2005 for (cks = 0; t >= 256 && cks <= 3; cks++)
2006 t >>= 2;
2007 }
2008 }
e108b2ca 2009
23241d43 2010 sci_port_enable(s);
36003386 2011
1ba76220 2012 sci_reset(port);
1da177e4 2013
2944a331 2014 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 2015
2016 uart_update_timeout(port, termios->c_cflag, baud);
2017
9d482cc3
TY		 2018 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2019 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 2020
4ffc3cdb 2021 if (t >= 0) {
26de4f1b 2022 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 2023 serial_port_out(port, SCBRR, t);
f303b364
UH		 2024 reg = sci_getreg(port, HSSRR);
2025 if (reg->size)
2026 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 2027 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 2028 } else
2029 serial_port_out(port, SCSMR, smr_val);
1da177e4 2030
d5701647 2031 sci_init_pins(port, termios->c_cflag);
0979e0e6 2032
73c3d53f
PM		 2033 reg = sci_getreg(port, SCFCR);
2034 if (reg->size) {
b12bb29f 2035 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2036
73c3d53f 2037 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2038 if (termios->c_cflag & CRTSCTS)
2039 ctrl |= SCFCR_MCE;
2040 else
2041 ctrl &= ~SCFCR_MCE;
faf02f8f 2042 }
73c3d53f
PM		 2043
2044 /*
2045 * As we've done a sci_reset() above, ensure we don't
2046 * interfere with the FIFOs while toggling MCE. As the
2047 * reset values could still be set, simply mask them out.
2048 */
2049 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2050
b12bb29f 2051 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2052 }
b7a76e4b 2053
b12bb29f 2054 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2055
3089f381
GL		 2056#ifdef CONFIG_SERIAL_SH_SCI_DMA
2057 /*
5f6d8515 2058 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2059 * See serial_core.c::uart_update_timeout().
2060 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2061 * function calculates 1 jiffie for the data plus 5 jiffies for the
2062 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2063 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2064 * value obtained by this formula is too small. Therefore, if the value
2065 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2066 */
2067 if (s->chan_rx) {
5f6d8515
NI		 2068 unsigned int bits;
2069
2070 /* byte size and parity */
2071 switch (termios->c_cflag & CSIZE) {
2072 case CS5:
2073 bits = 7;
2074 break;
2075 case CS6:
2076 bits = 8;
2077 break;
2078 case CS7:
2079 bits = 9;
2080 break;
2081 default:
2082 bits = 10;
2083 break;
2084 }
2085
2086 if (termios->c_cflag & CSTOPB)
2087 bits++;
2088 if (termios->c_cflag & PARENB)
2089 bits++;
2090 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2091 (baud / 10), 10);
9b971cd2 2092 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2093 s->rx_timeout * 1000 / HZ, port->timeout);
2094 if (s->rx_timeout < msecs_to_jiffies(20))
2095 s->rx_timeout = msecs_to_jiffies(20);
2096 }
2097#endif
2098
1da177e4 2099 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2100 sci_start_rx(port);
36003386 2101
23241d43 2102 sci_port_disable(s);
1da177e4
LT		 2103}
2104
0174e5ca
TK		 2105static void sci_pm(struct uart_port *port, unsigned int state,
2106 unsigned int oldstate)
2107{
2108 struct sci_port *sci_port = to_sci_port(port);
2109
2110 switch (state) {
d3dfe5d9 2111 case UART_PM_STATE_OFF:
0174e5ca
TK		 2112 sci_port_disable(sci_port);
2113 break;
2114 default:
2115 sci_port_enable(sci_port);
2116 break;
2117 }
2118}
2119
1da177e4
LT		 2120static const char *sci_type(struct uart_port *port)
2121{
2122 switch (port->type) {
e7c98dc7
MT		 2123 case PORT_IRDA:
2124 return "irda";
2125 case PORT_SCI:
2126 return "sci";
2127 case PORT_SCIF:
2128 return "scif";
2129 case PORT_SCIFA:
2130 return "scifa";
d1d4b10c
GL		 2131 case PORT_SCIFB:
2132 return "scifb";
f303b364
UH		 2133 case PORT_HSCIF:
2134 return "hscif";
1da177e4
LT		 2135 }
2136
fa43972f 2137 return NULL;
1da177e4
LT		 2138}
2139
f6e9495d
PM		 2140static int sci_remap_port(struct uart_port *port)
2141{
e4d6f911 2142 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2143
2144 /*
2145 * Nothing to do if there's already an established membase.
2146 */
2147 if (port->membase)
2148 return 0;
2149
2150 if (port->flags & UPF_IOREMAP) {
e4d6f911 2151 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2152 if (unlikely(!port->membase)) {
2153 dev_err(port->dev, "can't remap port#%d\n", port->line);
2154 return -ENXIO;
2155 }
2156 } else {
2157 /*
2158 * For the simple (and majority of) cases where we don't
2159 * need to do any remapping, just cast the cookie
2160 * directly.
2161 */
3af4e960 2162 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2163 }
2164
2165 return 0;
2166}
2167
e2651647 2168static void sci_release_port(struct uart_port *port)
1da177e4 2169{
e4d6f911
YS		 2170 struct sci_port *sport = to_sci_port(port);
2171
e2651647
PM		 2172 if (port->flags & UPF_IOREMAP) {
2173 iounmap(port->membase);
2174 port->membase = NULL;
2175 }
2176
e4d6f911 2177 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2178}
2179
e2651647 2180static int sci_request_port(struct uart_port *port)
1da177e4 2181{
e2651647 2182 struct resource *res;
e4d6f911 2183 struct sci_port *sport = to_sci_port(port);
f6e9495d 2184 int ret;
1da177e4 2185
e4d6f911
YS		 2186 res = request_mem_region(port->mapbase, sport->reg_size,
2187 dev_name(port->dev));
2188 if (unlikely(res == NULL)) {
2189 dev_err(port->dev, "request_mem_region failed.");
e2651647 2190 return -EBUSY;
e4d6f911 2191 }
1da177e4 2192
f6e9495d
PM		 2193 ret = sci_remap_port(port);
2194 if (unlikely(ret != 0)) {
2195 release_resource(res);
2196 return ret;
7ff731ae 2197 }
e2651647
PM		 2198
2199 return 0;
2200}
2201
2202static void sci_config_port(struct uart_port *port, int flags)
2203{
2204 if (flags & UART_CONFIG_TYPE) {
2205 struct sci_port *sport = to_sci_port(port);
2206
2207 port->type = sport->cfg->type;
2208 sci_request_port(port);
2209 }
1da177e4
LT		 2210}
2211
2212static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2213{
1da177e4
LT		 2214 if (ser->baud_base < 2400)
2215 /* No paper tape reader for Mitch.. */
2216 return -EINVAL;
2217
2218 return 0;
2219}
2220
2221static struct uart_ops sci_uart_ops = {
2222 .tx_empty = sci_tx_empty,
2223 .set_mctrl = sci_set_mctrl,
2224 .get_mctrl = sci_get_mctrl,
2225 .start_tx = sci_start_tx,
2226 .stop_tx = sci_stop_tx,
2227 .stop_rx = sci_stop_rx,
1da177e4
LT		 2228 .break_ctl = sci_break_ctl,
2229 .startup = sci_startup,
2230 .shutdown = sci_shutdown,
2231 .set_termios = sci_set_termios,
0174e5ca 2232 .pm = sci_pm,
1da177e4
LT		 2233 .type = sci_type,
2234 .release_port = sci_release_port,
2235 .request_port = sci_request_port,
2236 .config_port = sci_config_port,
2237 .verify_port = sci_verify_port,
07d2a1a1
PM		 2238#ifdef CONFIG_CONSOLE_POLL
2239 .poll_get_char = sci_poll_get_char,
2240 .poll_put_char = sci_poll_put_char,
2241#endif
1da177e4
LT		 2242};
2243
9671f099 2244static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2245 struct sci_port *sci_port, unsigned int index,
2246 struct plat_sci_port *p, bool early)
e108b2ca 2247{
73a19e4c 2248 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2249 const struct resource *res;
2250 unsigned int i;
3127c6b2 2251 int ret;
e108b2ca 2252
50f0959a
PM		 2253 sci_port->cfg = p;
2254
73a19e4c
GL		 2255 port->ops = &sci_uart_ops;
2256 port->iotype = UPIO_MEM;
2257 port->line = index;
75136d48 2258
89b5c1ab
LP		 2259 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2260 if (res == NULL)
2261 return -ENOMEM;
1fcc91a6 2262
89b5c1ab 2263 port->mapbase = res->start;
e4d6f911 2264 sci_port->reg_size = resource_size(res);
1fcc91a6 2265
89b5c1ab
LP		 2266 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2267 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2268
89b5c1ab
LP		 2269 /* The SCI generates several interrupts. They can be muxed together or
2270 * connected to different interrupt lines. In the muxed case only one
2271 * interrupt resource is specified. In the non-muxed case three or four
2272 * interrupt resources are specified, as the BRI interrupt is optional.
2273 */
2274 if (sci_port->irqs[0] < 0)
2275 return -ENXIO;
1fcc91a6 2276
89b5c1ab
LP		 2277 if (sci_port->irqs[1] < 0) {
2278 sci_port->irqs[1] = sci_port->irqs[0];
2279 sci_port->irqs[2] = sci_port->irqs[0];
2280 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2281 }
2282
b545e4f4
LP		 2283 if (p->regtype == SCIx_PROBE_REGTYPE) {
2284 ret = sci_probe_regmap(p);
2285 if (unlikely(ret))
2286 return ret;
2287 }
2288
75136d48 2289 switch (p->type) {
d1d4b10c
GL		 2290 case PORT_SCIFB:
2291 port->fifosize = 256;
2e0842a1 2292 sci_port->overrun_reg = SCxSR;
75c249fd 2293 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2294 sci_port->sampling_rate = 16;
d1d4b10c 2295 break;
f303b364
UH		 2296 case PORT_HSCIF:
2297 port->fifosize = 128;
2e0842a1 2298 sci_port->overrun_reg = SCLSR;
75c249fd 2299 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2300 sci_port->sampling_rate = 0;
f303b364 2301 break;
75136d48 2302 case PORT_SCIFA:
73a19e4c 2303 port->fifosize = 64;
2e0842a1 2304 sci_port->overrun_reg = SCxSR;
75c249fd 2305 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2306 sci_port->sampling_rate = 16;
75136d48
MP		 2307 break;
2308 case PORT_SCIF:
73a19e4c 2309 port->fifosize = 16;
ec09c5eb 2310 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2311 sci_port->overrun_reg = SCxSR;
75c249fd 2312 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2313 sci_port->sampling_rate = 16;
ec09c5eb 2314 } else {
2e0842a1 2315 sci_port->overrun_reg = SCLSR;
75c249fd 2316 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2317 sci_port->sampling_rate = 32;
ec09c5eb 2318 }
75136d48
MP		 2319 break;
2320 default:
73a19e4c 2321 port->fifosize = 1;
2e0842a1 2322 sci_port->overrun_reg = SCxSR;
75c249fd 2323 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2324 sci_port->sampling_rate = 32;
75136d48
MP		 2325 break;
2326 }
7b6fd3bf 2327
878fbb91
LP		 2328 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2329 * match the SoC datasheet, this should be investigated. Let platform
2330 * data override the sampling rate for now.
ec09c5eb 2331 */
f84b6bdc
GU		 2332 if (p->sampling_rate)
2333 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2334
1fcc91a6 2335 if (!early) {
c7ed1ab3
PM		 2336 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2337 if (IS_ERR(sci_port->iclk)) {
2338 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2339 if (IS_ERR(sci_port->iclk)) {
2340 dev_err(&dev->dev, "can't get iclk\n");
2341 return PTR_ERR(sci_port->iclk);
2342 }
2343 }
2344
2345 /*
2346 * The function clock is optional, ignore it if we can't
2347 * find it.
2348 */
2349 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2350 if (IS_ERR(sci_port->fclk))
2351 sci_port->fclk = NULL;
2352
73a19e4c 2353 port->dev = &dev->dev;
5e50d2d6
MD		 2354
2355 pm_runtime_enable(&dev->dev);
7b6fd3bf 2356 }
e108b2ca 2357
7ed7e071
MD		 2358 sci_port->break_timer.data = (unsigned long)sci_port;
2359 sci_port->break_timer.function = sci_break_timer;
2360 init_timer(&sci_port->break_timer);
2361
debf9507
PM		 2362 /*
2363 * Establish some sensible defaults for the error detection.
2364 */
5da0f468
GU		 2365 if (p->type == PORT_SCI) {
2366 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2367 sci_port->error_clear = SCI_ERROR_CLEAR;
2368 } else {
2369 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2370 sci_port->error_clear = SCIF_ERROR_CLEAR;
2371 }
debf9507 2372
3ae988d9
LP		 2373 /*
2374 * Make the error mask inclusive of overrun detection, if
2375 * supported.
2376 */
5da0f468 2377 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2378 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2379 sci_port->error_clear &= ~sci_port->overrun_mask;
2380 }
debf9507 2381
ce6738b6 2382 port->type = p->type;
b6e4a3f1 2383 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2384 port->regshift = p->regshift;
73a19e4c 2385
ce6738b6 2386 /*
61a6976b 2387 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2388 * for the multi-IRQ ports, which is where we are primarily
2389 * concerned with the shutdown path synchronization.
2390 *
2391 * For the muxed case there's nothing more to do.
2392 */
1fcc91a6 2393 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2394 port->irqflags = 0;
73a19e4c 2395
61a6976b
PM		 2396 port->serial_in = sci_serial_in;
2397 port->serial_out = sci_serial_out;
2398
937bb6e4
GL		 2399 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2400 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2401 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2402
c7ed1ab3 2403 return 0;
e108b2ca
PM		 2404}
2405
6dae1421
LP		 2406static void sci_cleanup_single(struct sci_port *port)
2407{
6dae1421
LP		 2408 clk_put(port->iclk);
2409 clk_put(port->fclk);
2410
2411 pm_runtime_disable(port->port.dev);
2412}
2413
1da177e4 2414#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2415static void serial_console_putchar(struct uart_port *port, int ch)
2416{
2417 sci_poll_put_char(port, ch);
2418}
2419
1da177e4
LT		 2420/*
2421 * Print a string to the serial port trying not to disturb
2422 * any possible real use of the port...
2423 */
2424static void serial_console_write(struct console *co, const char *s,
2425 unsigned count)
2426{
906b17dc
PM		 2427 struct sci_port *sci_port = &sci_ports[co->index];
2428 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2429 unsigned short bits, ctrl;
2430 unsigned long flags;
2431 int locked = 1;
2432
2433 local_irq_save(flags);
2434 if (port->sysrq)
2435 locked = 0;
2436 else if (oops_in_progress)
2437 locked = spin_trylock(&port->lock);
2438 else
2439 spin_lock(&port->lock);
2440
2441 /* first save the SCSCR then disable the interrupts */
2442 ctrl = serial_port_in(port, SCSCR);
2443 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2444
501b825d 2445 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2446
2447 /* wait until fifo is empty and last bit has been transmitted */
2448 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2449 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2450 cpu_relax();
40f70c03
SK		 2451
2452 /* restore the SCSCR */
2453 serial_port_out(port, SCSCR, ctrl);
2454
2455 if (locked)
2456 spin_unlock(&port->lock);
2457 local_irq_restore(flags);
1da177e4
LT		 2458}
2459
9671f099 2460static int serial_console_setup(struct console *co, char *options)
1da177e4 2461{
dc8e6f5b 2462 struct sci_port *sci_port;
1da177e4
LT		 2463 struct uart_port *port;
2464 int baud = 115200;
2465 int bits = 8;
2466 int parity = 'n';
2467 int flow = 'n';
2468 int ret;
2469
e108b2ca 2470 /*
906b17dc 2471 * Refuse to handle any bogus ports.
1da177e4 2472 */
906b17dc 2473 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2474 return -ENODEV;
e108b2ca 2475
906b17dc
PM		 2476 sci_port = &sci_ports[co->index];
2477 port = &sci_port->port;
2478
b2267a6b
AC		 2479 /*
2480 * Refuse to handle uninitialized ports.
2481 */
2482 if (!port->ops)
2483 return -ENODEV;
2484
f6e9495d
PM		 2485 ret = sci_remap_port(port);
2486 if (unlikely(ret != 0))
2487 return ret;
e108b2ca 2488
1da177e4
LT		 2489 if (options)
2490 uart_parse_options(options, &baud, &parity, &bits, &flow);
2491
ab7cfb55 2492 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2493}
2494
2495static struct console serial_console = {
2496 .name = "ttySC",
906b17dc 2497 .device = uart_console_device,
1da177e4
LT		 2498 .write = serial_console_write,
2499 .setup = serial_console_setup,
fa5da2f7 2500 .flags = CON_PRINTBUFFER,
1da177e4 2501 .index = -1,
906b17dc 2502 .data = &sci_uart_driver,
1da177e4
LT		 2503};
2504
7b6fd3bf
MD		 2505static struct console early_serial_console = {
2506 .name = "early_ttySC",
2507 .write = serial_console_write,
2508 .flags = CON_PRINTBUFFER,
906b17dc 2509 .index = -1,
7b6fd3bf 2510};
ecdf8a46 2511
7b6fd3bf
MD		 2512static char early_serial_buf[32];
2513
9671f099 2514static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2515{
574de559 2516 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2517
2518 if (early_serial_console.data)
2519 return -EEXIST;
2520
2521 early_serial_console.index = pdev->id;
ecdf8a46 2522
1fcc91a6 2523 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2524
2525 serial_console_setup(&early_serial_console, early_serial_buf);
2526
2527 if (!strstr(early_serial_buf, "keep"))
2528 early_serial_console.flags |= CON_BOOT;
2529
2530 register_console(&early_serial_console);
2531 return 0;
2532}
6a8c9799
NI		 2533
2534#define SCI_CONSOLE (&serial_console)
2535
ecdf8a46 2536#else
9671f099 2537static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2538{
2539 return -EINVAL;
2540}
1da177e4 2541
6a8c9799
NI		 2542#define SCI_CONSOLE NULL
2543
2544#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2545
6c13d5d2 2546static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2547
2548static struct uart_driver sci_uart_driver = {
2549 .owner = THIS_MODULE,
2550 .driver_name = "sci",
1da177e4
LT		 2551 .dev_name = "ttySC",
2552 .major = SCI_MAJOR,
2553 .minor = SCI_MINOR_START,
e108b2ca 2554 .nr = SCI_NPORTS,
1da177e4
LT		 2555 .cons = SCI_CONSOLE,
2556};
2557
54507f6e 2558static int sci_remove(struct platform_device *dev)
e552de24 2559{
d535a230 2560 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2561
d535a230
PM		 2562 cpufreq_unregister_notifier(&port->freq_transition,
2563 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2564
d535a230
PM		 2565 uart_remove_one_port(&sci_uart_driver, &port->port);
2566
6dae1421 2567 sci_cleanup_single(port);
e552de24 2568
e552de24
MD		 2569 return 0;
2570}
2571
20bdcab8
BH		 2572struct sci_port_info {
2573 unsigned int type;
2574 unsigned int regtype;
2575};
2576
2577static const struct of_device_id of_sci_match[] = {
2578 {
2579 .compatible = "renesas,scif",
ff43da00 2580 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2581 .type = PORT_SCIF,
2582 .regtype = SCIx_SH4_SCIF_REGTYPE,
2583 },
2584 }, {
2585 .compatible = "renesas,scifa",
ff43da00 2586 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2587 .type = PORT_SCIFA,
2588 .regtype = SCIx_SCIFA_REGTYPE,
2589 },
2590 }, {
2591 .compatible = "renesas,scifb",
ff43da00 2592 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2593 .type = PORT_SCIFB,
2594 .regtype = SCIx_SCIFB_REGTYPE,
2595 },
2596 }, {
2597 .compatible = "renesas,hscif",
ff43da00 2598 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2599 .type = PORT_HSCIF,
2600 .regtype = SCIx_HSCIF_REGTYPE,
2601 },
e1d0be61
YS		 2602 }, {
2603 .compatible = "renesas,sci",
2604 .data = &(const struct sci_port_info) {
2605 .type = PORT_SCI,
2606 .regtype = SCIx_SCI_REGTYPE,
2607 },
20bdcab8
BH		 2608 }, {
2609 /* Terminator */
2610 },
2611};
2612MODULE_DEVICE_TABLE(of, of_sci_match);
2613
2614static struct plat_sci_port *
2615sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2616{
2617 struct device_node *np = pdev->dev.of_node;
2618 const struct of_device_id *match;
2619 const struct sci_port_info *info;
2620 struct plat_sci_port *p;
2621 int id;
2622
2623 if (!IS_ENABLED(CONFIG_OF) || !np)
2624 return NULL;
2625
2626 match = of_match_node(of_sci_match, pdev->dev.of_node);
2627 if (!match)
2628 return NULL;
2629
2630 info = match->data;
2631
2632 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2633 if (!p)
20bdcab8 2634 return NULL;
20bdcab8
BH		 2635
2636 /* Get the line number for the aliases node. */
2637 id = of_alias_get_id(np, "serial");
2638 if (id < 0) {
2639 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2640 return NULL;
2641 }
2642
2643 *dev_id = id;
2644
2645 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2646 p->type = info->type;
2647 p->regtype = info->regtype;
2648 p->scscr = SCSCR_RE | SCSCR_TE;
2649
2650 return p;
2651}
2652
9671f099 2653static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2654 unsigned int index,
2655 struct plat_sci_port *p,
2656 struct sci_port *sciport)
2657{
0ee70712
MD		 2658 int ret;
2659
2660 /* Sanity check */
2661 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2662 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2663 index+1, SCI_NPORTS);
9b971cd2 2664 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2665 return -EINVAL;
0ee70712
MD		 2666 }
2667
1fcc91a6 2668 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2669 if (ret)
2670 return ret;
0ee70712 2671
6dae1421
LP		 2672 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2673 if (ret) {
2674 sci_cleanup_single(sciport);
2675 return ret;
2676 }
2677
2678 return 0;
0ee70712
MD		 2679}
2680
9671f099 2681static int sci_probe(struct platform_device *dev)
1da177e4 2682{
20bdcab8
BH		 2683 struct plat_sci_port *p;
2684 struct sci_port *sp;
2685 unsigned int dev_id;
ecdf8a46 2686 int ret;
d535a230 2687
ecdf8a46
PM		 2688 /*
2689 * If we've come here via earlyprintk initialization, head off to
2690 * the special early probe. We don't have sufficient device state
2691 * to make it beyond this yet.
2692 */
2693 if (is_early_platform_device(dev))
2694 return sci_probe_earlyprintk(dev);
7b6fd3bf 2695
20bdcab8
BH		 2696 if (dev->dev.of_node) {
2697 p = sci_parse_dt(dev, &dev_id);
2698 if (p == NULL)
2699 return -EINVAL;
2700 } else {
2701 p = dev->dev.platform_data;
2702 if (p == NULL) {
2703 dev_err(&dev->dev, "no platform data supplied\n");
2704 return -EINVAL;
2705 }
2706
2707 dev_id = dev->id;
2708 }
2709
2710 sp = &sci_ports[dev_id];
d535a230 2711 platform_set_drvdata(dev, sp);
e552de24 2712
20bdcab8 2713 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2714 if (ret)
6dae1421 2715 return ret;
e552de24 2716
d535a230 2717 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2718
d535a230
PM		 2719 ret = cpufreq_register_notifier(&sp->freq_transition,
2720 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2721 if (unlikely(ret < 0)) {
bf13c9a8 2722 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2723 sci_cleanup_single(sp);
2724 return ret;
2725 }
1da177e4
LT		 2726
2727#ifdef CONFIG_SH_STANDARD_BIOS
2728 sh_bios_gdb_detach();
2729#endif
2730
e108b2ca 2731 return 0;
1da177e4
LT		 2732}
2733
cb876341 2734static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2735{
d535a230 2736 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2737
d535a230
PM		 2738 if (sport)
2739 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2740
e108b2ca
PM		 2741 return 0;
2742}
1da177e4 2743
cb876341 2744static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2745{
d535a230 2746 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2747
d535a230
PM		 2748 if (sport)
2749 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2750
2751 return 0;
2752}
2753
cb876341 2754static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2755
e108b2ca
PM		 2756static struct platform_driver sci_driver = {
2757 .probe = sci_probe,
b9e39c89 2758 .remove = sci_remove,
e108b2ca
PM		 2759 .driver = {
2760 .name = "sh-sci",
6daa79b3 2761 .pm = &sci_dev_pm_ops,
20bdcab8 2762 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2763 },
2764};
2765
2766static int __init sci_init(void)
2767{
2768 int ret;
2769
6c13d5d2 2770 pr_info("%s\n", banner);
e108b2ca 2771
e108b2ca
PM		 2772 ret = uart_register_driver(&sci_uart_driver);
2773 if (likely(ret == 0)) {
2774 ret = platform_driver_register(&sci_driver);
2775 if (unlikely(ret))
2776 uart_unregister_driver(&sci_uart_driver);
2777 }
2778
2779 return ret;
2780}
2781
2782static void __exit sci_exit(void)
2783{
2784 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2785 uart_unregister_driver(&sci_uart_driver);
2786}
2787
7b6fd3bf
MD		 2788#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2789early_platform_init_buffer("earlyprintk", &sci_driver,
2790 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2791#endif
1da177e4
LT		 2792module_init(sci_init);
2793module_exit(sci_exit);
2794
e108b2ca 2795MODULE_LICENSE("GPL");
e169c139 2796MODULE_ALIAS("platform:sh-sci");
7f405f9c 2797MODULE_AUTHOR("Paul Mundt");
f303b364 2798MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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