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serial: sh-sci: Remove platform data scbrr_algo_id field
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
8fb9631c 42#include <linux/platform_device.h>
5e50d2d6 43#include <linux/pm_runtime.h>
73a19e4c 44#include <linux/scatterlist.h>
8fb9631c
LP		 45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
5a0e3ad6 48#include <linux/slab.h>
8fb9631c
LP		 49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
1da177e4
LT		 59#include "sh-sci.h"
60
e108b2ca
PM		 61struct sci_port {
62 struct uart_port port;
63
ce6738b6
PM		 64 /* Platform configuration */
65 struct plat_sci_port *cfg;
3ae988d9
LP		 66 int overrun_bit;
67 unsigned int error_mask;
ec09c5eb 68 unsigned int sampling_rate;
3ae988d9 69
e108b2ca 70
e108b2ca
PM		 71 /* Break timer */
72 struct timer_list break_timer;
73 int break_flag;
1534a3b3 74
501b825d
MD		 75 /* Interface clock */
76 struct clk *iclk;
c7ed1ab3
PM		 77 /* Function clock */
78 struct clk *fclk;
edad1f20 79
1fcc91a6 80 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 81 char *irqstr[SCIx_NR_IRQS];
82
73a19e4c
GL		 83 struct dma_chan *chan_tx;
84 struct dma_chan *chan_rx;
f43dc23d 85
73a19e4c 86#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 87 struct dma_async_tx_descriptor *desc_tx;
88 struct dma_async_tx_descriptor *desc_rx[2];
89 dma_cookie_t cookie_tx;
90 dma_cookie_t cookie_rx[2];
91 dma_cookie_t active_rx;
92 struct scatterlist sg_tx;
93 unsigned int sg_len_tx;
94 struct scatterlist sg_rx[2];
95 size_t buf_len_rx;
96 struct sh_dmae_slave param_tx;
97 struct sh_dmae_slave param_rx;
98 struct work_struct work_tx;
99 struct work_struct work_rx;
100 struct timer_list rx_timer;
3089f381 101 unsigned int rx_timeout;
73a19e4c 102#endif
e552de24 103
d535a230 104 struct notifier_block freq_transition;
e108b2ca
PM		 105};
106
1da177e4 107/* Function prototypes */
d535a230 108static void sci_start_tx(struct uart_port *port);
b129a8cc 109static void sci_stop_tx(struct uart_port *port);
d535a230 110static void sci_start_rx(struct uart_port *port);
1da177e4 111
e108b2ca 112#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 113
e108b2ca
PM		 114static struct sci_port sci_ports[SCI_NPORTS];
115static struct uart_driver sci_uart_driver;
1da177e4 116
e7c98dc7
MT		 117static inline struct sci_port *
118to_sci_port(struct uart_port *uart)
119{
120 return container_of(uart, struct sci_port, port);
121}
122
61a6976b
PM		 123struct plat_sci_reg {
124 u8 offset, size;
125};
126
127/* Helper for invalidating specific entries of an inherited map. */
128#define sci_reg_invalid { .offset = 0, .size = 0 }
129
130static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
131 [SCIx_PROBE_REGTYPE] = {
132 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 },
134
135 /*
136 * Common SCI definitions, dependent on the port's regshift
137 * value.
138 */
139 [SCIx_SCI_REGTYPE] = {
140 [SCSMR] = { 0x00, 8 },
141 [SCBRR] = { 0x01, 8 },
142 [SCSCR] = { 0x02, 8 },
143 [SCxTDR] = { 0x03, 8 },
144 [SCxSR] = { 0x04, 8 },
145 [SCxRDR] = { 0x05, 8 },
146 [SCFCR] = sci_reg_invalid,
147 [SCFDR] = sci_reg_invalid,
148 [SCTFDR] = sci_reg_invalid,
149 [SCRFDR] = sci_reg_invalid,
150 [SCSPTR] = sci_reg_invalid,
151 [SCLSR] = sci_reg_invalid,
f303b364 152 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 153 },
154
155 /*
156 * Common definitions for legacy IrDA ports, dependent on
157 * regshift value.
158 */
159 [SCIx_IRDA_REGTYPE] = {
160 [SCSMR] = { 0x00, 8 },
161 [SCBRR] = { 0x01, 8 },
162 [SCSCR] = { 0x02, 8 },
163 [SCxTDR] = { 0x03, 8 },
164 [SCxSR] = { 0x04, 8 },
165 [SCxRDR] = { 0x05, 8 },
166 [SCFCR] = { 0x06, 8 },
167 [SCFDR] = { 0x07, 16 },
168 [SCTFDR] = sci_reg_invalid,
169 [SCRFDR] = sci_reg_invalid,
170 [SCSPTR] = sci_reg_invalid,
171 [SCLSR] = sci_reg_invalid,
f303b364 172 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 173 },
174
175 /*
176 * Common SCIFA definitions.
177 */
178 [SCIx_SCIFA_REGTYPE] = {
179 [SCSMR] = { 0x00, 16 },
180 [SCBRR] = { 0x04, 8 },
181 [SCSCR] = { 0x08, 16 },
182 [SCxTDR] = { 0x20, 8 },
183 [SCxSR] = { 0x14, 16 },
184 [SCxRDR] = { 0x24, 8 },
185 [SCFCR] = { 0x18, 16 },
186 [SCFDR] = { 0x1c, 16 },
187 [SCTFDR] = sci_reg_invalid,
188 [SCRFDR] = sci_reg_invalid,
189 [SCSPTR] = sci_reg_invalid,
190 [SCLSR] = sci_reg_invalid,
f303b364 191 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 192 },
193
194 /*
195 * Common SCIFB definitions.
196 */
197 [SCIx_SCIFB_REGTYPE] = {
198 [SCSMR] = { 0x00, 16 },
199 [SCBRR] = { 0x04, 8 },
200 [SCSCR] = { 0x08, 16 },
201 [SCxTDR] = { 0x40, 8 },
202 [SCxSR] = { 0x14, 16 },
203 [SCxRDR] = { 0x60, 8 },
204 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 205 [SCFDR] = sci_reg_invalid,
206 [SCTFDR] = { 0x38, 16 },
207 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 208 [SCSPTR] = sci_reg_invalid,
209 [SCLSR] = sci_reg_invalid,
f303b364 210 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 211 },
212
3af1f8a4
PE		 213 /*
214 * Common SH-2(A) SCIF definitions for ports with FIFO data
215 * count registers.
216 */
217 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
218 [SCSMR] = { 0x00, 16 },
219 [SCBRR] = { 0x04, 8 },
220 [SCSCR] = { 0x08, 16 },
221 [SCxTDR] = { 0x0c, 8 },
222 [SCxSR] = { 0x10, 16 },
223 [SCxRDR] = { 0x14, 8 },
224 [SCFCR] = { 0x18, 16 },
225 [SCFDR] = { 0x1c, 16 },
226 [SCTFDR] = sci_reg_invalid,
227 [SCRFDR] = sci_reg_invalid,
228 [SCSPTR] = { 0x20, 16 },
229 [SCLSR] = { 0x24, 16 },
f303b364 230 [HSSRR] = sci_reg_invalid,
3af1f8a4
PE		 231 },
232
61a6976b
PM		 233 /*
234 * Common SH-3 SCIF definitions.
235 */
236 [SCIx_SH3_SCIF_REGTYPE] = {
237 [SCSMR] = { 0x00, 8 },
238 [SCBRR] = { 0x02, 8 },
239 [SCSCR] = { 0x04, 8 },
240 [SCxTDR] = { 0x06, 8 },
241 [SCxSR] = { 0x08, 16 },
242 [SCxRDR] = { 0x0a, 8 },
243 [SCFCR] = { 0x0c, 8 },
244 [SCFDR] = { 0x0e, 16 },
245 [SCTFDR] = sci_reg_invalid,
246 [SCRFDR] = sci_reg_invalid,
247 [SCSPTR] = sci_reg_invalid,
248 [SCLSR] = sci_reg_invalid,
f303b364 249 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 250 },
251
252 /*
253 * Common SH-4(A) SCIF(B) definitions.
254 */
255 [SCIx_SH4_SCIF_REGTYPE] = {
256 [SCSMR] = { 0x00, 16 },
257 [SCBRR] = { 0x04, 8 },
258 [SCSCR] = { 0x08, 16 },
259 [SCxTDR] = { 0x0c, 8 },
260 [SCxSR] = { 0x10, 16 },
261 [SCxRDR] = { 0x14, 8 },
262 [SCFCR] = { 0x18, 16 },
263 [SCFDR] = { 0x1c, 16 },
264 [SCTFDR] = sci_reg_invalid,
265 [SCRFDR] = sci_reg_invalid,
266 [SCSPTR] = { 0x20, 16 },
267 [SCLSR] = { 0x24, 16 },
f303b364
UH		 268 [HSSRR] = sci_reg_invalid,
269 },
270
271 /*
272 * Common HSCIF definitions.
273 */
274 [SCIx_HSCIF_REGTYPE] = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCTFDR] = sci_reg_invalid,
284 [SCRFDR] = sci_reg_invalid,
285 [SCSPTR] = { 0x20, 16 },
286 [SCLSR] = { 0x24, 16 },
287 [HSSRR] = { 0x40, 16 },
61a6976b
PM		 288 },
289
290 /*
291 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
292 * register.
293 */
294 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
295 [SCSMR] = { 0x00, 16 },
296 [SCBRR] = { 0x04, 8 },
297 [SCSCR] = { 0x08, 16 },
298 [SCxTDR] = { 0x0c, 8 },
299 [SCxSR] = { 0x10, 16 },
300 [SCxRDR] = { 0x14, 8 },
301 [SCFCR] = { 0x18, 16 },
302 [SCFDR] = { 0x1c, 16 },
303 [SCTFDR] = sci_reg_invalid,
304 [SCRFDR] = sci_reg_invalid,
305 [SCSPTR] = sci_reg_invalid,
306 [SCLSR] = { 0x24, 16 },
f303b364 307 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 308 },
309
310 /*
311 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
312 * count registers.
313 */
314 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
315 [SCSMR] = { 0x00, 16 },
316 [SCBRR] = { 0x04, 8 },
317 [SCSCR] = { 0x08, 16 },
318 [SCxTDR] = { 0x0c, 8 },
319 [SCxSR] = { 0x10, 16 },
320 [SCxRDR] = { 0x14, 8 },
321 [SCFCR] = { 0x18, 16 },
322 [SCFDR] = { 0x1c, 16 },
323 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
324 [SCRFDR] = { 0x20, 16 },
325 [SCSPTR] = { 0x24, 16 },
326 [SCLSR] = { 0x28, 16 },
f303b364 327 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 328 },
329
330 /*
331 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
332 * registers.
333 */
334 [SCIx_SH7705_SCIF_REGTYPE] = {
335 [SCSMR] = { 0x00, 16 },
336 [SCBRR] = { 0x04, 8 },
337 [SCSCR] = { 0x08, 16 },
338 [SCxTDR] = { 0x20, 8 },
339 [SCxSR] = { 0x14, 16 },
340 [SCxRDR] = { 0x24, 8 },
341 [SCFCR] = { 0x18, 16 },
342 [SCFDR] = { 0x1c, 16 },
343 [SCTFDR] = sci_reg_invalid,
344 [SCRFDR] = sci_reg_invalid,
345 [SCSPTR] = sci_reg_invalid,
346 [SCLSR] = sci_reg_invalid,
f303b364 347 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 348 },
349};
350
72b294cf
PM		 351#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
352
61a6976b
PM		 353/*
354 * The "offset" here is rather misleading, in that it refers to an enum
355 * value relative to the port mapping rather than the fixed offset
356 * itself, which needs to be manually retrieved from the platform's
357 * register map for the given port.
358 */
359static unsigned int sci_serial_in(struct uart_port *p, int offset)
360{
72b294cf 361 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 362
363 if (reg->size == 8)
364 return ioread8(p->membase + (reg->offset << p->regshift));
365 else if (reg->size == 16)
366 return ioread16(p->membase + (reg->offset << p->regshift));
367 else
368 WARN(1, "Invalid register access\n");
369
370 return 0;
371}
372
373static void sci_serial_out(struct uart_port *p, int offset, int value)
374{
72b294cf 375 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 376
377 if (reg->size == 8)
378 iowrite8(value, p->membase + (reg->offset << p->regshift));
379 else if (reg->size == 16)
380 iowrite16(value, p->membase + (reg->offset << p->regshift));
381 else
382 WARN(1, "Invalid register access\n");
383}
384
61a6976b
PM		 385static int sci_probe_regmap(struct plat_sci_port *cfg)
386{
387 switch (cfg->type) {
388 case PORT_SCI:
389 cfg->regtype = SCIx_SCI_REGTYPE;
390 break;
391 case PORT_IRDA:
392 cfg->regtype = SCIx_IRDA_REGTYPE;
393 break;
394 case PORT_SCIFA:
395 cfg->regtype = SCIx_SCIFA_REGTYPE;
396 break;
397 case PORT_SCIFB:
398 cfg->regtype = SCIx_SCIFB_REGTYPE;
399 break;
400 case PORT_SCIF:
401 /*
402 * The SH-4 is a bit of a misnomer here, although that's
403 * where this particular port layout originated. This
404 * configuration (or some slight variation thereof)
405 * remains the dominant model for all SCIFs.
406 */
407 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
408 break;
f303b364
UH		 409 case PORT_HSCIF:
410 cfg->regtype = SCIx_HSCIF_REGTYPE;
411 break;
61a6976b
PM		 412 default:
413 printk(KERN_ERR "Can't probe register map for given port\n");
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
23241d43
PM		 420static void sci_port_enable(struct sci_port *sci_port)
421{
422 if (!sci_port->port.dev)
423 return;
424
425 pm_runtime_get_sync(sci_port->port.dev);
426
b016b646 427 clk_prepare_enable(sci_port->iclk);
23241d43 428 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 429 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 430}
431
432static void sci_port_disable(struct sci_port *sci_port)
433{
434 if (!sci_port->port.dev)
435 return;
436
caec7038
LP		 437 /* Cancel the break timer to ensure that the timer handler will not try
438 * to access the hardware with clocks and power disabled. Reset the
439 * break flag to make the break debouncing state machine ready for the
440 * next break.
441 */
442 del_timer_sync(&sci_port->break_timer);
443 sci_port->break_flag = 0;
444
b016b646
LP		 445 clk_disable_unprepare(sci_port->fclk);
446 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 447
448 pm_runtime_put_sync(sci_port->port.dev);
449}
450
07d2a1a1 451#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 452
453#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 454static int sci_poll_get_char(struct uart_port *port)
1da177e4 455{
1da177e4
LT		 456 unsigned short status;
457 int c;
458
e108b2ca 459 do {
b12bb29f 460 status = serial_port_in(port, SCxSR);
1da177e4 461 if (status & SCxSR_ERRORS(port)) {
b12bb29f 462 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 463 continue;
464 }
3f255eb3
JW		 465 break;
466 } while (1);
467
468 if (!(status & SCxSR_RDxF(port)))
469 return NO_POLL_CHAR;
07d2a1a1 470
b12bb29f 471 c = serial_port_in(port, SCxRDR);
07d2a1a1 472
e7c98dc7 473 /* Dummy read */
b12bb29f
PM		 474 serial_port_in(port, SCxSR);
475 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 476
477 return c;
478}
1f6fd5c9 479#endif
1da177e4 480
07d2a1a1 481static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 482{
1da177e4
LT		 483 unsigned short status;
484
1da177e4 485 do {
b12bb29f 486 status = serial_port_in(port, SCxSR);
1da177e4
LT		 487 } while (!(status & SCxSR_TDxE(port)));
488
b12bb29f
PM		 489 serial_port_out(port, SCxTDR, c);
490 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 491}
07d2a1a1 492#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 493
61a6976b 494static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 495{
61a6976b
PM		 496 struct sci_port *s = to_sci_port(port);
497 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 498
61a6976b
PM		 499 /*
500 * Use port-specific handler if provided.
501 */
502 if (s->cfg->ops && s->cfg->ops->init_pins) {
503 s->cfg->ops->init_pins(port, cflag);
504 return;
1da177e4 505 }
41504c39 506
61a6976b
PM		 507 /*
508 * For the generic path SCSPTR is necessary. Bail out if that's
509 * unavailable, too.
510 */
511 if (!reg->size)
512 return;
41504c39 513
faf02f8f
PM		 514 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
515 ((!(cflag & CRTSCTS)))) {
516 unsigned short status;
517
b12bb29f 518 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 519 status &= ~SCSPTR_CTSIO;
520 status |= SCSPTR_RTSIO;
b12bb29f 521 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 522 }
d5701647 523}
e108b2ca 524
72b294cf 525static int sci_txfill(struct uart_port *port)
e108b2ca 526{
72b294cf 527 struct plat_sci_reg *reg;
e108b2ca 528
72b294cf
PM		 529 reg = sci_getreg(port, SCTFDR);
530 if (reg->size)
63f7ad11 531 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 532
72b294cf
PM		 533 reg = sci_getreg(port, SCFDR);
534 if (reg->size)
b12bb29f 535 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 536
b12bb29f 537 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 538}
539
73a19e4c
GL		 540static int sci_txroom(struct uart_port *port)
541{
72b294cf 542 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 543}
544
545static int sci_rxfill(struct uart_port *port)
e108b2ca 546{
72b294cf
PM		 547 struct plat_sci_reg *reg;
548
549 reg = sci_getreg(port, SCRFDR);
550 if (reg->size)
63f7ad11 551 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 552
553 reg = sci_getreg(port, SCFDR);
554 if (reg->size)
b12bb29f 555 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 556
b12bb29f 557 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 558}
559
514820eb
PM		 560/*
561 * SCI helper for checking the state of the muxed port/RXD pins.
562 */
563static inline int sci_rxd_in(struct uart_port *port)
564{
565 struct sci_port *s = to_sci_port(port);
566
567 if (s->cfg->port_reg <= 0)
568 return 1;
569
0dd4d5cb 570 /* Cast for ARM damage */
e2afca69 571 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 572}
573
1da177e4
LT		 574/* ********************************************************************** *
575 * the interrupt related routines *
576 * ********************************************************************** */
577
578static void sci_transmit_chars(struct uart_port *port)
579{
ebd2c8f6 580 struct circ_buf *xmit = &port->state->xmit;
1da177e4 581 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 582 unsigned short status;
583 unsigned short ctrl;
e108b2ca 584 int count;
1da177e4 585
b12bb29f 586 status = serial_port_in(port, SCxSR);
1da177e4 587 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 588 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 589 if (uart_circ_empty(xmit))
8e698614 590 ctrl &= ~SCSCR_TIE;
e7c98dc7 591 else
8e698614 592 ctrl |= SCSCR_TIE;
b12bb29f 593 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 594 return;
595 }
596
72b294cf 597 count = sci_txroom(port);
1da177e4
LT		 598
599 do {
600 unsigned char c;
601
602 if (port->x_char) {
603 c = port->x_char;
604 port->x_char = 0;
605 } else if (!uart_circ_empty(xmit) && !stopped) {
606 c = xmit->buf[xmit->tail];
607 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
608 } else {
609 break;
610 }
611
b12bb29f 612 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 613
614 port->icount.tx++;
615 } while (--count > 0);
616
b12bb29f 617 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 618
619 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
620 uart_write_wakeup(port);
621 if (uart_circ_empty(xmit)) {
b129a8cc 622 sci_stop_tx(port);
1da177e4 623 } else {
b12bb29f 624 ctrl = serial_port_in(port, SCSCR);
1da177e4 625
1a22f08d 626 if (port->type != PORT_SCI) {
b12bb29f
PM		 627 serial_port_in(port, SCxSR); /* Dummy read */
628 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 629 }
1da177e4 630
8e698614 631 ctrl |= SCSCR_TIE;
b12bb29f 632 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 633 }
634}
635
636/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 637#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 638
94c8b6db 639static void sci_receive_chars(struct uart_port *port)
1da177e4 640{
e7c98dc7 641 struct sci_port *sci_port = to_sci_port(port);
227434f8 642 struct tty_port *tport = &port->state->port;
1da177e4
LT		 643 int i, count, copied = 0;
644 unsigned short status;
33f0f88f 645 unsigned char flag;
1da177e4 646
b12bb29f 647 status = serial_port_in(port, SCxSR);
1da177e4
LT		 648 if (!(status & SCxSR_RDxF(port)))
649 return;
650
651 while (1) {
1da177e4 652 /* Don't copy more bytes than there is room for in the buffer */
227434f8 653 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 654
655 /* If for any reason we can't copy more data, we're done! */
656 if (count == 0)
657 break;
658
659 if (port->type == PORT_SCI) {
b12bb29f 660 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 661 if (uart_handle_sysrq_char(port, c) ||
662 sci_port->break_flag)
1da177e4 663 count = 0;
e7c98dc7 664 else
92a19f9c 665 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 666 } else {
e7c98dc7 667 for (i = 0; i < count; i++) {
b12bb29f 668 char c = serial_port_in(port, SCxRDR);
d97fbbed 669
b12bb29f 670 status = serial_port_in(port, SCxSR);
1da177e4
LT		 671#if defined(CONFIG_CPU_SH3)
672 /* Skip "chars" during break */
e108b2ca 673 if (sci_port->break_flag) {
1da177e4
LT		 674 if ((c == 0) &&
675 (status & SCxSR_FER(port))) {
676 count--; i--;
677 continue;
678 }
e108b2ca 679
1da177e4 680 /* Nonzero => end-of-break */
762c69e3 681 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 682 sci_port->break_flag = 0;
683
1da177e4
LT		 684 if (STEPFN(c)) {
685 count--; i--;
686 continue;
687 }
688 }
689#endif /* CONFIG_CPU_SH3 */
7d12e780 690 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 691 count--; i--;
692 continue;
693 }
694
695 /* Store data and status */
73a19e4c 696 if (status & SCxSR_FER(port)) {
33f0f88f 697 flag = TTY_FRAME;
d97fbbed 698 port->icount.frame++;
762c69e3 699 dev_notice(port->dev, "frame error\n");
73a19e4c 700 } else if (status & SCxSR_PER(port)) {
33f0f88f 701 flag = TTY_PARITY;
d97fbbed 702 port->icount.parity++;
762c69e3 703 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 704 } else
705 flag = TTY_NORMAL;
762c69e3 706
92a19f9c 707 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 708 }
709 }
710
b12bb29f
PM		 711 serial_port_in(port, SCxSR); /* dummy read */
712 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 713
1da177e4
LT		 714 copied += count;
715 port->icount.rx += count;
716 }
717
718 if (copied) {
719 /* Tell the rest of the system the news. New characters! */
2e124b4a 720 tty_flip_buffer_push(tport);
1da177e4 721 } else {
b12bb29f
PM		 722 serial_port_in(port, SCxSR); /* dummy read */
723 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 724 }
725}
726
727#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 728
729/*
730 * The sci generates interrupts during the break,
1da177e4
LT		 731 * 1 per millisecond or so during the break period, for 9600 baud.
732 * So dont bother disabling interrupts.
733 * But dont want more than 1 break event.
734 * Use a kernel timer to periodically poll the rx line until
735 * the break is finished.
736 */
94c8b6db 737static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 738{
bc9b3f5c 739 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 740}
94c8b6db 741
1da177e4
LT		 742/* Ensure that two consecutive samples find the break over. */
743static void sci_break_timer(unsigned long data)
744{
e108b2ca
PM		 745 struct sci_port *port = (struct sci_port *)data;
746
747 if (sci_rxd_in(&port->port) == 0) {
1da177e4 748 port->break_flag = 1;
e108b2ca
PM		 749 sci_schedule_break_timer(port);
750 } else if (port->break_flag == 1) {
1da177e4
LT		 751 /* break is over. */
752 port->break_flag = 2;
e108b2ca
PM		 753 sci_schedule_break_timer(port);
754 } else
755 port->break_flag = 0;
1da177e4
LT		 756}
757
94c8b6db 758static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 759{
760 int copied = 0;
b12bb29f 761 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 762 struct tty_port *tport = &port->state->port;
debf9507 763 struct sci_port *s = to_sci_port(port);
1da177e4 764
3ae988d9
LP		 765 /* Handle overruns */
766 if (status & (1 << s->overrun_bit)) {
767 port->icount.overrun++;
d97fbbed 768
3ae988d9
LP		 769 /* overrun error */
770 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
771 copied++;
762c69e3 772
3ae988d9 773 dev_notice(port->dev, "overrun error");
1da177e4
LT		 774 }
775
e108b2ca 776 if (status & SCxSR_FER(port)) {
1da177e4
LT		 777 if (sci_rxd_in(port) == 0) {
778 /* Notify of BREAK */
e7c98dc7 779 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 780
781 if (!sci_port->break_flag) {
d97fbbed
PM		 782 port->icount.brk++;
783
e108b2ca
PM		 784 sci_port->break_flag = 1;
785 sci_schedule_break_timer(sci_port);
786
1da177e4 787 /* Do sysrq handling. */
e108b2ca 788 if (uart_handle_break(port))
1da177e4 789 return 0;
762c69e3
PM		 790
791 dev_dbg(port->dev, "BREAK detected\n");
792
92a19f9c 793 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 794 copied++;
795 }
796
e108b2ca 797 } else {
1da177e4 798 /* frame error */
d97fbbed
PM		 799 port->icount.frame++;
800
92a19f9c 801 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 802 copied++;
762c69e3
PM		 803
804 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 805 }
806 }
807
e108b2ca 808 if (status & SCxSR_PER(port)) {
1da177e4 809 /* parity error */
d97fbbed
PM		 810 port->icount.parity++;
811
92a19f9c 812 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 813 copied++;
762c69e3
PM		 814
815 dev_notice(port->dev, "parity error");
1da177e4
LT		 816 }
817
33f0f88f 818 if (copied)
2e124b4a 819 tty_flip_buffer_push(tport);
1da177e4
LT		 820
821 return copied;
822}
823
94c8b6db 824static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 825{
92a19f9c 826 struct tty_port *tport = &port->state->port;
debf9507 827 struct sci_port *s = to_sci_port(port);
4b8c59a3 828 struct plat_sci_reg *reg;
d830fa45
PM		 829 int copied = 0;
830
4b8c59a3
PM		 831 reg = sci_getreg(port, SCLSR);
832 if (!reg->size)
d830fa45
PM		 833 return 0;
834
3ae988d9 835 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
b12bb29f 836 serial_port_out(port, SCLSR, 0);
d830fa45 837
d97fbbed
PM		 838 port->icount.overrun++;
839
92a19f9c 840 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 841 tty_flip_buffer_push(tport);
d830fa45
PM		 842
843 dev_notice(port->dev, "overrun error\n");
844 copied++;
845 }
846
847 return copied;
848}
849
94c8b6db 850static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 851{
852 int copied = 0;
b12bb29f 853 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 854 struct tty_port *tport = &port->state->port;
a5660ada 855 struct sci_port *s = to_sci_port(port);
1da177e4 856
0b3d4ef6
PM		 857 if (uart_handle_break(port))
858 return 0;
859
b7a76e4b 860 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 861#if defined(CONFIG_CPU_SH3)
862 /* Debounce break */
863 s->break_flag = 1;
864#endif
d97fbbed
PM		 865
866 port->icount.brk++;
867
1da177e4 868 /* Notify of BREAK */
92a19f9c 869 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 870 copied++;
762c69e3
PM		 871
872 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 873 }
874
33f0f88f 875 if (copied)
2e124b4a 876 tty_flip_buffer_push(tport);
e108b2ca 877
d830fa45
PM		 878 copied += sci_handle_fifo_overrun(port);
879
1da177e4
LT		 880 return copied;
881}
882
73a19e4c 883static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 884{
73a19e4c
GL		 885#ifdef CONFIG_SERIAL_SH_SCI_DMA
886 struct uart_port *port = ptr;
887 struct sci_port *s = to_sci_port(port);
888
889 if (s->chan_rx) {
b12bb29f
PM		 890 u16 scr = serial_port_in(port, SCSCR);
891 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 892
893 /* Disable future Rx interrupts */
d1d4b10c 894 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 895 disable_irq_nosync(irq);
896 scr |= 0x4000;
897 } else {
f43dc23d 898 scr &= ~SCSCR_RIE;
3089f381 899 }
b12bb29f 900 serial_port_out(port, SCSCR, scr);
73a19e4c 901 /* Clear current interrupt */
b12bb29f 902 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 903 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
904 jiffies, s->rx_timeout);
905 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 906
907 return IRQ_HANDLED;
908 }
909#endif
910
1da177e4
LT		 911 /* I think sci_receive_chars has to be called irrespective
912 * of whether the I_IXOFF is set, otherwise, how is the interrupt
913 * to be disabled?
914 */
73a19e4c 915 sci_receive_chars(ptr);
1da177e4
LT		 916
917 return IRQ_HANDLED;
918}
919
7d12e780 920static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 921{
922 struct uart_port *port = ptr;
fd78a76a 923 unsigned long flags;
1da177e4 924
fd78a76a 925 spin_lock_irqsave(&port->lock, flags);
1da177e4 926 sci_transmit_chars(port);
fd78a76a 927 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 928
929 return IRQ_HANDLED;
930}
931
7d12e780 932static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 933{
934 struct uart_port *port = ptr;
935
936 /* Handle errors */
937 if (port->type == PORT_SCI) {
938 if (sci_handle_errors(port)) {
939 /* discard character in rx buffer */
b12bb29f
PM		 940 serial_port_in(port, SCxSR);
941 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 942 }
943 } else {
d830fa45 944 sci_handle_fifo_overrun(port);
7d12e780 945 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 946 }
947
b12bb29f 948 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 949
950 /* Kick the transmission */
7d12e780 951 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 952
953 return IRQ_HANDLED;
954}
955
7d12e780 956static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 957{
958 struct uart_port *port = ptr;
959
960 /* Handle BREAKs */
961 sci_handle_breaks(port);
b12bb29f 962 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 963
964 return IRQ_HANDLED;
965}
966
f43dc23d
PM		 967static inline unsigned long port_rx_irq_mask(struct uart_port *port)
968{
969 /*
970 * Not all ports (such as SCIFA) will support REIE. Rather than
971 * special-casing the port type, we check the port initialization
972 * IRQ enable mask to see whether the IRQ is desired at all. If
973 * it's unset, it's logically inferred that there's no point in
974 * testing for it.
975 */
ce6738b6 976 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 977}
978
7d12e780 979static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 980{
44e18e9e 981 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 982 struct uart_port *port = ptr;
73a19e4c 983 struct sci_port *s = to_sci_port(port);
a8884e34 984 irqreturn_t ret = IRQ_NONE;
1da177e4 985
b12bb29f
PM		 986 ssr_status = serial_port_in(port, SCxSR);
987 scr_status = serial_port_in(port, SCSCR);
f43dc23d 988 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 989
990 /* Tx Interrupt */
f43dc23d 991 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 992 !s->chan_tx)
a8884e34 993 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 994
73a19e4c
GL		 995 /*
996 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
997 * DR flags
998 */
999 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 1000 (scr_status & SCSCR_RIE))
a8884e34 1001 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1002
1da177e4 1003 /* Error Interrupt */
dd4da3a5 1004 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1005 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1006
1da177e4 1007 /* Break Interrupt */
dd4da3a5 1008 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1009 ret = sci_br_interrupt(irq, ptr);
1da177e4 1010
a8884e34 1011 return ret;
1da177e4
LT		 1012}
1013
1da177e4 1014/*
25985edc 1015 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1016 * ports' baud rate when the peripheral clock changes.
1017 */
e108b2ca
PM		 1018static int sci_notifier(struct notifier_block *self,
1019 unsigned long phase, void *p)
1da177e4 1020{
e552de24
MD		 1021 struct sci_port *sci_port;
1022 unsigned long flags;
1da177e4 1023
d535a230
PM		 1024 sci_port = container_of(self, struct sci_port, freq_transition);
1025
1da177e4 1026 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 1027 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 1028 struct uart_port *port = &sci_port->port;
073e84c9 1029
d535a230
PM		 1030 spin_lock_irqsave(&port->lock, flags);
1031 port->uartclk = clk_get_rate(sci_port->iclk);
1032 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1033 }
1da177e4 1034
1da177e4
LT		 1035 return NOTIFY_OK;
1036}
501b825d 1037
9174fc8f
PM		 1038static struct sci_irq_desc {
1039 const char *desc;
1040 irq_handler_t handler;
1041} sci_irq_desc[] = {
1042 /*
1043 * Split out handlers, the default case.
1044 */
1045 [SCIx_ERI_IRQ] = {
1046 .desc = "rx err",
1047 .handler = sci_er_interrupt,
1048 },
1049
1050 [SCIx_RXI_IRQ] = {
1051 .desc = "rx full",
1052 .handler = sci_rx_interrupt,
1053 },
1054
1055 [SCIx_TXI_IRQ] = {
1056 .desc = "tx empty",
1057 .handler = sci_tx_interrupt,
1058 },
1059
1060 [SCIx_BRI_IRQ] = {
1061 .desc = "break",
1062 .handler = sci_br_interrupt,
1063 },
1064
1065 /*
1066 * Special muxed handler.
1067 */
1068 [SCIx_MUX_IRQ] = {
1069 .desc = "mux",
1070 .handler = sci_mpxed_interrupt,
1071 },
1072};
1073
1da177e4
LT		 1074static int sci_request_irq(struct sci_port *port)
1075{
9174fc8f
PM		 1076 struct uart_port *up = &port->port;
1077 int i, j, ret = 0;
1078
1079 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1080 struct sci_irq_desc *desc;
1fcc91a6 1081 int irq;
9174fc8f
PM		 1082
1083 if (SCIx_IRQ_IS_MUXED(port)) {
1084 i = SCIx_MUX_IRQ;
1085 irq = up->irq;
0e8963de 1086 } else {
1fcc91a6 1087 irq = port->irqs[i];
9174fc8f 1088
0e8963de
PM		 1089 /*
1090 * Certain port types won't support all of the
1091 * available interrupt sources.
1092 */
1fcc91a6 1093 if (unlikely(irq < 0))
0e8963de
PM		 1094 continue;
1095 }
1096
9174fc8f
PM		 1097 desc = sci_irq_desc + i;
1098 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1099 dev_name(up->dev), desc->desc);
1100 if (!port->irqstr[j]) {
1101 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1102 desc->desc);
1103 goto out_nomem;
1da177e4 1104 }
9174fc8f
PM		 1105
1106 ret = request_irq(irq, desc->handler, up->irqflags,
1107 port->irqstr[j], port);
1108 if (unlikely(ret)) {
1109 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1110 goto out_noirq;
1da177e4
LT		 1111 }
1112 }
1113
1114 return 0;
9174fc8f
PM		 1115
1116out_noirq:
1117 while (--i >= 0)
1fcc91a6 1118 free_irq(port->irqs[i], port);
9174fc8f
PM		 1119
1120out_nomem:
1121 while (--j >= 0)
1122 kfree(port->irqstr[j]);
1123
1124 return ret;
1da177e4
LT		 1125}
1126
1127static void sci_free_irq(struct sci_port *port)
1128{
1129 int i;
1130
9174fc8f
PM		 1131 /*
1132 * Intentionally in reverse order so we iterate over the muxed
1133 * IRQ first.
1134 */
1135 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1136 int irq = port->irqs[i];
0e8963de
PM		 1137
1138 /*
1139 * Certain port types won't support all of the available
1140 * interrupt sources.
1141 */
1fcc91a6 1142 if (unlikely(irq < 0))
0e8963de
PM		 1143 continue;
1144
1fcc91a6 1145 free_irq(port->irqs[i], port);
9174fc8f 1146 kfree(port->irqstr[i]);
1da177e4 1147
9174fc8f
PM		 1148 if (SCIx_IRQ_IS_MUXED(port)) {
1149 /* If there's only one IRQ, we're done. */
1150 return;
1da177e4
LT		 1151 }
1152 }
1153}
1154
1155static unsigned int sci_tx_empty(struct uart_port *port)
1156{
b12bb29f 1157 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1158 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1159
1160 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1161}
1162
cdf7c42f
PM		 1163/*
1164 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1165 * CTS/RTS is supported in hardware by at least one port and controlled
1166 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1167 * handled via the ->init_pins() op, which is a bit of a one-way street,
1168 * lacking any ability to defer pin control -- this will later be
1169 * converted over to the GPIO framework).
dc7e3ef7
PM		 1170 *
1171 * Other modes (such as loopback) are supported generically on certain
1172 * port types, but not others. For these it's sufficient to test for the
1173 * existence of the support register and simply ignore the port type.
cdf7c42f 1174 */
1da177e4
LT		 1175static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1176{
dc7e3ef7
PM		 1177 if (mctrl & TIOCM_LOOP) {
1178 struct plat_sci_reg *reg;
1179
1180 /*
1181 * Standard loopback mode for SCFCR ports.
1182 */
1183 reg = sci_getreg(port, SCFCR);
1184 if (reg->size)
b12bb29f 1185 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1186 }
1da177e4
LT		 1187}
1188
1189static unsigned int sci_get_mctrl(struct uart_port *port)
1190{
cdf7c42f
PM		 1191 /*
1192 * CTS/RTS is handled in hardware when supported, while nothing
1193 * else is wired up. Keep it simple and simply assert DSR/CAR.
1194 */
1195 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1196}
1197
73a19e4c
GL		 1198#ifdef CONFIG_SERIAL_SH_SCI_DMA
1199static void sci_dma_tx_complete(void *arg)
1200{
1201 struct sci_port *s = arg;
1202 struct uart_port *port = &s->port;
1203 struct circ_buf *xmit = &port->state->xmit;
1204 unsigned long flags;
1205
1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1207
1208 spin_lock_irqsave(&port->lock, flags);
1209
f354a381 1210 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1211 xmit->tail &= UART_XMIT_SIZE - 1;
1212
f354a381 1213 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1214
1215 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1216 s->desc_tx = NULL;
1217
73a19e4c
GL		 1218 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1219 uart_write_wakeup(port);
1220
3089f381 1221 if (!uart_circ_empty(xmit)) {
49d4bcad 1222 s->cookie_tx = 0;
73a19e4c 1223 schedule_work(&s->work_tx);
49d4bcad
YT		 1224 } else {
1225 s->cookie_tx = -EINVAL;
1226 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1227 u16 ctrl = serial_port_in(port, SCSCR);
1228 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1229 }
3089f381
GL		 1230 }
1231
1232 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1233}
1234
1235/* Locking: called with port lock held */
92a19f9c 1236static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1237{
1238 struct uart_port *port = &s->port;
227434f8 1239 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1240 int i, active, room;
1241
227434f8 1242 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1243
1244 if (s->active_rx == s->cookie_rx[0]) {
1245 active = 0;
1246 } else if (s->active_rx == s->cookie_rx[1]) {
1247 active = 1;
1248 } else {
1249 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1250 return 0;
1251 }
1252
1253 if (room < count)
e2afca69 1254 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1255 count - room);
1256 if (!room)
1257 return room;
1258
1259 for (i = 0; i < room; i++)
92a19f9c 1260 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1261 TTY_NORMAL);
1262
1263 port->icount.rx += room;
1264
1265 return room;
1266}
1267
1268static void sci_dma_rx_complete(void *arg)
1269{
1270 struct sci_port *s = arg;
1271 struct uart_port *port = &s->port;
73a19e4c
GL		 1272 unsigned long flags;
1273 int count;
1274
3089f381 1275 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1276
1277 spin_lock_irqsave(&port->lock, flags);
1278
92a19f9c 1279 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1280
3089f381 1281 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1282
1283 spin_unlock_irqrestore(&port->lock, flags);
1284
1285 if (count)
2e124b4a 1286 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1287
1288 schedule_work(&s->work_rx);
1289}
1290
73a19e4c
GL		 1291static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1292{
1293 struct dma_chan *chan = s->chan_rx;
1294 struct uart_port *port = &s->port;
73a19e4c
GL		 1295
1296 s->chan_rx = NULL;
1297 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1298 dma_release_channel(chan);
85b8e3ff
GL		 1299 if (sg_dma_address(&s->sg_rx[0]))
1300 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1301 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1302 if (enable_pio)
1303 sci_start_rx(port);
1304}
1305
1306static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1307{
1308 struct dma_chan *chan = s->chan_tx;
1309 struct uart_port *port = &s->port;
73a19e4c
GL		 1310
1311 s->chan_tx = NULL;
1312 s->cookie_tx = -EINVAL;
1313 dma_release_channel(chan);
1314 if (enable_pio)
1315 sci_start_tx(port);
1316}
1317
1318static void sci_submit_rx(struct sci_port *s)
1319{
1320 struct dma_chan *chan = s->chan_rx;
1321 int i;
1322
1323 for (i = 0; i < 2; i++) {
1324 struct scatterlist *sg = &s->sg_rx[i];
1325 struct dma_async_tx_descriptor *desc;
1326
16052827 1327 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1328 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1329
1330 if (desc) {
1331 s->desc_rx[i] = desc;
1332 desc->callback = sci_dma_rx_complete;
1333 desc->callback_param = s;
1334 s->cookie_rx[i] = desc->tx_submit(desc);
1335 }
1336
1337 if (!desc || s->cookie_rx[i] < 0) {
1338 if (i) {
1339 async_tx_ack(s->desc_rx[0]);
1340 s->cookie_rx[0] = -EINVAL;
1341 }
1342 if (desc) {
1343 async_tx_ack(desc);
1344 s->cookie_rx[i] = -EINVAL;
1345 }
1346 dev_warn(s->port.dev,
1347 "failed to re-start DMA, using PIO\n");
1348 sci_rx_dma_release(s, true);
1349 return;
1350 }
3089f381
GL		 1351 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1352 s->cookie_rx[i], i);
73a19e4c
GL		 1353 }
1354
1355 s->active_rx = s->cookie_rx[0];
1356
1357 dma_async_issue_pending(chan);
1358}
1359
1360static void work_fn_rx(struct work_struct *work)
1361{
1362 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1363 struct uart_port *port = &s->port;
1364 struct dma_async_tx_descriptor *desc;
1365 int new;
1366
1367 if (s->active_rx == s->cookie_rx[0]) {
1368 new = 0;
1369 } else if (s->active_rx == s->cookie_rx[1]) {
1370 new = 1;
1371 } else {
1372 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1373 return;
1374 }
1375 desc = s->desc_rx[new];
1376
1377 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1378 DMA_COMPLETE) {
73a19e4c 1379 /* Handle incomplete DMA receive */
73a19e4c 1380 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1381 struct shdma_desc *sh_desc = container_of(desc,
1382 struct shdma_desc, async_tx);
73a19e4c
GL		 1383 unsigned long flags;
1384 int count;
1385
05827630 1386 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
e2afca69 1387 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1388 sh_desc->partial, sh_desc->cookie);
1389
1390 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1391 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1392 spin_unlock_irqrestore(&port->lock, flags);
1393
1394 if (count)
2e124b4a 1395 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1396
1397 sci_submit_rx(s);
1398
1399 return;
1400 }
1401
1402 s->cookie_rx[new] = desc->tx_submit(desc);
1403 if (s->cookie_rx[new] < 0) {
1404 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1405 sci_rx_dma_release(s, true);
1406 return;
1407 }
1408
73a19e4c 1409 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1410
1411 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1412 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1413}
1414
1415static void work_fn_tx(struct work_struct *work)
1416{
1417 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1418 struct dma_async_tx_descriptor *desc;
1419 struct dma_chan *chan = s->chan_tx;
1420 struct uart_port *port = &s->port;
1421 struct circ_buf *xmit = &port->state->xmit;
1422 struct scatterlist *sg = &s->sg_tx;
1423
1424 /*
1425 * DMA is idle now.
1426 * Port xmit buffer is already mapped, and it is one page... Just adjust
1427 * offsets and lengths. Since it is a circular buffer, we have to
1428 * transmit till the end, and then the rest. Take the port lock to get a
1429 * consistent xmit buffer state.
1430 */
1431 spin_lock_irq(&port->lock);
1432 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1433 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1434 sg->offset;
f354a381 1435 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1436 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1437 spin_unlock_irq(&port->lock);
1438
f354a381 1439 BUG_ON(!sg_dma_len(sg));
73a19e4c 1440
16052827 1441 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1442 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1443 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1444 if (!desc) {
1445 /* switch to PIO */
1446 sci_tx_dma_release(s, true);
1447 return;
1448 }
1449
1450 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1451
1452 spin_lock_irq(&port->lock);
1453 s->desc_tx = desc;
1454 desc->callback = sci_dma_tx_complete;
1455 desc->callback_param = s;
1456 spin_unlock_irq(&port->lock);
1457 s->cookie_tx = desc->tx_submit(desc);
1458 if (s->cookie_tx < 0) {
1459 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1460 /* switch to PIO */
1461 sci_tx_dma_release(s, true);
1462 return;
1463 }
1464
1465 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1466 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1467
1468 dma_async_issue_pending(chan);
1469}
1470#endif
1471
b129a8cc 1472static void sci_start_tx(struct uart_port *port)
1da177e4 1473{
3089f381 1474 struct sci_port *s = to_sci_port(port);
e108b2ca 1475 unsigned short ctrl;
1da177e4 1476
73a19e4c 1477#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1478 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1479 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1480 if (s->chan_tx)
1481 new = scr | 0x8000;
1482 else
1483 new = scr & ~0x8000;
1484 if (new != scr)
b12bb29f 1485 serial_port_out(port, SCSCR, new);
73a19e4c 1486 }
f43dc23d 1487
3089f381 1488 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1489 s->cookie_tx < 0) {
1490 s->cookie_tx = 0;
3089f381 1491 schedule_work(&s->work_tx);
49d4bcad 1492 }
73a19e4c 1493#endif
f43dc23d 1494
d1d4b10c 1495 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1496 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1497 ctrl = serial_port_in(port, SCSCR);
1498 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1499 }
1da177e4
LT		 1500}
1501
b129a8cc 1502static void sci_stop_tx(struct uart_port *port)
1da177e4 1503{
1da177e4
LT		 1504 unsigned short ctrl;
1505
1506 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1507 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1508
d1d4b10c 1509 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1510 ctrl &= ~0x8000;
f43dc23d 1511
8e698614 1512 ctrl &= ~SCSCR_TIE;
f43dc23d 1513
b12bb29f 1514 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1515}
1516
73a19e4c 1517static void sci_start_rx(struct uart_port *port)
1da177e4 1518{
1da177e4
LT		 1519 unsigned short ctrl;
1520
b12bb29f 1521 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1522
d1d4b10c 1523 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1524 ctrl &= ~0x4000;
f43dc23d 1525
b12bb29f 1526 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1527}
1528
1529static void sci_stop_rx(struct uart_port *port)
1530{
1da177e4
LT		 1531 unsigned short ctrl;
1532
b12bb29f 1533 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1534
d1d4b10c 1535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1536 ctrl &= ~0x4000;
f43dc23d
PM		 1537
1538 ctrl &= ~port_rx_irq_mask(port);
1539
b12bb29f 1540 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1541}
1542
1543static void sci_enable_ms(struct uart_port *port)
1544{
d39ec6ce
PM		 1545 /*
1546 * Not supported by hardware, always a nop.
1547 */
1da177e4
LT		 1548}
1549
1550static void sci_break_ctl(struct uart_port *port, int break_state)
1551{
bbb4ce50 1552 struct sci_port *s = to_sci_port(port);
a4e02f6d 1553 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1554 unsigned short scscr, scsptr;
1555
a4e02f6d
SY		 1556 /* check wheter the port has SCSPTR */
1557 if (!reg->size) {
bbb4ce50
SY		 1558 /*
1559 * Not supported by hardware. Most parts couple break and rx
1560 * interrupts together, with break detection always enabled.
1561 */
a4e02f6d 1562 return;
bbb4ce50 1563 }
a4e02f6d
SY		 1564
1565 scsptr = serial_port_in(port, SCSPTR);
1566 scscr = serial_port_in(port, SCSCR);
1567
1568 if (break_state == -1) {
1569 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1570 scscr &= ~SCSCR_TE;
1571 } else {
1572 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1573 scscr |= SCSCR_TE;
1574 }
1575
1576 serial_port_out(port, SCSPTR, scsptr);
1577 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1578}
1579
73a19e4c
GL		 1580#ifdef CONFIG_SERIAL_SH_SCI_DMA
1581static bool filter(struct dma_chan *chan, void *slave)
1582{
1583 struct sh_dmae_slave *param = slave;
1584
1585 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1586 param->shdma_slave.slave_id);
73a19e4c 1587
d6fa5a4e 1588 chan->private = &param->shdma_slave;
937bb6e4 1589 return true;
73a19e4c
GL		 1590}
1591
1592static void rx_timer_fn(unsigned long arg)
1593{
1594 struct sci_port *s = (struct sci_port *)arg;
1595 struct uart_port *port = &s->port;
b12bb29f 1596 u16 scr = serial_port_in(port, SCSCR);
3089f381 1597
d1d4b10c 1598 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1599 scr &= ~0x4000;
1fcc91a6 1600 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1601 }
b12bb29f 1602 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1603 dev_dbg(port->dev, "DMA Rx timed out\n");
1604 schedule_work(&s->work_rx);
1605}
1606
1607static void sci_request_dma(struct uart_port *port)
1608{
1609 struct sci_port *s = to_sci_port(port);
1610 struct sh_dmae_slave *param;
1611 struct dma_chan *chan;
1612 dma_cap_mask_t mask;
1613 int nent;
1614
937bb6e4
GL		 1615 dev_dbg(port->dev, "%s: port %d\n", __func__,
1616 port->line);
73a19e4c 1617
937bb6e4 1618 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1619 return;
1620
1621 dma_cap_zero(mask);
1622 dma_cap_set(DMA_SLAVE, mask);
1623
1624 param = &s->param_tx;
1625
1626 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1627 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1628
1629 s->cookie_tx = -EINVAL;
1630 chan = dma_request_channel(mask, filter, param);
1631 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1632 if (chan) {
1633 s->chan_tx = chan;
1634 sg_init_table(&s->sg_tx, 1);
1635 /* UART circular tx buffer is an aligned page. */
e2afca69 1636 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1637 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1638 UART_XMIT_SIZE,
1639 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1640 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1641 if (!nent)
1642 sci_tx_dma_release(s, false);
1643 else
e2afca69
LP		 1644 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1645 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1646 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1647
1648 s->sg_len_tx = nent;
1649
1650 INIT_WORK(&s->work_tx, work_fn_tx);
1651 }
1652
1653 param = &s->param_rx;
1654
1655 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1656 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1657
1658 chan = dma_request_channel(mask, filter, param);
1659 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1660 if (chan) {
1661 dma_addr_t dma[2];
1662 void *buf[2];
1663 int i;
1664
1665 s->chan_rx = chan;
1666
1667 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1668 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1669 &dma[0], GFP_KERNEL);
1670
1671 if (!buf[0]) {
1672 dev_warn(port->dev,
1673 "failed to allocate dma buffer, using PIO\n");
1674 sci_rx_dma_release(s, true);
1675 return;
1676 }
1677
1678 buf[1] = buf[0] + s->buf_len_rx;
1679 dma[1] = dma[0] + s->buf_len_rx;
1680
1681 for (i = 0; i < 2; i++) {
1682 struct scatterlist *sg = &s->sg_rx[i];
1683
1684 sg_init_table(sg, 1);
1685 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1686 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1687 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1688 }
1689
1690 INIT_WORK(&s->work_rx, work_fn_rx);
1691 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1692
1693 sci_submit_rx(s);
1694 }
1695}
1696
1697static void sci_free_dma(struct uart_port *port)
1698{
1699 struct sci_port *s = to_sci_port(port);
1700
73a19e4c
GL		 1701 if (s->chan_tx)
1702 sci_tx_dma_release(s, false);
1703 if (s->chan_rx)
1704 sci_rx_dma_release(s, false);
1705}
27bd1075
PM		 1706#else
1707static inline void sci_request_dma(struct uart_port *port)
1708{
1709}
1710
1711static inline void sci_free_dma(struct uart_port *port)
1712{
1713}
73a19e4c
GL		 1714#endif
1715
1da177e4
LT		 1716static int sci_startup(struct uart_port *port)
1717{
a5660ada 1718 struct sci_port *s = to_sci_port(port);
33b48e16 1719 unsigned long flags;
073e84c9 1720 int ret;
1da177e4 1721
73a19e4c
GL		 1722 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1723
073e84c9
PM		 1724 ret = sci_request_irq(s);
1725 if (unlikely(ret < 0))
1726 return ret;
1727
73a19e4c 1728 sci_request_dma(port);
073e84c9 1729
33b48e16 1730 spin_lock_irqsave(&port->lock, flags);
d656901b 1731 sci_start_tx(port);
73a19e4c 1732 sci_start_rx(port);
33b48e16 1733 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1734
1735 return 0;
1736}
1737
1738static void sci_shutdown(struct uart_port *port)
1739{
a5660ada 1740 struct sci_port *s = to_sci_port(port);
33b48e16 1741 unsigned long flags;
1da177e4 1742
73a19e4c
GL		 1743 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1744
33b48e16 1745 spin_lock_irqsave(&port->lock, flags);
1da177e4 1746 sci_stop_rx(port);
b129a8cc 1747 sci_stop_tx(port);
33b48e16 1748 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1749
73a19e4c 1750 sci_free_dma(port);
1da177e4 1751 sci_free_irq(s);
1da177e4
LT		 1752}
1753
ec09c5eb 1754static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1755 unsigned long freq)
1756{
ec09c5eb
LP		 1757 if (s->sampling_rate)
1758 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1759
26c92f37
PM		 1760 /* Warn, but use a safe default */
1761 WARN_ON(1);
e8183a6c 1762
26c92f37
PM		 1763 return ((freq + 16 * bps) / (32 * bps) - 1);
1764}
1765
f303b364
UH		 1766/* calculate sample rate, BRR, and clock select for HSCIF */
1767static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1768 int *brr, unsigned int *srr,
1769 unsigned int *cks)
1770{
1771 int sr, c, br, err;
1772 int min_err = 1000; /* 100% */
1773
1774 /* Find the combination of sample rate and clock select with the
1775 smallest deviation from the desired baud rate. */
1776 for (sr = 8; sr <= 32; sr++) {
1777 for (c = 0; c <= 3; c++) {
1778 /* integerized formulas from HSCIF documentation */
1779 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1780 if (br < 0 || br > 255)
1781 continue;
1782 err = freq / ((br + 1) * bps * sr *
1783 (1 << (2 * c + 1)) / 1000) - 1000;
1784 if (min_err > err) {
1785 min_err = err;
1786 *brr = br;
1787 *srr = sr - 1;
1788 *cks = c;
1789 }
1790 }
1791 }
1792
1793 if (min_err == 1000) {
1794 WARN_ON(1);
1795 /* use defaults */
1796 *brr = 255;
1797 *srr = 15;
1798 *cks = 0;
1799 }
1800}
1801
1ba76220
MD		 1802static void sci_reset(struct uart_port *port)
1803{
0979e0e6 1804 struct plat_sci_reg *reg;
1ba76220
MD		 1805 unsigned int status;
1806
1807 do {
b12bb29f 1808 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1809 } while (!(status & SCxSR_TEND(port)));
1810
b12bb29f 1811 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1812
0979e0e6
PM		 1813 reg = sci_getreg(port, SCFCR);
1814 if (reg->size)
b12bb29f 1815 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1816}
1817
606d099c
AC		 1818static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1819 struct ktermios *old)
1da177e4 1820{
00b9de9c 1821 struct sci_port *s = to_sci_port(port);
0979e0e6 1822 struct plat_sci_reg *reg;
d4759ded 1823 unsigned int baud, smr_val, max_baud, cks = 0;
a2159b52 1824 int t = -1;
d4759ded 1825 unsigned int srr = 15;
1da177e4 1826
154280fd
MD		 1827 /*
1828 * earlyprintk comes here early on with port->uartclk set to zero.
1829 * the clock framework is not up and running at this point so here
1830 * we assume that 115200 is the maximum baud rate. please note that
1831 * the baud rate is not programmed during earlyprintk - it is assumed
1832 * that the previous boot loader has enabled required clocks and
1833 * setup the baud rate generator hardware for us already.
1834 */
1835 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1836
154280fd 1837 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1838 if (likely(baud && port->uartclk)) {
ec09c5eb 1839 if (s->cfg->type == PORT_HSCIF) {
f303b364
UH		 1840 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1841 &cks);
1842 } else {
ec09c5eb 1843 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1844 for (cks = 0; t >= 256 && cks <= 3; cks++)
1845 t >>= 2;
1846 }
1847 }
e108b2ca 1848
23241d43 1849 sci_port_enable(s);
36003386 1850
1ba76220 1851 sci_reset(port);
1da177e4 1852
b12bb29f 1853 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1854
1da177e4
LT		 1855 if ((termios->c_cflag & CSIZE) == CS7)
1856 smr_val |= 0x40;
1857 if (termios->c_cflag & PARENB)
1858 smr_val |= 0x20;
1859 if (termios->c_cflag & PARODD)
1860 smr_val |= 0x30;
1861 if (termios->c_cflag & CSTOPB)
1862 smr_val |= 0x08;
1863
1864 uart_update_timeout(port, termios->c_cflag, baud);
1865
9d482cc3
TY		 1866 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1867 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1868
4ffc3cdb 1869 if (t >= 0) {
9d482cc3 1870 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1871 serial_port_out(port, SCBRR, t);
f303b364
UH		 1872 reg = sci_getreg(port, HSSRR);
1873 if (reg->size)
1874 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1875 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1876 } else
1877 serial_port_out(port, SCSMR, smr_val);
1da177e4 1878
d5701647 1879 sci_init_pins(port, termios->c_cflag);
0979e0e6 1880
73c3d53f
PM		 1881 reg = sci_getreg(port, SCFCR);
1882 if (reg->size) {
b12bb29f 1883 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1884
73c3d53f 1885 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1886 if (termios->c_cflag & CRTSCTS)
1887 ctrl |= SCFCR_MCE;
1888 else
1889 ctrl &= ~SCFCR_MCE;
faf02f8f 1890 }
73c3d53f
PM		 1891
1892 /*
1893 * As we've done a sci_reset() above, ensure we don't
1894 * interfere with the FIFOs while toggling MCE. As the
1895 * reset values could still be set, simply mask them out.
1896 */
1897 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1898
b12bb29f 1899 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1900 }
b7a76e4b 1901
b12bb29f 1902 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1903
3089f381
GL		 1904#ifdef CONFIG_SERIAL_SH_SCI_DMA
1905 /*
1906 * Calculate delay for 1.5 DMA buffers: see
1907 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1908 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1909 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1910 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1911 * sizes), but it has been found out experimentally, that this is not
1912 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1913 * as a minimum seem to work perfectly.
1914 */
1915 if (s->chan_rx) {
1916 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1917 port->fifosize / 2;
1918 dev_dbg(port->dev,
1919 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1920 s->rx_timeout * 1000 / HZ, port->timeout);
1921 if (s->rx_timeout < msecs_to_jiffies(20))
1922 s->rx_timeout = msecs_to_jiffies(20);
1923 }
1924#endif
1925
1da177e4 1926 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1927 sci_start_rx(port);
36003386 1928
23241d43 1929 sci_port_disable(s);
1da177e4
LT		 1930}
1931
0174e5ca
TK		 1932static void sci_pm(struct uart_port *port, unsigned int state,
1933 unsigned int oldstate)
1934{
1935 struct sci_port *sci_port = to_sci_port(port);
1936
1937 switch (state) {
1938 case 3:
1939 sci_port_disable(sci_port);
1940 break;
1941 default:
1942 sci_port_enable(sci_port);
1943 break;
1944 }
1945}
1946
1da177e4
LT		 1947static const char *sci_type(struct uart_port *port)
1948{
1949 switch (port->type) {
e7c98dc7
MT		 1950 case PORT_IRDA:
1951 return "irda";
1952 case PORT_SCI:
1953 return "sci";
1954 case PORT_SCIF:
1955 return "scif";
1956 case PORT_SCIFA:
1957 return "scifa";
d1d4b10c
GL		 1958 case PORT_SCIFB:
1959 return "scifb";
f303b364
UH		 1960 case PORT_HSCIF:
1961 return "hscif";
1da177e4
LT		 1962 }
1963
fa43972f 1964 return NULL;
1da177e4
LT		 1965}
1966
e2651647 1967static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1968{
e2651647
PM		 1969 /*
1970 * Pick an arbitrary size that encapsulates all of the base
1971 * registers by default. This can be optimized later, or derived
1972 * from platform resource data at such a time that ports begin to
1973 * behave more erratically.
1974 */
f303b364
UH		 1975 if (port->type == PORT_HSCIF)
1976 return 96;
1977 else
1978 return 64;
1da177e4
LT		 1979}
1980
f6e9495d
PM		 1981static int sci_remap_port(struct uart_port *port)
1982{
1983 unsigned long size = sci_port_size(port);
1984
1985 /*
1986 * Nothing to do if there's already an established membase.
1987 */
1988 if (port->membase)
1989 return 0;
1990
1991 if (port->flags & UPF_IOREMAP) {
1992 port->membase = ioremap_nocache(port->mapbase, size);
1993 if (unlikely(!port->membase)) {
1994 dev_err(port->dev, "can't remap port#%d\n", port->line);
1995 return -ENXIO;
1996 }
1997 } else {
1998 /*
1999 * For the simple (and majority of) cases where we don't
2000 * need to do any remapping, just cast the cookie
2001 * directly.
2002 */
2003 port->membase = (void __iomem *)port->mapbase;
2004 }
2005
2006 return 0;
2007}
2008
e2651647 2009static void sci_release_port(struct uart_port *port)
1da177e4 2010{
e2651647
PM		 2011 if (port->flags & UPF_IOREMAP) {
2012 iounmap(port->membase);
2013 port->membase = NULL;
2014 }
2015
2016 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2017}
2018
e2651647 2019static int sci_request_port(struct uart_port *port)
1da177e4 2020{
e2651647
PM		 2021 unsigned long size = sci_port_size(port);
2022 struct resource *res;
f6e9495d 2023 int ret;
1da177e4 2024
1020520e 2025 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2026 if (unlikely(res == NULL))
2027 return -EBUSY;
1da177e4 2028
f6e9495d
PM		 2029 ret = sci_remap_port(port);
2030 if (unlikely(ret != 0)) {
2031 release_resource(res);
2032 return ret;
7ff731ae 2033 }
e2651647
PM		 2034
2035 return 0;
2036}
2037
2038static void sci_config_port(struct uart_port *port, int flags)
2039{
2040 if (flags & UART_CONFIG_TYPE) {
2041 struct sci_port *sport = to_sci_port(port);
2042
2043 port->type = sport->cfg->type;
2044 sci_request_port(port);
2045 }
1da177e4
LT		 2046}
2047
2048static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2049{
1da177e4
LT		 2050 if (ser->baud_base < 2400)
2051 /* No paper tape reader for Mitch.. */
2052 return -EINVAL;
2053
2054 return 0;
2055}
2056
2057static struct uart_ops sci_uart_ops = {
2058 .tx_empty = sci_tx_empty,
2059 .set_mctrl = sci_set_mctrl,
2060 .get_mctrl = sci_get_mctrl,
2061 .start_tx = sci_start_tx,
2062 .stop_tx = sci_stop_tx,
2063 .stop_rx = sci_stop_rx,
2064 .enable_ms = sci_enable_ms,
2065 .break_ctl = sci_break_ctl,
2066 .startup = sci_startup,
2067 .shutdown = sci_shutdown,
2068 .set_termios = sci_set_termios,
0174e5ca 2069 .pm = sci_pm,
1da177e4
LT		 2070 .type = sci_type,
2071 .release_port = sci_release_port,
2072 .request_port = sci_request_port,
2073 .config_port = sci_config_port,
2074 .verify_port = sci_verify_port,
07d2a1a1
PM		 2075#ifdef CONFIG_CONSOLE_POLL
2076 .poll_get_char = sci_poll_get_char,
2077 .poll_put_char = sci_poll_put_char,
2078#endif
1da177e4
LT		 2079};
2080
9671f099 2081static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2082 struct sci_port *sci_port, unsigned int index,
2083 struct plat_sci_port *p, bool early)
e108b2ca 2084{
73a19e4c 2085 struct uart_port *port = &sci_port->port;
1fcc91a6 2086 const struct resource *res;
ec09c5eb 2087 unsigned int sampling_rate;
1fcc91a6 2088 unsigned int i;
3127c6b2 2089 int ret;
e108b2ca 2090
50f0959a
PM		 2091 sci_port->cfg = p;
2092
73a19e4c
GL		 2093 port->ops = &sci_uart_ops;
2094 port->iotype = UPIO_MEM;
2095 port->line = index;
75136d48 2096
1fcc91a6
LP		 2097 if (dev->num_resources) {
2098 /* Device has resources, use them. */
2099 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2100 if (res == NULL)
2101 return -ENOMEM;
2102
2103 port->mapbase = res->start;
2104
2105 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2106 sci_port->irqs[i] = platform_get_irq(dev, i);
2107
2108 /* The SCI generates several interrupts. They can be muxed
2109 * together or connected to different interrupt lines. In the
2110 * muxed case only one interrupt resource is specified. In the
2111 * non-muxed case three or four interrupt resources are
2112 * specified, as the BRI interrupt is optional.
2113 */
2114 if (sci_port->irqs[0] < 0)
2115 return -ENXIO;
2116
2117 if (sci_port->irqs[1] < 0) {
2118 sci_port->irqs[1] = sci_port->irqs[0];
2119 sci_port->irqs[2] = sci_port->irqs[0];
2120 sci_port->irqs[3] = sci_port->irqs[0];
2121 }
2122 } else {
2123 /* No resources, use old-style platform data. */
2124 port->mapbase = p->mapbase;
2125 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2126 sci_port->irqs[i] = p->irqs[i] ? p->irqs[i] : -ENXIO;
2127 }
2128
b545e4f4
LP		 2129 if (p->regtype == SCIx_PROBE_REGTYPE) {
2130 ret = sci_probe_regmap(p);
2131 if (unlikely(ret))
2132 return ret;
2133 }
2134
75136d48 2135 switch (p->type) {
d1d4b10c
GL		 2136 case PORT_SCIFB:
2137 port->fifosize = 256;
b545e4f4 2138 sci_port->overrun_bit = 9;
ec09c5eb 2139 sampling_rate = 16;
d1d4b10c 2140 break;
f303b364
UH		 2141 case PORT_HSCIF:
2142 port->fifosize = 128;
ec09c5eb 2143 sampling_rate = 0;
b545e4f4 2144 sci_port->overrun_bit = 0;
f303b364 2145 break;
75136d48 2146 case PORT_SCIFA:
73a19e4c 2147 port->fifosize = 64;
b545e4f4 2148 sci_port->overrun_bit = 9;
ec09c5eb 2149 sampling_rate = 16;
75136d48
MP		 2150 break;
2151 case PORT_SCIF:
73a19e4c 2152 port->fifosize = 16;
ec09c5eb 2153 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
b545e4f4 2154 sci_port->overrun_bit = 9;
ec09c5eb
LP		 2155 sampling_rate = 16;
2156 } else {
b545e4f4 2157 sci_port->overrun_bit = 0;
ec09c5eb
LP		 2158 sampling_rate = 32;
2159 }
75136d48
MP		 2160 break;
2161 default:
73a19e4c 2162 port->fifosize = 1;
b545e4f4 2163 sci_port->overrun_bit = 5;
ec09c5eb 2164 sampling_rate = 32;
75136d48
MP		 2165 break;
2166 }
7b6fd3bf 2167
878fbb91
LP		 2168 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2169 * match the SoC datasheet, this should be investigated. Let platform
2170 * data override the sampling rate for now.
ec09c5eb 2171 */
878fbb91
LP		 2172 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2173 : sampling_rate;
ec09c5eb 2174
1fcc91a6 2175 if (!early) {
c7ed1ab3
PM		 2176 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2177 if (IS_ERR(sci_port->iclk)) {
2178 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2179 if (IS_ERR(sci_port->iclk)) {
2180 dev_err(&dev->dev, "can't get iclk\n");
2181 return PTR_ERR(sci_port->iclk);
2182 }
2183 }
2184
2185 /*
2186 * The function clock is optional, ignore it if we can't
2187 * find it.
2188 */
2189 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2190 if (IS_ERR(sci_port->fclk))
2191 sci_port->fclk = NULL;
2192
73a19e4c 2193 port->dev = &dev->dev;
5e50d2d6
MD		 2194
2195 pm_runtime_enable(&dev->dev);
7b6fd3bf 2196 }
e108b2ca 2197
7ed7e071
MD		 2198 sci_port->break_timer.data = (unsigned long)sci_port;
2199 sci_port->break_timer.function = sci_break_timer;
2200 init_timer(&sci_port->break_timer);
2201
debf9507
PM		 2202 /*
2203 * Establish some sensible defaults for the error detection.
2204 */
3ae988d9 2205 sci_port->error_mask = (p->type == PORT_SCI) ?
debf9507
PM		 2206 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2207
2208 /*
2209 * Establish sensible defaults for the overrun detection, unless
2210 * the part has explicitly disabled support for it.
2211 */
debf9507 2212
3ae988d9
LP		 2213 /*
2214 * Make the error mask inclusive of overrun detection, if
2215 * supported.
2216 */
2217 sci_port->error_mask |= 1 << sci_port->overrun_bit;
debf9507 2218
ce6738b6 2219 port->type = p->type;
b6e4a3f1 2220 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2221 port->regshift = p->regshift;
73a19e4c 2222
ce6738b6 2223 /*
61a6976b 2224 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2225 * for the multi-IRQ ports, which is where we are primarily
2226 * concerned with the shutdown path synchronization.
2227 *
2228 * For the muxed case there's nothing more to do.
2229 */
1fcc91a6 2230 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2231 port->irqflags = 0;
73a19e4c 2232
61a6976b
PM		 2233 port->serial_in = sci_serial_in;
2234 port->serial_out = sci_serial_out;
2235
937bb6e4
GL		 2236 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2237 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2238 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2239
c7ed1ab3 2240 return 0;
e108b2ca
PM		 2241}
2242
6dae1421
LP		 2243static void sci_cleanup_single(struct sci_port *port)
2244{
6dae1421
LP		 2245 clk_put(port->iclk);
2246 clk_put(port->fclk);
2247
2248 pm_runtime_disable(port->port.dev);
2249}
2250
1da177e4 2251#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2252static void serial_console_putchar(struct uart_port *port, int ch)
2253{
2254 sci_poll_put_char(port, ch);
2255}
2256
1da177e4
LT		 2257/*
2258 * Print a string to the serial port trying not to disturb
2259 * any possible real use of the port...
2260 */
2261static void serial_console_write(struct console *co, const char *s,
2262 unsigned count)
2263{
906b17dc
PM		 2264 struct sci_port *sci_port = &sci_ports[co->index];
2265 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2266 unsigned short bits, ctrl;
2267 unsigned long flags;
2268 int locked = 1;
2269
2270 local_irq_save(flags);
2271 if (port->sysrq)
2272 locked = 0;
2273 else if (oops_in_progress)
2274 locked = spin_trylock(&port->lock);
2275 else
2276 spin_lock(&port->lock);
2277
2278 /* first save the SCSCR then disable the interrupts */
2279 ctrl = serial_port_in(port, SCSCR);
2280 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2281
501b825d 2282 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2283
2284 /* wait until fifo is empty and last bit has been transmitted */
2285 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2286 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2287 cpu_relax();
40f70c03
SK		 2288
2289 /* restore the SCSCR */
2290 serial_port_out(port, SCSCR, ctrl);
2291
2292 if (locked)
2293 spin_unlock(&port->lock);
2294 local_irq_restore(flags);
1da177e4
LT		 2295}
2296
9671f099 2297static int serial_console_setup(struct console *co, char *options)
1da177e4 2298{
dc8e6f5b 2299 struct sci_port *sci_port;
1da177e4
LT		 2300 struct uart_port *port;
2301 int baud = 115200;
2302 int bits = 8;
2303 int parity = 'n';
2304 int flow = 'n';
2305 int ret;
2306
e108b2ca 2307 /*
906b17dc 2308 * Refuse to handle any bogus ports.
1da177e4 2309 */
906b17dc 2310 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2311 return -ENODEV;
e108b2ca 2312
906b17dc
PM		 2313 sci_port = &sci_ports[co->index];
2314 port = &sci_port->port;
2315
b2267a6b
AC		 2316 /*
2317 * Refuse to handle uninitialized ports.
2318 */
2319 if (!port->ops)
2320 return -ENODEV;
2321
f6e9495d
PM		 2322 ret = sci_remap_port(port);
2323 if (unlikely(ret != 0))
2324 return ret;
e108b2ca 2325
1da177e4
LT		 2326 if (options)
2327 uart_parse_options(options, &baud, &parity, &bits, &flow);
2328
ab7cfb55 2329 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2330}
2331
2332static struct console serial_console = {
2333 .name = "ttySC",
906b17dc 2334 .device = uart_console_device,
1da177e4
LT		 2335 .write = serial_console_write,
2336 .setup = serial_console_setup,
fa5da2f7 2337 .flags = CON_PRINTBUFFER,
1da177e4 2338 .index = -1,
906b17dc 2339 .data = &sci_uart_driver,
1da177e4
LT		 2340};
2341
7b6fd3bf
MD		 2342static struct console early_serial_console = {
2343 .name = "early_ttySC",
2344 .write = serial_console_write,
2345 .flags = CON_PRINTBUFFER,
906b17dc 2346 .index = -1,
7b6fd3bf 2347};
ecdf8a46 2348
7b6fd3bf
MD		 2349static char early_serial_buf[32];
2350
9671f099 2351static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2352{
574de559 2353 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2354
2355 if (early_serial_console.data)
2356 return -EEXIST;
2357
2358 early_serial_console.index = pdev->id;
ecdf8a46 2359
1fcc91a6 2360 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2361
2362 serial_console_setup(&early_serial_console, early_serial_buf);
2363
2364 if (!strstr(early_serial_buf, "keep"))
2365 early_serial_console.flags |= CON_BOOT;
2366
2367 register_console(&early_serial_console);
2368 return 0;
2369}
6a8c9799
NI		 2370
2371#define SCI_CONSOLE (&serial_console)
2372
ecdf8a46 2373#else
9671f099 2374static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2375{
2376 return -EINVAL;
2377}
1da177e4 2378
6a8c9799
NI		 2379#define SCI_CONSOLE NULL
2380
2381#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2382
2383static char banner[] __initdata =
f303b364 2384 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
1da177e4
LT		 2385
2386static struct uart_driver sci_uart_driver = {
2387 .owner = THIS_MODULE,
2388 .driver_name = "sci",
1da177e4
LT		 2389 .dev_name = "ttySC",
2390 .major = SCI_MAJOR,
2391 .minor = SCI_MINOR_START,
e108b2ca 2392 .nr = SCI_NPORTS,
1da177e4
LT		 2393 .cons = SCI_CONSOLE,
2394};
2395
54507f6e 2396static int sci_remove(struct platform_device *dev)
e552de24 2397{
d535a230 2398 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2399
d535a230
PM		 2400 cpufreq_unregister_notifier(&port->freq_transition,
2401 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2402
d535a230
PM		 2403 uart_remove_one_port(&sci_uart_driver, &port->port);
2404
6dae1421 2405 sci_cleanup_single(port);
e552de24 2406
e552de24
MD		 2407 return 0;
2408}
2409
9671f099 2410static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2411 unsigned int index,
2412 struct plat_sci_port *p,
2413 struct sci_port *sciport)
2414{
0ee70712
MD		 2415 int ret;
2416
2417 /* Sanity check */
2418 if (unlikely(index >= SCI_NPORTS)) {
2419 dev_notice(&dev->dev, "Attempting to register port "
2420 "%d when only %d are available.\n",
2421 index+1, SCI_NPORTS);
2422 dev_notice(&dev->dev, "Consider bumping "
2423 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2424 return -EINVAL;
0ee70712
MD		 2425 }
2426
1fcc91a6 2427 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2428 if (ret)
2429 return ret;
0ee70712 2430
6dae1421
LP		 2431 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2432 if (ret) {
2433 sci_cleanup_single(sciport);
2434 return ret;
2435 }
2436
2437 return 0;
0ee70712
MD		 2438}
2439
9671f099 2440static int sci_probe(struct platform_device *dev)
1da177e4 2441{
3ba35baa 2442 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
d535a230 2443 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2444 int ret;
d535a230 2445
ecdf8a46
PM		 2446 /*
2447 * If we've come here via earlyprintk initialization, head off to
2448 * the special early probe. We don't have sufficient device state
2449 * to make it beyond this yet.
2450 */
2451 if (is_early_platform_device(dev))
2452 return sci_probe_earlyprintk(dev);
7b6fd3bf 2453
d535a230 2454 platform_set_drvdata(dev, sp);
e552de24 2455
906b17dc 2456 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2457 if (ret)
6dae1421 2458 return ret;
e552de24 2459
d535a230 2460 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2461
d535a230
PM		 2462 ret = cpufreq_register_notifier(&sp->freq_transition,
2463 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2464 if (unlikely(ret < 0)) {
2465 sci_cleanup_single(sp);
2466 return ret;
2467 }
1da177e4
LT		 2468
2469#ifdef CONFIG_SH_STANDARD_BIOS
2470 sh_bios_gdb_detach();
2471#endif
2472
e108b2ca 2473 return 0;
1da177e4
LT		 2474}
2475
6daa79b3 2476static int sci_suspend(struct device *dev)
1da177e4 2477{
d535a230 2478 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2479
d535a230
PM		 2480 if (sport)
2481 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2482
e108b2ca
PM		 2483 return 0;
2484}
1da177e4 2485
6daa79b3 2486static int sci_resume(struct device *dev)
e108b2ca 2487{
d535a230 2488 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2489
d535a230
PM		 2490 if (sport)
2491 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2492
2493 return 0;
2494}
2495
47145210 2496static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2497 .suspend = sci_suspend,
2498 .resume = sci_resume,
2499};
2500
e108b2ca
PM		 2501static struct platform_driver sci_driver = {
2502 .probe = sci_probe,
b9e39c89 2503 .remove = sci_remove,
e108b2ca
PM		 2504 .driver = {
2505 .name = "sh-sci",
2506 .owner = THIS_MODULE,
6daa79b3 2507 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2508 },
2509};
2510
2511static int __init sci_init(void)
2512{
2513 int ret;
2514
2515 printk(banner);
2516
e108b2ca
PM		 2517 ret = uart_register_driver(&sci_uart_driver);
2518 if (likely(ret == 0)) {
2519 ret = platform_driver_register(&sci_driver);
2520 if (unlikely(ret))
2521 uart_unregister_driver(&sci_uart_driver);
2522 }
2523
2524 return ret;
2525}
2526
2527static void __exit sci_exit(void)
2528{
2529 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2530 uart_unregister_driver(&sci_uart_driver);
2531}
2532
7b6fd3bf
MD		 2533#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2534early_platform_init_buffer("earlyprintk", &sci_driver,
2535 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2536#endif
1da177e4
LT		 2537module_init(sci_init);
2538module_exit(sci_exit);
2539
e108b2ca 2540MODULE_LICENSE("GPL");
e169c139 2541MODULE_ALIAS("platform:sh-sci");
7f405f9c 2542MODULE_AUTHOR("Paul Mundt");
f303b364 2543MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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