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serial: sh-sci: Prevent compiler warnings on 64-bit
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
ec09c5eb 87 unsigned int sampling_rate;
e4d6f911 88 resource_size_t reg_size;
e108b2ca 89
e108b2ca
PM		 90 /* Break timer */
91 struct timer_list break_timer;
92 int break_flag;
1534a3b3 93
501b825d
MD		 94 /* Interface clock */
95 struct clk *iclk;
c7ed1ab3
PM		 96 /* Function clock */
97 struct clk *fclk;
edad1f20 98
1fcc91a6 99 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 100 char *irqstr[SCIx_NR_IRQS];
101
73a19e4c
GL		 102 struct dma_chan *chan_tx;
103 struct dma_chan *chan_rx;
f43dc23d 104
73a19e4c 105#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 106 struct dma_async_tx_descriptor *desc_tx;
107 struct dma_async_tx_descriptor *desc_rx[2];
108 dma_cookie_t cookie_tx;
109 dma_cookie_t cookie_rx[2];
110 dma_cookie_t active_rx;
111 struct scatterlist sg_tx;
112 unsigned int sg_len_tx;
113 struct scatterlist sg_rx[2];
114 size_t buf_len_rx;
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct work_struct work_rx;
119 struct timer_list rx_timer;
3089f381 120 unsigned int rx_timeout;
73a19e4c 121#endif
e552de24 122
d535a230 123 struct notifier_block freq_transition;
e108b2ca
PM		 124};
125
1da177e4 126/* Function prototypes */
d535a230 127static void sci_start_tx(struct uart_port *port);
b129a8cc 128static void sci_stop_tx(struct uart_port *port);
d535a230 129static void sci_start_rx(struct uart_port *port);
1da177e4 130
e108b2ca 131#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 132
e108b2ca
PM		 133static struct sci_port sci_ports[SCI_NPORTS];
134static struct uart_driver sci_uart_driver;
1da177e4 135
e7c98dc7
MT		 136static inline struct sci_port *
137to_sci_port(struct uart_port *uart)
138{
139 return container_of(uart, struct sci_port, port);
140}
141
61a6976b
PM		 142struct plat_sci_reg {
143 u8 offset, size;
144};
145
146/* Helper for invalidating specific entries of an inherited map. */
147#define sci_reg_invalid { .offset = 0, .size = 0 }
148
149static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
150 [SCIx_PROBE_REGTYPE] = {
151 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
152 },
153
154 /*
155 * Common SCI definitions, dependent on the port's regshift
156 * value.
157 */
158 [SCIx_SCI_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = sci_reg_invalid,
166 [SCFDR] = sci_reg_invalid,
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
f303b364 171 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 172 [SCPCR] = sci_reg_invalid,
173 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 174 },
175
176 /*
177 * Common definitions for legacy IrDA ports, dependent on
178 * regshift value.
179 */
180 [SCIx_IRDA_REGTYPE] = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 [SCFCR] = { 0x06, 8 },
188 [SCFDR] = { 0x07, 16 },
189 [SCTFDR] = sci_reg_invalid,
190 [SCRFDR] = sci_reg_invalid,
191 [SCSPTR] = sci_reg_invalid,
192 [SCLSR] = sci_reg_invalid,
f303b364 193 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 194 [SCPCR] = sci_reg_invalid,
195 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 196 },
197
198 /*
199 * Common SCIFA definitions.
200 */
201 [SCIx_SCIFA_REGTYPE] = {
202 [SCSMR] = { 0x00, 16 },
203 [SCBRR] = { 0x04, 8 },
204 [SCSCR] = { 0x08, 16 },
205 [SCxTDR] = { 0x20, 8 },
206 [SCxSR] = { 0x14, 16 },
207 [SCxRDR] = { 0x24, 8 },
208 [SCFCR] = { 0x18, 16 },
209 [SCFDR] = { 0x1c, 16 },
210 [SCTFDR] = sci_reg_invalid,
211 [SCRFDR] = sci_reg_invalid,
212 [SCSPTR] = sci_reg_invalid,
213 [SCLSR] = sci_reg_invalid,
f303b364 214 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 215 [SCPCR] = { 0x30, 16 },
216 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 217 },
218
219 /*
220 * Common SCIFB definitions.
221 */
222 [SCIx_SCIFB_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x40, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x60, 8 },
229 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 230 [SCFDR] = sci_reg_invalid,
231 [SCTFDR] = { 0x38, 16 },
232 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 233 [SCSPTR] = sci_reg_invalid,
234 [SCLSR] = sci_reg_invalid,
f303b364 235 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 236 [SCPCR] = { 0x30, 16 },
237 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 238 },
239
3af1f8a4
PE		 240 /*
241 * Common SH-2(A) SCIF definitions for ports with FIFO data
242 * count registers.
243 */
244 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
245 [SCSMR] = { 0x00, 16 },
246 [SCBRR] = { 0x04, 8 },
247 [SCSCR] = { 0x08, 16 },
248 [SCxTDR] = { 0x0c, 8 },
249 [SCxSR] = { 0x10, 16 },
250 [SCxRDR] = { 0x14, 8 },
251 [SCFCR] = { 0x18, 16 },
252 [SCFDR] = { 0x1c, 16 },
253 [SCTFDR] = sci_reg_invalid,
254 [SCRFDR] = sci_reg_invalid,
255 [SCSPTR] = { 0x20, 16 },
256 [SCLSR] = { 0x24, 16 },
f303b364 257 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 258 [SCPCR] = sci_reg_invalid,
259 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 260 },
261
61a6976b
PM		 262 /*
263 * Common SH-3 SCIF definitions.
264 */
265 [SCIx_SH3_SCIF_REGTYPE] = {
266 [SCSMR] = { 0x00, 8 },
267 [SCBRR] = { 0x02, 8 },
268 [SCSCR] = { 0x04, 8 },
269 [SCxTDR] = { 0x06, 8 },
270 [SCxSR] = { 0x08, 16 },
271 [SCxRDR] = { 0x0a, 8 },
272 [SCFCR] = { 0x0c, 8 },
273 [SCFDR] = { 0x0e, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = sci_reg_invalid,
f303b364 278 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 281 },
282
283 /*
284 * Common SH-4(A) SCIF(B) definitions.
285 */
286 [SCIx_SH4_SCIF_REGTYPE] = {
287 [SCSMR] = { 0x00, 16 },
288 [SCBRR] = { 0x04, 8 },
289 [SCSCR] = { 0x08, 16 },
290 [SCxTDR] = { 0x0c, 8 },
291 [SCxSR] = { 0x10, 16 },
292 [SCxRDR] = { 0x14, 8 },
293 [SCFCR] = { 0x18, 16 },
294 [SCFDR] = { 0x1c, 16 },
295 [SCTFDR] = sci_reg_invalid,
296 [SCRFDR] = sci_reg_invalid,
297 [SCSPTR] = { 0x20, 16 },
298 [SCLSR] = { 0x24, 16 },
f303b364 299 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 300 [SCPCR] = sci_reg_invalid,
301 [SCPDR] = sci_reg_invalid,
f303b364
UH		 302 },
303
304 /*
305 * Common HSCIF definitions.
306 */
307 [SCIx_HSCIF_REGTYPE] = {
308 [SCSMR] = { 0x00, 16 },
309 [SCBRR] = { 0x04, 8 },
310 [SCSCR] = { 0x08, 16 },
311 [SCxTDR] = { 0x0c, 8 },
312 [SCxSR] = { 0x10, 16 },
313 [SCxRDR] = { 0x14, 8 },
314 [SCFCR] = { 0x18, 16 },
315 [SCFDR] = { 0x1c, 16 },
316 [SCTFDR] = sci_reg_invalid,
317 [SCRFDR] = sci_reg_invalid,
318 [SCSPTR] = { 0x20, 16 },
319 [SCLSR] = { 0x24, 16 },
320 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 321 [SCPCR] = sci_reg_invalid,
322 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 323 },
324
325 /*
326 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
327 * register.
328 */
329 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
330 [SCSMR] = { 0x00, 16 },
331 [SCBRR] = { 0x04, 8 },
332 [SCSCR] = { 0x08, 16 },
333 [SCxTDR] = { 0x0c, 8 },
334 [SCxSR] = { 0x10, 16 },
335 [SCxRDR] = { 0x14, 8 },
336 [SCFCR] = { 0x18, 16 },
337 [SCFDR] = { 0x1c, 16 },
338 [SCTFDR] = sci_reg_invalid,
339 [SCRFDR] = sci_reg_invalid,
340 [SCSPTR] = sci_reg_invalid,
341 [SCLSR] = { 0x24, 16 },
f303b364 342 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 343 [SCPCR] = sci_reg_invalid,
344 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 345 },
346
347 /*
348 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
349 * count registers.
350 */
351 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
352 [SCSMR] = { 0x00, 16 },
353 [SCBRR] = { 0x04, 8 },
354 [SCSCR] = { 0x08, 16 },
355 [SCxTDR] = { 0x0c, 8 },
356 [SCxSR] = { 0x10, 16 },
357 [SCxRDR] = { 0x14, 8 },
358 [SCFCR] = { 0x18, 16 },
359 [SCFDR] = { 0x1c, 16 },
360 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
361 [SCRFDR] = { 0x20, 16 },
362 [SCSPTR] = { 0x24, 16 },
363 [SCLSR] = { 0x28, 16 },
f303b364 364 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 365 [SCPCR] = sci_reg_invalid,
366 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 367 },
368
369 /*
370 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
371 * registers.
372 */
373 [SCIx_SH7705_SCIF_REGTYPE] = {
374 [SCSMR] = { 0x00, 16 },
375 [SCBRR] = { 0x04, 8 },
376 [SCSCR] = { 0x08, 16 },
377 [SCxTDR] = { 0x20, 8 },
378 [SCxSR] = { 0x14, 16 },
379 [SCxRDR] = { 0x24, 8 },
380 [SCFCR] = { 0x18, 16 },
381 [SCFDR] = { 0x1c, 16 },
382 [SCTFDR] = sci_reg_invalid,
383 [SCRFDR] = sci_reg_invalid,
384 [SCSPTR] = sci_reg_invalid,
385 [SCLSR] = sci_reg_invalid,
f303b364 386 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 387 [SCPCR] = sci_reg_invalid,
388 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 389 },
390};
391
72b294cf
PM		 392#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
393
61a6976b
PM		 394/*
395 * The "offset" here is rather misleading, in that it refers to an enum
396 * value relative to the port mapping rather than the fixed offset
397 * itself, which needs to be manually retrieved from the platform's
398 * register map for the given port.
399 */
400static unsigned int sci_serial_in(struct uart_port *p, int offset)
401{
72b294cf 402 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 403
404 if (reg->size == 8)
405 return ioread8(p->membase + (reg->offset << p->regshift));
406 else if (reg->size == 16)
407 return ioread16(p->membase + (reg->offset << p->regshift));
408 else
409 WARN(1, "Invalid register access\n");
410
411 return 0;
412}
413
414static void sci_serial_out(struct uart_port *p, int offset, int value)
415{
72b294cf 416 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 417
418 if (reg->size == 8)
419 iowrite8(value, p->membase + (reg->offset << p->regshift));
420 else if (reg->size == 16)
421 iowrite16(value, p->membase + (reg->offset << p->regshift));
422 else
423 WARN(1, "Invalid register access\n");
424}
425
61a6976b
PM		 426static int sci_probe_regmap(struct plat_sci_port *cfg)
427{
428 switch (cfg->type) {
429 case PORT_SCI:
430 cfg->regtype = SCIx_SCI_REGTYPE;
431 break;
432 case PORT_IRDA:
433 cfg->regtype = SCIx_IRDA_REGTYPE;
434 break;
435 case PORT_SCIFA:
436 cfg->regtype = SCIx_SCIFA_REGTYPE;
437 break;
438 case PORT_SCIFB:
439 cfg->regtype = SCIx_SCIFB_REGTYPE;
440 break;
441 case PORT_SCIF:
442 /*
443 * The SH-4 is a bit of a misnomer here, although that's
444 * where this particular port layout originated. This
445 * configuration (or some slight variation thereof)
446 * remains the dominant model for all SCIFs.
447 */
448 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
449 break;
f303b364
UH		 450 case PORT_HSCIF:
451 cfg->regtype = SCIx_HSCIF_REGTYPE;
452 break;
61a6976b 453 default:
6c13d5d2 454 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 455 return -EINVAL;
456 }
457
458 return 0;
459}
460
23241d43
PM		 461static void sci_port_enable(struct sci_port *sci_port)
462{
463 if (!sci_port->port.dev)
464 return;
465
466 pm_runtime_get_sync(sci_port->port.dev);
467
b016b646 468 clk_prepare_enable(sci_port->iclk);
23241d43 469 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 470 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 471}
472
473static void sci_port_disable(struct sci_port *sci_port)
474{
475 if (!sci_port->port.dev)
476 return;
477
caec7038
LP		 478 /* Cancel the break timer to ensure that the timer handler will not try
479 * to access the hardware with clocks and power disabled. Reset the
480 * break flag to make the break debouncing state machine ready for the
481 * next break.
482 */
483 del_timer_sync(&sci_port->break_timer);
484 sci_port->break_flag = 0;
485
b016b646
LP		 486 clk_disable_unprepare(sci_port->fclk);
487 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 488
489 pm_runtime_put_sync(sci_port->port.dev);
490}
491
a1b5b43f
GU		 492static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
493{
494 if (port->type == PORT_SCI) {
495 /* Just store the mask */
496 serial_port_out(port, SCxSR, mask);
497 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
498 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
499 /* Only clear the status bits we want to clear */
500 serial_port_out(port, SCxSR,
501 serial_port_in(port, SCxSR) & mask);
502 } else {
503 /* Store the mask, clear parity/framing errors */
504 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
505 }
506}
507
07d2a1a1 508#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 509
510#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 511static int sci_poll_get_char(struct uart_port *port)
1da177e4 512{
1da177e4
LT		 513 unsigned short status;
514 int c;
515
e108b2ca 516 do {
b12bb29f 517 status = serial_port_in(port, SCxSR);
1da177e4 518 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 519 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 520 continue;
521 }
3f255eb3
JW		 522 break;
523 } while (1);
524
525 if (!(status & SCxSR_RDxF(port)))
526 return NO_POLL_CHAR;
07d2a1a1 527
b12bb29f 528 c = serial_port_in(port, SCxRDR);
07d2a1a1 529
e7c98dc7 530 /* Dummy read */
b12bb29f 531 serial_port_in(port, SCxSR);
a1b5b43f 532 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 533
534 return c;
535}
1f6fd5c9 536#endif
1da177e4 537
07d2a1a1 538static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 539{
1da177e4
LT		 540 unsigned short status;
541
1da177e4 542 do {
b12bb29f 543 status = serial_port_in(port, SCxSR);
1da177e4
LT		 544 } while (!(status & SCxSR_TDxE(port)));
545
b12bb29f 546 serial_port_out(port, SCxTDR, c);
a1b5b43f 547 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 548}
07d2a1a1 549#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 550
61a6976b 551static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 552{
61a6976b
PM		 553 struct sci_port *s = to_sci_port(port);
554 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 555
61a6976b
PM		 556 /*
557 * Use port-specific handler if provided.
558 */
559 if (s->cfg->ops && s->cfg->ops->init_pins) {
560 s->cfg->ops->init_pins(port, cflag);
561 return;
1da177e4 562 }
41504c39 563
61a6976b
PM		 564 /*
565 * For the generic path SCSPTR is necessary. Bail out if that's
566 * unavailable, too.
567 */
568 if (!reg->size)
569 return;
41504c39 570
faf02f8f
PM		 571 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
572 ((!(cflag & CRTSCTS)))) {
573 unsigned short status;
574
b12bb29f 575 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 576 status &= ~SCSPTR_CTSIO;
577 status |= SCSPTR_RTSIO;
b12bb29f 578 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 579 }
d5701647 580}
e108b2ca 581
72b294cf 582static int sci_txfill(struct uart_port *port)
e108b2ca 583{
72b294cf 584 struct plat_sci_reg *reg;
e108b2ca 585
72b294cf
PM		 586 reg = sci_getreg(port, SCTFDR);
587 if (reg->size)
63f7ad11 588 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 589
72b294cf
PM		 590 reg = sci_getreg(port, SCFDR);
591 if (reg->size)
b12bb29f 592 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 593
b12bb29f 594 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 595}
596
73a19e4c
GL		 597static int sci_txroom(struct uart_port *port)
598{
72b294cf 599 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 600}
601
602static int sci_rxfill(struct uart_port *port)
e108b2ca 603{
72b294cf
PM		 604 struct plat_sci_reg *reg;
605
606 reg = sci_getreg(port, SCRFDR);
607 if (reg->size)
63f7ad11 608 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 609
610 reg = sci_getreg(port, SCFDR);
611 if (reg->size)
b12bb29f 612 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 613
b12bb29f 614 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 615}
616
514820eb
PM		 617/*
618 * SCI helper for checking the state of the muxed port/RXD pins.
619 */
620static inline int sci_rxd_in(struct uart_port *port)
621{
622 struct sci_port *s = to_sci_port(port);
623
624 if (s->cfg->port_reg <= 0)
625 return 1;
626
0dd4d5cb 627 /* Cast for ARM damage */
e2afca69 628 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 629}
630
1da177e4
LT		 631/* ********************************************************************** *
632 * the interrupt related routines *
633 * ********************************************************************** */
634
635static void sci_transmit_chars(struct uart_port *port)
636{
ebd2c8f6 637 struct circ_buf *xmit = &port->state->xmit;
1da177e4 638 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 639 unsigned short status;
640 unsigned short ctrl;
e108b2ca 641 int count;
1da177e4 642
b12bb29f 643 status = serial_port_in(port, SCxSR);
1da177e4 644 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 645 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 646 if (uart_circ_empty(xmit))
8e698614 647 ctrl &= ~SCSCR_TIE;
e7c98dc7 648 else
8e698614 649 ctrl |= SCSCR_TIE;
b12bb29f 650 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 651 return;
652 }
653
72b294cf 654 count = sci_txroom(port);
1da177e4
LT		 655
656 do {
657 unsigned char c;
658
659 if (port->x_char) {
660 c = port->x_char;
661 port->x_char = 0;
662 } else if (!uart_circ_empty(xmit) && !stopped) {
663 c = xmit->buf[xmit->tail];
664 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
665 } else {
666 break;
667 }
668
b12bb29f 669 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 670
671 port->icount.tx++;
672 } while (--count > 0);
673
a1b5b43f 674 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 675
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(port);
678 if (uart_circ_empty(xmit)) {
b129a8cc 679 sci_stop_tx(port);
1da177e4 680 } else {
b12bb29f 681 ctrl = serial_port_in(port, SCSCR);
1da177e4 682
1a22f08d 683 if (port->type != PORT_SCI) {
b12bb29f 684 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 685 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 686 }
1da177e4 687
8e698614 688 ctrl |= SCSCR_TIE;
b12bb29f 689 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 690 }
691}
692
693/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 694#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 695
94c8b6db 696static void sci_receive_chars(struct uart_port *port)
1da177e4 697{
e7c98dc7 698 struct sci_port *sci_port = to_sci_port(port);
227434f8 699 struct tty_port *tport = &port->state->port;
1da177e4
LT		 700 int i, count, copied = 0;
701 unsigned short status;
33f0f88f 702 unsigned char flag;
1da177e4 703
b12bb29f 704 status = serial_port_in(port, SCxSR);
1da177e4
LT		 705 if (!(status & SCxSR_RDxF(port)))
706 return;
707
708 while (1) {
1da177e4 709 /* Don't copy more bytes than there is room for in the buffer */
227434f8 710 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 711
712 /* If for any reason we can't copy more data, we're done! */
713 if (count == 0)
714 break;
715
716 if (port->type == PORT_SCI) {
b12bb29f 717 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 718 if (uart_handle_sysrq_char(port, c) ||
719 sci_port->break_flag)
1da177e4 720 count = 0;
e7c98dc7 721 else
92a19f9c 722 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 723 } else {
e7c98dc7 724 for (i = 0; i < count; i++) {
b12bb29f 725 char c = serial_port_in(port, SCxRDR);
d97fbbed 726
b12bb29f 727 status = serial_port_in(port, SCxSR);
1da177e4
LT		 728#if defined(CONFIG_CPU_SH3)
729 /* Skip "chars" during break */
e108b2ca 730 if (sci_port->break_flag) {
1da177e4
LT		 731 if ((c == 0) &&
732 (status & SCxSR_FER(port))) {
733 count--; i--;
734 continue;
735 }
e108b2ca 736
1da177e4 737 /* Nonzero => end-of-break */
762c69e3 738 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 739 sci_port->break_flag = 0;
740
1da177e4
LT		 741 if (STEPFN(c)) {
742 count--; i--;
743 continue;
744 }
745 }
746#endif /* CONFIG_CPU_SH3 */
7d12e780 747 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 748 count--; i--;
749 continue;
750 }
751
752 /* Store data and status */
73a19e4c 753 if (status & SCxSR_FER(port)) {
33f0f88f 754 flag = TTY_FRAME;
d97fbbed 755 port->icount.frame++;
762c69e3 756 dev_notice(port->dev, "frame error\n");
73a19e4c 757 } else if (status & SCxSR_PER(port)) {
33f0f88f 758 flag = TTY_PARITY;
d97fbbed 759 port->icount.parity++;
762c69e3 760 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 761 } else
762 flag = TTY_NORMAL;
762c69e3 763
92a19f9c 764 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 765 }
766 }
767
b12bb29f 768 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 769 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 770
1da177e4
LT		 771 copied += count;
772 port->icount.rx += count;
773 }
774
775 if (copied) {
776 /* Tell the rest of the system the news. New characters! */
2e124b4a 777 tty_flip_buffer_push(tport);
1da177e4 778 } else {
b12bb29f 779 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 780 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 781 }
782}
783
784#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 785
786/*
787 * The sci generates interrupts during the break,
1da177e4
LT		 788 * 1 per millisecond or so during the break period, for 9600 baud.
789 * So dont bother disabling interrupts.
790 * But dont want more than 1 break event.
791 * Use a kernel timer to periodically poll the rx line until
792 * the break is finished.
793 */
94c8b6db 794static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 795{
bc9b3f5c 796 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 797}
94c8b6db 798
1da177e4
LT		 799/* Ensure that two consecutive samples find the break over. */
800static void sci_break_timer(unsigned long data)
801{
e108b2ca
PM		 802 struct sci_port *port = (struct sci_port *)data;
803
804 if (sci_rxd_in(&port->port) == 0) {
1da177e4 805 port->break_flag = 1;
e108b2ca
PM		 806 sci_schedule_break_timer(port);
807 } else if (port->break_flag == 1) {
1da177e4
LT		 808 /* break is over. */
809 port->break_flag = 2;
e108b2ca
PM		 810 sci_schedule_break_timer(port);
811 } else
812 port->break_flag = 0;
1da177e4
LT		 813}
814
94c8b6db 815static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 816{
817 int copied = 0;
b12bb29f 818 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 819 struct tty_port *tport = &port->state->port;
debf9507 820 struct sci_port *s = to_sci_port(port);
1da177e4 821
3ae988d9 822 /* Handle overruns */
75c249fd 823 if (status & s->overrun_mask) {
3ae988d9 824 port->icount.overrun++;
d97fbbed 825
3ae988d9
LP		 826 /* overrun error */
827 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
828 copied++;
762c69e3 829
9b971cd2 830 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 831 }
832
e108b2ca 833 if (status & SCxSR_FER(port)) {
1da177e4
LT		 834 if (sci_rxd_in(port) == 0) {
835 /* Notify of BREAK */
e7c98dc7 836 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 837
838 if (!sci_port->break_flag) {
d97fbbed
PM		 839 port->icount.brk++;
840
e108b2ca
PM		 841 sci_port->break_flag = 1;
842 sci_schedule_break_timer(sci_port);
843
1da177e4 844 /* Do sysrq handling. */
e108b2ca 845 if (uart_handle_break(port))
1da177e4 846 return 0;
762c69e3
PM		 847
848 dev_dbg(port->dev, "BREAK detected\n");
849
92a19f9c 850 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 851 copied++;
852 }
853
e108b2ca 854 } else {
1da177e4 855 /* frame error */
d97fbbed
PM		 856 port->icount.frame++;
857
92a19f9c 858 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 859 copied++;
762c69e3
PM		 860
861 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 862 }
863 }
864
e108b2ca 865 if (status & SCxSR_PER(port)) {
1da177e4 866 /* parity error */
d97fbbed
PM		 867 port->icount.parity++;
868
92a19f9c 869 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 870 copied++;
762c69e3 871
9b971cd2 872 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 873 }
874
33f0f88f 875 if (copied)
2e124b4a 876 tty_flip_buffer_push(tport);
1da177e4
LT		 877
878 return copied;
879}
880
94c8b6db 881static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 882{
92a19f9c 883 struct tty_port *tport = &port->state->port;
debf9507 884 struct sci_port *s = to_sci_port(port);
4b8c59a3 885 struct plat_sci_reg *reg;
2e0842a1 886 int copied = 0;
75c249fd 887 u16 status;
d830fa45 888
2e0842a1 889 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 890 if (!reg->size)
d830fa45
PM		 891 return 0;
892
2e0842a1 893 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 894 if (status & s->overrun_mask) {
895 status &= ~s->overrun_mask;
2e0842a1 896 serial_port_out(port, s->overrun_reg, status);
d830fa45 897
d97fbbed
PM		 898 port->icount.overrun++;
899
92a19f9c 900 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 901 tty_flip_buffer_push(tport);
d830fa45 902
51b31f1c 903 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 904 copied++;
905 }
906
907 return copied;
908}
909
94c8b6db 910static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 911{
912 int copied = 0;
b12bb29f 913 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 914 struct tty_port *tport = &port->state->port;
a5660ada 915 struct sci_port *s = to_sci_port(port);
1da177e4 916
0b3d4ef6
PM		 917 if (uart_handle_break(port))
918 return 0;
919
b7a76e4b 920 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 921#if defined(CONFIG_CPU_SH3)
922 /* Debounce break */
923 s->break_flag = 1;
924#endif
d97fbbed
PM		 925
926 port->icount.brk++;
927
1da177e4 928 /* Notify of BREAK */
92a19f9c 929 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 930 copied++;
762c69e3
PM		 931
932 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 933 }
934
33f0f88f 935 if (copied)
2e124b4a 936 tty_flip_buffer_push(tport);
e108b2ca 937
d830fa45
PM		 938 copied += sci_handle_fifo_overrun(port);
939
1da177e4
LT		 940 return copied;
941}
942
73a19e4c 943static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 944{
73a19e4c
GL		 945#ifdef CONFIG_SERIAL_SH_SCI_DMA
946 struct uart_port *port = ptr;
947 struct sci_port *s = to_sci_port(port);
948
949 if (s->chan_rx) {
b12bb29f
PM		 950 u16 scr = serial_port_in(port, SCSCR);
951 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 952
953 /* Disable future Rx interrupts */
d1d4b10c 954 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 955 disable_irq_nosync(irq);
26de4f1b 956 scr |= SCSCR_RDRQE;
3089f381 957 } else {
f43dc23d 958 scr &= ~SCSCR_RIE;
3089f381 959 }
b12bb29f 960 serial_port_out(port, SCSCR, scr);
73a19e4c 961 /* Clear current interrupt */
b12bb29f 962 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 963 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
964 jiffies, s->rx_timeout);
965 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 966
967 return IRQ_HANDLED;
968 }
969#endif
970
1da177e4
LT		 971 /* I think sci_receive_chars has to be called irrespective
972 * of whether the I_IXOFF is set, otherwise, how is the interrupt
973 * to be disabled?
974 */
73a19e4c 975 sci_receive_chars(ptr);
1da177e4
LT		 976
977 return IRQ_HANDLED;
978}
979
7d12e780 980static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 981{
982 struct uart_port *port = ptr;
fd78a76a 983 unsigned long flags;
1da177e4 984
fd78a76a 985 spin_lock_irqsave(&port->lock, flags);
1da177e4 986 sci_transmit_chars(port);
fd78a76a 987 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 988
989 return IRQ_HANDLED;
990}
991
7d12e780 992static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 993{
994 struct uart_port *port = ptr;
995
996 /* Handle errors */
997 if (port->type == PORT_SCI) {
998 if (sci_handle_errors(port)) {
999 /* discard character in rx buffer */
b12bb29f 1000 serial_port_in(port, SCxSR);
a1b5b43f 1001 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 1002 }
1003 } else {
d830fa45 1004 sci_handle_fifo_overrun(port);
7d12e780 1005 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 1006 }
1007
a1b5b43f 1008 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 1009
1010 /* Kick the transmission */
7d12e780 1011 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 1012
1013 return IRQ_HANDLED;
1014}
1015
7d12e780 1016static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 1017{
1018 struct uart_port *port = ptr;
1019
1020 /* Handle BREAKs */
1021 sci_handle_breaks(port);
a1b5b43f 1022 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 1023
1024 return IRQ_HANDLED;
1025}
1026
f43dc23d
PM		 1027static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1028{
1029 /*
1030 * Not all ports (such as SCIFA) will support REIE. Rather than
1031 * special-casing the port type, we check the port initialization
1032 * IRQ enable mask to see whether the IRQ is desired at all. If
1033 * it's unset, it's logically inferred that there's no point in
1034 * testing for it.
1035 */
ce6738b6 1036 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 1037}
1038
7d12e780 1039static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 1040{
cb772fe7 1041 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
a8884e34 1042 struct uart_port *port = ptr;
73a19e4c 1043 struct sci_port *s = to_sci_port(port);
a8884e34 1044 irqreturn_t ret = IRQ_NONE;
1da177e4 1045
b12bb29f
PM		 1046 ssr_status = serial_port_in(port, SCxSR);
1047 scr_status = serial_port_in(port, SCSCR);
2e0842a1 1048 if (s->overrun_reg == SCxSR)
cb772fe7 1049 orer_status = ssr_status;
2e0842a1
GU		 1050 else {
1051 if (sci_getreg(port, s->overrun_reg)->size)
1052 orer_status = serial_port_in(port, s->overrun_reg);
cb772fe7
NI		 1053 }
1054
f43dc23d 1055 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 1056
1057 /* Tx Interrupt */
f43dc23d 1058 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 1059 !s->chan_tx)
a8884e34 1060 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 1061
73a19e4c
GL		 1062 /*
1063 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1064 * DR flags
1065 */
1066 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
8b6ff84c
HN		 1067 (scr_status & SCSCR_RIE)) {
1068 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1069 sci_handle_fifo_overrun(port);
a8884e34 1070 ret = sci_rx_interrupt(irq, ptr);
8b6ff84c 1071 }
f43dc23d 1072
1da177e4 1073 /* Error Interrupt */
dd4da3a5 1074 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1075 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1076
1da177e4 1077 /* Break Interrupt */
dd4da3a5 1078 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1079 ret = sci_br_interrupt(irq, ptr);
1da177e4 1080
8b6ff84c 1081 /* Overrun Interrupt */
75c249fd 1082 if (orer_status & s->overrun_mask)
cb772fe7 1083 sci_handle_fifo_overrun(port);
8b6ff84c 1084
a8884e34 1085 return ret;
1da177e4
LT		 1086}
1087
1da177e4 1088/*
25985edc 1089 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1090 * ports' baud rate when the peripheral clock changes.
1091 */
e108b2ca
PM		 1092static int sci_notifier(struct notifier_block *self,
1093 unsigned long phase, void *p)
1da177e4 1094{
e552de24
MD		 1095 struct sci_port *sci_port;
1096 unsigned long flags;
1da177e4 1097
d535a230
PM		 1098 sci_port = container_of(self, struct sci_port, freq_transition);
1099
0b443ead 1100 if (phase == CPUFREQ_POSTCHANGE) {
d535a230 1101 struct uart_port *port = &sci_port->port;
073e84c9 1102
d535a230
PM		 1103 spin_lock_irqsave(&port->lock, flags);
1104 port->uartclk = clk_get_rate(sci_port->iclk);
1105 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1106 }
1da177e4 1107
1da177e4
LT		 1108 return NOTIFY_OK;
1109}
501b825d 1110
9174fc8f
PM		 1111static struct sci_irq_desc {
1112 const char *desc;
1113 irq_handler_t handler;
1114} sci_irq_desc[] = {
1115 /*
1116 * Split out handlers, the default case.
1117 */
1118 [SCIx_ERI_IRQ] = {
1119 .desc = "rx err",
1120 .handler = sci_er_interrupt,
1121 },
1122
1123 [SCIx_RXI_IRQ] = {
1124 .desc = "rx full",
1125 .handler = sci_rx_interrupt,
1126 },
1127
1128 [SCIx_TXI_IRQ] = {
1129 .desc = "tx empty",
1130 .handler = sci_tx_interrupt,
1131 },
1132
1133 [SCIx_BRI_IRQ] = {
1134 .desc = "break",
1135 .handler = sci_br_interrupt,
1136 },
1137
1138 /*
1139 * Special muxed handler.
1140 */
1141 [SCIx_MUX_IRQ] = {
1142 .desc = "mux",
1143 .handler = sci_mpxed_interrupt,
1144 },
1145};
1146
1da177e4
LT		 1147static int sci_request_irq(struct sci_port *port)
1148{
9174fc8f
PM		 1149 struct uart_port *up = &port->port;
1150 int i, j, ret = 0;
1151
1152 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1153 struct sci_irq_desc *desc;
1fcc91a6 1154 int irq;
9174fc8f
PM		 1155
1156 if (SCIx_IRQ_IS_MUXED(port)) {
1157 i = SCIx_MUX_IRQ;
1158 irq = up->irq;
0e8963de 1159 } else {
1fcc91a6 1160 irq = port->irqs[i];
9174fc8f 1161
0e8963de
PM		 1162 /*
1163 * Certain port types won't support all of the
1164 * available interrupt sources.
1165 */
1fcc91a6 1166 if (unlikely(irq < 0))
0e8963de
PM		 1167 continue;
1168 }
1169
9174fc8f
PM		 1170 desc = sci_irq_desc + i;
1171 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1172 dev_name(up->dev), desc->desc);
1173 if (!port->irqstr[j]) {
1174 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1175 desc->desc);
1176 goto out_nomem;
1da177e4 1177 }
9174fc8f
PM		 1178
1179 ret = request_irq(irq, desc->handler, up->irqflags,
1180 port->irqstr[j], port);
1181 if (unlikely(ret)) {
1182 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1183 goto out_noirq;
1da177e4
LT		 1184 }
1185 }
1186
1187 return 0;
9174fc8f
PM		 1188
1189out_noirq:
1190 while (--i >= 0)
1fcc91a6 1191 free_irq(port->irqs[i], port);
9174fc8f
PM		 1192
1193out_nomem:
1194 while (--j >= 0)
1195 kfree(port->irqstr[j]);
1196
1197 return ret;
1da177e4
LT		 1198}
1199
1200static void sci_free_irq(struct sci_port *port)
1201{
1202 int i;
1203
9174fc8f
PM		 1204 /*
1205 * Intentionally in reverse order so we iterate over the muxed
1206 * IRQ first.
1207 */
1208 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1209 int irq = port->irqs[i];
0e8963de
PM		 1210
1211 /*
1212 * Certain port types won't support all of the available
1213 * interrupt sources.
1214 */
1fcc91a6 1215 if (unlikely(irq < 0))
0e8963de
PM		 1216 continue;
1217
1fcc91a6 1218 free_irq(port->irqs[i], port);
9174fc8f 1219 kfree(port->irqstr[i]);
1da177e4 1220
9174fc8f
PM		 1221 if (SCIx_IRQ_IS_MUXED(port)) {
1222 /* If there's only one IRQ, we're done. */
1223 return;
1da177e4
LT		 1224 }
1225 }
1226}
1227
1228static unsigned int sci_tx_empty(struct uart_port *port)
1229{
b12bb29f 1230 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1231 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1232
1233 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1234}
1235
cdf7c42f
PM		 1236/*
1237 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1238 * CTS/RTS is supported in hardware by at least one port and controlled
1239 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1240 * handled via the ->init_pins() op, which is a bit of a one-way street,
1241 * lacking any ability to defer pin control -- this will later be
1242 * converted over to the GPIO framework).
dc7e3ef7
PM		 1243 *
1244 * Other modes (such as loopback) are supported generically on certain
1245 * port types, but not others. For these it's sufficient to test for the
1246 * existence of the support register and simply ignore the port type.
cdf7c42f 1247 */
1da177e4
LT		 1248static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1249{
dc7e3ef7
PM		 1250 if (mctrl & TIOCM_LOOP) {
1251 struct plat_sci_reg *reg;
1252
1253 /*
1254 * Standard loopback mode for SCFCR ports.
1255 */
1256 reg = sci_getreg(port, SCFCR);
1257 if (reg->size)
26de4f1b
GU		 1258 serial_port_out(port, SCFCR,
1259 serial_port_in(port, SCFCR) |
1260 SCFCR_LOOP);
dc7e3ef7 1261 }
1da177e4
LT		 1262}
1263
1264static unsigned int sci_get_mctrl(struct uart_port *port)
1265{
cdf7c42f
PM		 1266 /*
1267 * CTS/RTS is handled in hardware when supported, while nothing
1268 * else is wired up. Keep it simple and simply assert DSR/CAR.
1269 */
1270 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1271}
1272
73a19e4c
GL		 1273#ifdef CONFIG_SERIAL_SH_SCI_DMA
1274static void sci_dma_tx_complete(void *arg)
1275{
1276 struct sci_port *s = arg;
1277 struct uart_port *port = &s->port;
1278 struct circ_buf *xmit = &port->state->xmit;
1279 unsigned long flags;
1280
1281 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1282
1283 spin_lock_irqsave(&port->lock, flags);
1284
f354a381 1285 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1286 xmit->tail &= UART_XMIT_SIZE - 1;
1287
f354a381 1288 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1289
1290 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1291 s->desc_tx = NULL;
1292
73a19e4c
GL		 1293 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1294 uart_write_wakeup(port);
1295
3089f381 1296 if (!uart_circ_empty(xmit)) {
49d4bcad 1297 s->cookie_tx = 0;
73a19e4c 1298 schedule_work(&s->work_tx);
49d4bcad
YT		 1299 } else {
1300 s->cookie_tx = -EINVAL;
1301 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1302 u16 ctrl = serial_port_in(port, SCSCR);
1303 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1304 }
3089f381
GL		 1305 }
1306
1307 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1308}
1309
1310/* Locking: called with port lock held */
92a19f9c 1311static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1312{
1313 struct uart_port *port = &s->port;
227434f8 1314 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1315 int i, active, room;
1316
227434f8 1317 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1318
1319 if (s->active_rx == s->cookie_rx[0]) {
1320 active = 0;
1321 } else if (s->active_rx == s->cookie_rx[1]) {
1322 active = 1;
1323 } else {
1324 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1325 return 0;
1326 }
1327
1328 if (room < count)
e2afca69 1329 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1330 count - room);
1331 if (!room)
1332 return room;
1333
1334 for (i = 0; i < room; i++)
92a19f9c 1335 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1336 TTY_NORMAL);
1337
1338 port->icount.rx += room;
1339
1340 return room;
1341}
1342
1343static void sci_dma_rx_complete(void *arg)
1344{
1345 struct sci_port *s = arg;
1346 struct uart_port *port = &s->port;
73a19e4c
GL		 1347 unsigned long flags;
1348 int count;
1349
9b971cd2
JP		 1350 dev_dbg(port->dev, "%s(%d) active #%d\n",
1351 __func__, port->line, s->active_rx);
73a19e4c
GL		 1352
1353 spin_lock_irqsave(&port->lock, flags);
1354
92a19f9c 1355 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1356
3089f381 1357 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1358
1359 spin_unlock_irqrestore(&port->lock, flags);
1360
1361 if (count)
2e124b4a 1362 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1363
1364 schedule_work(&s->work_rx);
1365}
1366
73a19e4c
GL		 1367static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1368{
1369 struct dma_chan *chan = s->chan_rx;
1370 struct uart_port *port = &s->port;
73a19e4c
GL		 1371
1372 s->chan_rx = NULL;
1373 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1374 dma_release_channel(chan);
85b8e3ff
GL		 1375 if (sg_dma_address(&s->sg_rx[0]))
1376 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1377 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1378 if (enable_pio)
1379 sci_start_rx(port);
1380}
1381
1382static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1383{
1384 struct dma_chan *chan = s->chan_tx;
1385 struct uart_port *port = &s->port;
73a19e4c
GL		 1386
1387 s->chan_tx = NULL;
1388 s->cookie_tx = -EINVAL;
1389 dma_release_channel(chan);
1390 if (enable_pio)
1391 sci_start_tx(port);
1392}
1393
1394static void sci_submit_rx(struct sci_port *s)
1395{
1396 struct dma_chan *chan = s->chan_rx;
1397 int i;
1398
1399 for (i = 0; i < 2; i++) {
1400 struct scatterlist *sg = &s->sg_rx[i];
1401 struct dma_async_tx_descriptor *desc;
1402
16052827 1403 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1404 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1405
1406 if (desc) {
1407 s->desc_rx[i] = desc;
1408 desc->callback = sci_dma_rx_complete;
1409 desc->callback_param = s;
1410 s->cookie_rx[i] = desc->tx_submit(desc);
1411 }
1412
1413 if (!desc || s->cookie_rx[i] < 0) {
1414 if (i) {
1415 async_tx_ack(s->desc_rx[0]);
1416 s->cookie_rx[0] = -EINVAL;
1417 }
1418 if (desc) {
1419 async_tx_ack(desc);
1420 s->cookie_rx[i] = -EINVAL;
1421 }
1422 dev_warn(s->port.dev,
1423 "failed to re-start DMA, using PIO\n");
1424 sci_rx_dma_release(s, true);
1425 return;
1426 }
9b971cd2
JP		 1427 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1428 __func__, s->cookie_rx[i], i);
73a19e4c
GL		 1429 }
1430
1431 s->active_rx = s->cookie_rx[0];
1432
1433 dma_async_issue_pending(chan);
1434}
1435
1436static void work_fn_rx(struct work_struct *work)
1437{
1438 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1439 struct uart_port *port = &s->port;
1440 struct dma_async_tx_descriptor *desc;
1441 int new;
1442
1443 if (s->active_rx == s->cookie_rx[0]) {
1444 new = 0;
1445 } else if (s->active_rx == s->cookie_rx[1]) {
1446 new = 1;
1447 } else {
1448 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1449 return;
1450 }
1451 desc = s->desc_rx[new];
1452
1453 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1454 DMA_COMPLETE) {
73a19e4c 1455 /* Handle incomplete DMA receive */
73a19e4c 1456 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1457 struct shdma_desc *sh_desc = container_of(desc,
1458 struct shdma_desc, async_tx);
73a19e4c
GL		 1459 unsigned long flags;
1460 int count;
1461
2bcd90d5 1462 dmaengine_terminate_all(chan);
e2afca69 1463 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1464 sh_desc->partial, sh_desc->cookie);
1465
1466 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1467 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1468 spin_unlock_irqrestore(&port->lock, flags);
1469
1470 if (count)
2e124b4a 1471 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1472
1473 sci_submit_rx(s);
1474
1475 return;
1476 }
1477
1478 s->cookie_rx[new] = desc->tx_submit(desc);
1479 if (s->cookie_rx[new] < 0) {
1480 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1481 sci_rx_dma_release(s, true);
1482 return;
1483 }
1484
73a19e4c 1485 s->active_rx = s->cookie_rx[!new];
3089f381 1486
9b971cd2
JP		 1487 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1488 __func__, s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1489}
1490
1491static void work_fn_tx(struct work_struct *work)
1492{
1493 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1494 struct dma_async_tx_descriptor *desc;
1495 struct dma_chan *chan = s->chan_tx;
1496 struct uart_port *port = &s->port;
1497 struct circ_buf *xmit = &port->state->xmit;
1498 struct scatterlist *sg = &s->sg_tx;
1499
1500 /*
1501 * DMA is idle now.
1502 * Port xmit buffer is already mapped, and it is one page... Just adjust
1503 * offsets and lengths. Since it is a circular buffer, we have to
1504 * transmit till the end, and then the rest. Take the port lock to get a
1505 * consistent xmit buffer state.
1506 */
1507 spin_lock_irq(&port->lock);
1508 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1509 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1510 sg->offset;
f354a381 1511 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1512 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1513 spin_unlock_irq(&port->lock);
1514
f354a381 1515 BUG_ON(!sg_dma_len(sg));
73a19e4c 1516
16052827 1517 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1518 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1519 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1520 if (!desc) {
1521 /* switch to PIO */
1522 sci_tx_dma_release(s, true);
1523 return;
1524 }
1525
1526 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1527
1528 spin_lock_irq(&port->lock);
1529 s->desc_tx = desc;
1530 desc->callback = sci_dma_tx_complete;
1531 desc->callback_param = s;
1532 spin_unlock_irq(&port->lock);
1533 s->cookie_tx = desc->tx_submit(desc);
1534 if (s->cookie_tx < 0) {
1535 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1536 /* switch to PIO */
1537 sci_tx_dma_release(s, true);
1538 return;
1539 }
1540
9b971cd2
JP		 1541 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1542 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c
GL		 1543
1544 dma_async_issue_pending(chan);
1545}
1546#endif
1547
b129a8cc 1548static void sci_start_tx(struct uart_port *port)
1da177e4 1549{
3089f381 1550 struct sci_port *s = to_sci_port(port);
e108b2ca 1551 unsigned short ctrl;
1da177e4 1552
73a19e4c 1553#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1554 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1555 u16 new, scr = serial_port_in(port, SCSCR);
3089f381 1556 if (s->chan_tx)
26de4f1b 1557 new = scr | SCSCR_TDRQE;
3089f381 1558 else
26de4f1b 1559 new = scr & ~SCSCR_TDRQE;
3089f381 1560 if (new != scr)
b12bb29f 1561 serial_port_out(port, SCSCR, new);
73a19e4c 1562 }
f43dc23d 1563
3089f381 1564 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1565 s->cookie_tx < 0) {
1566 s->cookie_tx = 0;
3089f381 1567 schedule_work(&s->work_tx);
49d4bcad 1568 }
73a19e4c 1569#endif
f43dc23d 1570
d1d4b10c 1571 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1572 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1573 ctrl = serial_port_in(port, SCSCR);
1574 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1575 }
1da177e4
LT		 1576}
1577
b129a8cc 1578static void sci_stop_tx(struct uart_port *port)
1da177e4 1579{
1da177e4
LT		 1580 unsigned short ctrl;
1581
1582 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1583 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1584
d1d4b10c 1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1586 ctrl &= ~SCSCR_TDRQE;
f43dc23d 1587
8e698614 1588 ctrl &= ~SCSCR_TIE;
f43dc23d 1589
b12bb29f 1590 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1591}
1592
73a19e4c 1593static void sci_start_rx(struct uart_port *port)
1da177e4 1594{
1da177e4
LT		 1595 unsigned short ctrl;
1596
b12bb29f 1597 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1598
d1d4b10c 1599 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1600 ctrl &= ~SCSCR_RDRQE;
f43dc23d 1601
b12bb29f 1602 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1603}
1604
1605static void sci_stop_rx(struct uart_port *port)
1606{
1da177e4
LT		 1607 unsigned short ctrl;
1608
b12bb29f 1609 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1610
d1d4b10c 1611 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1612 ctrl &= ~SCSCR_RDRQE;
f43dc23d
PM		 1613
1614 ctrl &= ~port_rx_irq_mask(port);
1615
b12bb29f 1616 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1617}
1618
1da177e4
LT		 1619static void sci_break_ctl(struct uart_port *port, int break_state)
1620{
bbb4ce50 1621 struct sci_port *s = to_sci_port(port);
a4e02f6d 1622 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1623 unsigned short scscr, scsptr;
1624
a4e02f6d
SY		 1625 /* check wheter the port has SCSPTR */
1626 if (!reg->size) {
bbb4ce50
SY		 1627 /*
1628 * Not supported by hardware. Most parts couple break and rx
1629 * interrupts together, with break detection always enabled.
1630 */
a4e02f6d 1631 return;
bbb4ce50 1632 }
a4e02f6d
SY		 1633
1634 scsptr = serial_port_in(port, SCSPTR);
1635 scscr = serial_port_in(port, SCSCR);
1636
1637 if (break_state == -1) {
1638 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1639 scscr &= ~SCSCR_TE;
1640 } else {
1641 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1642 scscr |= SCSCR_TE;
1643 }
1644
1645 serial_port_out(port, SCSPTR, scsptr);
1646 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1647}
1648
73a19e4c
GL		 1649#ifdef CONFIG_SERIAL_SH_SCI_DMA
1650static bool filter(struct dma_chan *chan, void *slave)
1651{
1652 struct sh_dmae_slave *param = slave;
1653
9b971cd2
JP		 1654 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1655 __func__, param->shdma_slave.slave_id);
73a19e4c 1656
d6fa5a4e 1657 chan->private = &param->shdma_slave;
937bb6e4 1658 return true;
73a19e4c
GL		 1659}
1660
1661static void rx_timer_fn(unsigned long arg)
1662{
1663 struct sci_port *s = (struct sci_port *)arg;
1664 struct uart_port *port = &s->port;
b12bb29f 1665 u16 scr = serial_port_in(port, SCSCR);
3089f381 1666
d1d4b10c 1667 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
26de4f1b 1668 scr &= ~SCSCR_RDRQE;
1fcc91a6 1669 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1670 }
b12bb29f 1671 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1672 dev_dbg(port->dev, "DMA Rx timed out\n");
1673 schedule_work(&s->work_rx);
1674}
1675
1676static void sci_request_dma(struct uart_port *port)
1677{
1678 struct sci_port *s = to_sci_port(port);
1679 struct sh_dmae_slave *param;
1680 struct dma_chan *chan;
1681 dma_cap_mask_t mask;
1682 int nent;
1683
9b971cd2 1684 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1685
937bb6e4 1686 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1687 return;
1688
1689 dma_cap_zero(mask);
1690 dma_cap_set(DMA_SLAVE, mask);
1691
1692 param = &s->param_tx;
1693
1694 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1695 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1696
1697 s->cookie_tx = -EINVAL;
1698 chan = dma_request_channel(mask, filter, param);
1699 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1700 if (chan) {
1701 s->chan_tx = chan;
1702 sg_init_table(&s->sg_tx, 1);
1703 /* UART circular tx buffer is an aligned page. */
e2afca69 1704 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1705 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1706 UART_XMIT_SIZE,
1707 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1708 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1709 if (!nent)
1710 sci_tx_dma_release(s, false);
1711 else
9b971cd2
JP		 1712 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1713 __func__,
e2afca69
LP		 1714 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1715 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1716
1717 s->sg_len_tx = nent;
1718
1719 INIT_WORK(&s->work_tx, work_fn_tx);
1720 }
1721
1722 param = &s->param_rx;
1723
1724 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1725 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1726
1727 chan = dma_request_channel(mask, filter, param);
1728 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1729 if (chan) {
1730 dma_addr_t dma[2];
1731 void *buf[2];
1732 int i;
1733
1734 s->chan_rx = chan;
1735
1736 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1737 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1738 &dma[0], GFP_KERNEL);
1739
1740 if (!buf[0]) {
1741 dev_warn(port->dev,
1742 "failed to allocate dma buffer, using PIO\n");
1743 sci_rx_dma_release(s, true);
1744 return;
1745 }
1746
1747 buf[1] = buf[0] + s->buf_len_rx;
1748 dma[1] = dma[0] + s->buf_len_rx;
1749
1750 for (i = 0; i < 2; i++) {
1751 struct scatterlist *sg = &s->sg_rx[i];
1752
1753 sg_init_table(sg, 1);
1754 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1755 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1756 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1757 }
1758
1759 INIT_WORK(&s->work_rx, work_fn_rx);
1760 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1761
1762 sci_submit_rx(s);
1763 }
1764}
1765
1766static void sci_free_dma(struct uart_port *port)
1767{
1768 struct sci_port *s = to_sci_port(port);
1769
73a19e4c
GL		 1770 if (s->chan_tx)
1771 sci_tx_dma_release(s, false);
1772 if (s->chan_rx)
1773 sci_rx_dma_release(s, false);
1774}
27bd1075
PM		 1775#else
1776static inline void sci_request_dma(struct uart_port *port)
1777{
1778}
1779
1780static inline void sci_free_dma(struct uart_port *port)
1781{
1782}
73a19e4c
GL		 1783#endif
1784
1da177e4
LT		 1785static int sci_startup(struct uart_port *port)
1786{
a5660ada 1787 struct sci_port *s = to_sci_port(port);
33b48e16 1788 unsigned long flags;
073e84c9 1789 int ret;
1da177e4 1790
73a19e4c
GL		 1791 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1792
073e84c9
PM		 1793 ret = sci_request_irq(s);
1794 if (unlikely(ret < 0))
1795 return ret;
1796
73a19e4c 1797 sci_request_dma(port);
073e84c9 1798
33b48e16 1799 spin_lock_irqsave(&port->lock, flags);
d656901b 1800 sci_start_tx(port);
73a19e4c 1801 sci_start_rx(port);
33b48e16 1802 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1803
1804 return 0;
1805}
1806
1807static void sci_shutdown(struct uart_port *port)
1808{
a5660ada 1809 struct sci_port *s = to_sci_port(port);
33b48e16 1810 unsigned long flags;
1da177e4 1811
73a19e4c
GL		 1812 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1813
33b48e16 1814 spin_lock_irqsave(&port->lock, flags);
1da177e4 1815 sci_stop_rx(port);
b129a8cc 1816 sci_stop_tx(port);
33b48e16 1817 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1818
73a19e4c 1819 sci_free_dma(port);
1da177e4 1820 sci_free_irq(s);
1da177e4
LT		 1821}
1822
ec09c5eb 1823static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1824 unsigned long freq)
1825{
ec09c5eb
LP		 1826 if (s->sampling_rate)
1827 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1828
26c92f37
PM		 1829 /* Warn, but use a safe default */
1830 WARN_ON(1);
e8183a6c 1831
26c92f37
PM		 1832 return ((freq + 16 * bps) / (32 * bps) - 1);
1833}
1834
730c4e78
NI		 1835/* calculate frame length from SMR */
1836static int sci_baud_calc_frame_len(unsigned int smr_val)
1837{
1838 int len = 10;
1839
1840 if (smr_val & SCSMR_CHR)
1841 len--;
1842 if (smr_val & SCSMR_PE)
1843 len++;
1844 if (smr_val & SCSMR_STOP)
1845 len++;
1846
1847 return len;
1848}
1849
1850
f303b364
UH		 1851/* calculate sample rate, BRR, and clock select for HSCIF */
1852static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1853 int *brr, unsigned int *srr,
730c4e78 1854 unsigned int *cks, int frame_len)
f303b364 1855{
730c4e78 1856 int sr, c, br, err, recv_margin;
f303b364 1857 int min_err = 1000; /* 100% */
730c4e78 1858 int recv_max_margin = 0;
f303b364
UH		 1859
1860 /* Find the combination of sample rate and clock select with the
1861 smallest deviation from the desired baud rate. */
1862 for (sr = 8; sr <= 32; sr++) {
1863 for (c = 0; c <= 3; c++) {
1864 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1865 br = DIV_ROUND_CLOSEST(freq, (sr *
1866 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1867 br = clamp(br, 0, 255);
b7d66397
NI		 1868 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1869 (1 << (2 * c + 1)) / 1000)) -
1870 1000;
730c4e78
NI		 1871 /* Calc recv margin
1872 * M: Receive margin (%)
1873 * N: Ratio of bit rate to clock (N = sampling rate)
1874 * D: Clock duty (D = 0 to 1.0)
1875 * L: Frame length (L = 9 to 12)
1876 * F: Absolute value of clock frequency deviation
1877 *
1878 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1879 * (|D - 0.5| / N * (1 + F))|
1880 * NOTE: Usually, treat D for 0.5, F is 0 by this
1881 * calculation.
1882 */
1883 recv_margin = abs((500 -
1884 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1885 if (abs(min_err) > abs(err)) {
f303b364 1886 min_err = err;
730c4e78
NI		 1887 recv_max_margin = recv_margin;
1888 } else if ((min_err == err) &&
1889 (recv_margin > recv_max_margin))
1890 recv_max_margin = recv_margin;
1891 else
1892 continue;
1893
1894 *brr = br;
1895 *srr = sr - 1;
1896 *cks = c;
f303b364
UH		 1897 }
1898 }
1899
1900 if (min_err == 1000) {
1901 WARN_ON(1);
1902 /* use defaults */
1903 *brr = 255;
1904 *srr = 15;
1905 *cks = 0;
1906 }
1907}
1908
1ba76220
MD		 1909static void sci_reset(struct uart_port *port)
1910{
0979e0e6 1911 struct plat_sci_reg *reg;
1ba76220
MD		 1912 unsigned int status;
1913
1914 do {
b12bb29f 1915 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1916 } while (!(status & SCxSR_TEND(port)));
1917
b12bb29f 1918 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1919
0979e0e6
PM		 1920 reg = sci_getreg(port, SCFCR);
1921 if (reg->size)
b12bb29f 1922 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1923}
1924
606d099c
AC		 1925static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1926 struct ktermios *old)
1da177e4 1927{
00b9de9c 1928 struct sci_port *s = to_sci_port(port);
0979e0e6 1929 struct plat_sci_reg *reg;
730c4e78 1930 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1931 int t = -1;
d4759ded 1932 unsigned int srr = 15;
1da177e4 1933
730c4e78
NI		 1934 if ((termios->c_cflag & CSIZE) == CS7)
1935 smr_val |= SCSMR_CHR;
1936 if (termios->c_cflag & PARENB)
1937 smr_val |= SCSMR_PE;
1938 if (termios->c_cflag & PARODD)
1939 smr_val |= SCSMR_PE | SCSMR_ODD;
1940 if (termios->c_cflag & CSTOPB)
1941 smr_val |= SCSMR_STOP;
1942
154280fd
MD		 1943 /*
1944 * earlyprintk comes here early on with port->uartclk set to zero.
1945 * the clock framework is not up and running at this point so here
1946 * we assume that 115200 is the maximum baud rate. please note that
1947 * the baud rate is not programmed during earlyprintk - it is assumed
1948 * that the previous boot loader has enabled required clocks and
1949 * setup the baud rate generator hardware for us already.
1950 */
1951 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1952
154280fd 1953 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1954 if (likely(baud && port->uartclk)) {
ec09c5eb 1955 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1956 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1957 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1958 &cks, frame_len);
f303b364 1959 } else {
ec09c5eb 1960 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1961 for (cks = 0; t >= 256 && cks <= 3; cks++)
1962 t >>= 2;
1963 }
1964 }
e108b2ca 1965
23241d43 1966 sci_port_enable(s);
36003386 1967
1ba76220 1968 sci_reset(port);
1da177e4 1969
730c4e78 1970 smr_val |= serial_port_in(port, SCSMR) & 3;
1da177e4
LT		 1971
1972 uart_update_timeout(port, termios->c_cflag, baud);
1973
9d482cc3
TY		 1974 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1975 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1976
4ffc3cdb 1977 if (t >= 0) {
26de4f1b 1978 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1979 serial_port_out(port, SCBRR, t);
f303b364
UH		 1980 reg = sci_getreg(port, HSSRR);
1981 if (reg->size)
1982 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1983 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1984 } else
1985 serial_port_out(port, SCSMR, smr_val);
1da177e4 1986
d5701647 1987 sci_init_pins(port, termios->c_cflag);
0979e0e6 1988
73c3d53f
PM		 1989 reg = sci_getreg(port, SCFCR);
1990 if (reg->size) {
b12bb29f 1991 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1992
73c3d53f 1993 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1994 if (termios->c_cflag & CRTSCTS)
1995 ctrl |= SCFCR_MCE;
1996 else
1997 ctrl &= ~SCFCR_MCE;
faf02f8f 1998 }
73c3d53f
PM		 1999
2000 /*
2001 * As we've done a sci_reset() above, ensure we don't
2002 * interfere with the FIFOs while toggling MCE. As the
2003 * reset values could still be set, simply mask them out.
2004 */
2005 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2006
b12bb29f 2007 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2008 }
b7a76e4b 2009
b12bb29f 2010 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2011
3089f381
GL		 2012#ifdef CONFIG_SERIAL_SH_SCI_DMA
2013 /*
5f6d8515
NI		 2014 * Calculate delay for 2 DMA buffers (4 FIFO).
2015 * See drivers/serial/serial_core.c::uart_update_timeout(). With 10
2016 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
3089f381 2017 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
5f6d8515
NI		 2018 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
2019 * sizes), but when performing a faster transfer, value obtained by
2020 * this formula is may not enough. Therefore, if value is smaller than
2021 * 20msec, this sets 20msec as timeout of DMA.
3089f381
GL		 2022 */
2023 if (s->chan_rx) {
5f6d8515
NI		 2024 unsigned int bits;
2025
2026 /* byte size and parity */
2027 switch (termios->c_cflag & CSIZE) {
2028 case CS5:
2029 bits = 7;
2030 break;
2031 case CS6:
2032 bits = 8;
2033 break;
2034 case CS7:
2035 bits = 9;
2036 break;
2037 default:
2038 bits = 10;
2039 break;
2040 }
2041
2042 if (termios->c_cflag & CSTOPB)
2043 bits++;
2044 if (termios->c_cflag & PARENB)
2045 bits++;
2046 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2047 (baud / 10), 10);
9b971cd2 2048 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2049 s->rx_timeout * 1000 / HZ, port->timeout);
2050 if (s->rx_timeout < msecs_to_jiffies(20))
2051 s->rx_timeout = msecs_to_jiffies(20);
2052 }
2053#endif
2054
1da177e4 2055 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2056 sci_start_rx(port);
36003386 2057
23241d43 2058 sci_port_disable(s);
1da177e4
LT		 2059}
2060
0174e5ca
TK		 2061static void sci_pm(struct uart_port *port, unsigned int state,
2062 unsigned int oldstate)
2063{
2064 struct sci_port *sci_port = to_sci_port(port);
2065
2066 switch (state) {
d3dfe5d9 2067 case UART_PM_STATE_OFF:
0174e5ca
TK		 2068 sci_port_disable(sci_port);
2069 break;
2070 default:
2071 sci_port_enable(sci_port);
2072 break;
2073 }
2074}
2075
1da177e4
LT		 2076static const char *sci_type(struct uart_port *port)
2077{
2078 switch (port->type) {
e7c98dc7
MT		 2079 case PORT_IRDA:
2080 return "irda";
2081 case PORT_SCI:
2082 return "sci";
2083 case PORT_SCIF:
2084 return "scif";
2085 case PORT_SCIFA:
2086 return "scifa";
d1d4b10c
GL		 2087 case PORT_SCIFB:
2088 return "scifb";
f303b364
UH		 2089 case PORT_HSCIF:
2090 return "hscif";
1da177e4
LT		 2091 }
2092
fa43972f 2093 return NULL;
1da177e4
LT		 2094}
2095
f6e9495d
PM		 2096static int sci_remap_port(struct uart_port *port)
2097{
e4d6f911 2098 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2099
2100 /*
2101 * Nothing to do if there's already an established membase.
2102 */
2103 if (port->membase)
2104 return 0;
2105
2106 if (port->flags & UPF_IOREMAP) {
e4d6f911 2107 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2108 if (unlikely(!port->membase)) {
2109 dev_err(port->dev, "can't remap port#%d\n", port->line);
2110 return -ENXIO;
2111 }
2112 } else {
2113 /*
2114 * For the simple (and majority of) cases where we don't
2115 * need to do any remapping, just cast the cookie
2116 * directly.
2117 */
3af4e960 2118 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2119 }
2120
2121 return 0;
2122}
2123
e2651647 2124static void sci_release_port(struct uart_port *port)
1da177e4 2125{
e4d6f911
YS		 2126 struct sci_port *sport = to_sci_port(port);
2127
e2651647
PM		 2128 if (port->flags & UPF_IOREMAP) {
2129 iounmap(port->membase);
2130 port->membase = NULL;
2131 }
2132
e4d6f911 2133 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2134}
2135
e2651647 2136static int sci_request_port(struct uart_port *port)
1da177e4 2137{
e2651647 2138 struct resource *res;
e4d6f911 2139 struct sci_port *sport = to_sci_port(port);
f6e9495d 2140 int ret;
1da177e4 2141
e4d6f911
YS		 2142 res = request_mem_region(port->mapbase, sport->reg_size,
2143 dev_name(port->dev));
2144 if (unlikely(res == NULL)) {
2145 dev_err(port->dev, "request_mem_region failed.");
e2651647 2146 return -EBUSY;
e4d6f911 2147 }
1da177e4 2148
f6e9495d
PM		 2149 ret = sci_remap_port(port);
2150 if (unlikely(ret != 0)) {
2151 release_resource(res);
2152 return ret;
7ff731ae 2153 }
e2651647
PM		 2154
2155 return 0;
2156}
2157
2158static void sci_config_port(struct uart_port *port, int flags)
2159{
2160 if (flags & UART_CONFIG_TYPE) {
2161 struct sci_port *sport = to_sci_port(port);
2162
2163 port->type = sport->cfg->type;
2164 sci_request_port(port);
2165 }
1da177e4
LT		 2166}
2167
2168static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2169{
1da177e4
LT		 2170 if (ser->baud_base < 2400)
2171 /* No paper tape reader for Mitch.. */
2172 return -EINVAL;
2173
2174 return 0;
2175}
2176
2177static struct uart_ops sci_uart_ops = {
2178 .tx_empty = sci_tx_empty,
2179 .set_mctrl = sci_set_mctrl,
2180 .get_mctrl = sci_get_mctrl,
2181 .start_tx = sci_start_tx,
2182 .stop_tx = sci_stop_tx,
2183 .stop_rx = sci_stop_rx,
1da177e4
LT		 2184 .break_ctl = sci_break_ctl,
2185 .startup = sci_startup,
2186 .shutdown = sci_shutdown,
2187 .set_termios = sci_set_termios,
0174e5ca 2188 .pm = sci_pm,
1da177e4
LT		 2189 .type = sci_type,
2190 .release_port = sci_release_port,
2191 .request_port = sci_request_port,
2192 .config_port = sci_config_port,
2193 .verify_port = sci_verify_port,
07d2a1a1
PM		 2194#ifdef CONFIG_CONSOLE_POLL
2195 .poll_get_char = sci_poll_get_char,
2196 .poll_put_char = sci_poll_put_char,
2197#endif
1da177e4
LT		 2198};
2199
9671f099 2200static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2201 struct sci_port *sci_port, unsigned int index,
2202 struct plat_sci_port *p, bool early)
e108b2ca 2203{
73a19e4c 2204 struct uart_port *port = &sci_port->port;
1fcc91a6 2205 const struct resource *res;
ec09c5eb 2206 unsigned int sampling_rate;
1fcc91a6 2207 unsigned int i;
3127c6b2 2208 int ret;
e108b2ca 2209
50f0959a
PM		 2210 sci_port->cfg = p;
2211
73a19e4c
GL		 2212 port->ops = &sci_uart_ops;
2213 port->iotype = UPIO_MEM;
2214 port->line = index;
75136d48 2215
89b5c1ab
LP		 2216 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2217 if (res == NULL)
2218 return -ENOMEM;
1fcc91a6 2219
89b5c1ab 2220 port->mapbase = res->start;
e4d6f911 2221 sci_port->reg_size = resource_size(res);
1fcc91a6 2222
89b5c1ab
LP		 2223 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2224 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2225
89b5c1ab
LP		 2226 /* The SCI generates several interrupts. They can be muxed together or
2227 * connected to different interrupt lines. In the muxed case only one
2228 * interrupt resource is specified. In the non-muxed case three or four
2229 * interrupt resources are specified, as the BRI interrupt is optional.
2230 */
2231 if (sci_port->irqs[0] < 0)
2232 return -ENXIO;
1fcc91a6 2233
89b5c1ab
LP		 2234 if (sci_port->irqs[1] < 0) {
2235 sci_port->irqs[1] = sci_port->irqs[0];
2236 sci_port->irqs[2] = sci_port->irqs[0];
2237 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2238 }
2239
b545e4f4
LP		 2240 if (p->regtype == SCIx_PROBE_REGTYPE) {
2241 ret = sci_probe_regmap(p);
2242 if (unlikely(ret))
2243 return ret;
2244 }
2245
75136d48 2246 switch (p->type) {
d1d4b10c
GL		 2247 case PORT_SCIFB:
2248 port->fifosize = 256;
2e0842a1 2249 sci_port->overrun_reg = SCxSR;
75c249fd 2250 sci_port->overrun_mask = SCIFA_ORER;
ec09c5eb 2251 sampling_rate = 16;
d1d4b10c 2252 break;
f303b364
UH		 2253 case PORT_HSCIF:
2254 port->fifosize = 128;
ec09c5eb 2255 sampling_rate = 0;
2e0842a1 2256 sci_port->overrun_reg = SCLSR;
75c249fd 2257 sci_port->overrun_mask = SCLSR_ORER;
f303b364 2258 break;
75136d48 2259 case PORT_SCIFA:
73a19e4c 2260 port->fifosize = 64;
2e0842a1 2261 sci_port->overrun_reg = SCxSR;
75c249fd 2262 sci_port->overrun_mask = SCIFA_ORER;
ec09c5eb 2263 sampling_rate = 16;
75136d48
MP		 2264 break;
2265 case PORT_SCIF:
73a19e4c 2266 port->fifosize = 16;
ec09c5eb 2267 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2268 sci_port->overrun_reg = SCxSR;
75c249fd 2269 sci_port->overrun_mask = SCIFA_ORER;
ec09c5eb
LP		 2270 sampling_rate = 16;
2271 } else {
2e0842a1 2272 sci_port->overrun_reg = SCLSR;
75c249fd 2273 sci_port->overrun_mask = SCLSR_ORER;
ec09c5eb
LP		 2274 sampling_rate = 32;
2275 }
75136d48
MP		 2276 break;
2277 default:
73a19e4c 2278 port->fifosize = 1;
2e0842a1 2279 sci_port->overrun_reg = SCxSR;
75c249fd 2280 sci_port->overrun_mask = SCI_ORER;
ec09c5eb 2281 sampling_rate = 32;
75136d48
MP		 2282 break;
2283 }
7b6fd3bf 2284
878fbb91
LP		 2285 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2286 * match the SoC datasheet, this should be investigated. Let platform
2287 * data override the sampling rate for now.
ec09c5eb 2288 */
878fbb91
LP		 2289 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2290 : sampling_rate;
ec09c5eb 2291
1fcc91a6 2292 if (!early) {
c7ed1ab3
PM		 2293 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2294 if (IS_ERR(sci_port->iclk)) {
2295 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2296 if (IS_ERR(sci_port->iclk)) {
2297 dev_err(&dev->dev, "can't get iclk\n");
2298 return PTR_ERR(sci_port->iclk);
2299 }
2300 }
2301
2302 /*
2303 * The function clock is optional, ignore it if we can't
2304 * find it.
2305 */
2306 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2307 if (IS_ERR(sci_port->fclk))
2308 sci_port->fclk = NULL;
2309
73a19e4c 2310 port->dev = &dev->dev;
5e50d2d6
MD		 2311
2312 pm_runtime_enable(&dev->dev);
7b6fd3bf 2313 }
e108b2ca 2314
7ed7e071
MD		 2315 sci_port->break_timer.data = (unsigned long)sci_port;
2316 sci_port->break_timer.function = sci_break_timer;
2317 init_timer(&sci_port->break_timer);
2318
debf9507
PM		 2319 /*
2320 * Establish some sensible defaults for the error detection.
2321 */
3ae988d9 2322 sci_port->error_mask = (p->type == PORT_SCI) ?
debf9507
PM		 2323 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2324
3ae988d9
LP		 2325 /*
2326 * Make the error mask inclusive of overrun detection, if
2327 * supported.
2328 */
afd66db6
GU		 2329 if (sci_port->overrun_reg == SCxSR)
2330 sci_port->error_mask |= sci_port->overrun_mask;
debf9507 2331
ce6738b6 2332 port->type = p->type;
b6e4a3f1 2333 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2334 port->regshift = p->regshift;
73a19e4c 2335
ce6738b6 2336 /*
61a6976b 2337 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2338 * for the multi-IRQ ports, which is where we are primarily
2339 * concerned with the shutdown path synchronization.
2340 *
2341 * For the muxed case there's nothing more to do.
2342 */
1fcc91a6 2343 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2344 port->irqflags = 0;
73a19e4c 2345
61a6976b
PM		 2346 port->serial_in = sci_serial_in;
2347 port->serial_out = sci_serial_out;
2348
937bb6e4
GL		 2349 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2350 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2351 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2352
c7ed1ab3 2353 return 0;
e108b2ca
PM		 2354}
2355
6dae1421
LP		 2356static void sci_cleanup_single(struct sci_port *port)
2357{
6dae1421
LP		 2358 clk_put(port->iclk);
2359 clk_put(port->fclk);
2360
2361 pm_runtime_disable(port->port.dev);
2362}
2363
1da177e4 2364#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2365static void serial_console_putchar(struct uart_port *port, int ch)
2366{
2367 sci_poll_put_char(port, ch);
2368}
2369
1da177e4
LT		 2370/*
2371 * Print a string to the serial port trying not to disturb
2372 * any possible real use of the port...
2373 */
2374static void serial_console_write(struct console *co, const char *s,
2375 unsigned count)
2376{
906b17dc
PM		 2377 struct sci_port *sci_port = &sci_ports[co->index];
2378 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2379 unsigned short bits, ctrl;
2380 unsigned long flags;
2381 int locked = 1;
2382
2383 local_irq_save(flags);
2384 if (port->sysrq)
2385 locked = 0;
2386 else if (oops_in_progress)
2387 locked = spin_trylock(&port->lock);
2388 else
2389 spin_lock(&port->lock);
2390
2391 /* first save the SCSCR then disable the interrupts */
2392 ctrl = serial_port_in(port, SCSCR);
2393 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2394
501b825d 2395 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2396
2397 /* wait until fifo is empty and last bit has been transmitted */
2398 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2399 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2400 cpu_relax();
40f70c03
SK		 2401
2402 /* restore the SCSCR */
2403 serial_port_out(port, SCSCR, ctrl);
2404
2405 if (locked)
2406 spin_unlock(&port->lock);
2407 local_irq_restore(flags);
1da177e4
LT		 2408}
2409
9671f099 2410static int serial_console_setup(struct console *co, char *options)
1da177e4 2411{
dc8e6f5b 2412 struct sci_port *sci_port;
1da177e4
LT		 2413 struct uart_port *port;
2414 int baud = 115200;
2415 int bits = 8;
2416 int parity = 'n';
2417 int flow = 'n';
2418 int ret;
2419
e108b2ca 2420 /*
906b17dc 2421 * Refuse to handle any bogus ports.
1da177e4 2422 */
906b17dc 2423 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2424 return -ENODEV;
e108b2ca 2425
906b17dc
PM		 2426 sci_port = &sci_ports[co->index];
2427 port = &sci_port->port;
2428
b2267a6b
AC		 2429 /*
2430 * Refuse to handle uninitialized ports.
2431 */
2432 if (!port->ops)
2433 return -ENODEV;
2434
f6e9495d
PM		 2435 ret = sci_remap_port(port);
2436 if (unlikely(ret != 0))
2437 return ret;
e108b2ca 2438
1da177e4
LT		 2439 if (options)
2440 uart_parse_options(options, &baud, &parity, &bits, &flow);
2441
ab7cfb55 2442 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2443}
2444
2445static struct console serial_console = {
2446 .name = "ttySC",
906b17dc 2447 .device = uart_console_device,
1da177e4
LT		 2448 .write = serial_console_write,
2449 .setup = serial_console_setup,
fa5da2f7 2450 .flags = CON_PRINTBUFFER,
1da177e4 2451 .index = -1,
906b17dc 2452 .data = &sci_uart_driver,
1da177e4
LT		 2453};
2454
7b6fd3bf
MD		 2455static struct console early_serial_console = {
2456 .name = "early_ttySC",
2457 .write = serial_console_write,
2458 .flags = CON_PRINTBUFFER,
906b17dc 2459 .index = -1,
7b6fd3bf 2460};
ecdf8a46 2461
7b6fd3bf
MD		 2462static char early_serial_buf[32];
2463
9671f099 2464static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2465{
574de559 2466 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2467
2468 if (early_serial_console.data)
2469 return -EEXIST;
2470
2471 early_serial_console.index = pdev->id;
ecdf8a46 2472
1fcc91a6 2473 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2474
2475 serial_console_setup(&early_serial_console, early_serial_buf);
2476
2477 if (!strstr(early_serial_buf, "keep"))
2478 early_serial_console.flags |= CON_BOOT;
2479
2480 register_console(&early_serial_console);
2481 return 0;
2482}
6a8c9799
NI		 2483
2484#define SCI_CONSOLE (&serial_console)
2485
ecdf8a46 2486#else
9671f099 2487static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2488{
2489 return -EINVAL;
2490}
1da177e4 2491
6a8c9799
NI		 2492#define SCI_CONSOLE NULL
2493
2494#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2495
6c13d5d2 2496static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2497
2498static struct uart_driver sci_uart_driver = {
2499 .owner = THIS_MODULE,
2500 .driver_name = "sci",
1da177e4
LT		 2501 .dev_name = "ttySC",
2502 .major = SCI_MAJOR,
2503 .minor = SCI_MINOR_START,
e108b2ca 2504 .nr = SCI_NPORTS,
1da177e4
LT		 2505 .cons = SCI_CONSOLE,
2506};
2507
54507f6e 2508static int sci_remove(struct platform_device *dev)
e552de24 2509{
d535a230 2510 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2511
d535a230
PM		 2512 cpufreq_unregister_notifier(&port->freq_transition,
2513 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2514
d535a230
PM		 2515 uart_remove_one_port(&sci_uart_driver, &port->port);
2516
6dae1421 2517 sci_cleanup_single(port);
e552de24 2518
e552de24
MD		 2519 return 0;
2520}
2521
20bdcab8
BH		 2522struct sci_port_info {
2523 unsigned int type;
2524 unsigned int regtype;
2525};
2526
2527static const struct of_device_id of_sci_match[] = {
2528 {
2529 .compatible = "renesas,scif",
ff43da00 2530 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2531 .type = PORT_SCIF,
2532 .regtype = SCIx_SH4_SCIF_REGTYPE,
2533 },
2534 }, {
2535 .compatible = "renesas,scifa",
ff43da00 2536 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2537 .type = PORT_SCIFA,
2538 .regtype = SCIx_SCIFA_REGTYPE,
2539 },
2540 }, {
2541 .compatible = "renesas,scifb",
ff43da00 2542 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2543 .type = PORT_SCIFB,
2544 .regtype = SCIx_SCIFB_REGTYPE,
2545 },
2546 }, {
2547 .compatible = "renesas,hscif",
ff43da00 2548 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2549 .type = PORT_HSCIF,
2550 .regtype = SCIx_HSCIF_REGTYPE,
2551 },
e1d0be61
YS		 2552 }, {
2553 .compatible = "renesas,sci",
2554 .data = &(const struct sci_port_info) {
2555 .type = PORT_SCI,
2556 .regtype = SCIx_SCI_REGTYPE,
2557 },
20bdcab8
BH		 2558 }, {
2559 /* Terminator */
2560 },
2561};
2562MODULE_DEVICE_TABLE(of, of_sci_match);
2563
2564static struct plat_sci_port *
2565sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2566{
2567 struct device_node *np = pdev->dev.of_node;
2568 const struct of_device_id *match;
2569 const struct sci_port_info *info;
2570 struct plat_sci_port *p;
2571 int id;
2572
2573 if (!IS_ENABLED(CONFIG_OF) || !np)
2574 return NULL;
2575
2576 match = of_match_node(of_sci_match, pdev->dev.of_node);
2577 if (!match)
2578 return NULL;
2579
2580 info = match->data;
2581
2582 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2583 if (!p) {
2584 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2585 return NULL;
2586 }
2587
2588 /* Get the line number for the aliases node. */
2589 id = of_alias_get_id(np, "serial");
2590 if (id < 0) {
2591 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2592 return NULL;
2593 }
2594
2595 *dev_id = id;
2596
2597 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2598 p->type = info->type;
2599 p->regtype = info->regtype;
2600 p->scscr = SCSCR_RE | SCSCR_TE;
2601
2602 return p;
2603}
2604
9671f099 2605static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2606 unsigned int index,
2607 struct plat_sci_port *p,
2608 struct sci_port *sciport)
2609{
0ee70712
MD		 2610 int ret;
2611
2612 /* Sanity check */
2613 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2614 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2615 index+1, SCI_NPORTS);
9b971cd2 2616 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2617 return -EINVAL;
0ee70712
MD		 2618 }
2619
1fcc91a6 2620 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2621 if (ret)
2622 return ret;
0ee70712 2623
6dae1421
LP		 2624 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2625 if (ret) {
2626 sci_cleanup_single(sciport);
2627 return ret;
2628 }
2629
2630 return 0;
0ee70712
MD		 2631}
2632
9671f099 2633static int sci_probe(struct platform_device *dev)
1da177e4 2634{
20bdcab8
BH		 2635 struct plat_sci_port *p;
2636 struct sci_port *sp;
2637 unsigned int dev_id;
ecdf8a46 2638 int ret;
d535a230 2639
ecdf8a46
PM		 2640 /*
2641 * If we've come here via earlyprintk initialization, head off to
2642 * the special early probe. We don't have sufficient device state
2643 * to make it beyond this yet.
2644 */
2645 if (is_early_platform_device(dev))
2646 return sci_probe_earlyprintk(dev);
7b6fd3bf 2647
20bdcab8
BH		 2648 if (dev->dev.of_node) {
2649 p = sci_parse_dt(dev, &dev_id);
2650 if (p == NULL)
2651 return -EINVAL;
2652 } else {
2653 p = dev->dev.platform_data;
2654 if (p == NULL) {
2655 dev_err(&dev->dev, "no platform data supplied\n");
2656 return -EINVAL;
2657 }
2658
2659 dev_id = dev->id;
2660 }
2661
2662 sp = &sci_ports[dev_id];
d535a230 2663 platform_set_drvdata(dev, sp);
e552de24 2664
20bdcab8 2665 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2666 if (ret)
6dae1421 2667 return ret;
e552de24 2668
d535a230 2669 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2670
d535a230
PM		 2671 ret = cpufreq_register_notifier(&sp->freq_transition,
2672 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2673 if (unlikely(ret < 0)) {
bf13c9a8 2674 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2675 sci_cleanup_single(sp);
2676 return ret;
2677 }
1da177e4
LT		 2678
2679#ifdef CONFIG_SH_STANDARD_BIOS
2680 sh_bios_gdb_detach();
2681#endif
2682
e108b2ca 2683 return 0;
1da177e4
LT		 2684}
2685
cb876341 2686static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2687{
d535a230 2688 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2689
d535a230
PM		 2690 if (sport)
2691 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2692
e108b2ca
PM		 2693 return 0;
2694}
1da177e4 2695
cb876341 2696static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2697{
d535a230 2698 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2699
d535a230
PM		 2700 if (sport)
2701 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2702
2703 return 0;
2704}
2705
cb876341 2706static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2707
e108b2ca
PM		 2708static struct platform_driver sci_driver = {
2709 .probe = sci_probe,
b9e39c89 2710 .remove = sci_remove,
e108b2ca
PM		 2711 .driver = {
2712 .name = "sh-sci",
6daa79b3 2713 .pm = &sci_dev_pm_ops,
20bdcab8 2714 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2715 },
2716};
2717
2718static int __init sci_init(void)
2719{
2720 int ret;
2721
6c13d5d2 2722 pr_info("%s\n", banner);
e108b2ca 2723
e108b2ca
PM		 2724 ret = uart_register_driver(&sci_uart_driver);
2725 if (likely(ret == 0)) {
2726 ret = platform_driver_register(&sci_driver);
2727 if (unlikely(ret))
2728 uart_unregister_driver(&sci_uart_driver);
2729 }
2730
2731 return ret;
2732}
2733
2734static void __exit sci_exit(void)
2735{
2736 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2737 uart_unregister_driver(&sci_uart_driver);
2738}
2739
7b6fd3bf
MD		 2740#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2741early_platform_init_buffer("earlyprintk", &sci_driver,
2742 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2743#endif
1da177e4
LT		 2744module_init(sci_init);
2745module_exit(sci_exit);
2746
e108b2ca 2747MODULE_LICENSE("GPL");
e169c139 2748MODULE_ALIAS("platform:sh-sci");
7f405f9c 2749MODULE_AUTHOR("Paul Mundt");
f303b364 2750MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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