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serial: sh-sci: Remove duplicate interrupt check in verify port op
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c
LP		 35#include <linux/gpio.h>
36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
1da177e4 42#include <linux/notifier.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
e108b2ca
PM		 62struct sci_port {
63 struct uart_port port;
64
ce6738b6
PM		 65 /* Platform configuration */
66 struct plat_sci_port *cfg;
e108b2ca 67
e108b2ca
PM		 68 /* Break timer */
69 struct timer_list break_timer;
70 int break_flag;
1534a3b3 71
501b825d
MD		 72 /* Interface clock */
73 struct clk *iclk;
c7ed1ab3
PM		 74 /* Function clock */
75 struct clk *fclk;
edad1f20 76
9174fc8f 77 char *irqstr[SCIx_NR_IRQS];
50f0959a 78 char *gpiostr[SCIx_NR_FNS];
9174fc8f 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
e108b2ca
PM		 102};
103
1da177e4 104/* Function prototypes */
d535a230 105static void sci_start_tx(struct uart_port *port);
b129a8cc 106static void sci_stop_tx(struct uart_port *port);
d535a230 107static void sci_start_rx(struct uart_port *port);
1da177e4 108
e108b2ca 109#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 110
e108b2ca
PM		 111static struct sci_port sci_ports[SCI_NPORTS];
112static struct uart_driver sci_uart_driver;
1da177e4 113
e7c98dc7
MT		 114static inline struct sci_port *
115to_sci_port(struct uart_port *uart)
116{
117 return container_of(uart, struct sci_port, port);
118}
119
61a6976b
PM		 120struct plat_sci_reg {
121 u8 offset, size;
122};
123
124/* Helper for invalidating specific entries of an inherited map. */
125#define sci_reg_invalid { .offset = 0, .size = 0 }
126
127static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
130 },
131
132 /*
133 * Common SCI definitions, dependent on the port's regshift
134 * value.
135 */
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
f303b364 149 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 150 },
151
152 /*
153 * Common definitions for legacy IrDA ports, dependent on
154 * regshift value.
155 */
156 [SCIx_IRDA_REGTYPE] = {
157 [SCSMR] = { 0x00, 8 },
158 [SCBRR] = { 0x01, 8 },
159 [SCSCR] = { 0x02, 8 },
160 [SCxTDR] = { 0x03, 8 },
161 [SCxSR] = { 0x04, 8 },
162 [SCxRDR] = { 0x05, 8 },
163 [SCFCR] = { 0x06, 8 },
164 [SCFDR] = { 0x07, 16 },
165 [SCTFDR] = sci_reg_invalid,
166 [SCRFDR] = sci_reg_invalid,
167 [SCSPTR] = sci_reg_invalid,
168 [SCLSR] = sci_reg_invalid,
f303b364 169 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 170 },
171
172 /*
173 * Common SCIFA definitions.
174 */
175 [SCIx_SCIFA_REGTYPE] = {
176 [SCSMR] = { 0x00, 16 },
177 [SCBRR] = { 0x04, 8 },
178 [SCSCR] = { 0x08, 16 },
179 [SCxTDR] = { 0x20, 8 },
180 [SCxSR] = { 0x14, 16 },
181 [SCxRDR] = { 0x24, 8 },
182 [SCFCR] = { 0x18, 16 },
183 [SCFDR] = { 0x1c, 16 },
184 [SCTFDR] = sci_reg_invalid,
185 [SCRFDR] = sci_reg_invalid,
186 [SCSPTR] = sci_reg_invalid,
187 [SCLSR] = sci_reg_invalid,
f303b364 188 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 189 },
190
191 /*
192 * Common SCIFB definitions.
193 */
194 [SCIx_SCIFB_REGTYPE] = {
195 [SCSMR] = { 0x00, 16 },
196 [SCBRR] = { 0x04, 8 },
197 [SCSCR] = { 0x08, 16 },
198 [SCxTDR] = { 0x40, 8 },
199 [SCxSR] = { 0x14, 16 },
200 [SCxRDR] = { 0x60, 8 },
201 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 202 [SCFDR] = sci_reg_invalid,
203 [SCTFDR] = { 0x38, 16 },
204 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 205 [SCSPTR] = sci_reg_invalid,
206 [SCLSR] = sci_reg_invalid,
f303b364 207 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 208 },
209
3af1f8a4
PE		 210 /*
211 * Common SH-2(A) SCIF definitions for ports with FIFO data
212 * count registers.
213 */
214 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x0c, 8 },
219 [SCxSR] = { 0x10, 16 },
220 [SCxRDR] = { 0x14, 8 },
221 [SCFCR] = { 0x18, 16 },
222 [SCFDR] = { 0x1c, 16 },
223 [SCTFDR] = sci_reg_invalid,
224 [SCRFDR] = sci_reg_invalid,
225 [SCSPTR] = { 0x20, 16 },
226 [SCLSR] = { 0x24, 16 },
f303b364 227 [HSSRR] = sci_reg_invalid,
3af1f8a4
PE		 228 },
229
61a6976b
PM		 230 /*
231 * Common SH-3 SCIF definitions.
232 */
233 [SCIx_SH3_SCIF_REGTYPE] = {
234 [SCSMR] = { 0x00, 8 },
235 [SCBRR] = { 0x02, 8 },
236 [SCSCR] = { 0x04, 8 },
237 [SCxTDR] = { 0x06, 8 },
238 [SCxSR] = { 0x08, 16 },
239 [SCxRDR] = { 0x0a, 8 },
240 [SCFCR] = { 0x0c, 8 },
241 [SCFDR] = { 0x0e, 16 },
242 [SCTFDR] = sci_reg_invalid,
243 [SCRFDR] = sci_reg_invalid,
244 [SCSPTR] = sci_reg_invalid,
245 [SCLSR] = sci_reg_invalid,
f303b364 246 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 247 },
248
249 /*
250 * Common SH-4(A) SCIF(B) definitions.
251 */
252 [SCIx_SH4_SCIF_REGTYPE] = {
253 [SCSMR] = { 0x00, 16 },
254 [SCBRR] = { 0x04, 8 },
255 [SCSCR] = { 0x08, 16 },
256 [SCxTDR] = { 0x0c, 8 },
257 [SCxSR] = { 0x10, 16 },
258 [SCxRDR] = { 0x14, 8 },
259 [SCFCR] = { 0x18, 16 },
260 [SCFDR] = { 0x1c, 16 },
261 [SCTFDR] = sci_reg_invalid,
262 [SCRFDR] = sci_reg_invalid,
263 [SCSPTR] = { 0x20, 16 },
264 [SCLSR] = { 0x24, 16 },
f303b364
UH		 265 [HSSRR] = sci_reg_invalid,
266 },
267
268 /*
269 * Common HSCIF definitions.
270 */
271 [SCIx_HSCIF_REGTYPE] = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCTFDR] = sci_reg_invalid,
281 [SCRFDR] = sci_reg_invalid,
282 [SCSPTR] = { 0x20, 16 },
283 [SCLSR] = { 0x24, 16 },
284 [HSSRR] = { 0x40, 16 },
61a6976b
PM		 285 },
286
287 /*
288 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
289 * register.
290 */
291 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
292 [SCSMR] = { 0x00, 16 },
293 [SCBRR] = { 0x04, 8 },
294 [SCSCR] = { 0x08, 16 },
295 [SCxTDR] = { 0x0c, 8 },
296 [SCxSR] = { 0x10, 16 },
297 [SCxRDR] = { 0x14, 8 },
298 [SCFCR] = { 0x18, 16 },
299 [SCFDR] = { 0x1c, 16 },
300 [SCTFDR] = sci_reg_invalid,
301 [SCRFDR] = sci_reg_invalid,
302 [SCSPTR] = sci_reg_invalid,
303 [SCLSR] = { 0x24, 16 },
f303b364 304 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 305 },
306
307 /*
308 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
309 * count registers.
310 */
311 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
312 [SCSMR] = { 0x00, 16 },
313 [SCBRR] = { 0x04, 8 },
314 [SCSCR] = { 0x08, 16 },
315 [SCxTDR] = { 0x0c, 8 },
316 [SCxSR] = { 0x10, 16 },
317 [SCxRDR] = { 0x14, 8 },
318 [SCFCR] = { 0x18, 16 },
319 [SCFDR] = { 0x1c, 16 },
320 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
321 [SCRFDR] = { 0x20, 16 },
322 [SCSPTR] = { 0x24, 16 },
323 [SCLSR] = { 0x28, 16 },
f303b364 324 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 325 },
326
327 /*
328 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
329 * registers.
330 */
331 [SCIx_SH7705_SCIF_REGTYPE] = {
332 [SCSMR] = { 0x00, 16 },
333 [SCBRR] = { 0x04, 8 },
334 [SCSCR] = { 0x08, 16 },
335 [SCxTDR] = { 0x20, 8 },
336 [SCxSR] = { 0x14, 16 },
337 [SCxRDR] = { 0x24, 8 },
338 [SCFCR] = { 0x18, 16 },
339 [SCFDR] = { 0x1c, 16 },
340 [SCTFDR] = sci_reg_invalid,
341 [SCRFDR] = sci_reg_invalid,
342 [SCSPTR] = sci_reg_invalid,
343 [SCLSR] = sci_reg_invalid,
f303b364 344 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 345 },
346};
347
72b294cf
PM		 348#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
349
61a6976b
PM		 350/*
351 * The "offset" here is rather misleading, in that it refers to an enum
352 * value relative to the port mapping rather than the fixed offset
353 * itself, which needs to be manually retrieved from the platform's
354 * register map for the given port.
355 */
356static unsigned int sci_serial_in(struct uart_port *p, int offset)
357{
72b294cf 358 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 359
360 if (reg->size == 8)
361 return ioread8(p->membase + (reg->offset << p->regshift));
362 else if (reg->size == 16)
363 return ioread16(p->membase + (reg->offset << p->regshift));
364 else
365 WARN(1, "Invalid register access\n");
366
367 return 0;
368}
369
370static void sci_serial_out(struct uart_port *p, int offset, int value)
371{
72b294cf 372 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 373
374 if (reg->size == 8)
375 iowrite8(value, p->membase + (reg->offset << p->regshift));
376 else if (reg->size == 16)
377 iowrite16(value, p->membase + (reg->offset << p->regshift));
378 else
379 WARN(1, "Invalid register access\n");
380}
381
61a6976b
PM		 382static int sci_probe_regmap(struct plat_sci_port *cfg)
383{
384 switch (cfg->type) {
385 case PORT_SCI:
386 cfg->regtype = SCIx_SCI_REGTYPE;
387 break;
388 case PORT_IRDA:
389 cfg->regtype = SCIx_IRDA_REGTYPE;
390 break;
391 case PORT_SCIFA:
392 cfg->regtype = SCIx_SCIFA_REGTYPE;
393 break;
394 case PORT_SCIFB:
395 cfg->regtype = SCIx_SCIFB_REGTYPE;
396 break;
397 case PORT_SCIF:
398 /*
399 * The SH-4 is a bit of a misnomer here, although that's
400 * where this particular port layout originated. This
401 * configuration (or some slight variation thereof)
402 * remains the dominant model for all SCIFs.
403 */
404 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
405 break;
f303b364
UH		 406 case PORT_HSCIF:
407 cfg->regtype = SCIx_HSCIF_REGTYPE;
408 break;
61a6976b
PM		 409 default:
410 printk(KERN_ERR "Can't probe register map for given port\n");
411 return -EINVAL;
412 }
413
414 return 0;
415}
416
23241d43
PM		 417static void sci_port_enable(struct sci_port *sci_port)
418{
419 if (!sci_port->port.dev)
420 return;
421
422 pm_runtime_get_sync(sci_port->port.dev);
423
b016b646 424 clk_prepare_enable(sci_port->iclk);
23241d43 425 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 426 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 427}
428
429static void sci_port_disable(struct sci_port *sci_port)
430{
431 if (!sci_port->port.dev)
432 return;
433
caec7038
LP		 434 /* Cancel the break timer to ensure that the timer handler will not try
435 * to access the hardware with clocks and power disabled. Reset the
436 * break flag to make the break debouncing state machine ready for the
437 * next break.
438 */
439 del_timer_sync(&sci_port->break_timer);
440 sci_port->break_flag = 0;
441
b016b646
LP		 442 clk_disable_unprepare(sci_port->fclk);
443 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 444
445 pm_runtime_put_sync(sci_port->port.dev);
446}
447
07d2a1a1 448#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 449
450#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 451static int sci_poll_get_char(struct uart_port *port)
1da177e4 452{
1da177e4
LT		 453 unsigned short status;
454 int c;
455
e108b2ca 456 do {
b12bb29f 457 status = serial_port_in(port, SCxSR);
1da177e4 458 if (status & SCxSR_ERRORS(port)) {
b12bb29f 459 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 460 continue;
461 }
3f255eb3
JW		 462 break;
463 } while (1);
464
465 if (!(status & SCxSR_RDxF(port)))
466 return NO_POLL_CHAR;
07d2a1a1 467
b12bb29f 468 c = serial_port_in(port, SCxRDR);
07d2a1a1 469
e7c98dc7 470 /* Dummy read */
b12bb29f
PM		 471 serial_port_in(port, SCxSR);
472 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 473
474 return c;
475}
1f6fd5c9 476#endif
1da177e4 477
07d2a1a1 478static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 479{
1da177e4
LT		 480 unsigned short status;
481
1da177e4 482 do {
b12bb29f 483 status = serial_port_in(port, SCxSR);
1da177e4
LT		 484 } while (!(status & SCxSR_TDxE(port)));
485
b12bb29f
PM		 486 serial_port_out(port, SCxTDR, c);
487 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 488}
07d2a1a1 489#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 490
61a6976b 491static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 492{
61a6976b
PM		 493 struct sci_port *s = to_sci_port(port);
494 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 495
61a6976b
PM		 496 /*
497 * Use port-specific handler if provided.
498 */
499 if (s->cfg->ops && s->cfg->ops->init_pins) {
500 s->cfg->ops->init_pins(port, cflag);
501 return;
1da177e4 502 }
41504c39 503
61a6976b
PM		 504 /*
505 * For the generic path SCSPTR is necessary. Bail out if that's
506 * unavailable, too.
507 */
508 if (!reg->size)
509 return;
41504c39 510
faf02f8f
PM		 511 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
512 ((!(cflag & CRTSCTS)))) {
513 unsigned short status;
514
b12bb29f 515 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 516 status &= ~SCSPTR_CTSIO;
517 status |= SCSPTR_RTSIO;
b12bb29f 518 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 519 }
d5701647 520}
e108b2ca 521
72b294cf 522static int sci_txfill(struct uart_port *port)
e108b2ca 523{
72b294cf 524 struct plat_sci_reg *reg;
e108b2ca 525
72b294cf
PM		 526 reg = sci_getreg(port, SCTFDR);
527 if (reg->size)
63f7ad11 528 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 529
72b294cf
PM		 530 reg = sci_getreg(port, SCFDR);
531 if (reg->size)
b12bb29f 532 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 533
b12bb29f 534 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 535}
536
73a19e4c
GL		 537static int sci_txroom(struct uart_port *port)
538{
72b294cf 539 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 540}
541
542static int sci_rxfill(struct uart_port *port)
e108b2ca 543{
72b294cf
PM		 544 struct plat_sci_reg *reg;
545
546 reg = sci_getreg(port, SCRFDR);
547 if (reg->size)
63f7ad11 548 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 549
550 reg = sci_getreg(port, SCFDR);
551 if (reg->size)
b12bb29f 552 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 553
b12bb29f 554 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 555}
556
514820eb
PM		 557/*
558 * SCI helper for checking the state of the muxed port/RXD pins.
559 */
560static inline int sci_rxd_in(struct uart_port *port)
561{
562 struct sci_port *s = to_sci_port(port);
563
564 if (s->cfg->port_reg <= 0)
565 return 1;
566
0dd4d5cb 567 /* Cast for ARM damage */
e2afca69 568 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 569}
570
1da177e4
LT		 571/* ********************************************************************** *
572 * the interrupt related routines *
573 * ********************************************************************** */
574
575static void sci_transmit_chars(struct uart_port *port)
576{
ebd2c8f6 577 struct circ_buf *xmit = &port->state->xmit;
1da177e4 578 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 579 unsigned short status;
580 unsigned short ctrl;
e108b2ca 581 int count;
1da177e4 582
b12bb29f 583 status = serial_port_in(port, SCxSR);
1da177e4 584 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 585 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 586 if (uart_circ_empty(xmit))
8e698614 587 ctrl &= ~SCSCR_TIE;
e7c98dc7 588 else
8e698614 589 ctrl |= SCSCR_TIE;
b12bb29f 590 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 591 return;
592 }
593
72b294cf 594 count = sci_txroom(port);
1da177e4
LT		 595
596 do {
597 unsigned char c;
598
599 if (port->x_char) {
600 c = port->x_char;
601 port->x_char = 0;
602 } else if (!uart_circ_empty(xmit) && !stopped) {
603 c = xmit->buf[xmit->tail];
604 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
605 } else {
606 break;
607 }
608
b12bb29f 609 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 610
611 port->icount.tx++;
612 } while (--count > 0);
613
b12bb29f 614 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 615
616 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
617 uart_write_wakeup(port);
618 if (uart_circ_empty(xmit)) {
b129a8cc 619 sci_stop_tx(port);
1da177e4 620 } else {
b12bb29f 621 ctrl = serial_port_in(port, SCSCR);
1da177e4 622
1a22f08d 623 if (port->type != PORT_SCI) {
b12bb29f
PM		 624 serial_port_in(port, SCxSR); /* Dummy read */
625 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 626 }
1da177e4 627
8e698614 628 ctrl |= SCSCR_TIE;
b12bb29f 629 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 630 }
631}
632
633/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 634#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 635
94c8b6db 636static void sci_receive_chars(struct uart_port *port)
1da177e4 637{
e7c98dc7 638 struct sci_port *sci_port = to_sci_port(port);
227434f8 639 struct tty_port *tport = &port->state->port;
1da177e4
LT		 640 int i, count, copied = 0;
641 unsigned short status;
33f0f88f 642 unsigned char flag;
1da177e4 643
b12bb29f 644 status = serial_port_in(port, SCxSR);
1da177e4
LT		 645 if (!(status & SCxSR_RDxF(port)))
646 return;
647
648 while (1) {
1da177e4 649 /* Don't copy more bytes than there is room for in the buffer */
227434f8 650 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 651
652 /* If for any reason we can't copy more data, we're done! */
653 if (count == 0)
654 break;
655
656 if (port->type == PORT_SCI) {
b12bb29f 657 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 658 if (uart_handle_sysrq_char(port, c) ||
659 sci_port->break_flag)
1da177e4 660 count = 0;
e7c98dc7 661 else
92a19f9c 662 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 663 } else {
e7c98dc7 664 for (i = 0; i < count; i++) {
b12bb29f 665 char c = serial_port_in(port, SCxRDR);
d97fbbed 666
b12bb29f 667 status = serial_port_in(port, SCxSR);
1da177e4
LT		 668#if defined(CONFIG_CPU_SH3)
669 /* Skip "chars" during break */
e108b2ca 670 if (sci_port->break_flag) {
1da177e4
LT		 671 if ((c == 0) &&
672 (status & SCxSR_FER(port))) {
673 count--; i--;
674 continue;
675 }
e108b2ca 676
1da177e4 677 /* Nonzero => end-of-break */
762c69e3 678 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 679 sci_port->break_flag = 0;
680
1da177e4
LT		 681 if (STEPFN(c)) {
682 count--; i--;
683 continue;
684 }
685 }
686#endif /* CONFIG_CPU_SH3 */
7d12e780 687 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 688 count--; i--;
689 continue;
690 }
691
692 /* Store data and status */
73a19e4c 693 if (status & SCxSR_FER(port)) {
33f0f88f 694 flag = TTY_FRAME;
d97fbbed 695 port->icount.frame++;
762c69e3 696 dev_notice(port->dev, "frame error\n");
73a19e4c 697 } else if (status & SCxSR_PER(port)) {
33f0f88f 698 flag = TTY_PARITY;
d97fbbed 699 port->icount.parity++;
762c69e3 700 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 701 } else
702 flag = TTY_NORMAL;
762c69e3 703
92a19f9c 704 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 705 }
706 }
707
b12bb29f
PM		 708 serial_port_in(port, SCxSR); /* dummy read */
709 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 710
1da177e4
LT		 711 copied += count;
712 port->icount.rx += count;
713 }
714
715 if (copied) {
716 /* Tell the rest of the system the news. New characters! */
2e124b4a 717 tty_flip_buffer_push(tport);
1da177e4 718 } else {
b12bb29f
PM		 719 serial_port_in(port, SCxSR); /* dummy read */
720 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 721 }
722}
723
724#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 725
726/*
727 * The sci generates interrupts during the break,
1da177e4
LT		 728 * 1 per millisecond or so during the break period, for 9600 baud.
729 * So dont bother disabling interrupts.
730 * But dont want more than 1 break event.
731 * Use a kernel timer to periodically poll the rx line until
732 * the break is finished.
733 */
94c8b6db 734static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 735{
bc9b3f5c 736 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 737}
94c8b6db 738
1da177e4
LT		 739/* Ensure that two consecutive samples find the break over. */
740static void sci_break_timer(unsigned long data)
741{
e108b2ca
PM		 742 struct sci_port *port = (struct sci_port *)data;
743
744 if (sci_rxd_in(&port->port) == 0) {
1da177e4 745 port->break_flag = 1;
e108b2ca
PM		 746 sci_schedule_break_timer(port);
747 } else if (port->break_flag == 1) {
1da177e4
LT		 748 /* break is over. */
749 port->break_flag = 2;
e108b2ca
PM		 750 sci_schedule_break_timer(port);
751 } else
752 port->break_flag = 0;
1da177e4
LT		 753}
754
94c8b6db 755static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 756{
757 int copied = 0;
b12bb29f 758 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 759 struct tty_port *tport = &port->state->port;
debf9507 760 struct sci_port *s = to_sci_port(port);
1da177e4 761
debf9507
PM		 762 /*
763 * Handle overruns, if supported.
764 */
765 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
766 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 767 port->icount.overrun++;
768
debf9507 769 /* overrun error */
92a19f9c 770 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
debf9507 771 copied++;
762c69e3 772
debf9507
PM		 773 dev_notice(port->dev, "overrun error");
774 }
1da177e4
LT		 775 }
776
e108b2ca 777 if (status & SCxSR_FER(port)) {
1da177e4
LT		 778 if (sci_rxd_in(port) == 0) {
779 /* Notify of BREAK */
e7c98dc7 780 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 781
782 if (!sci_port->break_flag) {
d97fbbed
PM		 783 port->icount.brk++;
784
e108b2ca
PM		 785 sci_port->break_flag = 1;
786 sci_schedule_break_timer(sci_port);
787
1da177e4 788 /* Do sysrq handling. */
e108b2ca 789 if (uart_handle_break(port))
1da177e4 790 return 0;
762c69e3
PM		 791
792 dev_dbg(port->dev, "BREAK detected\n");
793
92a19f9c 794 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 795 copied++;
796 }
797
e108b2ca 798 } else {
1da177e4 799 /* frame error */
d97fbbed
PM		 800 port->icount.frame++;
801
92a19f9c 802 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 803 copied++;
762c69e3
PM		 804
805 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 806 }
807 }
808
e108b2ca 809 if (status & SCxSR_PER(port)) {
1da177e4 810 /* parity error */
d97fbbed
PM		 811 port->icount.parity++;
812
92a19f9c 813 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 814 copied++;
762c69e3
PM		 815
816 dev_notice(port->dev, "parity error");
1da177e4
LT		 817 }
818
33f0f88f 819 if (copied)
2e124b4a 820 tty_flip_buffer_push(tport);
1da177e4
LT		 821
822 return copied;
823}
824
94c8b6db 825static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 826{
92a19f9c 827 struct tty_port *tport = &port->state->port;
debf9507 828 struct sci_port *s = to_sci_port(port);
4b8c59a3 829 struct plat_sci_reg *reg;
d830fa45
PM		 830 int copied = 0;
831
4b8c59a3
PM		 832 reg = sci_getreg(port, SCLSR);
833 if (!reg->size)
d830fa45
PM		 834 return 0;
835
b12bb29f
PM		 836 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
837 serial_port_out(port, SCLSR, 0);
d830fa45 838
d97fbbed
PM		 839 port->icount.overrun++;
840
92a19f9c 841 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 842 tty_flip_buffer_push(tport);
d830fa45
PM		 843
844 dev_notice(port->dev, "overrun error\n");
845 copied++;
846 }
847
848 return copied;
849}
850
94c8b6db 851static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 852{
853 int copied = 0;
b12bb29f 854 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 855 struct tty_port *tport = &port->state->port;
a5660ada 856 struct sci_port *s = to_sci_port(port);
1da177e4 857
0b3d4ef6
PM		 858 if (uart_handle_break(port))
859 return 0;
860
b7a76e4b 861 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 862#if defined(CONFIG_CPU_SH3)
863 /* Debounce break */
864 s->break_flag = 1;
865#endif
d97fbbed
PM		 866
867 port->icount.brk++;
868
1da177e4 869 /* Notify of BREAK */
92a19f9c 870 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 871 copied++;
762c69e3
PM		 872
873 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 874 }
875
33f0f88f 876 if (copied)
2e124b4a 877 tty_flip_buffer_push(tport);
e108b2ca 878
d830fa45
PM		 879 copied += sci_handle_fifo_overrun(port);
880
1da177e4
LT		 881 return copied;
882}
883
73a19e4c 884static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 885{
73a19e4c
GL		 886#ifdef CONFIG_SERIAL_SH_SCI_DMA
887 struct uart_port *port = ptr;
888 struct sci_port *s = to_sci_port(port);
889
890 if (s->chan_rx) {
b12bb29f
PM		 891 u16 scr = serial_port_in(port, SCSCR);
892 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 893
894 /* Disable future Rx interrupts */
d1d4b10c 895 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 896 disable_irq_nosync(irq);
897 scr |= 0x4000;
898 } else {
f43dc23d 899 scr &= ~SCSCR_RIE;
3089f381 900 }
b12bb29f 901 serial_port_out(port, SCSCR, scr);
73a19e4c 902 /* Clear current interrupt */
b12bb29f 903 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 904 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
905 jiffies, s->rx_timeout);
906 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 907
908 return IRQ_HANDLED;
909 }
910#endif
911
1da177e4
LT		 912 /* I think sci_receive_chars has to be called irrespective
913 * of whether the I_IXOFF is set, otherwise, how is the interrupt
914 * to be disabled?
915 */
73a19e4c 916 sci_receive_chars(ptr);
1da177e4
LT		 917
918 return IRQ_HANDLED;
919}
920
7d12e780 921static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 922{
923 struct uart_port *port = ptr;
fd78a76a 924 unsigned long flags;
1da177e4 925
fd78a76a 926 spin_lock_irqsave(&port->lock, flags);
1da177e4 927 sci_transmit_chars(port);
fd78a76a 928 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 929
930 return IRQ_HANDLED;
931}
932
7d12e780 933static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 934{
935 struct uart_port *port = ptr;
936
937 /* Handle errors */
938 if (port->type == PORT_SCI) {
939 if (sci_handle_errors(port)) {
940 /* discard character in rx buffer */
b12bb29f
PM		 941 serial_port_in(port, SCxSR);
942 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 943 }
944 } else {
d830fa45 945 sci_handle_fifo_overrun(port);
7d12e780 946 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 947 }
948
b12bb29f 949 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 950
951 /* Kick the transmission */
7d12e780 952 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 953
954 return IRQ_HANDLED;
955}
956
7d12e780 957static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 958{
959 struct uart_port *port = ptr;
960
961 /* Handle BREAKs */
962 sci_handle_breaks(port);
b12bb29f 963 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 964
965 return IRQ_HANDLED;
966}
967
f43dc23d
PM		 968static inline unsigned long port_rx_irq_mask(struct uart_port *port)
969{
970 /*
971 * Not all ports (such as SCIFA) will support REIE. Rather than
972 * special-casing the port type, we check the port initialization
973 * IRQ enable mask to see whether the IRQ is desired at all. If
974 * it's unset, it's logically inferred that there's no point in
975 * testing for it.
976 */
ce6738b6 977 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 978}
979
7d12e780 980static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 981{
44e18e9e 982 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 983 struct uart_port *port = ptr;
73a19e4c 984 struct sci_port *s = to_sci_port(port);
a8884e34 985 irqreturn_t ret = IRQ_NONE;
1da177e4 986
b12bb29f
PM		 987 ssr_status = serial_port_in(port, SCxSR);
988 scr_status = serial_port_in(port, SCSCR);
f43dc23d 989 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 990
991 /* Tx Interrupt */
f43dc23d 992 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 993 !s->chan_tx)
a8884e34 994 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 995
73a19e4c
GL		 996 /*
997 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
998 * DR flags
999 */
1000 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 1001 (scr_status & SCSCR_RIE))
a8884e34 1002 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 1003
1da177e4 1004 /* Error Interrupt */
dd4da3a5 1005 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1006 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1007
1da177e4 1008 /* Break Interrupt */
dd4da3a5 1009 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1010 ret = sci_br_interrupt(irq, ptr);
1da177e4 1011
a8884e34 1012 return ret;
1da177e4
LT		 1013}
1014
1da177e4 1015/*
25985edc 1016 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1017 * ports' baud rate when the peripheral clock changes.
1018 */
e108b2ca
PM		 1019static int sci_notifier(struct notifier_block *self,
1020 unsigned long phase, void *p)
1da177e4 1021{
e552de24
MD		 1022 struct sci_port *sci_port;
1023 unsigned long flags;
1da177e4 1024
d535a230
PM		 1025 sci_port = container_of(self, struct sci_port, freq_transition);
1026
1da177e4 1027 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 1028 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 1029 struct uart_port *port = &sci_port->port;
073e84c9 1030
d535a230
PM		 1031 spin_lock_irqsave(&port->lock, flags);
1032 port->uartclk = clk_get_rate(sci_port->iclk);
1033 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1034 }
1da177e4 1035
1da177e4
LT		 1036 return NOTIFY_OK;
1037}
501b825d 1038
9174fc8f
PM		 1039static struct sci_irq_desc {
1040 const char *desc;
1041 irq_handler_t handler;
1042} sci_irq_desc[] = {
1043 /*
1044 * Split out handlers, the default case.
1045 */
1046 [SCIx_ERI_IRQ] = {
1047 .desc = "rx err",
1048 .handler = sci_er_interrupt,
1049 },
1050
1051 [SCIx_RXI_IRQ] = {
1052 .desc = "rx full",
1053 .handler = sci_rx_interrupt,
1054 },
1055
1056 [SCIx_TXI_IRQ] = {
1057 .desc = "tx empty",
1058 .handler = sci_tx_interrupt,
1059 },
1060
1061 [SCIx_BRI_IRQ] = {
1062 .desc = "break",
1063 .handler = sci_br_interrupt,
1064 },
1065
1066 /*
1067 * Special muxed handler.
1068 */
1069 [SCIx_MUX_IRQ] = {
1070 .desc = "mux",
1071 .handler = sci_mpxed_interrupt,
1072 },
1073};
1074
1da177e4
LT		 1075static int sci_request_irq(struct sci_port *port)
1076{
9174fc8f
PM		 1077 struct uart_port *up = &port->port;
1078 int i, j, ret = 0;
1079
1080 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1081 struct sci_irq_desc *desc;
1082 unsigned int irq;
1083
1084 if (SCIx_IRQ_IS_MUXED(port)) {
1085 i = SCIx_MUX_IRQ;
1086 irq = up->irq;
0e8963de 1087 } else {
9174fc8f
PM		 1088 irq = port->cfg->irqs[i];
1089
0e8963de
PM		 1090 /*
1091 * Certain port types won't support all of the
1092 * available interrupt sources.
1093 */
1094 if (unlikely(!irq))
1095 continue;
1096 }
1097
9174fc8f
PM		 1098 desc = sci_irq_desc + i;
1099 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1100 dev_name(up->dev), desc->desc);
1101 if (!port->irqstr[j]) {
1102 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1103 desc->desc);
1104 goto out_nomem;
1da177e4 1105 }
9174fc8f
PM		 1106
1107 ret = request_irq(irq, desc->handler, up->irqflags,
1108 port->irqstr[j], port);
1109 if (unlikely(ret)) {
1110 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1111 goto out_noirq;
1da177e4
LT		 1112 }
1113 }
1114
1115 return 0;
9174fc8f
PM		 1116
1117out_noirq:
1118 while (--i >= 0)
1119 free_irq(port->cfg->irqs[i], port);
1120
1121out_nomem:
1122 while (--j >= 0)
1123 kfree(port->irqstr[j]);
1124
1125 return ret;
1da177e4
LT		 1126}
1127
1128static void sci_free_irq(struct sci_port *port)
1129{
1130 int i;
1131
9174fc8f
PM		 1132 /*
1133 * Intentionally in reverse order so we iterate over the muxed
1134 * IRQ first.
1135 */
1136 for (i = 0; i < SCIx_NR_IRQS; i++) {
0e8963de
PM		 1137 unsigned int irq = port->cfg->irqs[i];
1138
1139 /*
1140 * Certain port types won't support all of the available
1141 * interrupt sources.
1142 */
1143 if (unlikely(!irq))
1144 continue;
1145
9174fc8f
PM		 1146 free_irq(port->cfg->irqs[i], port);
1147 kfree(port->irqstr[i]);
1da177e4 1148
9174fc8f
PM		 1149 if (SCIx_IRQ_IS_MUXED(port)) {
1150 /* If there's only one IRQ, we're done. */
1151 return;
1da177e4
LT		 1152 }
1153 }
1154}
1155
50f0959a
PM		 1156static const char *sci_gpio_names[SCIx_NR_FNS] = {
1157 "sck", "rxd", "txd", "cts", "rts",
1158};
1159
1160static const char *sci_gpio_str(unsigned int index)
1161{
1162 return sci_gpio_names[index];
1163}
1164
9671f099 1165static void sci_init_gpios(struct sci_port *port)
50f0959a
PM		 1166{
1167 struct uart_port *up = &port->port;
1168 int i;
1169
1170 if (!port->cfg)
1171 return;
1172
1173 for (i = 0; i < SCIx_NR_FNS; i++) {
1174 const char *desc;
1175 int ret;
1176
1177 if (!port->cfg->gpios[i])
1178 continue;
1179
1180 desc = sci_gpio_str(i);
1181
1182 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1183 dev_name(up->dev), desc);
1184
1185 /*
1186 * If we've failed the allocation, we can still continue
1187 * on with a NULL string.
1188 */
1189 if (!port->gpiostr[i])
1190 dev_notice(up->dev, "%s string allocation failure\n",
1191 desc);
1192
1193 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1194 if (unlikely(ret != 0)) {
1195 dev_notice(up->dev, "failed %s gpio request\n", desc);
1196
1197 /*
1198 * If we can't get the GPIO for whatever reason,
1199 * no point in keeping the verbose string around.
1200 */
1201 kfree(port->gpiostr[i]);
1202 }
1203 }
1204}
1205
1206static void sci_free_gpios(struct sci_port *port)
1207{
1208 int i;
1209
1210 for (i = 0; i < SCIx_NR_FNS; i++)
1211 if (port->cfg->gpios[i]) {
1212 gpio_free(port->cfg->gpios[i]);
1213 kfree(port->gpiostr[i]);
1214 }
1215}
1216
1da177e4
LT		 1217static unsigned int sci_tx_empty(struct uart_port *port)
1218{
b12bb29f 1219 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1220 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1221
1222 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1223}
1224
cdf7c42f
PM		 1225/*
1226 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1227 * CTS/RTS is supported in hardware by at least one port and controlled
1228 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1229 * handled via the ->init_pins() op, which is a bit of a one-way street,
1230 * lacking any ability to defer pin control -- this will later be
1231 * converted over to the GPIO framework).
dc7e3ef7
PM		 1232 *
1233 * Other modes (such as loopback) are supported generically on certain
1234 * port types, but not others. For these it's sufficient to test for the
1235 * existence of the support register and simply ignore the port type.
cdf7c42f 1236 */
1da177e4
LT		 1237static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1238{
dc7e3ef7
PM		 1239 if (mctrl & TIOCM_LOOP) {
1240 struct plat_sci_reg *reg;
1241
1242 /*
1243 * Standard loopback mode for SCFCR ports.
1244 */
1245 reg = sci_getreg(port, SCFCR);
1246 if (reg->size)
b12bb29f 1247 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1248 }
1da177e4
LT		 1249}
1250
1251static unsigned int sci_get_mctrl(struct uart_port *port)
1252{
cdf7c42f
PM		 1253 /*
1254 * CTS/RTS is handled in hardware when supported, while nothing
1255 * else is wired up. Keep it simple and simply assert DSR/CAR.
1256 */
1257 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1258}
1259
73a19e4c
GL		 1260#ifdef CONFIG_SERIAL_SH_SCI_DMA
1261static void sci_dma_tx_complete(void *arg)
1262{
1263 struct sci_port *s = arg;
1264 struct uart_port *port = &s->port;
1265 struct circ_buf *xmit = &port->state->xmit;
1266 unsigned long flags;
1267
1268 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1269
1270 spin_lock_irqsave(&port->lock, flags);
1271
f354a381 1272 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1273 xmit->tail &= UART_XMIT_SIZE - 1;
1274
f354a381 1275 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1276
1277 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1278 s->desc_tx = NULL;
1279
73a19e4c
GL		 1280 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1281 uart_write_wakeup(port);
1282
3089f381 1283 if (!uart_circ_empty(xmit)) {
49d4bcad 1284 s->cookie_tx = 0;
73a19e4c 1285 schedule_work(&s->work_tx);
49d4bcad
YT		 1286 } else {
1287 s->cookie_tx = -EINVAL;
1288 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1289 u16 ctrl = serial_port_in(port, SCSCR);
1290 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1291 }
3089f381
GL		 1292 }
1293
1294 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1295}
1296
1297/* Locking: called with port lock held */
92a19f9c 1298static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1299{
1300 struct uart_port *port = &s->port;
227434f8 1301 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1302 int i, active, room;
1303
227434f8 1304 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1305
1306 if (s->active_rx == s->cookie_rx[0]) {
1307 active = 0;
1308 } else if (s->active_rx == s->cookie_rx[1]) {
1309 active = 1;
1310 } else {
1311 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1312 return 0;
1313 }
1314
1315 if (room < count)
e2afca69 1316 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1317 count - room);
1318 if (!room)
1319 return room;
1320
1321 for (i = 0; i < room; i++)
92a19f9c 1322 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1323 TTY_NORMAL);
1324
1325 port->icount.rx += room;
1326
1327 return room;
1328}
1329
1330static void sci_dma_rx_complete(void *arg)
1331{
1332 struct sci_port *s = arg;
1333 struct uart_port *port = &s->port;
73a19e4c
GL		 1334 unsigned long flags;
1335 int count;
1336
3089f381 1337 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1338
1339 spin_lock_irqsave(&port->lock, flags);
1340
92a19f9c 1341 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1342
3089f381 1343 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1344
1345 spin_unlock_irqrestore(&port->lock, flags);
1346
1347 if (count)
2e124b4a 1348 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1349
1350 schedule_work(&s->work_rx);
1351}
1352
73a19e4c
GL		 1353static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1354{
1355 struct dma_chan *chan = s->chan_rx;
1356 struct uart_port *port = &s->port;
73a19e4c
GL		 1357
1358 s->chan_rx = NULL;
1359 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1360 dma_release_channel(chan);
85b8e3ff
GL		 1361 if (sg_dma_address(&s->sg_rx[0]))
1362 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1363 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1364 if (enable_pio)
1365 sci_start_rx(port);
1366}
1367
1368static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1369{
1370 struct dma_chan *chan = s->chan_tx;
1371 struct uart_port *port = &s->port;
73a19e4c
GL		 1372
1373 s->chan_tx = NULL;
1374 s->cookie_tx = -EINVAL;
1375 dma_release_channel(chan);
1376 if (enable_pio)
1377 sci_start_tx(port);
1378}
1379
1380static void sci_submit_rx(struct sci_port *s)
1381{
1382 struct dma_chan *chan = s->chan_rx;
1383 int i;
1384
1385 for (i = 0; i < 2; i++) {
1386 struct scatterlist *sg = &s->sg_rx[i];
1387 struct dma_async_tx_descriptor *desc;
1388
16052827 1389 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1390 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1391
1392 if (desc) {
1393 s->desc_rx[i] = desc;
1394 desc->callback = sci_dma_rx_complete;
1395 desc->callback_param = s;
1396 s->cookie_rx[i] = desc->tx_submit(desc);
1397 }
1398
1399 if (!desc || s->cookie_rx[i] < 0) {
1400 if (i) {
1401 async_tx_ack(s->desc_rx[0]);
1402 s->cookie_rx[0] = -EINVAL;
1403 }
1404 if (desc) {
1405 async_tx_ack(desc);
1406 s->cookie_rx[i] = -EINVAL;
1407 }
1408 dev_warn(s->port.dev,
1409 "failed to re-start DMA, using PIO\n");
1410 sci_rx_dma_release(s, true);
1411 return;
1412 }
3089f381
GL		 1413 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1414 s->cookie_rx[i], i);
73a19e4c
GL		 1415 }
1416
1417 s->active_rx = s->cookie_rx[0];
1418
1419 dma_async_issue_pending(chan);
1420}
1421
1422static void work_fn_rx(struct work_struct *work)
1423{
1424 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1425 struct uart_port *port = &s->port;
1426 struct dma_async_tx_descriptor *desc;
1427 int new;
1428
1429 if (s->active_rx == s->cookie_rx[0]) {
1430 new = 0;
1431 } else if (s->active_rx == s->cookie_rx[1]) {
1432 new = 1;
1433 } else {
1434 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1435 return;
1436 }
1437 desc = s->desc_rx[new];
1438
1439 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1440 DMA_COMPLETE) {
73a19e4c 1441 /* Handle incomplete DMA receive */
73a19e4c 1442 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1443 struct shdma_desc *sh_desc = container_of(desc,
1444 struct shdma_desc, async_tx);
73a19e4c
GL		 1445 unsigned long flags;
1446 int count;
1447
05827630 1448 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
e2afca69 1449 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1450 sh_desc->partial, sh_desc->cookie);
1451
1452 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1453 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1454 spin_unlock_irqrestore(&port->lock, flags);
1455
1456 if (count)
2e124b4a 1457 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1458
1459 sci_submit_rx(s);
1460
1461 return;
1462 }
1463
1464 s->cookie_rx[new] = desc->tx_submit(desc);
1465 if (s->cookie_rx[new] < 0) {
1466 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1467 sci_rx_dma_release(s, true);
1468 return;
1469 }
1470
73a19e4c 1471 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1472
1473 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1474 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1475}
1476
1477static void work_fn_tx(struct work_struct *work)
1478{
1479 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1480 struct dma_async_tx_descriptor *desc;
1481 struct dma_chan *chan = s->chan_tx;
1482 struct uart_port *port = &s->port;
1483 struct circ_buf *xmit = &port->state->xmit;
1484 struct scatterlist *sg = &s->sg_tx;
1485
1486 /*
1487 * DMA is idle now.
1488 * Port xmit buffer is already mapped, and it is one page... Just adjust
1489 * offsets and lengths. Since it is a circular buffer, we have to
1490 * transmit till the end, and then the rest. Take the port lock to get a
1491 * consistent xmit buffer state.
1492 */
1493 spin_lock_irq(&port->lock);
1494 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1495 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1496 sg->offset;
f354a381 1497 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1498 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1499 spin_unlock_irq(&port->lock);
1500
f354a381 1501 BUG_ON(!sg_dma_len(sg));
73a19e4c 1502
16052827 1503 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1504 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1505 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1506 if (!desc) {
1507 /* switch to PIO */
1508 sci_tx_dma_release(s, true);
1509 return;
1510 }
1511
1512 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1513
1514 spin_lock_irq(&port->lock);
1515 s->desc_tx = desc;
1516 desc->callback = sci_dma_tx_complete;
1517 desc->callback_param = s;
1518 spin_unlock_irq(&port->lock);
1519 s->cookie_tx = desc->tx_submit(desc);
1520 if (s->cookie_tx < 0) {
1521 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1522 /* switch to PIO */
1523 sci_tx_dma_release(s, true);
1524 return;
1525 }
1526
1527 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1528 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1529
1530 dma_async_issue_pending(chan);
1531}
1532#endif
1533
b129a8cc 1534static void sci_start_tx(struct uart_port *port)
1da177e4 1535{
3089f381 1536 struct sci_port *s = to_sci_port(port);
e108b2ca 1537 unsigned short ctrl;
1da177e4 1538
73a19e4c 1539#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1540 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1541 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1542 if (s->chan_tx)
1543 new = scr | 0x8000;
1544 else
1545 new = scr & ~0x8000;
1546 if (new != scr)
b12bb29f 1547 serial_port_out(port, SCSCR, new);
73a19e4c 1548 }
f43dc23d 1549
3089f381 1550 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1551 s->cookie_tx < 0) {
1552 s->cookie_tx = 0;
3089f381 1553 schedule_work(&s->work_tx);
49d4bcad 1554 }
73a19e4c 1555#endif
f43dc23d 1556
d1d4b10c 1557 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1558 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1559 ctrl = serial_port_in(port, SCSCR);
1560 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1561 }
1da177e4
LT		 1562}
1563
b129a8cc 1564static void sci_stop_tx(struct uart_port *port)
1da177e4 1565{
1da177e4
LT		 1566 unsigned short ctrl;
1567
1568 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1569 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1570
d1d4b10c 1571 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1572 ctrl &= ~0x8000;
f43dc23d 1573
8e698614 1574 ctrl &= ~SCSCR_TIE;
f43dc23d 1575
b12bb29f 1576 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1577}
1578
73a19e4c 1579static void sci_start_rx(struct uart_port *port)
1da177e4 1580{
1da177e4
LT		 1581 unsigned short ctrl;
1582
b12bb29f 1583 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1584
d1d4b10c 1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1586 ctrl &= ~0x4000;
f43dc23d 1587
b12bb29f 1588 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1589}
1590
1591static void sci_stop_rx(struct uart_port *port)
1592{
1da177e4
LT		 1593 unsigned short ctrl;
1594
b12bb29f 1595 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1596
d1d4b10c 1597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1598 ctrl &= ~0x4000;
f43dc23d
PM		 1599
1600 ctrl &= ~port_rx_irq_mask(port);
1601
b12bb29f 1602 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1603}
1604
1605static void sci_enable_ms(struct uart_port *port)
1606{
d39ec6ce
PM		 1607 /*
1608 * Not supported by hardware, always a nop.
1609 */
1da177e4
LT		 1610}
1611
1612static void sci_break_ctl(struct uart_port *port, int break_state)
1613{
bbb4ce50 1614 struct sci_port *s = to_sci_port(port);
a4e02f6d 1615 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1616 unsigned short scscr, scsptr;
1617
a4e02f6d
SY		 1618 /* check wheter the port has SCSPTR */
1619 if (!reg->size) {
bbb4ce50
SY		 1620 /*
1621 * Not supported by hardware. Most parts couple break and rx
1622 * interrupts together, with break detection always enabled.
1623 */
a4e02f6d 1624 return;
bbb4ce50 1625 }
a4e02f6d
SY		 1626
1627 scsptr = serial_port_in(port, SCSPTR);
1628 scscr = serial_port_in(port, SCSCR);
1629
1630 if (break_state == -1) {
1631 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1632 scscr &= ~SCSCR_TE;
1633 } else {
1634 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1635 scscr |= SCSCR_TE;
1636 }
1637
1638 serial_port_out(port, SCSPTR, scsptr);
1639 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1640}
1641
73a19e4c
GL		 1642#ifdef CONFIG_SERIAL_SH_SCI_DMA
1643static bool filter(struct dma_chan *chan, void *slave)
1644{
1645 struct sh_dmae_slave *param = slave;
1646
1647 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1648 param->shdma_slave.slave_id);
73a19e4c 1649
d6fa5a4e 1650 chan->private = &param->shdma_slave;
937bb6e4 1651 return true;
73a19e4c
GL		 1652}
1653
1654static void rx_timer_fn(unsigned long arg)
1655{
1656 struct sci_port *s = (struct sci_port *)arg;
1657 struct uart_port *port = &s->port;
b12bb29f 1658 u16 scr = serial_port_in(port, SCSCR);
3089f381 1659
d1d4b10c 1660 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1661 scr &= ~0x4000;
ce6738b6 1662 enable_irq(s->cfg->irqs[1]);
3089f381 1663 }
b12bb29f 1664 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1665 dev_dbg(port->dev, "DMA Rx timed out\n");
1666 schedule_work(&s->work_rx);
1667}
1668
1669static void sci_request_dma(struct uart_port *port)
1670{
1671 struct sci_port *s = to_sci_port(port);
1672 struct sh_dmae_slave *param;
1673 struct dma_chan *chan;
1674 dma_cap_mask_t mask;
1675 int nent;
1676
937bb6e4
GL		 1677 dev_dbg(port->dev, "%s: port %d\n", __func__,
1678 port->line);
73a19e4c 1679
937bb6e4 1680 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1681 return;
1682
1683 dma_cap_zero(mask);
1684 dma_cap_set(DMA_SLAVE, mask);
1685
1686 param = &s->param_tx;
1687
1688 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1689 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1690
1691 s->cookie_tx = -EINVAL;
1692 chan = dma_request_channel(mask, filter, param);
1693 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1694 if (chan) {
1695 s->chan_tx = chan;
1696 sg_init_table(&s->sg_tx, 1);
1697 /* UART circular tx buffer is an aligned page. */
e2afca69 1698 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1699 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1700 UART_XMIT_SIZE,
1701 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1702 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1703 if (!nent)
1704 sci_tx_dma_release(s, false);
1705 else
e2afca69
LP		 1706 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1707 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1708 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1709
1710 s->sg_len_tx = nent;
1711
1712 INIT_WORK(&s->work_tx, work_fn_tx);
1713 }
1714
1715 param = &s->param_rx;
1716
1717 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1718 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1719
1720 chan = dma_request_channel(mask, filter, param);
1721 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1722 if (chan) {
1723 dma_addr_t dma[2];
1724 void *buf[2];
1725 int i;
1726
1727 s->chan_rx = chan;
1728
1729 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1730 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1731 &dma[0], GFP_KERNEL);
1732
1733 if (!buf[0]) {
1734 dev_warn(port->dev,
1735 "failed to allocate dma buffer, using PIO\n");
1736 sci_rx_dma_release(s, true);
1737 return;
1738 }
1739
1740 buf[1] = buf[0] + s->buf_len_rx;
1741 dma[1] = dma[0] + s->buf_len_rx;
1742
1743 for (i = 0; i < 2; i++) {
1744 struct scatterlist *sg = &s->sg_rx[i];
1745
1746 sg_init_table(sg, 1);
1747 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1748 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1749 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1750 }
1751
1752 INIT_WORK(&s->work_rx, work_fn_rx);
1753 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1754
1755 sci_submit_rx(s);
1756 }
1757}
1758
1759static void sci_free_dma(struct uart_port *port)
1760{
1761 struct sci_port *s = to_sci_port(port);
1762
73a19e4c
GL		 1763 if (s->chan_tx)
1764 sci_tx_dma_release(s, false);
1765 if (s->chan_rx)
1766 sci_rx_dma_release(s, false);
1767}
27bd1075
PM		 1768#else
1769static inline void sci_request_dma(struct uart_port *port)
1770{
1771}
1772
1773static inline void sci_free_dma(struct uart_port *port)
1774{
1775}
73a19e4c
GL		 1776#endif
1777
1da177e4
LT		 1778static int sci_startup(struct uart_port *port)
1779{
a5660ada 1780 struct sci_port *s = to_sci_port(port);
33b48e16 1781 unsigned long flags;
073e84c9 1782 int ret;
1da177e4 1783
73a19e4c
GL		 1784 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1785
073e84c9
PM		 1786 ret = sci_request_irq(s);
1787 if (unlikely(ret < 0))
1788 return ret;
1789
73a19e4c 1790 sci_request_dma(port);
073e84c9 1791
33b48e16 1792 spin_lock_irqsave(&port->lock, flags);
d656901b 1793 sci_start_tx(port);
73a19e4c 1794 sci_start_rx(port);
33b48e16 1795 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1796
1797 return 0;
1798}
1799
1800static void sci_shutdown(struct uart_port *port)
1801{
a5660ada 1802 struct sci_port *s = to_sci_port(port);
33b48e16 1803 unsigned long flags;
1da177e4 1804
73a19e4c
GL		 1805 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1806
33b48e16 1807 spin_lock_irqsave(&port->lock, flags);
1da177e4 1808 sci_stop_rx(port);
b129a8cc 1809 sci_stop_tx(port);
33b48e16 1810 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1811
73a19e4c 1812 sci_free_dma(port);
1da177e4 1813 sci_free_irq(s);
1da177e4
LT		 1814}
1815
26c92f37
PM		 1816static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1817 unsigned long freq)
1818{
1819 switch (algo_id) {
1820 case SCBRR_ALGO_1:
6557b1f6 1821 return freq / (16 * bps);
26c92f37 1822 case SCBRR_ALGO_2:
6557b1f6 1823 return DIV_ROUND_CLOSEST(freq, 32 * bps) - 1;
26c92f37 1824 case SCBRR_ALGO_3:
6557b1f6 1825 return freq / (8 * bps);
26c92f37 1826 case SCBRR_ALGO_4:
6557b1f6 1827 return DIV_ROUND_CLOSEST(freq, 16 * bps) - 1;
26c92f37
PM		 1828 }
1829
1830 /* Warn, but use a safe default */
1831 WARN_ON(1);
e8183a6c 1832
26c92f37
PM		 1833 return ((freq + 16 * bps) / (32 * bps) - 1);
1834}
1835
f303b364
UH		 1836/* calculate sample rate, BRR, and clock select for HSCIF */
1837static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1838 int *brr, unsigned int *srr,
1839 unsigned int *cks)
1840{
1841 int sr, c, br, err;
1842 int min_err = 1000; /* 100% */
1843
1844 /* Find the combination of sample rate and clock select with the
1845 smallest deviation from the desired baud rate. */
1846 for (sr = 8; sr <= 32; sr++) {
1847 for (c = 0; c <= 3; c++) {
1848 /* integerized formulas from HSCIF documentation */
1849 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1850 if (br < 0 || br > 255)
1851 continue;
1852 err = freq / ((br + 1) * bps * sr *
1853 (1 << (2 * c + 1)) / 1000) - 1000;
1854 if (min_err > err) {
1855 min_err = err;
1856 *brr = br;
1857 *srr = sr - 1;
1858 *cks = c;
1859 }
1860 }
1861 }
1862
1863 if (min_err == 1000) {
1864 WARN_ON(1);
1865 /* use defaults */
1866 *brr = 255;
1867 *srr = 15;
1868 *cks = 0;
1869 }
1870}
1871
1ba76220
MD		 1872static void sci_reset(struct uart_port *port)
1873{
0979e0e6 1874 struct plat_sci_reg *reg;
1ba76220
MD		 1875 unsigned int status;
1876
1877 do {
b12bb29f 1878 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1879 } while (!(status & SCxSR_TEND(port)));
1880
b12bb29f 1881 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1882
0979e0e6
PM		 1883 reg = sci_getreg(port, SCFCR);
1884 if (reg->size)
b12bb29f 1885 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1886}
1887
606d099c
AC		 1888static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1889 struct ktermios *old)
1da177e4 1890{
00b9de9c 1891 struct sci_port *s = to_sci_port(port);
0979e0e6 1892 struct plat_sci_reg *reg;
d4759ded 1893 unsigned int baud, smr_val, max_baud, cks = 0;
a2159b52 1894 int t = -1;
d4759ded 1895 unsigned int srr = 15;
1da177e4 1896
154280fd
MD		 1897 /*
1898 * earlyprintk comes here early on with port->uartclk set to zero.
1899 * the clock framework is not up and running at this point so here
1900 * we assume that 115200 is the maximum baud rate. please note that
1901 * the baud rate is not programmed during earlyprintk - it is assumed
1902 * that the previous boot loader has enabled required clocks and
1903 * setup the baud rate generator hardware for us already.
1904 */
1905 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1906
154280fd 1907 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364
UH		 1908 if (likely(baud && port->uartclk)) {
1909 if (s->cfg->scbrr_algo_id == SCBRR_ALGO_6) {
1910 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1911 &cks);
1912 } else {
1913 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud,
1914 port->uartclk);
1915 for (cks = 0; t >= 256 && cks <= 3; cks++)
1916 t >>= 2;
1917 }
1918 }
e108b2ca 1919
23241d43 1920 sci_port_enable(s);
36003386 1921
1ba76220 1922 sci_reset(port);
1da177e4 1923
b12bb29f 1924 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1925
1da177e4
LT		 1926 if ((termios->c_cflag & CSIZE) == CS7)
1927 smr_val |= 0x40;
1928 if (termios->c_cflag & PARENB)
1929 smr_val |= 0x20;
1930 if (termios->c_cflag & PARODD)
1931 smr_val |= 0x30;
1932 if (termios->c_cflag & CSTOPB)
1933 smr_val |= 0x08;
1934
1935 uart_update_timeout(port, termios->c_cflag, baud);
1936
9d482cc3
TY		 1937 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1938 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1939
4ffc3cdb 1940 if (t >= 0) {
9d482cc3 1941 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1942 serial_port_out(port, SCBRR, t);
f303b364
UH		 1943 reg = sci_getreg(port, HSSRR);
1944 if (reg->size)
1945 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1946 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1947 } else
1948 serial_port_out(port, SCSMR, smr_val);
1da177e4 1949
d5701647 1950 sci_init_pins(port, termios->c_cflag);
0979e0e6 1951
73c3d53f
PM		 1952 reg = sci_getreg(port, SCFCR);
1953 if (reg->size) {
b12bb29f 1954 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1955
73c3d53f 1956 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1957 if (termios->c_cflag & CRTSCTS)
1958 ctrl |= SCFCR_MCE;
1959 else
1960 ctrl &= ~SCFCR_MCE;
faf02f8f 1961 }
73c3d53f
PM		 1962
1963 /*
1964 * As we've done a sci_reset() above, ensure we don't
1965 * interfere with the FIFOs while toggling MCE. As the
1966 * reset values could still be set, simply mask them out.
1967 */
1968 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1969
b12bb29f 1970 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1971 }
b7a76e4b 1972
b12bb29f 1973 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1974
3089f381
GL		 1975#ifdef CONFIG_SERIAL_SH_SCI_DMA
1976 /*
1977 * Calculate delay for 1.5 DMA buffers: see
1978 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1979 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1980 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1981 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1982 * sizes), but it has been found out experimentally, that this is not
1983 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1984 * as a minimum seem to work perfectly.
1985 */
1986 if (s->chan_rx) {
1987 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1988 port->fifosize / 2;
1989 dev_dbg(port->dev,
1990 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1991 s->rx_timeout * 1000 / HZ, port->timeout);
1992 if (s->rx_timeout < msecs_to_jiffies(20))
1993 s->rx_timeout = msecs_to_jiffies(20);
1994 }
1995#endif
1996
1da177e4 1997 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1998 sci_start_rx(port);
36003386 1999
23241d43 2000 sci_port_disable(s);
1da177e4
LT		 2001}
2002
0174e5ca
TK		 2003static void sci_pm(struct uart_port *port, unsigned int state,
2004 unsigned int oldstate)
2005{
2006 struct sci_port *sci_port = to_sci_port(port);
2007
2008 switch (state) {
2009 case 3:
2010 sci_port_disable(sci_port);
2011 break;
2012 default:
2013 sci_port_enable(sci_port);
2014 break;
2015 }
2016}
2017
1da177e4
LT		 2018static const char *sci_type(struct uart_port *port)
2019{
2020 switch (port->type) {
e7c98dc7
MT		 2021 case PORT_IRDA:
2022 return "irda";
2023 case PORT_SCI:
2024 return "sci";
2025 case PORT_SCIF:
2026 return "scif";
2027 case PORT_SCIFA:
2028 return "scifa";
d1d4b10c
GL		 2029 case PORT_SCIFB:
2030 return "scifb";
f303b364
UH		 2031 case PORT_HSCIF:
2032 return "hscif";
1da177e4
LT		 2033 }
2034
fa43972f 2035 return NULL;
1da177e4
LT		 2036}
2037
e2651647 2038static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 2039{
e2651647
PM		 2040 /*
2041 * Pick an arbitrary size that encapsulates all of the base
2042 * registers by default. This can be optimized later, or derived
2043 * from platform resource data at such a time that ports begin to
2044 * behave more erratically.
2045 */
f303b364
UH		 2046 if (port->type == PORT_HSCIF)
2047 return 96;
2048 else
2049 return 64;
1da177e4
LT		 2050}
2051
f6e9495d
PM		 2052static int sci_remap_port(struct uart_port *port)
2053{
2054 unsigned long size = sci_port_size(port);
2055
2056 /*
2057 * Nothing to do if there's already an established membase.
2058 */
2059 if (port->membase)
2060 return 0;
2061
2062 if (port->flags & UPF_IOREMAP) {
2063 port->membase = ioremap_nocache(port->mapbase, size);
2064 if (unlikely(!port->membase)) {
2065 dev_err(port->dev, "can't remap port#%d\n", port->line);
2066 return -ENXIO;
2067 }
2068 } else {
2069 /*
2070 * For the simple (and majority of) cases where we don't
2071 * need to do any remapping, just cast the cookie
2072 * directly.
2073 */
2074 port->membase = (void __iomem *)port->mapbase;
2075 }
2076
2077 return 0;
2078}
2079
e2651647 2080static void sci_release_port(struct uart_port *port)
1da177e4 2081{
e2651647
PM		 2082 if (port->flags & UPF_IOREMAP) {
2083 iounmap(port->membase);
2084 port->membase = NULL;
2085 }
2086
2087 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2088}
2089
e2651647 2090static int sci_request_port(struct uart_port *port)
1da177e4 2091{
e2651647
PM		 2092 unsigned long size = sci_port_size(port);
2093 struct resource *res;
f6e9495d 2094 int ret;
1da177e4 2095
1020520e 2096 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2097 if (unlikely(res == NULL))
2098 return -EBUSY;
1da177e4 2099
f6e9495d
PM		 2100 ret = sci_remap_port(port);
2101 if (unlikely(ret != 0)) {
2102 release_resource(res);
2103 return ret;
7ff731ae 2104 }
e2651647
PM		 2105
2106 return 0;
2107}
2108
2109static void sci_config_port(struct uart_port *port, int flags)
2110{
2111 if (flags & UART_CONFIG_TYPE) {
2112 struct sci_port *sport = to_sci_port(port);
2113
2114 port->type = sport->cfg->type;
2115 sci_request_port(port);
2116 }
1da177e4
LT		 2117}
2118
2119static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2120{
a5660ada 2121 struct sci_port *s = to_sci_port(port);
1da177e4 2122
b5e17b71 2123 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ])
1da177e4
LT		 2124 return -EINVAL;
2125 if (ser->baud_base < 2400)
2126 /* No paper tape reader for Mitch.. */
2127 return -EINVAL;
2128
2129 return 0;
2130}
2131
2132static struct uart_ops sci_uart_ops = {
2133 .tx_empty = sci_tx_empty,
2134 .set_mctrl = sci_set_mctrl,
2135 .get_mctrl = sci_get_mctrl,
2136 .start_tx = sci_start_tx,
2137 .stop_tx = sci_stop_tx,
2138 .stop_rx = sci_stop_rx,
2139 .enable_ms = sci_enable_ms,
2140 .break_ctl = sci_break_ctl,
2141 .startup = sci_startup,
2142 .shutdown = sci_shutdown,
2143 .set_termios = sci_set_termios,
0174e5ca 2144 .pm = sci_pm,
1da177e4
LT		 2145 .type = sci_type,
2146 .release_port = sci_release_port,
2147 .request_port = sci_request_port,
2148 .config_port = sci_config_port,
2149 .verify_port = sci_verify_port,
07d2a1a1
PM		 2150#ifdef CONFIG_CONSOLE_POLL
2151 .poll_get_char = sci_poll_get_char,
2152 .poll_put_char = sci_poll_put_char,
2153#endif
1da177e4
LT		 2154};
2155
9671f099 2156static int sci_init_single(struct platform_device *dev,
c7ed1ab3
PM		 2157 struct sci_port *sci_port,
2158 unsigned int index,
2159 struct plat_sci_port *p)
e108b2ca 2160{
73a19e4c 2161 struct uart_port *port = &sci_port->port;
3127c6b2 2162 int ret;
e108b2ca 2163
50f0959a
PM		 2164 sci_port->cfg = p;
2165
73a19e4c
GL		 2166 port->ops = &sci_uart_ops;
2167 port->iotype = UPIO_MEM;
2168 port->line = index;
75136d48
MP		 2169
2170 switch (p->type) {
d1d4b10c
GL		 2171 case PORT_SCIFB:
2172 port->fifosize = 256;
2173 break;
f303b364
UH		 2174 case PORT_HSCIF:
2175 port->fifosize = 128;
2176 break;
75136d48 2177 case PORT_SCIFA:
73a19e4c 2178 port->fifosize = 64;
75136d48
MP		 2179 break;
2180 case PORT_SCIF:
73a19e4c 2181 port->fifosize = 16;
75136d48
MP		 2182 break;
2183 default:
73a19e4c 2184 port->fifosize = 1;
75136d48
MP		 2185 break;
2186 }
7b6fd3bf 2187
3127c6b2
PM		 2188 if (p->regtype == SCIx_PROBE_REGTYPE) {
2189 ret = sci_probe_regmap(p);
fc97114b 2190 if (unlikely(ret))
3127c6b2
PM		 2191 return ret;
2192 }
61a6976b 2193
7b6fd3bf 2194 if (dev) {
c7ed1ab3
PM		 2195 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2196 if (IS_ERR(sci_port->iclk)) {
2197 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2198 if (IS_ERR(sci_port->iclk)) {
2199 dev_err(&dev->dev, "can't get iclk\n");
2200 return PTR_ERR(sci_port->iclk);
2201 }
2202 }
2203
2204 /*
2205 * The function clock is optional, ignore it if we can't
2206 * find it.
2207 */
2208 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2209 if (IS_ERR(sci_port->fclk))
2210 sci_port->fclk = NULL;
2211
73a19e4c 2212 port->dev = &dev->dev;
5e50d2d6 2213
50f0959a
PM		 2214 sci_init_gpios(sci_port);
2215
5e50d2d6 2216 pm_runtime_enable(&dev->dev);
7b6fd3bf 2217 }
e108b2ca 2218
7ed7e071
MD		 2219 sci_port->break_timer.data = (unsigned long)sci_port;
2220 sci_port->break_timer.function = sci_break_timer;
2221 init_timer(&sci_port->break_timer);
2222
debf9507
PM		 2223 /*
2224 * Establish some sensible defaults for the error detection.
2225 */
2226 if (!p->error_mask)
2227 p->error_mask = (p->type == PORT_SCI) ?
2228 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2229
2230 /*
2231 * Establish sensible defaults for the overrun detection, unless
2232 * the part has explicitly disabled support for it.
2233 */
2234 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2235 if (p->type == PORT_SCI)
2236 p->overrun_bit = 5;
2237 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2238 p->overrun_bit = 9;
2239 else
2240 p->overrun_bit = 0;
2241
2242 /*
2243 * Make the error mask inclusive of overrun detection, if
2244 * supported.
2245 */
2246 p->error_mask |= (1 << p->overrun_bit);
2247 }
2248
ce6738b6
PM		 2249 port->mapbase = p->mapbase;
2250 port->type = p->type;
f43dc23d 2251 port->flags = p->flags;
61a6976b 2252 port->regshift = p->regshift;
73a19e4c 2253
ce6738b6 2254 /*
61a6976b 2255 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2256 * for the multi-IRQ ports, which is where we are primarily
2257 * concerned with the shutdown path synchronization.
2258 *
2259 * For the muxed case there's nothing more to do.
2260 */
54aa89ea 2261 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2262 port->irqflags = 0;
73a19e4c 2263
61a6976b
PM		 2264 port->serial_in = sci_serial_in;
2265 port->serial_out = sci_serial_out;
2266
937bb6e4
GL		 2267 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2268 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2269 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2270
c7ed1ab3 2271 return 0;
e108b2ca
PM		 2272}
2273
6dae1421
LP		 2274static void sci_cleanup_single(struct sci_port *port)
2275{
2276 sci_free_gpios(port);
2277
2278 clk_put(port->iclk);
2279 clk_put(port->fclk);
2280
2281 pm_runtime_disable(port->port.dev);
2282}
2283
1da177e4 2284#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2285static void serial_console_putchar(struct uart_port *port, int ch)
2286{
2287 sci_poll_put_char(port, ch);
2288}
2289
1da177e4
LT		 2290/*
2291 * Print a string to the serial port trying not to disturb
2292 * any possible real use of the port...
2293 */
2294static void serial_console_write(struct console *co, const char *s,
2295 unsigned count)
2296{
906b17dc
PM		 2297 struct sci_port *sci_port = &sci_ports[co->index];
2298 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2299 unsigned short bits, ctrl;
2300 unsigned long flags;
2301 int locked = 1;
2302
2303 local_irq_save(flags);
2304 if (port->sysrq)
2305 locked = 0;
2306 else if (oops_in_progress)
2307 locked = spin_trylock(&port->lock);
2308 else
2309 spin_lock(&port->lock);
2310
2311 /* first save the SCSCR then disable the interrupts */
2312 ctrl = serial_port_in(port, SCSCR);
2313 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2314
501b825d 2315 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2316
2317 /* wait until fifo is empty and last bit has been transmitted */
2318 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2319 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2320 cpu_relax();
40f70c03
SK		 2321
2322 /* restore the SCSCR */
2323 serial_port_out(port, SCSCR, ctrl);
2324
2325 if (locked)
2326 spin_unlock(&port->lock);
2327 local_irq_restore(flags);
1da177e4
LT		 2328}
2329
9671f099 2330static int serial_console_setup(struct console *co, char *options)
1da177e4 2331{
dc8e6f5b 2332 struct sci_port *sci_port;
1da177e4
LT		 2333 struct uart_port *port;
2334 int baud = 115200;
2335 int bits = 8;
2336 int parity = 'n';
2337 int flow = 'n';
2338 int ret;
2339
e108b2ca 2340 /*
906b17dc 2341 * Refuse to handle any bogus ports.
1da177e4 2342 */
906b17dc 2343 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2344 return -ENODEV;
e108b2ca 2345
906b17dc
PM		 2346 sci_port = &sci_ports[co->index];
2347 port = &sci_port->port;
2348
b2267a6b
AC		 2349 /*
2350 * Refuse to handle uninitialized ports.
2351 */
2352 if (!port->ops)
2353 return -ENODEV;
2354
f6e9495d
PM		 2355 ret = sci_remap_port(port);
2356 if (unlikely(ret != 0))
2357 return ret;
e108b2ca 2358
1da177e4
LT		 2359 if (options)
2360 uart_parse_options(options, &baud, &parity, &bits, &flow);
2361
ab7cfb55 2362 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2363}
2364
2365static struct console serial_console = {
2366 .name = "ttySC",
906b17dc 2367 .device = uart_console_device,
1da177e4
LT		 2368 .write = serial_console_write,
2369 .setup = serial_console_setup,
fa5da2f7 2370 .flags = CON_PRINTBUFFER,
1da177e4 2371 .index = -1,
906b17dc 2372 .data = &sci_uart_driver,
1da177e4
LT		 2373};
2374
7b6fd3bf
MD		 2375static struct console early_serial_console = {
2376 .name = "early_ttySC",
2377 .write = serial_console_write,
2378 .flags = CON_PRINTBUFFER,
906b17dc 2379 .index = -1,
7b6fd3bf 2380};
ecdf8a46 2381
7b6fd3bf
MD		 2382static char early_serial_buf[32];
2383
9671f099 2384static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2385{
574de559 2386 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2387
2388 if (early_serial_console.data)
2389 return -EEXIST;
2390
2391 early_serial_console.index = pdev->id;
ecdf8a46 2392
906b17dc 2393 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2394
2395 serial_console_setup(&early_serial_console, early_serial_buf);
2396
2397 if (!strstr(early_serial_buf, "keep"))
2398 early_serial_console.flags |= CON_BOOT;
2399
2400 register_console(&early_serial_console);
2401 return 0;
2402}
6a8c9799
NI		 2403
2404#define SCI_CONSOLE (&serial_console)
2405
ecdf8a46 2406#else
9671f099 2407static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2408{
2409 return -EINVAL;
2410}
1da177e4 2411
6a8c9799
NI		 2412#define SCI_CONSOLE NULL
2413
2414#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2415
2416static char banner[] __initdata =
f303b364 2417 KERN_INFO "SuperH (H)SCI(F) driver initialized\n";
1da177e4
LT		 2418
2419static struct uart_driver sci_uart_driver = {
2420 .owner = THIS_MODULE,
2421 .driver_name = "sci",
1da177e4
LT		 2422 .dev_name = "ttySC",
2423 .major = SCI_MAJOR,
2424 .minor = SCI_MINOR_START,
e108b2ca 2425 .nr = SCI_NPORTS,
1da177e4
LT		 2426 .cons = SCI_CONSOLE,
2427};
2428
54507f6e 2429static int sci_remove(struct platform_device *dev)
e552de24 2430{
d535a230 2431 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2432
d535a230
PM		 2433 cpufreq_unregister_notifier(&port->freq_transition,
2434 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2435
d535a230
PM		 2436 uart_remove_one_port(&sci_uart_driver, &port->port);
2437
6dae1421 2438 sci_cleanup_single(port);
e552de24 2439
e552de24
MD		 2440 return 0;
2441}
2442
9671f099 2443static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2444 unsigned int index,
2445 struct plat_sci_port *p,
2446 struct sci_port *sciport)
2447{
0ee70712
MD		 2448 int ret;
2449
2450 /* Sanity check */
2451 if (unlikely(index >= SCI_NPORTS)) {
2452 dev_notice(&dev->dev, "Attempting to register port "
2453 "%d when only %d are available.\n",
2454 index+1, SCI_NPORTS);
2455 dev_notice(&dev->dev, "Consider bumping "
2456 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2457 return -EINVAL;
0ee70712
MD		 2458 }
2459
c7ed1ab3
PM		 2460 ret = sci_init_single(dev, sciport, index, p);
2461 if (ret)
2462 return ret;
0ee70712 2463
6dae1421
LP		 2464 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2465 if (ret) {
2466 sci_cleanup_single(sciport);
2467 return ret;
2468 }
2469
2470 return 0;
0ee70712
MD		 2471}
2472
9671f099 2473static int sci_probe(struct platform_device *dev)
1da177e4 2474{
3ba35baa 2475 struct plat_sci_port *p = dev_get_platdata(&dev->dev);
d535a230 2476 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2477 int ret;
d535a230 2478
ecdf8a46
PM		 2479 /*
2480 * If we've come here via earlyprintk initialization, head off to
2481 * the special early probe. We don't have sufficient device state
2482 * to make it beyond this yet.
2483 */
2484 if (is_early_platform_device(dev))
2485 return sci_probe_earlyprintk(dev);
7b6fd3bf 2486
d535a230 2487 platform_set_drvdata(dev, sp);
e552de24 2488
906b17dc 2489 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2490 if (ret)
6dae1421 2491 return ret;
e552de24 2492
d535a230 2493 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2494
d535a230
PM		 2495 ret = cpufreq_register_notifier(&sp->freq_transition,
2496 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2497 if (unlikely(ret < 0)) {
2498 sci_cleanup_single(sp);
2499 return ret;
2500 }
1da177e4
LT		 2501
2502#ifdef CONFIG_SH_STANDARD_BIOS
2503 sh_bios_gdb_detach();
2504#endif
2505
e108b2ca 2506 return 0;
1da177e4
LT		 2507}
2508
6daa79b3 2509static int sci_suspend(struct device *dev)
1da177e4 2510{
d535a230 2511 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2512
d535a230
PM		 2513 if (sport)
2514 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2515
e108b2ca
PM		 2516 return 0;
2517}
1da177e4 2518
6daa79b3 2519static int sci_resume(struct device *dev)
e108b2ca 2520{
d535a230 2521 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2522
d535a230
PM		 2523 if (sport)
2524 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2525
2526 return 0;
2527}
2528
47145210 2529static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2530 .suspend = sci_suspend,
2531 .resume = sci_resume,
2532};
2533
e108b2ca
PM		 2534static struct platform_driver sci_driver = {
2535 .probe = sci_probe,
b9e39c89 2536 .remove = sci_remove,
e108b2ca
PM		 2537 .driver = {
2538 .name = "sh-sci",
2539 .owner = THIS_MODULE,
6daa79b3 2540 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2541 },
2542};
2543
2544static int __init sci_init(void)
2545{
2546 int ret;
2547
2548 printk(banner);
2549
e108b2ca
PM		 2550 ret = uart_register_driver(&sci_uart_driver);
2551 if (likely(ret == 0)) {
2552 ret = platform_driver_register(&sci_driver);
2553 if (unlikely(ret))
2554 uart_unregister_driver(&sci_uart_driver);
2555 }
2556
2557 return ret;
2558}
2559
2560static void __exit sci_exit(void)
2561{
2562 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2563 uart_unregister_driver(&sci_uart_driver);
2564}
2565
7b6fd3bf
MD		 2566#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2567early_platform_init_buffer("earlyprintk", &sci_driver,
2568 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2569#endif
1da177e4
LT		 2570module_init(sci_init);
2571module_exit(sci_exit);
2572
e108b2ca 2573MODULE_LICENSE("GPL");
e169c139 2574MODULE_ALIAS("platform:sh-sci");
7f405f9c 2575MODULE_AUTHOR("Paul Mundt");
f303b364 2576MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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