projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sh: Fix conflicting definitions of ptrace_triggered
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
1da177e4
LT		 28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
e108b2ca 41#include <linux/platform_device.h>
96de1a8f 42#include <linux/serial_sci.h>
1da177e4 43#include <linux/notifier.h>
5e50d2d6 44#include <linux/pm_runtime.h>
1da177e4 45#include <linux/cpufreq.h>
85f094ec 46#include <linux/clk.h>
fa5da2f7 47#include <linux/ctype.h>
7ff731ae 48#include <linux/err.h>
73a19e4c 49#include <linux/dmaengine.h>
5beabc7f 50#include <linux/dma-mapping.h>
73a19e4c 51#include <linux/scatterlist.h>
5a0e3ad6 52#include <linux/slab.h>
85f094ec
PM		 53
54#ifdef CONFIG_SUPERH
1da177e4
LT		 55#include <asm/sh_bios.h>
56#endif
57
1da177e4
LT		 58#include "sh-sci.h"
59
e108b2ca
PM		 60struct sci_port {
61 struct uart_port port;
62
ce6738b6
PM		 63 /* Platform configuration */
64 struct plat_sci_port *cfg;
e108b2ca 65
e108b2ca
PM		 66 /* Break timer */
67 struct timer_list break_timer;
68 int break_flag;
1534a3b3 69
501b825d
MD		 70 /* Interface clock */
71 struct clk *iclk;
c7ed1ab3
PM		 72 /* Function clock */
73 struct clk *fclk;
edad1f20 74
9174fc8f
PM		 75 char *irqstr[SCIx_NR_IRQS];
76
73a19e4c
GL		 77 struct dma_chan *chan_tx;
78 struct dma_chan *chan_rx;
f43dc23d 79
73a19e4c 80#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 81 struct dma_async_tx_descriptor *desc_tx;
82 struct dma_async_tx_descriptor *desc_rx[2];
83 dma_cookie_t cookie_tx;
84 dma_cookie_t cookie_rx[2];
85 dma_cookie_t active_rx;
86 struct scatterlist sg_tx;
87 unsigned int sg_len_tx;
88 struct scatterlist sg_rx[2];
89 size_t buf_len_rx;
90 struct sh_dmae_slave param_tx;
91 struct sh_dmae_slave param_rx;
92 struct work_struct work_tx;
93 struct work_struct work_rx;
94 struct timer_list rx_timer;
3089f381 95 unsigned int rx_timeout;
73a19e4c 96#endif
e552de24 97
d535a230 98 struct notifier_block freq_transition;
e108b2ca
PM		 99};
100
1da177e4 101/* Function prototypes */
d535a230 102static void sci_start_tx(struct uart_port *port);
b129a8cc 103static void sci_stop_tx(struct uart_port *port);
d535a230 104static void sci_start_rx(struct uart_port *port);
1da177e4 105
e108b2ca 106#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 107
e108b2ca
PM		 108static struct sci_port sci_ports[SCI_NPORTS];
109static struct uart_driver sci_uart_driver;
1da177e4 110
e7c98dc7
MT		 111static inline struct sci_port *
112to_sci_port(struct uart_port *uart)
113{
114 return container_of(uart, struct sci_port, port);
115}
116
61a6976b
PM		 117struct plat_sci_reg {
118 u8 offset, size;
119};
120
121/* Helper for invalidating specific entries of an inherited map. */
122#define sci_reg_invalid { .offset = 0, .size = 0 }
123
124static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
125 [SCIx_PROBE_REGTYPE] = {
126 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
127 },
128
129 /*
130 * Common SCI definitions, dependent on the port's regshift
131 * value.
132 */
133 [SCIx_SCI_REGTYPE] = {
134 [SCSMR] = { 0x00, 8 },
135 [SCBRR] = { 0x01, 8 },
136 [SCSCR] = { 0x02, 8 },
137 [SCxTDR] = { 0x03, 8 },
138 [SCxSR] = { 0x04, 8 },
139 [SCxRDR] = { 0x05, 8 },
140 [SCFCR] = sci_reg_invalid,
141 [SCFDR] = sci_reg_invalid,
142 [SCTFDR] = sci_reg_invalid,
143 [SCRFDR] = sci_reg_invalid,
144 [SCSPTR] = sci_reg_invalid,
145 [SCLSR] = sci_reg_invalid,
146 },
147
148 /*
149 * Common definitions for legacy IrDA ports, dependent on
150 * regshift value.
151 */
152 [SCIx_IRDA_REGTYPE] = {
153 [SCSMR] = { 0x00, 8 },
154 [SCBRR] = { 0x01, 8 },
155 [SCSCR] = { 0x02, 8 },
156 [SCxTDR] = { 0x03, 8 },
157 [SCxSR] = { 0x04, 8 },
158 [SCxRDR] = { 0x05, 8 },
159 [SCFCR] = { 0x06, 8 },
160 [SCFDR] = { 0x07, 16 },
161 [SCTFDR] = sci_reg_invalid,
162 [SCRFDR] = sci_reg_invalid,
163 [SCSPTR] = sci_reg_invalid,
164 [SCLSR] = sci_reg_invalid,
165 },
166
167 /*
168 * Common SCIFA definitions.
169 */
170 [SCIx_SCIFA_REGTYPE] = {
171 [SCSMR] = { 0x00, 16 },
172 [SCBRR] = { 0x04, 8 },
173 [SCSCR] = { 0x08, 16 },
174 [SCxTDR] = { 0x20, 8 },
175 [SCxSR] = { 0x14, 16 },
176 [SCxRDR] = { 0x24, 8 },
177 [SCFCR] = { 0x18, 16 },
178 [SCFDR] = { 0x1c, 16 },
179 [SCTFDR] = sci_reg_invalid,
180 [SCRFDR] = sci_reg_invalid,
181 [SCSPTR] = sci_reg_invalid,
182 [SCLSR] = sci_reg_invalid,
183 },
184
185 /*
186 * Common SCIFB definitions.
187 */
188 [SCIx_SCIFB_REGTYPE] = {
189 [SCSMR] = { 0x00, 16 },
190 [SCBRR] = { 0x04, 8 },
191 [SCSCR] = { 0x08, 16 },
192 [SCxTDR] = { 0x40, 8 },
193 [SCxSR] = { 0x14, 16 },
194 [SCxRDR] = { 0x60, 8 },
195 [SCFCR] = { 0x18, 16 },
196 [SCFDR] = { 0x1c, 16 },
197 [SCTFDR] = sci_reg_invalid,
198 [SCRFDR] = sci_reg_invalid,
199 [SCSPTR] = sci_reg_invalid,
200 [SCLSR] = sci_reg_invalid,
201 },
202
203 /*
204 * Common SH-3 SCIF definitions.
205 */
206 [SCIx_SH3_SCIF_REGTYPE] = {
207 [SCSMR] = { 0x00, 8 },
208 [SCBRR] = { 0x02, 8 },
209 [SCSCR] = { 0x04, 8 },
210 [SCxTDR] = { 0x06, 8 },
211 [SCxSR] = { 0x08, 16 },
212 [SCxRDR] = { 0x0a, 8 },
213 [SCFCR] = { 0x0c, 8 },
214 [SCFDR] = { 0x0e, 16 },
215 [SCTFDR] = sci_reg_invalid,
216 [SCRFDR] = sci_reg_invalid,
217 [SCSPTR] = sci_reg_invalid,
218 [SCLSR] = sci_reg_invalid,
219 },
220
221 /*
222 * Common SH-4(A) SCIF(B) definitions.
223 */
224 [SCIx_SH4_SCIF_REGTYPE] = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x0c, 8 },
229 [SCxSR] = { 0x10, 16 },
230 [SCxRDR] = { 0x14, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCTFDR] = sci_reg_invalid,
234 [SCRFDR] = sci_reg_invalid,
235 [SCSPTR] = { 0x20, 16 },
236 [SCLSR] = { 0x24, 16 },
237 },
238
239 /*
240 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
241 * register.
242 */
243 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x0c, 8 },
248 [SCxSR] = { 0x10, 16 },
249 [SCxRDR] = { 0x14, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = { 0x1c, 16 },
252 [SCTFDR] = sci_reg_invalid,
253 [SCRFDR] = sci_reg_invalid,
254 [SCSPTR] = sci_reg_invalid,
255 [SCLSR] = { 0x24, 16 },
256 },
257
258 /*
259 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
260 * count registers.
261 */
262 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
263 [SCSMR] = { 0x00, 16 },
264 [SCBRR] = { 0x04, 8 },
265 [SCSCR] = { 0x08, 16 },
266 [SCxTDR] = { 0x0c, 8 },
267 [SCxSR] = { 0x10, 16 },
268 [SCxRDR] = { 0x14, 8 },
269 [SCFCR] = { 0x18, 16 },
270 [SCFDR] = { 0x1c, 16 },
271 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
272 [SCRFDR] = { 0x20, 16 },
273 [SCSPTR] = { 0x24, 16 },
274 [SCLSR] = { 0x28, 16 },
275 },
276
277 /*
278 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
279 * registers.
280 */
281 [SCIx_SH7705_SCIF_REGTYPE] = {
282 [SCSMR] = { 0x00, 16 },
283 [SCBRR] = { 0x04, 8 },
284 [SCSCR] = { 0x08, 16 },
285 [SCxTDR] = { 0x20, 8 },
286 [SCxSR] = { 0x14, 16 },
287 [SCxRDR] = { 0x24, 8 },
288 [SCFCR] = { 0x18, 16 },
289 [SCFDR] = { 0x1c, 16 },
290 [SCTFDR] = sci_reg_invalid,
291 [SCRFDR] = sci_reg_invalid,
292 [SCSPTR] = sci_reg_invalid,
293 [SCLSR] = sci_reg_invalid,
294 },
295};
296
72b294cf
PM		 297#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
298
61a6976b
PM		 299/*
300 * The "offset" here is rather misleading, in that it refers to an enum
301 * value relative to the port mapping rather than the fixed offset
302 * itself, which needs to be manually retrieved from the platform's
303 * register map for the given port.
304 */
305static unsigned int sci_serial_in(struct uart_port *p, int offset)
306{
72b294cf 307 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 308
309 if (reg->size == 8)
310 return ioread8(p->membase + (reg->offset << p->regshift));
311 else if (reg->size == 16)
312 return ioread16(p->membase + (reg->offset << p->regshift));
313 else
314 WARN(1, "Invalid register access\n");
315
316 return 0;
317}
318
319static void sci_serial_out(struct uart_port *p, int offset, int value)
320{
72b294cf 321 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 322
323 if (reg->size == 8)
324 iowrite8(value, p->membase + (reg->offset << p->regshift));
325 else if (reg->size == 16)
326 iowrite16(value, p->membase + (reg->offset << p->regshift));
327 else
328 WARN(1, "Invalid register access\n");
329}
330
331#define sci_in(up, offset) (up->serial_in(up, offset))
332#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
333
334static int sci_probe_regmap(struct plat_sci_port *cfg)
335{
336 switch (cfg->type) {
337 case PORT_SCI:
338 cfg->regtype = SCIx_SCI_REGTYPE;
339 break;
340 case PORT_IRDA:
341 cfg->regtype = SCIx_IRDA_REGTYPE;
342 break;
343 case PORT_SCIFA:
344 cfg->regtype = SCIx_SCIFA_REGTYPE;
345 break;
346 case PORT_SCIFB:
347 cfg->regtype = SCIx_SCIFB_REGTYPE;
348 break;
349 case PORT_SCIF:
350 /*
351 * The SH-4 is a bit of a misnomer here, although that's
352 * where this particular port layout originated. This
353 * configuration (or some slight variation thereof)
354 * remains the dominant model for all SCIFs.
355 */
356 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
357 break;
358 default:
359 printk(KERN_ERR "Can't probe register map for given port\n");
360 return -EINVAL;
361 }
362
363 return 0;
364}
365
23241d43
PM		 366static void sci_port_enable(struct sci_port *sci_port)
367{
368 if (!sci_port->port.dev)
369 return;
370
371 pm_runtime_get_sync(sci_port->port.dev);
372
373 clk_enable(sci_port->iclk);
374 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
375 clk_enable(sci_port->fclk);
376}
377
378static void sci_port_disable(struct sci_port *sci_port)
379{
380 if (!sci_port->port.dev)
381 return;
382
383 clk_disable(sci_port->fclk);
384 clk_disable(sci_port->iclk);
385
386 pm_runtime_put_sync(sci_port->port.dev);
387}
388
07d2a1a1 389#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 390
391#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 392static int sci_poll_get_char(struct uart_port *port)
1da177e4 393{
1da177e4
LT		 394 unsigned short status;
395 int c;
396
e108b2ca 397 do {
1da177e4
LT		 398 status = sci_in(port, SCxSR);
399 if (status & SCxSR_ERRORS(port)) {
94c8b6db 400 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 401 continue;
402 }
3f255eb3
JW		 403 break;
404 } while (1);
405
406 if (!(status & SCxSR_RDxF(port)))
407 return NO_POLL_CHAR;
07d2a1a1 408
1da177e4 409 c = sci_in(port, SCxRDR);
07d2a1a1 410
e7c98dc7
MT		 411 /* Dummy read */
412 sci_in(port, SCxSR);
1da177e4 413 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 414
415 return c;
416}
1f6fd5c9 417#endif
1da177e4 418
07d2a1a1 419static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 420{
1da177e4
LT		 421 unsigned short status;
422
1da177e4
LT		 423 do {
424 status = sci_in(port, SCxSR);
425 } while (!(status & SCxSR_TDxE(port)));
426
272966c0 427 sci_out(port, SCxTDR, c);
dd0a3e77 428 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 429}
07d2a1a1 430#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 431
61a6976b 432static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 433{
61a6976b
PM		 434 struct sci_port *s = to_sci_port(port);
435 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 436
61a6976b
PM		 437 /*
438 * Use port-specific handler if provided.
439 */
440 if (s->cfg->ops && s->cfg->ops->init_pins) {
441 s->cfg->ops->init_pins(port, cflag);
442 return;
1da177e4 443 }
41504c39 444
61a6976b
PM		 445 /*
446 * For the generic path SCSPTR is necessary. Bail out if that's
447 * unavailable, too.
448 */
449 if (!reg->size)
450 return;
41504c39 451
d5701647 452 if (!(cflag & CRTSCTS))
61a6976b 453 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
d5701647 454}
e108b2ca 455
72b294cf 456static int sci_txfill(struct uart_port *port)
e108b2ca 457{
72b294cf 458 struct plat_sci_reg *reg;
e108b2ca 459
72b294cf
PM		 460 reg = sci_getreg(port, SCTFDR);
461 if (reg->size)
73a19e4c 462 return sci_in(port, SCTFDR) & 0xff;
c63847a3 463
72b294cf
PM		 464 reg = sci_getreg(port, SCFDR);
465 if (reg->size)
d1d4b10c 466 return sci_in(port, SCFDR) >> 8;
d1d4b10c 467
73a19e4c 468 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 469}
470
73a19e4c
GL		 471static int sci_txroom(struct uart_port *port)
472{
72b294cf 473 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 474}
475
476static int sci_rxfill(struct uart_port *port)
e108b2ca 477{
72b294cf
PM		 478 struct plat_sci_reg *reg;
479
480 reg = sci_getreg(port, SCRFDR);
481 if (reg->size)
482 return sci_in(port, SCRFDR) & 0xff;
483
484 reg = sci_getreg(port, SCFDR);
485 if (reg->size)
486 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
487
e7c98dc7 488 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 489}
490
514820eb
PM		 491/*
492 * SCI helper for checking the state of the muxed port/RXD pins.
493 */
494static inline int sci_rxd_in(struct uart_port *port)
495{
496 struct sci_port *s = to_sci_port(port);
497
498 if (s->cfg->port_reg <= 0)
499 return 1;
500
501 return !!__raw_readb(s->cfg->port_reg);
502}
503
1da177e4
LT		 504/* ********************************************************************** *
505 * the interrupt related routines *
506 * ********************************************************************** */
507
508static void sci_transmit_chars(struct uart_port *port)
509{
ebd2c8f6 510 struct circ_buf *xmit = &port->state->xmit;
1da177e4 511 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 512 unsigned short status;
513 unsigned short ctrl;
e108b2ca 514 int count;
1da177e4
LT		 515
516 status = sci_in(port, SCxSR);
517 if (!(status & SCxSR_TDxE(port))) {
1da177e4 518 ctrl = sci_in(port, SCSCR);
e7c98dc7 519 if (uart_circ_empty(xmit))
8e698614 520 ctrl &= ~SCSCR_TIE;
e7c98dc7 521 else
8e698614 522 ctrl |= SCSCR_TIE;
1da177e4 523 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 524 return;
525 }
526
72b294cf 527 count = sci_txroom(port);
1da177e4
LT		 528
529 do {
530 unsigned char c;
531
532 if (port->x_char) {
533 c = port->x_char;
534 port->x_char = 0;
535 } else if (!uart_circ_empty(xmit) && !stopped) {
536 c = xmit->buf[xmit->tail];
537 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
538 } else {
539 break;
540 }
541
542 sci_out(port, SCxTDR, c);
543
544 port->icount.tx++;
545 } while (--count > 0);
546
547 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
548
549 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
550 uart_write_wakeup(port);
551 if (uart_circ_empty(xmit)) {
b129a8cc 552 sci_stop_tx(port);
1da177e4 553 } else {
1da177e4
LT		 554 ctrl = sci_in(port, SCSCR);
555
1a22f08d 556 if (port->type != PORT_SCI) {
1da177e4
LT		 557 sci_in(port, SCxSR); /* Dummy read */
558 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
559 }
1da177e4 560
8e698614 561 ctrl |= SCSCR_TIE;
1da177e4 562 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 563 }
564}
565
566/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 567#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 568
94c8b6db 569static void sci_receive_chars(struct uart_port *port)
1da177e4 570{
e7c98dc7 571 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 572 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 573 int i, count, copied = 0;
574 unsigned short status;
33f0f88f 575 unsigned char flag;
1da177e4
LT		 576
577 status = sci_in(port, SCxSR);
578 if (!(status & SCxSR_RDxF(port)))
579 return;
580
581 while (1) {
1da177e4 582 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 583 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 584
585 /* If for any reason we can't copy more data, we're done! */
586 if (count == 0)
587 break;
588
589 if (port->type == PORT_SCI) {
590 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 591 if (uart_handle_sysrq_char(port, c) ||
592 sci_port->break_flag)
1da177e4 593 count = 0;
e7c98dc7 594 else
e108b2ca 595 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 596 } else {
e7c98dc7 597 for (i = 0; i < count; i++) {
1da177e4
LT		 598 char c = sci_in(port, SCxRDR);
599 status = sci_in(port, SCxSR);
600#if defined(CONFIG_CPU_SH3)
601 /* Skip "chars" during break */
e108b2ca 602 if (sci_port->break_flag) {
1da177e4
LT		 603 if ((c == 0) &&
604 (status & SCxSR_FER(port))) {
605 count--; i--;
606 continue;
607 }
e108b2ca 608
1da177e4 609 /* Nonzero => end-of-break */
762c69e3 610 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 611 sci_port->break_flag = 0;
612
1da177e4
LT		 613 if (STEPFN(c)) {
614 count--; i--;
615 continue;
616 }
617 }
618#endif /* CONFIG_CPU_SH3 */
7d12e780 619 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 620 count--; i--;
621 continue;
622 }
623
624 /* Store data and status */
73a19e4c 625 if (status & SCxSR_FER(port)) {
33f0f88f 626 flag = TTY_FRAME;
762c69e3 627 dev_notice(port->dev, "frame error\n");
73a19e4c 628 } else if (status & SCxSR_PER(port)) {
33f0f88f 629 flag = TTY_PARITY;
762c69e3 630 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 631 } else
632 flag = TTY_NORMAL;
762c69e3 633
33f0f88f 634 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 635 }
636 }
637
638 sci_in(port, SCxSR); /* dummy read */
639 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
640
1da177e4
LT		 641 copied += count;
642 port->icount.rx += count;
643 }
644
645 if (copied) {
646 /* Tell the rest of the system the news. New characters! */
647 tty_flip_buffer_push(tty);
648 } else {
649 sci_in(port, SCxSR); /* dummy read */
650 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
651 }
652}
653
654#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 655
656/*
657 * The sci generates interrupts during the break,
1da177e4
LT		 658 * 1 per millisecond or so during the break period, for 9600 baud.
659 * So dont bother disabling interrupts.
660 * But dont want more than 1 break event.
661 * Use a kernel timer to periodically poll the rx line until
662 * the break is finished.
663 */
94c8b6db 664static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 665{
bc9b3f5c 666 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 667}
94c8b6db 668
1da177e4
LT		 669/* Ensure that two consecutive samples find the break over. */
670static void sci_break_timer(unsigned long data)
671{
e108b2ca
PM		 672 struct sci_port *port = (struct sci_port *)data;
673
23241d43 674 sci_port_enable(port);
5e50d2d6 675
e108b2ca 676 if (sci_rxd_in(&port->port) == 0) {
1da177e4 677 port->break_flag = 1;
e108b2ca
PM		 678 sci_schedule_break_timer(port);
679 } else if (port->break_flag == 1) {
1da177e4
LT		 680 /* break is over. */
681 port->break_flag = 2;
e108b2ca
PM		 682 sci_schedule_break_timer(port);
683 } else
684 port->break_flag = 0;
5e50d2d6 685
23241d43 686 sci_port_disable(port);
1da177e4
LT		 687}
688
94c8b6db 689static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 690{
691 int copied = 0;
692 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 693 struct tty_struct *tty = port->state->port.tty;
debf9507 694 struct sci_port *s = to_sci_port(port);
1da177e4 695
debf9507
PM		 696 /*
697 * Handle overruns, if supported.
698 */
699 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
700 if (status & (1 << s->cfg->overrun_bit)) {
701 /* overrun error */
702 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
703 copied++;
762c69e3 704
debf9507
PM		 705 dev_notice(port->dev, "overrun error");
706 }
1da177e4
LT		 707 }
708
e108b2ca 709 if (status & SCxSR_FER(port)) {
1da177e4
LT		 710 if (sci_rxd_in(port) == 0) {
711 /* Notify of BREAK */
e7c98dc7 712 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 713
714 if (!sci_port->break_flag) {
715 sci_port->break_flag = 1;
716 sci_schedule_break_timer(sci_port);
717
1da177e4 718 /* Do sysrq handling. */
e108b2ca 719 if (uart_handle_break(port))
1da177e4 720 return 0;
762c69e3
PM		 721
722 dev_dbg(port->dev, "BREAK detected\n");
723
e108b2ca 724 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 725 copied++;
726 }
727
e108b2ca 728 } else {
1da177e4 729 /* frame error */
e108b2ca 730 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 731 copied++;
762c69e3
PM		 732
733 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 734 }
735 }
736
e108b2ca 737 if (status & SCxSR_PER(port)) {
1da177e4 738 /* parity error */
e108b2ca
PM		 739 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
740 copied++;
762c69e3
PM		 741
742 dev_notice(port->dev, "parity error");
1da177e4
LT		 743 }
744
33f0f88f 745 if (copied)
1da177e4 746 tty_flip_buffer_push(tty);
1da177e4
LT		 747
748 return copied;
749}
750
94c8b6db 751static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 752{
ebd2c8f6 753 struct tty_struct *tty = port->state->port.tty;
debf9507 754 struct sci_port *s = to_sci_port(port);
4b8c59a3 755 struct plat_sci_reg *reg;
d830fa45
PM		 756 int copied = 0;
757
4b8c59a3
PM		 758 reg = sci_getreg(port, SCLSR);
759 if (!reg->size)
d830fa45
PM		 760 return 0;
761
debf9507 762 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
d830fa45
PM		 763 sci_out(port, SCLSR, 0);
764
765 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
766 tty_flip_buffer_push(tty);
767
768 dev_notice(port->dev, "overrun error\n");
769 copied++;
770 }
771
772 return copied;
773}
774
94c8b6db 775static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 776{
777 int copied = 0;
778 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 779 struct tty_struct *tty = port->state->port.tty;
a5660ada 780 struct sci_port *s = to_sci_port(port);
1da177e4 781
0b3d4ef6
PM		 782 if (uart_handle_break(port))
783 return 0;
784
b7a76e4b 785 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 786#if defined(CONFIG_CPU_SH3)
787 /* Debounce break */
788 s->break_flag = 1;
789#endif
790 /* Notify of BREAK */
e108b2ca 791 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 792 copied++;
762c69e3
PM		 793
794 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 795 }
796
33f0f88f 797 if (copied)
1da177e4 798 tty_flip_buffer_push(tty);
e108b2ca 799
d830fa45
PM		 800 copied += sci_handle_fifo_overrun(port);
801
1da177e4
LT		 802 return copied;
803}
804
73a19e4c 805static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 806{
73a19e4c
GL		 807#ifdef CONFIG_SERIAL_SH_SCI_DMA
808 struct uart_port *port = ptr;
809 struct sci_port *s = to_sci_port(port);
810
811 if (s->chan_rx) {
73a19e4c
GL		 812 u16 scr = sci_in(port, SCSCR);
813 u16 ssr = sci_in(port, SCxSR);
814
815 /* Disable future Rx interrupts */
d1d4b10c 816 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 817 disable_irq_nosync(irq);
818 scr |= 0x4000;
819 } else {
f43dc23d 820 scr &= ~SCSCR_RIE;
3089f381
GL		 821 }
822 sci_out(port, SCSCR, scr);
73a19e4c
GL		 823 /* Clear current interrupt */
824 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 825 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
826 jiffies, s->rx_timeout);
827 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 828
829 return IRQ_HANDLED;
830 }
831#endif
832
1da177e4
LT		 833 /* I think sci_receive_chars has to be called irrespective
834 * of whether the I_IXOFF is set, otherwise, how is the interrupt
835 * to be disabled?
836 */
73a19e4c 837 sci_receive_chars(ptr);
1da177e4
LT		 838
839 return IRQ_HANDLED;
840}
841
7d12e780 842static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 843{
844 struct uart_port *port = ptr;
fd78a76a 845 unsigned long flags;
1da177e4 846
fd78a76a 847 spin_lock_irqsave(&port->lock, flags);
1da177e4 848 sci_transmit_chars(port);
fd78a76a 849 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 850
851 return IRQ_HANDLED;
852}
853
7d12e780 854static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 855{
856 struct uart_port *port = ptr;
857
858 /* Handle errors */
859 if (port->type == PORT_SCI) {
860 if (sci_handle_errors(port)) {
861 /* discard character in rx buffer */
862 sci_in(port, SCxSR);
863 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
864 }
865 } else {
d830fa45 866 sci_handle_fifo_overrun(port);
7d12e780 867 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 868 }
869
870 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
871
872 /* Kick the transmission */
7d12e780 873 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 874
875 return IRQ_HANDLED;
876}
877
7d12e780 878static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 879{
880 struct uart_port *port = ptr;
881
882 /* Handle BREAKs */
883 sci_handle_breaks(port);
884 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
885
886 return IRQ_HANDLED;
887}
888
f43dc23d
PM		 889static inline unsigned long port_rx_irq_mask(struct uart_port *port)
890{
891 /*
892 * Not all ports (such as SCIFA) will support REIE. Rather than
893 * special-casing the port type, we check the port initialization
894 * IRQ enable mask to see whether the IRQ is desired at all. If
895 * it's unset, it's logically inferred that there's no point in
896 * testing for it.
897 */
ce6738b6 898 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 899}
900
7d12e780 901static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 902{
44e18e9e 903 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 904 struct uart_port *port = ptr;
73a19e4c 905 struct sci_port *s = to_sci_port(port);
a8884e34 906 irqreturn_t ret = IRQ_NONE;
1da177e4 907
e7c98dc7
MT		 908 ssr_status = sci_in(port, SCxSR);
909 scr_status = sci_in(port, SCSCR);
f43dc23d 910 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 911
912 /* Tx Interrupt */
f43dc23d 913 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 914 !s->chan_tx)
a8884e34 915 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 916
73a19e4c
GL		 917 /*
918 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
919 * DR flags
920 */
921 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 922 (scr_status & SCSCR_RIE))
a8884e34 923 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 924
1da177e4 925 /* Error Interrupt */
dd4da3a5 926 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 927 ret = sci_er_interrupt(irq, ptr);
f43dc23d 928
1da177e4 929 /* Break Interrupt */
dd4da3a5 930 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 931 ret = sci_br_interrupt(irq, ptr);
1da177e4 932
a8884e34 933 return ret;
1da177e4
LT		 934}
935
1da177e4 936/*
25985edc 937 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 938 * ports' baud rate when the peripheral clock changes.
939 */
e108b2ca
PM		 940static int sci_notifier(struct notifier_block *self,
941 unsigned long phase, void *p)
1da177e4 942{
e552de24
MD		 943 struct sci_port *sci_port;
944 unsigned long flags;
1da177e4 945
d535a230
PM		 946 sci_port = container_of(self, struct sci_port, freq_transition);
947
1da177e4 948 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 949 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 950 struct uart_port *port = &sci_port->port;
073e84c9 951
d535a230
PM		 952 spin_lock_irqsave(&port->lock, flags);
953 port->uartclk = clk_get_rate(sci_port->iclk);
954 spin_unlock_irqrestore(&port->lock, flags);
e552de24 955 }
1da177e4 956
1da177e4
LT		 957 return NOTIFY_OK;
958}
501b825d 959
9174fc8f
PM		 960static struct sci_irq_desc {
961 const char *desc;
962 irq_handler_t handler;
963} sci_irq_desc[] = {
964 /*
965 * Split out handlers, the default case.
966 */
967 [SCIx_ERI_IRQ] = {
968 .desc = "rx err",
969 .handler = sci_er_interrupt,
970 },
971
972 [SCIx_RXI_IRQ] = {
973 .desc = "rx full",
974 .handler = sci_rx_interrupt,
975 },
976
977 [SCIx_TXI_IRQ] = {
978 .desc = "tx empty",
979 .handler = sci_tx_interrupt,
980 },
981
982 [SCIx_BRI_IRQ] = {
983 .desc = "break",
984 .handler = sci_br_interrupt,
985 },
986
987 /*
988 * Special muxed handler.
989 */
990 [SCIx_MUX_IRQ] = {
991 .desc = "mux",
992 .handler = sci_mpxed_interrupt,
993 },
994};
995
1da177e4
LT		 996static int sci_request_irq(struct sci_port *port)
997{
9174fc8f
PM		 998 struct uart_port *up = &port->port;
999 int i, j, ret = 0;
1000
1001 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1002 struct sci_irq_desc *desc;
1003 unsigned int irq;
1004
1005 if (SCIx_IRQ_IS_MUXED(port)) {
1006 i = SCIx_MUX_IRQ;
1007 irq = up->irq;
1008 } else
1009 irq = port->cfg->irqs[i];
1010
1011 desc = sci_irq_desc + i;
1012 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1013 dev_name(up->dev), desc->desc);
1014 if (!port->irqstr[j]) {
1015 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1016 desc->desc);
1017 goto out_nomem;
1da177e4 1018 }
9174fc8f
PM		 1019
1020 ret = request_irq(irq, desc->handler, up->irqflags,
1021 port->irqstr[j], port);
1022 if (unlikely(ret)) {
1023 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1024 goto out_noirq;
1da177e4
LT		 1025 }
1026 }
1027
1028 return 0;
9174fc8f
PM		 1029
1030out_noirq:
1031 while (--i >= 0)
1032 free_irq(port->cfg->irqs[i], port);
1033
1034out_nomem:
1035 while (--j >= 0)
1036 kfree(port->irqstr[j]);
1037
1038 return ret;
1da177e4
LT		 1039}
1040
1041static void sci_free_irq(struct sci_port *port)
1042{
1043 int i;
1044
9174fc8f
PM		 1045 /*
1046 * Intentionally in reverse order so we iterate over the muxed
1047 * IRQ first.
1048 */
1049 for (i = 0; i < SCIx_NR_IRQS; i++) {
1050 free_irq(port->cfg->irqs[i], port);
1051 kfree(port->irqstr[i]);
1da177e4 1052
9174fc8f
PM		 1053 if (SCIx_IRQ_IS_MUXED(port)) {
1054 /* If there's only one IRQ, we're done. */
1055 return;
1da177e4
LT		 1056 }
1057 }
1058}
1059
1060static unsigned int sci_tx_empty(struct uart_port *port)
1061{
b1516803 1062 unsigned short status = sci_in(port, SCxSR);
72b294cf 1063 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1064
1065 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1066}
1067
1068static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1069{
1070 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
1071 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
1072 /* If you have signals for DTR and DCD, please implement here. */
1073}
1074
1075static unsigned int sci_get_mctrl(struct uart_port *port)
1076{
73a19e4c 1077 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 1078 and CTS/RTS */
1079
1080 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
1081}
1082
73a19e4c
GL		 1083#ifdef CONFIG_SERIAL_SH_SCI_DMA
1084static void sci_dma_tx_complete(void *arg)
1085{
1086 struct sci_port *s = arg;
1087 struct uart_port *port = &s->port;
1088 struct circ_buf *xmit = &port->state->xmit;
1089 unsigned long flags;
1090
1091 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1092
1093 spin_lock_irqsave(&port->lock, flags);
1094
f354a381 1095 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1096 xmit->tail &= UART_XMIT_SIZE - 1;
1097
f354a381 1098 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1099
1100 async_tx_ack(s->desc_tx);
1101 s->cookie_tx = -EINVAL;
1102 s->desc_tx = NULL;
1103
73a19e4c
GL		 1104 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1105 uart_write_wakeup(port);
1106
3089f381 1107 if (!uart_circ_empty(xmit)) {
73a19e4c 1108 schedule_work(&s->work_tx);
d1d4b10c 1109 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1110 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 1111 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 1112 }
1113
1114 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1115}
1116
1117/* Locking: called with port lock held */
1118static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1119 size_t count)
1120{
1121 struct uart_port *port = &s->port;
1122 int i, active, room;
1123
1124 room = tty_buffer_request_room(tty, count);
1125
1126 if (s->active_rx == s->cookie_rx[0]) {
1127 active = 0;
1128 } else if (s->active_rx == s->cookie_rx[1]) {
1129 active = 1;
1130 } else {
1131 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1132 return 0;
1133 }
1134
1135 if (room < count)
1136 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1137 count - room);
1138 if (!room)
1139 return room;
1140
1141 for (i = 0; i < room; i++)
1142 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1143 TTY_NORMAL);
1144
1145 port->icount.rx += room;
1146
1147 return room;
1148}
1149
1150static void sci_dma_rx_complete(void *arg)
1151{
1152 struct sci_port *s = arg;
1153 struct uart_port *port = &s->port;
1154 struct tty_struct *tty = port->state->port.tty;
1155 unsigned long flags;
1156 int count;
1157
3089f381 1158 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1159
1160 spin_lock_irqsave(&port->lock, flags);
1161
1162 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1163
3089f381 1164 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1165
1166 spin_unlock_irqrestore(&port->lock, flags);
1167
1168 if (count)
1169 tty_flip_buffer_push(tty);
1170
1171 schedule_work(&s->work_rx);
1172}
1173
73a19e4c
GL		 1174static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1175{
1176 struct dma_chan *chan = s->chan_rx;
1177 struct uart_port *port = &s->port;
73a19e4c
GL		 1178
1179 s->chan_rx = NULL;
1180 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1181 dma_release_channel(chan);
85b8e3ff
GL		 1182 if (sg_dma_address(&s->sg_rx[0]))
1183 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1184 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1185 if (enable_pio)
1186 sci_start_rx(port);
1187}
1188
1189static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1190{
1191 struct dma_chan *chan = s->chan_tx;
1192 struct uart_port *port = &s->port;
73a19e4c
GL		 1193
1194 s->chan_tx = NULL;
1195 s->cookie_tx = -EINVAL;
1196 dma_release_channel(chan);
1197 if (enable_pio)
1198 sci_start_tx(port);
1199}
1200
1201static void sci_submit_rx(struct sci_port *s)
1202{
1203 struct dma_chan *chan = s->chan_rx;
1204 int i;
1205
1206 for (i = 0; i < 2; i++) {
1207 struct scatterlist *sg = &s->sg_rx[i];
1208 struct dma_async_tx_descriptor *desc;
1209
1210 desc = chan->device->device_prep_slave_sg(chan,
1211 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1212
1213 if (desc) {
1214 s->desc_rx[i] = desc;
1215 desc->callback = sci_dma_rx_complete;
1216 desc->callback_param = s;
1217 s->cookie_rx[i] = desc->tx_submit(desc);
1218 }
1219
1220 if (!desc || s->cookie_rx[i] < 0) {
1221 if (i) {
1222 async_tx_ack(s->desc_rx[0]);
1223 s->cookie_rx[0] = -EINVAL;
1224 }
1225 if (desc) {
1226 async_tx_ack(desc);
1227 s->cookie_rx[i] = -EINVAL;
1228 }
1229 dev_warn(s->port.dev,
1230 "failed to re-start DMA, using PIO\n");
1231 sci_rx_dma_release(s, true);
1232 return;
1233 }
3089f381
GL		 1234 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1235 s->cookie_rx[i], i);
73a19e4c
GL		 1236 }
1237
1238 s->active_rx = s->cookie_rx[0];
1239
1240 dma_async_issue_pending(chan);
1241}
1242
1243static void work_fn_rx(struct work_struct *work)
1244{
1245 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1246 struct uart_port *port = &s->port;
1247 struct dma_async_tx_descriptor *desc;
1248 int new;
1249
1250 if (s->active_rx == s->cookie_rx[0]) {
1251 new = 0;
1252 } else if (s->active_rx == s->cookie_rx[1]) {
1253 new = 1;
1254 } else {
1255 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1256 return;
1257 }
1258 desc = s->desc_rx[new];
1259
1260 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1261 DMA_SUCCESS) {
1262 /* Handle incomplete DMA receive */
1263 struct tty_struct *tty = port->state->port.tty;
1264 struct dma_chan *chan = s->chan_rx;
1265 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1266 async_tx);
1267 unsigned long flags;
1268 int count;
1269
05827630 1270 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1271 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1272 sh_desc->partial, sh_desc->cookie);
1273
1274 spin_lock_irqsave(&port->lock, flags);
1275 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1276 spin_unlock_irqrestore(&port->lock, flags);
1277
1278 if (count)
1279 tty_flip_buffer_push(tty);
1280
1281 sci_submit_rx(s);
1282
1283 return;
1284 }
1285
1286 s->cookie_rx[new] = desc->tx_submit(desc);
1287 if (s->cookie_rx[new] < 0) {
1288 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1289 sci_rx_dma_release(s, true);
1290 return;
1291 }
1292
73a19e4c 1293 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1294
1295 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1296 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1297}
1298
1299static void work_fn_tx(struct work_struct *work)
1300{
1301 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1302 struct dma_async_tx_descriptor *desc;
1303 struct dma_chan *chan = s->chan_tx;
1304 struct uart_port *port = &s->port;
1305 struct circ_buf *xmit = &port->state->xmit;
1306 struct scatterlist *sg = &s->sg_tx;
1307
1308 /*
1309 * DMA is idle now.
1310 * Port xmit buffer is already mapped, and it is one page... Just adjust
1311 * offsets and lengths. Since it is a circular buffer, we have to
1312 * transmit till the end, and then the rest. Take the port lock to get a
1313 * consistent xmit buffer state.
1314 */
1315 spin_lock_irq(&port->lock);
1316 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1317 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1318 sg->offset;
f354a381 1319 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1320 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1321 spin_unlock_irq(&port->lock);
1322
f354a381 1323 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1324
1325 desc = chan->device->device_prep_slave_sg(chan,
1326 sg, s->sg_len_tx, DMA_TO_DEVICE,
1327 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1328 if (!desc) {
1329 /* switch to PIO */
1330 sci_tx_dma_release(s, true);
1331 return;
1332 }
1333
1334 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1335
1336 spin_lock_irq(&port->lock);
1337 s->desc_tx = desc;
1338 desc->callback = sci_dma_tx_complete;
1339 desc->callback_param = s;
1340 spin_unlock_irq(&port->lock);
1341 s->cookie_tx = desc->tx_submit(desc);
1342 if (s->cookie_tx < 0) {
1343 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1344 /* switch to PIO */
1345 sci_tx_dma_release(s, true);
1346 return;
1347 }
1348
1349 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1350 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1351
1352 dma_async_issue_pending(chan);
1353}
1354#endif
1355
b129a8cc 1356static void sci_start_tx(struct uart_port *port)
1da177e4 1357{
3089f381 1358 struct sci_port *s = to_sci_port(port);
e108b2ca 1359 unsigned short ctrl;
1da177e4 1360
73a19e4c 1361#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1362 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1363 u16 new, scr = sci_in(port, SCSCR);
1364 if (s->chan_tx)
1365 new = scr | 0x8000;
1366 else
1367 new = scr & ~0x8000;
1368 if (new != scr)
1369 sci_out(port, SCSCR, new);
73a19e4c 1370 }
f43dc23d 1371
3089f381
GL		 1372 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1373 s->cookie_tx < 0)
1374 schedule_work(&s->work_tx);
73a19e4c 1375#endif
f43dc23d 1376
d1d4b10c 1377 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1378 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1379 ctrl = sci_in(port, SCSCR);
f43dc23d 1380 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1381 }
1da177e4
LT		 1382}
1383
b129a8cc 1384static void sci_stop_tx(struct uart_port *port)
1da177e4 1385{
1da177e4
LT		 1386 unsigned short ctrl;
1387
1388 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1389 ctrl = sci_in(port, SCSCR);
f43dc23d 1390
d1d4b10c 1391 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1392 ctrl &= ~0x8000;
f43dc23d 1393
8e698614 1394 ctrl &= ~SCSCR_TIE;
f43dc23d 1395
1da177e4 1396 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1397}
1398
73a19e4c 1399static void sci_start_rx(struct uart_port *port)
1da177e4 1400{
1da177e4
LT		 1401 unsigned short ctrl;
1402
f43dc23d 1403 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1404
d1d4b10c 1405 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1406 ctrl &= ~0x4000;
f43dc23d 1407
1da177e4 1408 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1409}
1410
1411static void sci_stop_rx(struct uart_port *port)
1412{
1da177e4
LT		 1413 unsigned short ctrl;
1414
1da177e4 1415 ctrl = sci_in(port, SCSCR);
f43dc23d 1416
d1d4b10c 1417 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1418 ctrl &= ~0x4000;
f43dc23d
PM		 1419
1420 ctrl &= ~port_rx_irq_mask(port);
1421
1da177e4 1422 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1423}
1424
1425static void sci_enable_ms(struct uart_port *port)
1426{
1427 /* Nothing here yet .. */
1428}
1429
1430static void sci_break_ctl(struct uart_port *port, int break_state)
1431{
1432 /* Nothing here yet .. */
1433}
1434
73a19e4c
GL		 1435#ifdef CONFIG_SERIAL_SH_SCI_DMA
1436static bool filter(struct dma_chan *chan, void *slave)
1437{
1438 struct sh_dmae_slave *param = slave;
1439
1440 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1441 param->slave_id);
1442
1443 if (param->dma_dev == chan->device->dev) {
1444 chan->private = param;
1445 return true;
1446 } else {
1447 return false;
1448 }
1449}
1450
1451static void rx_timer_fn(unsigned long arg)
1452{
1453 struct sci_port *s = (struct sci_port *)arg;
1454 struct uart_port *port = &s->port;
73a19e4c 1455 u16 scr = sci_in(port, SCSCR);
3089f381 1456
d1d4b10c 1457 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1458 scr &= ~0x4000;
ce6738b6 1459 enable_irq(s->cfg->irqs[1]);
3089f381 1460 }
f43dc23d 1461 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1462 dev_dbg(port->dev, "DMA Rx timed out\n");
1463 schedule_work(&s->work_rx);
1464}
1465
1466static void sci_request_dma(struct uart_port *port)
1467{
1468 struct sci_port *s = to_sci_port(port);
1469 struct sh_dmae_slave *param;
1470 struct dma_chan *chan;
1471 dma_cap_mask_t mask;
1472 int nent;
1473
1474 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
ce6738b6 1475 port->line, s->cfg->dma_dev);
73a19e4c 1476
ce6738b6 1477 if (!s->cfg->dma_dev)
73a19e4c
GL		 1478 return;
1479
1480 dma_cap_zero(mask);
1481 dma_cap_set(DMA_SLAVE, mask);
1482
1483 param = &s->param_tx;
1484
1485 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6
PM		 1486 param->slave_id = s->cfg->dma_slave_tx;
1487 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1488
1489 s->cookie_tx = -EINVAL;
1490 chan = dma_request_channel(mask, filter, param);
1491 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1492 if (chan) {
1493 s->chan_tx = chan;
1494 sg_init_table(&s->sg_tx, 1);
1495 /* UART circular tx buffer is an aligned page. */
1496 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1497 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1498 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1499 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1500 if (!nent)
1501 sci_tx_dma_release(s, false);
1502 else
1503 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1504 sg_dma_len(&s->sg_tx),
1505 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1506
1507 s->sg_len_tx = nent;
1508
1509 INIT_WORK(&s->work_tx, work_fn_tx);
1510 }
1511
1512 param = &s->param_rx;
1513
1514 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6
PM		 1515 param->slave_id = s->cfg->dma_slave_rx;
1516 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1517
1518 chan = dma_request_channel(mask, filter, param);
1519 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1520 if (chan) {
1521 dma_addr_t dma[2];
1522 void *buf[2];
1523 int i;
1524
1525 s->chan_rx = chan;
1526
1527 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1528 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1529 &dma[0], GFP_KERNEL);
1530
1531 if (!buf[0]) {
1532 dev_warn(port->dev,
1533 "failed to allocate dma buffer, using PIO\n");
1534 sci_rx_dma_release(s, true);
1535 return;
1536 }
1537
1538 buf[1] = buf[0] + s->buf_len_rx;
1539 dma[1] = dma[0] + s->buf_len_rx;
1540
1541 for (i = 0; i < 2; i++) {
1542 struct scatterlist *sg = &s->sg_rx[i];
1543
1544 sg_init_table(sg, 1);
1545 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1546 (int)buf[i] & ~PAGE_MASK);
f354a381 1547 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1548 }
1549
1550 INIT_WORK(&s->work_rx, work_fn_rx);
1551 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1552
1553 sci_submit_rx(s);
1554 }
1555}
1556
1557static void sci_free_dma(struct uart_port *port)
1558{
1559 struct sci_port *s = to_sci_port(port);
1560
ce6738b6 1561 if (!s->cfg->dma_dev)
73a19e4c
GL		 1562 return;
1563
1564 if (s->chan_tx)
1565 sci_tx_dma_release(s, false);
1566 if (s->chan_rx)
1567 sci_rx_dma_release(s, false);
1568}
27bd1075
PM		 1569#else
1570static inline void sci_request_dma(struct uart_port *port)
1571{
1572}
1573
1574static inline void sci_free_dma(struct uart_port *port)
1575{
1576}
73a19e4c
GL		 1577#endif
1578
1da177e4
LT		 1579static int sci_startup(struct uart_port *port)
1580{
a5660ada 1581 struct sci_port *s = to_sci_port(port);
073e84c9 1582 int ret;
1da177e4 1583
73a19e4c
GL		 1584 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1585
23241d43 1586 sci_port_enable(s);
1da177e4 1587
073e84c9
PM		 1588 ret = sci_request_irq(s);
1589 if (unlikely(ret < 0))
1590 return ret;
1591
73a19e4c 1592 sci_request_dma(port);
073e84c9 1593
d656901b 1594 sci_start_tx(port);
73a19e4c 1595 sci_start_rx(port);
1da177e4
LT		 1596
1597 return 0;
1598}
1599
1600static void sci_shutdown(struct uart_port *port)
1601{
a5660ada 1602 struct sci_port *s = to_sci_port(port);
1da177e4 1603
73a19e4c
GL		 1604 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1605
1da177e4 1606 sci_stop_rx(port);
b129a8cc 1607 sci_stop_tx(port);
073e84c9 1608
73a19e4c 1609 sci_free_dma(port);
1da177e4
LT		 1610 sci_free_irq(s);
1611
23241d43 1612 sci_port_disable(s);
1da177e4
LT		 1613}
1614
26c92f37
PM		 1615static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1616 unsigned long freq)
1617{
1618 switch (algo_id) {
1619 case SCBRR_ALGO_1:
1620 return ((freq + 16 * bps) / (16 * bps) - 1);
1621 case SCBRR_ALGO_2:
1622 return ((freq + 16 * bps) / (32 * bps) - 1);
1623 case SCBRR_ALGO_3:
1624 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1625 case SCBRR_ALGO_4:
1626 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1627 case SCBRR_ALGO_5:
1628 return (((freq * 1000 / 32) / bps) - 1);
1629 }
1630
1631 /* Warn, but use a safe default */
1632 WARN_ON(1);
e8183a6c 1633
26c92f37
PM		 1634 return ((freq + 16 * bps) / (32 * bps) - 1);
1635}
1636
606d099c
AC		 1637static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1638 struct ktermios *old)
1da177e4 1639{
00b9de9c 1640 struct sci_port *s = to_sci_port(port);
154280fd 1641 unsigned int status, baud, smr_val, max_baud;
a2159b52 1642 int t = -1;
3089f381 1643 u16 scfcr = 0;
1da177e4 1644
154280fd
MD		 1645 /*
1646 * earlyprintk comes here early on with port->uartclk set to zero.
1647 * the clock framework is not up and running at this point so here
1648 * we assume that 115200 is the maximum baud rate. please note that
1649 * the baud rate is not programmed during earlyprintk - it is assumed
1650 * that the previous boot loader has enabled required clocks and
1651 * setup the baud rate generator hardware for us already.
1652 */
1653 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1654
154280fd
MD		 1655 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1656 if (likely(baud && port->uartclk))
ce6738b6 1657 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1658
23241d43 1659 sci_port_enable(s);
36003386 1660
1da177e4
LT		 1661 do {
1662 status = sci_in(port, SCxSR);
1663 } while (!(status & SCxSR_TEND(port)));
1664
1665 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1666
1a22f08d 1667 if (port->type != PORT_SCI)
3089f381 1668 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1669
1670 smr_val = sci_in(port, SCSMR) & 3;
e8183a6c 1671
1da177e4
LT		 1672 if ((termios->c_cflag & CSIZE) == CS7)
1673 smr_val |= 0x40;
1674 if (termios->c_cflag & PARENB)
1675 smr_val |= 0x20;
1676 if (termios->c_cflag & PARODD)
1677 smr_val |= 0x30;
1678 if (termios->c_cflag & CSTOPB)
1679 smr_val |= 0x08;
1680
1681 uart_update_timeout(port, termios->c_cflag, baud);
1682
1683 sci_out(port, SCSMR, smr_val);
1684
73a19e4c 1685 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1686 s->cfg->scscr);
73a19e4c 1687
1da177e4 1688 if (t > 0) {
e7c98dc7 1689 if (t >= 256) {
1da177e4
LT		 1690 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1691 t >>= 2;
e7c98dc7 1692 } else
1da177e4 1693 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1694
1da177e4
LT		 1695 sci_out(port, SCBRR, t);
1696 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1697 }
1698
d5701647 1699 sci_init_pins(port, termios->c_cflag);
3089f381 1700 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
b7a76e4b 1701
ce6738b6 1702 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1703
3089f381
GL		 1704#ifdef CONFIG_SERIAL_SH_SCI_DMA
1705 /*
1706 * Calculate delay for 1.5 DMA buffers: see
1707 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1708 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1709 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1710 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1711 * sizes), but it has been found out experimentally, that this is not
1712 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1713 * as a minimum seem to work perfectly.
1714 */
1715 if (s->chan_rx) {
1716 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1717 port->fifosize / 2;
1718 dev_dbg(port->dev,
1719 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1720 s->rx_timeout * 1000 / HZ, port->timeout);
1721 if (s->rx_timeout < msecs_to_jiffies(20))
1722 s->rx_timeout = msecs_to_jiffies(20);
1723 }
1724#endif
1725
1da177e4 1726 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1727 sci_start_rx(port);
36003386 1728
23241d43 1729 sci_port_disable(s);
1da177e4
LT		 1730}
1731
1732static const char *sci_type(struct uart_port *port)
1733{
1734 switch (port->type) {
e7c98dc7
MT		 1735 case PORT_IRDA:
1736 return "irda";
1737 case PORT_SCI:
1738 return "sci";
1739 case PORT_SCIF:
1740 return "scif";
1741 case PORT_SCIFA:
1742 return "scifa";
d1d4b10c
GL		 1743 case PORT_SCIFB:
1744 return "scifb";
1da177e4
LT		 1745 }
1746
fa43972f 1747 return NULL;
1da177e4
LT		 1748}
1749
e2651647 1750static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1751{
e2651647
PM		 1752 /*
1753 * Pick an arbitrary size that encapsulates all of the base
1754 * registers by default. This can be optimized later, or derived
1755 * from platform resource data at such a time that ports begin to
1756 * behave more erratically.
1757 */
1758 return 64;
1da177e4
LT		 1759}
1760
f6e9495d
PM		 1761static int sci_remap_port(struct uart_port *port)
1762{
1763 unsigned long size = sci_port_size(port);
1764
1765 /*
1766 * Nothing to do if there's already an established membase.
1767 */
1768 if (port->membase)
1769 return 0;
1770
1771 if (port->flags & UPF_IOREMAP) {
1772 port->membase = ioremap_nocache(port->mapbase, size);
1773 if (unlikely(!port->membase)) {
1774 dev_err(port->dev, "can't remap port#%d\n", port->line);
1775 return -ENXIO;
1776 }
1777 } else {
1778 /*
1779 * For the simple (and majority of) cases where we don't
1780 * need to do any remapping, just cast the cookie
1781 * directly.
1782 */
1783 port->membase = (void __iomem *)port->mapbase;
1784 }
1785
1786 return 0;
1787}
1788
e2651647 1789static void sci_release_port(struct uart_port *port)
1da177e4 1790{
e2651647
PM		 1791 if (port->flags & UPF_IOREMAP) {
1792 iounmap(port->membase);
1793 port->membase = NULL;
1794 }
1795
1796 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1797}
1798
e2651647 1799static int sci_request_port(struct uart_port *port)
1da177e4 1800{
e2651647
PM		 1801 unsigned long size = sci_port_size(port);
1802 struct resource *res;
f6e9495d 1803 int ret;
1da177e4 1804
1020520e 1805 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 1806 if (unlikely(res == NULL))
1807 return -EBUSY;
1da177e4 1808
f6e9495d
PM		 1809 ret = sci_remap_port(port);
1810 if (unlikely(ret != 0)) {
1811 release_resource(res);
1812 return ret;
7ff731ae 1813 }
e2651647
PM		 1814
1815 return 0;
1816}
1817
1818static void sci_config_port(struct uart_port *port, int flags)
1819{
1820 if (flags & UART_CONFIG_TYPE) {
1821 struct sci_port *sport = to_sci_port(port);
1822
1823 port->type = sport->cfg->type;
1824 sci_request_port(port);
1825 }
1da177e4
LT		 1826}
1827
1828static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1829{
a5660ada 1830 struct sci_port *s = to_sci_port(port);
1da177e4 1831
ce6738b6 1832 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1833 return -EINVAL;
1834 if (ser->baud_base < 2400)
1835 /* No paper tape reader for Mitch.. */
1836 return -EINVAL;
1837
1838 return 0;
1839}
1840
1841static struct uart_ops sci_uart_ops = {
1842 .tx_empty = sci_tx_empty,
1843 .set_mctrl = sci_set_mctrl,
1844 .get_mctrl = sci_get_mctrl,
1845 .start_tx = sci_start_tx,
1846 .stop_tx = sci_stop_tx,
1847 .stop_rx = sci_stop_rx,
1848 .enable_ms = sci_enable_ms,
1849 .break_ctl = sci_break_ctl,
1850 .startup = sci_startup,
1851 .shutdown = sci_shutdown,
1852 .set_termios = sci_set_termios,
1853 .type = sci_type,
1854 .release_port = sci_release_port,
1855 .request_port = sci_request_port,
1856 .config_port = sci_config_port,
1857 .verify_port = sci_verify_port,
07d2a1a1
PM		 1858#ifdef CONFIG_CONSOLE_POLL
1859 .poll_get_char = sci_poll_get_char,
1860 .poll_put_char = sci_poll_put_char,
1861#endif
1da177e4
LT		 1862};
1863
c7ed1ab3
PM		 1864static int __devinit sci_init_single(struct platform_device *dev,
1865 struct sci_port *sci_port,
1866 unsigned int index,
1867 struct plat_sci_port *p)
e108b2ca 1868{
73a19e4c 1869 struct uart_port *port = &sci_port->port;
3127c6b2 1870 int ret;
e108b2ca 1871
73a19e4c
GL		 1872 port->ops = &sci_uart_ops;
1873 port->iotype = UPIO_MEM;
1874 port->line = index;
75136d48
MP		 1875
1876 switch (p->type) {
d1d4b10c
GL		 1877 case PORT_SCIFB:
1878 port->fifosize = 256;
1879 break;
75136d48 1880 case PORT_SCIFA:
73a19e4c 1881 port->fifosize = 64;
75136d48
MP		 1882 break;
1883 case PORT_SCIF:
73a19e4c 1884 port->fifosize = 16;
75136d48
MP		 1885 break;
1886 default:
73a19e4c 1887 port->fifosize = 1;
75136d48
MP		 1888 break;
1889 }
7b6fd3bf 1890
3127c6b2
PM		 1891 if (p->regtype == SCIx_PROBE_REGTYPE) {
1892 ret = sci_probe_regmap(p);
ad75b88a 1893 if (unlikely(ret != 0))
3127c6b2
PM		 1894 return ret;
1895 }
61a6976b 1896
7b6fd3bf 1897 if (dev) {
c7ed1ab3
PM		 1898 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1899 if (IS_ERR(sci_port->iclk)) {
1900 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1901 if (IS_ERR(sci_port->iclk)) {
1902 dev_err(&dev->dev, "can't get iclk\n");
1903 return PTR_ERR(sci_port->iclk);
1904 }
1905 }
1906
1907 /*
1908 * The function clock is optional, ignore it if we can't
1909 * find it.
1910 */
1911 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1912 if (IS_ERR(sci_port->fclk))
1913 sci_port->fclk = NULL;
1914
73a19e4c 1915 port->dev = &dev->dev;
5e50d2d6
MD		 1916
1917 pm_runtime_enable(&dev->dev);
7b6fd3bf 1918 }
e108b2ca 1919
7ed7e071
MD		 1920 sci_port->break_timer.data = (unsigned long)sci_port;
1921 sci_port->break_timer.function = sci_break_timer;
1922 init_timer(&sci_port->break_timer);
1923
debf9507
PM		 1924 /*
1925 * Establish some sensible defaults for the error detection.
1926 */
1927 if (!p->error_mask)
1928 p->error_mask = (p->type == PORT_SCI) ?
1929 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1930
1931 /*
1932 * Establish sensible defaults for the overrun detection, unless
1933 * the part has explicitly disabled support for it.
1934 */
1935 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1936 if (p->type == PORT_SCI)
1937 p->overrun_bit = 5;
1938 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1939 p->overrun_bit = 9;
1940 else
1941 p->overrun_bit = 0;
1942
1943 /*
1944 * Make the error mask inclusive of overrun detection, if
1945 * supported.
1946 */
1947 p->error_mask |= (1 << p->overrun_bit);
1948 }
1949
ce6738b6 1950 sci_port->cfg = p;
7ed7e071 1951
ce6738b6
PM		 1952 port->mapbase = p->mapbase;
1953 port->type = p->type;
f43dc23d 1954 port->flags = p->flags;
61a6976b 1955 port->regshift = p->regshift;
73a19e4c 1956
ce6738b6 1957 /*
61a6976b 1958 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 1959 * for the multi-IRQ ports, which is where we are primarily
1960 * concerned with the shutdown path synchronization.
1961 *
1962 * For the muxed case there's nothing more to do.
1963 */
54aa89ea 1964 port->irq = p->irqs[SCIx_RXI_IRQ];
9174fc8f 1965 port->irqflags = IRQF_DISABLED;
73a19e4c 1966
61a6976b
PM		 1967 port->serial_in = sci_serial_in;
1968 port->serial_out = sci_serial_out;
1969
ce6738b6
PM		 1970 if (p->dma_dev)
1971 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1972 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 1973
c7ed1ab3 1974 return 0;
e108b2ca
PM		 1975}
1976
1da177e4 1977#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1978static void serial_console_putchar(struct uart_port *port, int ch)
1979{
1980 sci_poll_put_char(port, ch);
1981}
1982
1da177e4
LT		 1983/*
1984 * Print a string to the serial port trying not to disturb
1985 * any possible real use of the port...
1986 */
1987static void serial_console_write(struct console *co, const char *s,
1988 unsigned count)
1989{
906b17dc
PM		 1990 struct sci_port *sci_port = &sci_ports[co->index];
1991 struct uart_port *port = &sci_port->port;
973e5d52 1992 unsigned short bits;
07d2a1a1 1993
23241d43 1994 sci_port_enable(sci_port);
501b825d
MD		 1995
1996 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1997
1998 /* wait until fifo is empty and last bit has been transmitted */
1999 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2000 while ((sci_in(port, SCxSR) & bits) != bits)
2001 cpu_relax();
501b825d 2002
23241d43 2003 sci_port_disable(sci_port);
1da177e4
LT		 2004}
2005
7b6fd3bf 2006static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 2007{
dc8e6f5b 2008 struct sci_port *sci_port;
1da177e4
LT		 2009 struct uart_port *port;
2010 int baud = 115200;
2011 int bits = 8;
2012 int parity = 'n';
2013 int flow = 'n';
2014 int ret;
2015
e108b2ca 2016 /*
906b17dc 2017 * Refuse to handle any bogus ports.
1da177e4 2018 */
906b17dc 2019 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2020 return -ENODEV;
e108b2ca 2021
906b17dc
PM		 2022 sci_port = &sci_ports[co->index];
2023 port = &sci_port->port;
2024
b2267a6b
AC		 2025 /*
2026 * Refuse to handle uninitialized ports.
2027 */
2028 if (!port->ops)
2029 return -ENODEV;
2030
f6e9495d
PM		 2031 ret = sci_remap_port(port);
2032 if (unlikely(ret != 0))
2033 return ret;
e108b2ca 2034
23241d43 2035 sci_port_enable(sci_port);
b7a76e4b 2036
1da177e4
LT		 2037 if (options)
2038 uart_parse_options(options, &baud, &parity, &bits, &flow);
2039
501b825d 2040 /* TODO: disable clock */
ab7cfb55 2041 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2042}
2043
2044static struct console serial_console = {
2045 .name = "ttySC",
906b17dc 2046 .device = uart_console_device,
1da177e4
LT		 2047 .write = serial_console_write,
2048 .setup = serial_console_setup,
fa5da2f7 2049 .flags = CON_PRINTBUFFER,
1da177e4 2050 .index = -1,
906b17dc 2051 .data = &sci_uart_driver,
1da177e4
LT		 2052};
2053
7b6fd3bf
MD		 2054static struct console early_serial_console = {
2055 .name = "early_ttySC",
2056 .write = serial_console_write,
2057 .flags = CON_PRINTBUFFER,
906b17dc 2058 .index = -1,
7b6fd3bf 2059};
ecdf8a46 2060
7b6fd3bf
MD		 2061static char early_serial_buf[32];
2062
ecdf8a46
PM		 2063static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2064{
2065 struct plat_sci_port *cfg = pdev->dev.platform_data;
2066
2067 if (early_serial_console.data)
2068 return -EEXIST;
2069
2070 early_serial_console.index = pdev->id;
ecdf8a46 2071
906b17dc 2072 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2073
2074 serial_console_setup(&early_serial_console, early_serial_buf);
2075
2076 if (!strstr(early_serial_buf, "keep"))
2077 early_serial_console.flags |= CON_BOOT;
2078
2079 register_console(&early_serial_console);
2080 return 0;
2081}
6a8c9799
NI		 2082
2083#define SCI_CONSOLE (&serial_console)
2084
ecdf8a46
PM		 2085#else
2086static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2087{
2088 return -EINVAL;
2089}
1da177e4 2090
6a8c9799
NI		 2091#define SCI_CONSOLE NULL
2092
2093#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2094
2095static char banner[] __initdata =
2096 KERN_INFO "SuperH SCI(F) driver initialized\n";
2097
2098static struct uart_driver sci_uart_driver = {
2099 .owner = THIS_MODULE,
2100 .driver_name = "sci",
1da177e4
LT		 2101 .dev_name = "ttySC",
2102 .major = SCI_MAJOR,
2103 .minor = SCI_MINOR_START,
e108b2ca 2104 .nr = SCI_NPORTS,
1da177e4
LT		 2105 .cons = SCI_CONSOLE,
2106};
2107
54507f6e 2108static int sci_remove(struct platform_device *dev)
e552de24 2109{
d535a230 2110 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2111
d535a230
PM		 2112 cpufreq_unregister_notifier(&port->freq_transition,
2113 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2114
d535a230
PM		 2115 uart_remove_one_port(&sci_uart_driver, &port->port);
2116
2117 clk_put(port->iclk);
2118 clk_put(port->fclk);
e552de24 2119
5e50d2d6 2120 pm_runtime_disable(&dev->dev);
e552de24
MD		 2121 return 0;
2122}
2123
0ee70712
MD		 2124static int __devinit sci_probe_single(struct platform_device *dev,
2125 unsigned int index,
2126 struct plat_sci_port *p,
2127 struct sci_port *sciport)
2128{
0ee70712
MD		 2129 int ret;
2130
2131 /* Sanity check */
2132 if (unlikely(index >= SCI_NPORTS)) {
2133 dev_notice(&dev->dev, "Attempting to register port "
2134 "%d when only %d are available.\n",
2135 index+1, SCI_NPORTS);
2136 dev_notice(&dev->dev, "Consider bumping "
2137 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2138 return 0;
2139 }
2140
c7ed1ab3
PM		 2141 ret = sci_init_single(dev, sciport, index, p);
2142 if (ret)
2143 return ret;
0ee70712 2144
d535a230 2145 return uart_add_one_port(&sci_uart_driver, &sciport->port);
0ee70712
MD		 2146}
2147
e108b2ca 2148static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2149{
e108b2ca 2150 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2151 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2152 int ret;
d535a230 2153
ecdf8a46
PM		 2154 /*
2155 * If we've come here via earlyprintk initialization, head off to
2156 * the special early probe. We don't have sufficient device state
2157 * to make it beyond this yet.
2158 */
2159 if (is_early_platform_device(dev))
2160 return sci_probe_earlyprintk(dev);
7b6fd3bf 2161
d535a230 2162 platform_set_drvdata(dev, sp);
e552de24 2163
906b17dc 2164 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230
PM		 2165 if (ret)
2166 goto err_unreg;
e552de24 2167
d535a230 2168 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2169
d535a230
PM		 2170 ret = cpufreq_register_notifier(&sp->freq_transition,
2171 CPUFREQ_TRANSITION_NOTIFIER);
2172 if (unlikely(ret < 0))
2173 goto err_unreg;
1da177e4
LT		 2174
2175#ifdef CONFIG_SH_STANDARD_BIOS
2176 sh_bios_gdb_detach();
2177#endif
2178
e108b2ca 2179 return 0;
7ff731ae
PM		 2180
2181err_unreg:
e552de24 2182 sci_remove(dev);
7ff731ae 2183 return ret;
1da177e4
LT		 2184}
2185
6daa79b3 2186static int sci_suspend(struct device *dev)
1da177e4 2187{
d535a230 2188 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2189
d535a230
PM		 2190 if (sport)
2191 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2192
e108b2ca
PM		 2193 return 0;
2194}
1da177e4 2195
6daa79b3 2196static int sci_resume(struct device *dev)
e108b2ca 2197{
d535a230 2198 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2199
d535a230
PM		 2200 if (sport)
2201 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2202
2203 return 0;
2204}
2205
47145210 2206static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2207 .suspend = sci_suspend,
2208 .resume = sci_resume,
2209};
2210
e108b2ca
PM		 2211static struct platform_driver sci_driver = {
2212 .probe = sci_probe,
b9e39c89 2213 .remove = sci_remove,
e108b2ca
PM		 2214 .driver = {
2215 .name = "sh-sci",
2216 .owner = THIS_MODULE,
6daa79b3 2217 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2218 },
2219};
2220
2221static int __init sci_init(void)
2222{
2223 int ret;
2224
2225 printk(banner);
2226
e108b2ca
PM		 2227 ret = uart_register_driver(&sci_uart_driver);
2228 if (likely(ret == 0)) {
2229 ret = platform_driver_register(&sci_driver);
2230 if (unlikely(ret))
2231 uart_unregister_driver(&sci_uart_driver);
2232 }
2233
2234 return ret;
2235}
2236
2237static void __exit sci_exit(void)
2238{
2239 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2240 uart_unregister_driver(&sci_uart_driver);
2241}
2242
7b6fd3bf
MD		 2243#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2244early_platform_init_buffer("earlyprintk", &sci_driver,
2245 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2246#endif
1da177e4
LT		 2247module_init(sci_init);
2248module_exit(sci_exit);
2249
e108b2ca 2250MODULE_LICENSE("GPL");
e169c139 2251MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2252MODULE_AUTHOR("Paul Mundt");
2253MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux kernel - Deliverables
This page took 2.007303 seconds and 5 git commands to generate.