projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sh: Wire up kcmp syscall.
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
4dc4c516 28#include <linux/sh_dma.h>
1da177e4
LT		 29#include <linux/timer.h>
30#include <linux/interrupt.h>
31#include <linux/tty.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/sysrq.h>
1da177e4
LT		 37#include <linux/ioport.h>
38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/console.h>
e108b2ca 42#include <linux/platform_device.h>
96de1a8f 43#include <linux/serial_sci.h>
1da177e4 44#include <linux/notifier.h>
5e50d2d6 45#include <linux/pm_runtime.h>
1da177e4 46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
73a19e4c 50#include <linux/dmaengine.h>
5beabc7f 51#include <linux/dma-mapping.h>
73a19e4c 52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
50f0959a 54#include <linux/gpio.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
e108b2ca
PM		 62struct sci_port {
63 struct uart_port port;
64
ce6738b6
PM		 65 /* Platform configuration */
66 struct plat_sci_port *cfg;
e108b2ca 67
e108b2ca
PM		 68 /* Break timer */
69 struct timer_list break_timer;
70 int break_flag;
1534a3b3 71
501b825d
MD		 72 /* Interface clock */
73 struct clk *iclk;
c7ed1ab3
PM		 74 /* Function clock */
75 struct clk *fclk;
edad1f20 76
9174fc8f 77 char *irqstr[SCIx_NR_IRQS];
50f0959a 78 char *gpiostr[SCIx_NR_FNS];
9174fc8f 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
1ba76220
MD		 102
103#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
104 unsigned short saved_smr;
105 unsigned short saved_fcr;
106 unsigned char saved_brr;
107#endif
e108b2ca
PM		 108};
109
1da177e4 110/* Function prototypes */
d535a230 111static void sci_start_tx(struct uart_port *port);
b129a8cc 112static void sci_stop_tx(struct uart_port *port);
d535a230 113static void sci_start_rx(struct uart_port *port);
1da177e4 114
e108b2ca 115#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 116
e108b2ca
PM		 117static struct sci_port sci_ports[SCI_NPORTS];
118static struct uart_driver sci_uart_driver;
1da177e4 119
e7c98dc7
MT		 120static inline struct sci_port *
121to_sci_port(struct uart_port *uart)
122{
123 return container_of(uart, struct sci_port, port);
124}
125
61a6976b
PM		 126struct plat_sci_reg {
127 u8 offset, size;
128};
129
130/* Helper for invalidating specific entries of an inherited map. */
131#define sci_reg_invalid { .offset = 0, .size = 0 }
132
133static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
134 [SCIx_PROBE_REGTYPE] = {
135 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
136 },
137
138 /*
139 * Common SCI definitions, dependent on the port's regshift
140 * value.
141 */
142 [SCIx_SCI_REGTYPE] = {
143 [SCSMR] = { 0x00, 8 },
144 [SCBRR] = { 0x01, 8 },
145 [SCSCR] = { 0x02, 8 },
146 [SCxTDR] = { 0x03, 8 },
147 [SCxSR] = { 0x04, 8 },
148 [SCxRDR] = { 0x05, 8 },
149 [SCFCR] = sci_reg_invalid,
150 [SCFDR] = sci_reg_invalid,
151 [SCTFDR] = sci_reg_invalid,
152 [SCRFDR] = sci_reg_invalid,
153 [SCSPTR] = sci_reg_invalid,
154 [SCLSR] = sci_reg_invalid,
155 },
156
157 /*
158 * Common definitions for legacy IrDA ports, dependent on
159 * regshift value.
160 */
161 [SCIx_IRDA_REGTYPE] = {
162 [SCSMR] = { 0x00, 8 },
163 [SCBRR] = { 0x01, 8 },
164 [SCSCR] = { 0x02, 8 },
165 [SCxTDR] = { 0x03, 8 },
166 [SCxSR] = { 0x04, 8 },
167 [SCxRDR] = { 0x05, 8 },
168 [SCFCR] = { 0x06, 8 },
169 [SCFDR] = { 0x07, 16 },
170 [SCTFDR] = sci_reg_invalid,
171 [SCRFDR] = sci_reg_invalid,
172 [SCSPTR] = sci_reg_invalid,
173 [SCLSR] = sci_reg_invalid,
174 },
175
176 /*
177 * Common SCIFA definitions.
178 */
179 [SCIx_SCIFA_REGTYPE] = {
180 [SCSMR] = { 0x00, 16 },
181 [SCBRR] = { 0x04, 8 },
182 [SCSCR] = { 0x08, 16 },
183 [SCxTDR] = { 0x20, 8 },
184 [SCxSR] = { 0x14, 16 },
185 [SCxRDR] = { 0x24, 8 },
186 [SCFCR] = { 0x18, 16 },
187 [SCFDR] = { 0x1c, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
192 },
193
194 /*
195 * Common SCIFB definitions.
196 */
197 [SCIx_SCIFB_REGTYPE] = {
198 [SCSMR] = { 0x00, 16 },
199 [SCBRR] = { 0x04, 8 },
200 [SCSCR] = { 0x08, 16 },
201 [SCxTDR] = { 0x40, 8 },
202 [SCxSR] = { 0x14, 16 },
203 [SCxRDR] = { 0x60, 8 },
204 [SCFCR] = { 0x18, 16 },
205 [SCFDR] = { 0x1c, 16 },
206 [SCTFDR] = sci_reg_invalid,
207 [SCRFDR] = sci_reg_invalid,
208 [SCSPTR] = sci_reg_invalid,
209 [SCLSR] = sci_reg_invalid,
210 },
211
3af1f8a4
PE		 212 /*
213 * Common SH-2(A) SCIF definitions for ports with FIFO data
214 * count registers.
215 */
216 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
217 [SCSMR] = { 0x00, 16 },
218 [SCBRR] = { 0x04, 8 },
219 [SCSCR] = { 0x08, 16 },
220 [SCxTDR] = { 0x0c, 8 },
221 [SCxSR] = { 0x10, 16 },
222 [SCxRDR] = { 0x14, 8 },
223 [SCFCR] = { 0x18, 16 },
224 [SCFDR] = { 0x1c, 16 },
225 [SCTFDR] = sci_reg_invalid,
226 [SCRFDR] = sci_reg_invalid,
227 [SCSPTR] = { 0x20, 16 },
228 [SCLSR] = { 0x24, 16 },
229 },
230
61a6976b
PM		 231 /*
232 * Common SH-3 SCIF definitions.
233 */
234 [SCIx_SH3_SCIF_REGTYPE] = {
235 [SCSMR] = { 0x00, 8 },
236 [SCBRR] = { 0x02, 8 },
237 [SCSCR] = { 0x04, 8 },
238 [SCxTDR] = { 0x06, 8 },
239 [SCxSR] = { 0x08, 16 },
240 [SCxRDR] = { 0x0a, 8 },
241 [SCFCR] = { 0x0c, 8 },
242 [SCFDR] = { 0x0e, 16 },
243 [SCTFDR] = sci_reg_invalid,
244 [SCRFDR] = sci_reg_invalid,
245 [SCSPTR] = sci_reg_invalid,
246 [SCLSR] = sci_reg_invalid,
247 },
248
249 /*
250 * Common SH-4(A) SCIF(B) definitions.
251 */
252 [SCIx_SH4_SCIF_REGTYPE] = {
253 [SCSMR] = { 0x00, 16 },
254 [SCBRR] = { 0x04, 8 },
255 [SCSCR] = { 0x08, 16 },
256 [SCxTDR] = { 0x0c, 8 },
257 [SCxSR] = { 0x10, 16 },
258 [SCxRDR] = { 0x14, 8 },
259 [SCFCR] = { 0x18, 16 },
260 [SCFDR] = { 0x1c, 16 },
261 [SCTFDR] = sci_reg_invalid,
262 [SCRFDR] = sci_reg_invalid,
263 [SCSPTR] = { 0x20, 16 },
264 [SCLSR] = { 0x24, 16 },
265 },
266
267 /*
268 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
269 * register.
270 */
271 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCTFDR] = sci_reg_invalid,
281 [SCRFDR] = sci_reg_invalid,
282 [SCSPTR] = sci_reg_invalid,
283 [SCLSR] = { 0x24, 16 },
284 },
285
286 /*
287 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
288 * count registers.
289 */
290 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
291 [SCSMR] = { 0x00, 16 },
292 [SCBRR] = { 0x04, 8 },
293 [SCSCR] = { 0x08, 16 },
294 [SCxTDR] = { 0x0c, 8 },
295 [SCxSR] = { 0x10, 16 },
296 [SCxRDR] = { 0x14, 8 },
297 [SCFCR] = { 0x18, 16 },
298 [SCFDR] = { 0x1c, 16 },
299 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
300 [SCRFDR] = { 0x20, 16 },
301 [SCSPTR] = { 0x24, 16 },
302 [SCLSR] = { 0x28, 16 },
303 },
304
305 /*
306 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
307 * registers.
308 */
309 [SCIx_SH7705_SCIF_REGTYPE] = {
310 [SCSMR] = { 0x00, 16 },
311 [SCBRR] = { 0x04, 8 },
312 [SCSCR] = { 0x08, 16 },
313 [SCxTDR] = { 0x20, 8 },
314 [SCxSR] = { 0x14, 16 },
315 [SCxRDR] = { 0x24, 8 },
316 [SCFCR] = { 0x18, 16 },
317 [SCFDR] = { 0x1c, 16 },
318 [SCTFDR] = sci_reg_invalid,
319 [SCRFDR] = sci_reg_invalid,
320 [SCSPTR] = sci_reg_invalid,
321 [SCLSR] = sci_reg_invalid,
322 },
323};
324
72b294cf
PM		 325#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
326
61a6976b
PM		 327/*
328 * The "offset" here is rather misleading, in that it refers to an enum
329 * value relative to the port mapping rather than the fixed offset
330 * itself, which needs to be manually retrieved from the platform's
331 * register map for the given port.
332 */
333static unsigned int sci_serial_in(struct uart_port *p, int offset)
334{
72b294cf 335 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 336
337 if (reg->size == 8)
338 return ioread8(p->membase + (reg->offset << p->regshift));
339 else if (reg->size == 16)
340 return ioread16(p->membase + (reg->offset << p->regshift));
341 else
342 WARN(1, "Invalid register access\n");
343
344 return 0;
345}
346
347static void sci_serial_out(struct uart_port *p, int offset, int value)
348{
72b294cf 349 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 350
351 if (reg->size == 8)
352 iowrite8(value, p->membase + (reg->offset << p->regshift));
353 else if (reg->size == 16)
354 iowrite16(value, p->membase + (reg->offset << p->regshift));
355 else
356 WARN(1, "Invalid register access\n");
357}
358
61a6976b
PM		 359static int sci_probe_regmap(struct plat_sci_port *cfg)
360{
361 switch (cfg->type) {
362 case PORT_SCI:
363 cfg->regtype = SCIx_SCI_REGTYPE;
364 break;
365 case PORT_IRDA:
366 cfg->regtype = SCIx_IRDA_REGTYPE;
367 break;
368 case PORT_SCIFA:
369 cfg->regtype = SCIx_SCIFA_REGTYPE;
370 break;
371 case PORT_SCIFB:
372 cfg->regtype = SCIx_SCIFB_REGTYPE;
373 break;
374 case PORT_SCIF:
375 /*
376 * The SH-4 is a bit of a misnomer here, although that's
377 * where this particular port layout originated. This
378 * configuration (or some slight variation thereof)
379 * remains the dominant model for all SCIFs.
380 */
381 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
382 break;
383 default:
384 printk(KERN_ERR "Can't probe register map for given port\n");
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
23241d43
PM		 391static void sci_port_enable(struct sci_port *sci_port)
392{
393 if (!sci_port->port.dev)
394 return;
395
396 pm_runtime_get_sync(sci_port->port.dev);
397
398 clk_enable(sci_port->iclk);
399 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
400 clk_enable(sci_port->fclk);
401}
402
403static void sci_port_disable(struct sci_port *sci_port)
404{
405 if (!sci_port->port.dev)
406 return;
407
408 clk_disable(sci_port->fclk);
409 clk_disable(sci_port->iclk);
410
411 pm_runtime_put_sync(sci_port->port.dev);
412}
413
07d2a1a1 414#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 415
416#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 417static int sci_poll_get_char(struct uart_port *port)
1da177e4 418{
1da177e4
LT		 419 unsigned short status;
420 int c;
421
e108b2ca 422 do {
b12bb29f 423 status = serial_port_in(port, SCxSR);
1da177e4 424 if (status & SCxSR_ERRORS(port)) {
b12bb29f 425 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 426 continue;
427 }
3f255eb3
JW		 428 break;
429 } while (1);
430
431 if (!(status & SCxSR_RDxF(port)))
432 return NO_POLL_CHAR;
07d2a1a1 433
b12bb29f 434 c = serial_port_in(port, SCxRDR);
07d2a1a1 435
e7c98dc7 436 /* Dummy read */
b12bb29f
PM		 437 serial_port_in(port, SCxSR);
438 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 439
440 return c;
441}
1f6fd5c9 442#endif
1da177e4 443
07d2a1a1 444static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 445{
1da177e4
LT		 446 unsigned short status;
447
1da177e4 448 do {
b12bb29f 449 status = serial_port_in(port, SCxSR);
1da177e4
LT		 450 } while (!(status & SCxSR_TDxE(port)));
451
b12bb29f
PM		 452 serial_port_out(port, SCxTDR, c);
453 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 454}
07d2a1a1 455#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 456
61a6976b 457static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 458{
61a6976b
PM		 459 struct sci_port *s = to_sci_port(port);
460 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 461
61a6976b
PM		 462 /*
463 * Use port-specific handler if provided.
464 */
465 if (s->cfg->ops && s->cfg->ops->init_pins) {
466 s->cfg->ops->init_pins(port, cflag);
467 return;
1da177e4 468 }
41504c39 469
61a6976b
PM		 470 /*
471 * For the generic path SCSPTR is necessary. Bail out if that's
472 * unavailable, too.
473 */
474 if (!reg->size)
475 return;
41504c39 476
faf02f8f
PM		 477 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
478 ((!(cflag & CRTSCTS)))) {
479 unsigned short status;
480
b12bb29f 481 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 482 status &= ~SCSPTR_CTSIO;
483 status |= SCSPTR_RTSIO;
b12bb29f 484 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 485 }
d5701647 486}
e108b2ca 487
72b294cf 488static int sci_txfill(struct uart_port *port)
e108b2ca 489{
72b294cf 490 struct plat_sci_reg *reg;
e108b2ca 491
72b294cf
PM		 492 reg = sci_getreg(port, SCTFDR);
493 if (reg->size)
b12bb29f 494 return serial_port_in(port, SCTFDR) & 0xff;
c63847a3 495
72b294cf
PM		 496 reg = sci_getreg(port, SCFDR);
497 if (reg->size)
b12bb29f 498 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 499
b12bb29f 500 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 501}
502
73a19e4c
GL		 503static int sci_txroom(struct uart_port *port)
504{
72b294cf 505 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 506}
507
508static int sci_rxfill(struct uart_port *port)
e108b2ca 509{
72b294cf
PM		 510 struct plat_sci_reg *reg;
511
512 reg = sci_getreg(port, SCRFDR);
513 if (reg->size)
b12bb29f 514 return serial_port_in(port, SCRFDR) & 0xff;
72b294cf
PM		 515
516 reg = sci_getreg(port, SCFDR);
517 if (reg->size)
b12bb29f 518 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 519
b12bb29f 520 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 521}
522
514820eb
PM		 523/*
524 * SCI helper for checking the state of the muxed port/RXD pins.
525 */
526static inline int sci_rxd_in(struct uart_port *port)
527{
528 struct sci_port *s = to_sci_port(port);
529
530 if (s->cfg->port_reg <= 0)
531 return 1;
532
533 return !!__raw_readb(s->cfg->port_reg);
534}
535
1da177e4
LT		 536/* ********************************************************************** *
537 * the interrupt related routines *
538 * ********************************************************************** */
539
540static void sci_transmit_chars(struct uart_port *port)
541{
ebd2c8f6 542 struct circ_buf *xmit = &port->state->xmit;
1da177e4 543 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 544 unsigned short status;
545 unsigned short ctrl;
e108b2ca 546 int count;
1da177e4 547
b12bb29f 548 status = serial_port_in(port, SCxSR);
1da177e4 549 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 550 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 551 if (uart_circ_empty(xmit))
8e698614 552 ctrl &= ~SCSCR_TIE;
e7c98dc7 553 else
8e698614 554 ctrl |= SCSCR_TIE;
b12bb29f 555 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 556 return;
557 }
558
72b294cf 559 count = sci_txroom(port);
1da177e4
LT		 560
561 do {
562 unsigned char c;
563
564 if (port->x_char) {
565 c = port->x_char;
566 port->x_char = 0;
567 } else if (!uart_circ_empty(xmit) && !stopped) {
568 c = xmit->buf[xmit->tail];
569 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
570 } else {
571 break;
572 }
573
b12bb29f 574 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 575
576 port->icount.tx++;
577 } while (--count > 0);
578
b12bb29f 579 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 580
581 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
582 uart_write_wakeup(port);
583 if (uart_circ_empty(xmit)) {
b129a8cc 584 sci_stop_tx(port);
1da177e4 585 } else {
b12bb29f 586 ctrl = serial_port_in(port, SCSCR);
1da177e4 587
1a22f08d 588 if (port->type != PORT_SCI) {
b12bb29f
PM		 589 serial_port_in(port, SCxSR); /* Dummy read */
590 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 591 }
1da177e4 592
8e698614 593 ctrl |= SCSCR_TIE;
b12bb29f 594 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 595 }
596}
597
598/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 599#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 600
94c8b6db 601static void sci_receive_chars(struct uart_port *port)
1da177e4 602{
e7c98dc7 603 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 604 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 605 int i, count, copied = 0;
606 unsigned short status;
33f0f88f 607 unsigned char flag;
1da177e4 608
b12bb29f 609 status = serial_port_in(port, SCxSR);
1da177e4
LT		 610 if (!(status & SCxSR_RDxF(port)))
611 return;
612
613 while (1) {
1da177e4 614 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 615 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 616
617 /* If for any reason we can't copy more data, we're done! */
618 if (count == 0)
619 break;
620
621 if (port->type == PORT_SCI) {
b12bb29f 622 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 623 if (uart_handle_sysrq_char(port, c) ||
624 sci_port->break_flag)
1da177e4 625 count = 0;
e7c98dc7 626 else
e108b2ca 627 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 628 } else {
e7c98dc7 629 for (i = 0; i < count; i++) {
b12bb29f 630 char c = serial_port_in(port, SCxRDR);
d97fbbed 631
b12bb29f 632 status = serial_port_in(port, SCxSR);
1da177e4
LT		 633#if defined(CONFIG_CPU_SH3)
634 /* Skip "chars" during break */
e108b2ca 635 if (sci_port->break_flag) {
1da177e4
LT		 636 if ((c == 0) &&
637 (status & SCxSR_FER(port))) {
638 count--; i--;
639 continue;
640 }
e108b2ca 641
1da177e4 642 /* Nonzero => end-of-break */
762c69e3 643 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 644 sci_port->break_flag = 0;
645
1da177e4
LT		 646 if (STEPFN(c)) {
647 count--; i--;
648 continue;
649 }
650 }
651#endif /* CONFIG_CPU_SH3 */
7d12e780 652 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 653 count--; i--;
654 continue;
655 }
656
657 /* Store data and status */
73a19e4c 658 if (status & SCxSR_FER(port)) {
33f0f88f 659 flag = TTY_FRAME;
d97fbbed 660 port->icount.frame++;
762c69e3 661 dev_notice(port->dev, "frame error\n");
73a19e4c 662 } else if (status & SCxSR_PER(port)) {
33f0f88f 663 flag = TTY_PARITY;
d97fbbed 664 port->icount.parity++;
762c69e3 665 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 666 } else
667 flag = TTY_NORMAL;
762c69e3 668
33f0f88f 669 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 670 }
671 }
672
b12bb29f
PM		 673 serial_port_in(port, SCxSR); /* dummy read */
674 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 675
1da177e4
LT		 676 copied += count;
677 port->icount.rx += count;
678 }
679
680 if (copied) {
681 /* Tell the rest of the system the news. New characters! */
682 tty_flip_buffer_push(tty);
683 } else {
b12bb29f
PM		 684 serial_port_in(port, SCxSR); /* dummy read */
685 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 686 }
687}
688
689#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 690
691/*
692 * The sci generates interrupts during the break,
1da177e4
LT		 693 * 1 per millisecond or so during the break period, for 9600 baud.
694 * So dont bother disabling interrupts.
695 * But dont want more than 1 break event.
696 * Use a kernel timer to periodically poll the rx line until
697 * the break is finished.
698 */
94c8b6db 699static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 700{
bc9b3f5c 701 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 702}
94c8b6db 703
1da177e4
LT		 704/* Ensure that two consecutive samples find the break over. */
705static void sci_break_timer(unsigned long data)
706{
e108b2ca
PM		 707 struct sci_port *port = (struct sci_port *)data;
708
23241d43 709 sci_port_enable(port);
5e50d2d6 710
e108b2ca 711 if (sci_rxd_in(&port->port) == 0) {
1da177e4 712 port->break_flag = 1;
e108b2ca
PM		 713 sci_schedule_break_timer(port);
714 } else if (port->break_flag == 1) {
1da177e4
LT		 715 /* break is over. */
716 port->break_flag = 2;
e108b2ca
PM		 717 sci_schedule_break_timer(port);
718 } else
719 port->break_flag = 0;
5e50d2d6 720
23241d43 721 sci_port_disable(port);
1da177e4
LT		 722}
723
94c8b6db 724static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 725{
726 int copied = 0;
b12bb29f 727 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 728 struct tty_struct *tty = port->state->port.tty;
debf9507 729 struct sci_port *s = to_sci_port(port);
1da177e4 730
debf9507
PM		 731 /*
732 * Handle overruns, if supported.
733 */
734 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
735 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 736 port->icount.overrun++;
737
debf9507
PM		 738 /* overrun error */
739 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
740 copied++;
762c69e3 741
debf9507
PM		 742 dev_notice(port->dev, "overrun error");
743 }
1da177e4
LT		 744 }
745
e108b2ca 746 if (status & SCxSR_FER(port)) {
1da177e4
LT		 747 if (sci_rxd_in(port) == 0) {
748 /* Notify of BREAK */
e7c98dc7 749 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 750
751 if (!sci_port->break_flag) {
d97fbbed
PM		 752 port->icount.brk++;
753
e108b2ca
PM		 754 sci_port->break_flag = 1;
755 sci_schedule_break_timer(sci_port);
756
1da177e4 757 /* Do sysrq handling. */
e108b2ca 758 if (uart_handle_break(port))
1da177e4 759 return 0;
762c69e3
PM		 760
761 dev_dbg(port->dev, "BREAK detected\n");
762
e108b2ca 763 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 764 copied++;
765 }
766
e108b2ca 767 } else {
1da177e4 768 /* frame error */
d97fbbed
PM		 769 port->icount.frame++;
770
e108b2ca 771 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 772 copied++;
762c69e3
PM		 773
774 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 775 }
776 }
777
e108b2ca 778 if (status & SCxSR_PER(port)) {
1da177e4 779 /* parity error */
d97fbbed
PM		 780 port->icount.parity++;
781
e108b2ca
PM		 782 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
783 copied++;
762c69e3
PM		 784
785 dev_notice(port->dev, "parity error");
1da177e4
LT		 786 }
787
33f0f88f 788 if (copied)
1da177e4 789 tty_flip_buffer_push(tty);
1da177e4
LT		 790
791 return copied;
792}
793
94c8b6db 794static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 795{
ebd2c8f6 796 struct tty_struct *tty = port->state->port.tty;
debf9507 797 struct sci_port *s = to_sci_port(port);
4b8c59a3 798 struct plat_sci_reg *reg;
d830fa45
PM		 799 int copied = 0;
800
4b8c59a3
PM		 801 reg = sci_getreg(port, SCLSR);
802 if (!reg->size)
d830fa45
PM		 803 return 0;
804
b12bb29f
PM		 805 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
806 serial_port_out(port, SCLSR, 0);
d830fa45 807
d97fbbed
PM		 808 port->icount.overrun++;
809
d830fa45
PM		 810 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
811 tty_flip_buffer_push(tty);
812
813 dev_notice(port->dev, "overrun error\n");
814 copied++;
815 }
816
817 return copied;
818}
819
94c8b6db 820static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 821{
822 int copied = 0;
b12bb29f 823 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 824 struct tty_struct *tty = port->state->port.tty;
a5660ada 825 struct sci_port *s = to_sci_port(port);
1da177e4 826
0b3d4ef6
PM		 827 if (uart_handle_break(port))
828 return 0;
829
b7a76e4b 830 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 831#if defined(CONFIG_CPU_SH3)
832 /* Debounce break */
833 s->break_flag = 1;
834#endif
d97fbbed
PM		 835
836 port->icount.brk++;
837
1da177e4 838 /* Notify of BREAK */
e108b2ca 839 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 840 copied++;
762c69e3
PM		 841
842 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 843 }
844
33f0f88f 845 if (copied)
1da177e4 846 tty_flip_buffer_push(tty);
e108b2ca 847
d830fa45
PM		 848 copied += sci_handle_fifo_overrun(port);
849
1da177e4
LT		 850 return copied;
851}
852
73a19e4c 853static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 854{
73a19e4c
GL		 855#ifdef CONFIG_SERIAL_SH_SCI_DMA
856 struct uart_port *port = ptr;
857 struct sci_port *s = to_sci_port(port);
858
859 if (s->chan_rx) {
b12bb29f
PM		 860 u16 scr = serial_port_in(port, SCSCR);
861 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 862
863 /* Disable future Rx interrupts */
d1d4b10c 864 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 865 disable_irq_nosync(irq);
866 scr |= 0x4000;
867 } else {
f43dc23d 868 scr &= ~SCSCR_RIE;
3089f381 869 }
b12bb29f 870 serial_port_out(port, SCSCR, scr);
73a19e4c 871 /* Clear current interrupt */
b12bb29f 872 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 873 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
874 jiffies, s->rx_timeout);
875 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 876
877 return IRQ_HANDLED;
878 }
879#endif
880
1da177e4
LT		 881 /* I think sci_receive_chars has to be called irrespective
882 * of whether the I_IXOFF is set, otherwise, how is the interrupt
883 * to be disabled?
884 */
73a19e4c 885 sci_receive_chars(ptr);
1da177e4
LT		 886
887 return IRQ_HANDLED;
888}
889
7d12e780 890static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 891{
892 struct uart_port *port = ptr;
fd78a76a 893 unsigned long flags;
1da177e4 894
fd78a76a 895 spin_lock_irqsave(&port->lock, flags);
1da177e4 896 sci_transmit_chars(port);
fd78a76a 897 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 898
899 return IRQ_HANDLED;
900}
901
7d12e780 902static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 903{
904 struct uart_port *port = ptr;
905
906 /* Handle errors */
907 if (port->type == PORT_SCI) {
908 if (sci_handle_errors(port)) {
909 /* discard character in rx buffer */
b12bb29f
PM		 910 serial_port_in(port, SCxSR);
911 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 912 }
913 } else {
d830fa45 914 sci_handle_fifo_overrun(port);
7d12e780 915 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 916 }
917
b12bb29f 918 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 919
920 /* Kick the transmission */
7d12e780 921 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 922
923 return IRQ_HANDLED;
924}
925
7d12e780 926static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 927{
928 struct uart_port *port = ptr;
929
930 /* Handle BREAKs */
931 sci_handle_breaks(port);
b12bb29f 932 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 933
934 return IRQ_HANDLED;
935}
936
f43dc23d
PM		 937static inline unsigned long port_rx_irq_mask(struct uart_port *port)
938{
939 /*
940 * Not all ports (such as SCIFA) will support REIE. Rather than
941 * special-casing the port type, we check the port initialization
942 * IRQ enable mask to see whether the IRQ is desired at all. If
943 * it's unset, it's logically inferred that there's no point in
944 * testing for it.
945 */
ce6738b6 946 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 947}
948
7d12e780 949static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 950{
44e18e9e 951 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 952 struct uart_port *port = ptr;
73a19e4c 953 struct sci_port *s = to_sci_port(port);
a8884e34 954 irqreturn_t ret = IRQ_NONE;
1da177e4 955
b12bb29f
PM		 956 ssr_status = serial_port_in(port, SCxSR);
957 scr_status = serial_port_in(port, SCSCR);
f43dc23d 958 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 959
960 /* Tx Interrupt */
f43dc23d 961 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 962 !s->chan_tx)
a8884e34 963 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 964
73a19e4c
GL		 965 /*
966 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
967 * DR flags
968 */
969 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 970 (scr_status & SCSCR_RIE))
a8884e34 971 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 972
1da177e4 973 /* Error Interrupt */
dd4da3a5 974 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 975 ret = sci_er_interrupt(irq, ptr);
f43dc23d 976
1da177e4 977 /* Break Interrupt */
dd4da3a5 978 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 979 ret = sci_br_interrupt(irq, ptr);
1da177e4 980
a8884e34 981 return ret;
1da177e4
LT		 982}
983
1da177e4 984/*
25985edc 985 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 986 * ports' baud rate when the peripheral clock changes.
987 */
e108b2ca
PM		 988static int sci_notifier(struct notifier_block *self,
989 unsigned long phase, void *p)
1da177e4 990{
e552de24
MD		 991 struct sci_port *sci_port;
992 unsigned long flags;
1da177e4 993
d535a230
PM		 994 sci_port = container_of(self, struct sci_port, freq_transition);
995
1da177e4 996 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 997 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 998 struct uart_port *port = &sci_port->port;
073e84c9 999
d535a230
PM		 1000 spin_lock_irqsave(&port->lock, flags);
1001 port->uartclk = clk_get_rate(sci_port->iclk);
1002 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1003 }
1da177e4 1004
1da177e4
LT		 1005 return NOTIFY_OK;
1006}
501b825d 1007
9174fc8f
PM		 1008static struct sci_irq_desc {
1009 const char *desc;
1010 irq_handler_t handler;
1011} sci_irq_desc[] = {
1012 /*
1013 * Split out handlers, the default case.
1014 */
1015 [SCIx_ERI_IRQ] = {
1016 .desc = "rx err",
1017 .handler = sci_er_interrupt,
1018 },
1019
1020 [SCIx_RXI_IRQ] = {
1021 .desc = "rx full",
1022 .handler = sci_rx_interrupt,
1023 },
1024
1025 [SCIx_TXI_IRQ] = {
1026 .desc = "tx empty",
1027 .handler = sci_tx_interrupt,
1028 },
1029
1030 [SCIx_BRI_IRQ] = {
1031 .desc = "break",
1032 .handler = sci_br_interrupt,
1033 },
1034
1035 /*
1036 * Special muxed handler.
1037 */
1038 [SCIx_MUX_IRQ] = {
1039 .desc = "mux",
1040 .handler = sci_mpxed_interrupt,
1041 },
1042};
1043
1da177e4
LT		 1044static int sci_request_irq(struct sci_port *port)
1045{
9174fc8f
PM		 1046 struct uart_port *up = &port->port;
1047 int i, j, ret = 0;
1048
1049 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1050 struct sci_irq_desc *desc;
1051 unsigned int irq;
1052
1053 if (SCIx_IRQ_IS_MUXED(port)) {
1054 i = SCIx_MUX_IRQ;
1055 irq = up->irq;
0e8963de 1056 } else {
9174fc8f
PM		 1057 irq = port->cfg->irqs[i];
1058
0e8963de
PM		 1059 /*
1060 * Certain port types won't support all of the
1061 * available interrupt sources.
1062 */
1063 if (unlikely(!irq))
1064 continue;
1065 }
1066
9174fc8f
PM		 1067 desc = sci_irq_desc + i;
1068 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1069 dev_name(up->dev), desc->desc);
1070 if (!port->irqstr[j]) {
1071 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1072 desc->desc);
1073 goto out_nomem;
1da177e4 1074 }
9174fc8f
PM		 1075
1076 ret = request_irq(irq, desc->handler, up->irqflags,
1077 port->irqstr[j], port);
1078 if (unlikely(ret)) {
1079 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1080 goto out_noirq;
1da177e4
LT		 1081 }
1082 }
1083
1084 return 0;
9174fc8f
PM		 1085
1086out_noirq:
1087 while (--i >= 0)
1088 free_irq(port->cfg->irqs[i], port);
1089
1090out_nomem:
1091 while (--j >= 0)
1092 kfree(port->irqstr[j]);
1093
1094 return ret;
1da177e4
LT		 1095}
1096
1097static void sci_free_irq(struct sci_port *port)
1098{
1099 int i;
1100
9174fc8f
PM		 1101 /*
1102 * Intentionally in reverse order so we iterate over the muxed
1103 * IRQ first.
1104 */
1105 for (i = 0; i < SCIx_NR_IRQS; i++) {
0e8963de
PM		 1106 unsigned int irq = port->cfg->irqs[i];
1107
1108 /*
1109 * Certain port types won't support all of the available
1110 * interrupt sources.
1111 */
1112 if (unlikely(!irq))
1113 continue;
1114
9174fc8f
PM		 1115 free_irq(port->cfg->irqs[i], port);
1116 kfree(port->irqstr[i]);
1da177e4 1117
9174fc8f
PM		 1118 if (SCIx_IRQ_IS_MUXED(port)) {
1119 /* If there's only one IRQ, we're done. */
1120 return;
1da177e4
LT		 1121 }
1122 }
1123}
1124
50f0959a
PM		 1125static const char *sci_gpio_names[SCIx_NR_FNS] = {
1126 "sck", "rxd", "txd", "cts", "rts",
1127};
1128
1129static const char *sci_gpio_str(unsigned int index)
1130{
1131 return sci_gpio_names[index];
1132}
1133
1134static void __devinit sci_init_gpios(struct sci_port *port)
1135{
1136 struct uart_port *up = &port->port;
1137 int i;
1138
1139 if (!port->cfg)
1140 return;
1141
1142 for (i = 0; i < SCIx_NR_FNS; i++) {
1143 const char *desc;
1144 int ret;
1145
1146 if (!port->cfg->gpios[i])
1147 continue;
1148
1149 desc = sci_gpio_str(i);
1150
1151 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1152 dev_name(up->dev), desc);
1153
1154 /*
1155 * If we've failed the allocation, we can still continue
1156 * on with a NULL string.
1157 */
1158 if (!port->gpiostr[i])
1159 dev_notice(up->dev, "%s string allocation failure\n",
1160 desc);
1161
1162 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1163 if (unlikely(ret != 0)) {
1164 dev_notice(up->dev, "failed %s gpio request\n", desc);
1165
1166 /*
1167 * If we can't get the GPIO for whatever reason,
1168 * no point in keeping the verbose string around.
1169 */
1170 kfree(port->gpiostr[i]);
1171 }
1172 }
1173}
1174
1175static void sci_free_gpios(struct sci_port *port)
1176{
1177 int i;
1178
1179 for (i = 0; i < SCIx_NR_FNS; i++)
1180 if (port->cfg->gpios[i]) {
1181 gpio_free(port->cfg->gpios[i]);
1182 kfree(port->gpiostr[i]);
1183 }
1184}
1185
1da177e4
LT		 1186static unsigned int sci_tx_empty(struct uart_port *port)
1187{
b12bb29f 1188 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1189 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1190
1191 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1192}
1193
cdf7c42f
PM		 1194/*
1195 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1196 * CTS/RTS is supported in hardware by at least one port and controlled
1197 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1198 * handled via the ->init_pins() op, which is a bit of a one-way street,
1199 * lacking any ability to defer pin control -- this will later be
1200 * converted over to the GPIO framework).
dc7e3ef7
PM		 1201 *
1202 * Other modes (such as loopback) are supported generically on certain
1203 * port types, but not others. For these it's sufficient to test for the
1204 * existence of the support register and simply ignore the port type.
cdf7c42f 1205 */
1da177e4
LT		 1206static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1207{
dc7e3ef7
PM		 1208 if (mctrl & TIOCM_LOOP) {
1209 struct plat_sci_reg *reg;
1210
1211 /*
1212 * Standard loopback mode for SCFCR ports.
1213 */
1214 reg = sci_getreg(port, SCFCR);
1215 if (reg->size)
b12bb29f 1216 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1217 }
1da177e4
LT		 1218}
1219
1220static unsigned int sci_get_mctrl(struct uart_port *port)
1221{
cdf7c42f
PM		 1222 /*
1223 * CTS/RTS is handled in hardware when supported, while nothing
1224 * else is wired up. Keep it simple and simply assert DSR/CAR.
1225 */
1226 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1227}
1228
73a19e4c
GL		 1229#ifdef CONFIG_SERIAL_SH_SCI_DMA
1230static void sci_dma_tx_complete(void *arg)
1231{
1232 struct sci_port *s = arg;
1233 struct uart_port *port = &s->port;
1234 struct circ_buf *xmit = &port->state->xmit;
1235 unsigned long flags;
1236
1237 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1238
1239 spin_lock_irqsave(&port->lock, flags);
1240
f354a381 1241 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1242 xmit->tail &= UART_XMIT_SIZE - 1;
1243
f354a381 1244 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1245
1246 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1247 s->desc_tx = NULL;
1248
73a19e4c
GL		 1249 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1250 uart_write_wakeup(port);
1251
3089f381 1252 if (!uart_circ_empty(xmit)) {
49d4bcad 1253 s->cookie_tx = 0;
73a19e4c 1254 schedule_work(&s->work_tx);
49d4bcad
YT		 1255 } else {
1256 s->cookie_tx = -EINVAL;
1257 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1258 u16 ctrl = serial_port_in(port, SCSCR);
1259 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1260 }
3089f381
GL		 1261 }
1262
1263 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1264}
1265
1266/* Locking: called with port lock held */
1267static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1268 size_t count)
1269{
1270 struct uart_port *port = &s->port;
1271 int i, active, room;
1272
1273 room = tty_buffer_request_room(tty, count);
1274
1275 if (s->active_rx == s->cookie_rx[0]) {
1276 active = 0;
1277 } else if (s->active_rx == s->cookie_rx[1]) {
1278 active = 1;
1279 } else {
1280 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1281 return 0;
1282 }
1283
1284 if (room < count)
1285 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1286 count - room);
1287 if (!room)
1288 return room;
1289
1290 for (i = 0; i < room; i++)
1291 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1292 TTY_NORMAL);
1293
1294 port->icount.rx += room;
1295
1296 return room;
1297}
1298
1299static void sci_dma_rx_complete(void *arg)
1300{
1301 struct sci_port *s = arg;
1302 struct uart_port *port = &s->port;
1303 struct tty_struct *tty = port->state->port.tty;
1304 unsigned long flags;
1305 int count;
1306
3089f381 1307 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1308
1309 spin_lock_irqsave(&port->lock, flags);
1310
1311 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1312
3089f381 1313 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1314
1315 spin_unlock_irqrestore(&port->lock, flags);
1316
1317 if (count)
1318 tty_flip_buffer_push(tty);
1319
1320 schedule_work(&s->work_rx);
1321}
1322
73a19e4c
GL		 1323static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1324{
1325 struct dma_chan *chan = s->chan_rx;
1326 struct uart_port *port = &s->port;
73a19e4c
GL		 1327
1328 s->chan_rx = NULL;
1329 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1330 dma_release_channel(chan);
85b8e3ff
GL		 1331 if (sg_dma_address(&s->sg_rx[0]))
1332 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1333 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1334 if (enable_pio)
1335 sci_start_rx(port);
1336}
1337
1338static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1339{
1340 struct dma_chan *chan = s->chan_tx;
1341 struct uart_port *port = &s->port;
73a19e4c
GL		 1342
1343 s->chan_tx = NULL;
1344 s->cookie_tx = -EINVAL;
1345 dma_release_channel(chan);
1346 if (enable_pio)
1347 sci_start_tx(port);
1348}
1349
1350static void sci_submit_rx(struct sci_port *s)
1351{
1352 struct dma_chan *chan = s->chan_rx;
1353 int i;
1354
1355 for (i = 0; i < 2; i++) {
1356 struct scatterlist *sg = &s->sg_rx[i];
1357 struct dma_async_tx_descriptor *desc;
1358
16052827 1359 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1360 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1361
1362 if (desc) {
1363 s->desc_rx[i] = desc;
1364 desc->callback = sci_dma_rx_complete;
1365 desc->callback_param = s;
1366 s->cookie_rx[i] = desc->tx_submit(desc);
1367 }
1368
1369 if (!desc || s->cookie_rx[i] < 0) {
1370 if (i) {
1371 async_tx_ack(s->desc_rx[0]);
1372 s->cookie_rx[0] = -EINVAL;
1373 }
1374 if (desc) {
1375 async_tx_ack(desc);
1376 s->cookie_rx[i] = -EINVAL;
1377 }
1378 dev_warn(s->port.dev,
1379 "failed to re-start DMA, using PIO\n");
1380 sci_rx_dma_release(s, true);
1381 return;
1382 }
3089f381
GL		 1383 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1384 s->cookie_rx[i], i);
73a19e4c
GL		 1385 }
1386
1387 s->active_rx = s->cookie_rx[0];
1388
1389 dma_async_issue_pending(chan);
1390}
1391
1392static void work_fn_rx(struct work_struct *work)
1393{
1394 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1395 struct uart_port *port = &s->port;
1396 struct dma_async_tx_descriptor *desc;
1397 int new;
1398
1399 if (s->active_rx == s->cookie_rx[0]) {
1400 new = 0;
1401 } else if (s->active_rx == s->cookie_rx[1]) {
1402 new = 1;
1403 } else {
1404 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1405 return;
1406 }
1407 desc = s->desc_rx[new];
1408
1409 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1410 DMA_SUCCESS) {
1411 /* Handle incomplete DMA receive */
1412 struct tty_struct *tty = port->state->port.tty;
1413 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1414 struct shdma_desc *sh_desc = container_of(desc,
1415 struct shdma_desc, async_tx);
73a19e4c
GL		 1416 unsigned long flags;
1417 int count;
1418
05827630 1419 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1420 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1421 sh_desc->partial, sh_desc->cookie);
1422
1423 spin_lock_irqsave(&port->lock, flags);
1424 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1425 spin_unlock_irqrestore(&port->lock, flags);
1426
1427 if (count)
1428 tty_flip_buffer_push(tty);
1429
1430 sci_submit_rx(s);
1431
1432 return;
1433 }
1434
1435 s->cookie_rx[new] = desc->tx_submit(desc);
1436 if (s->cookie_rx[new] < 0) {
1437 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1438 sci_rx_dma_release(s, true);
1439 return;
1440 }
1441
73a19e4c 1442 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1443
1444 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1445 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1446}
1447
1448static void work_fn_tx(struct work_struct *work)
1449{
1450 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1451 struct dma_async_tx_descriptor *desc;
1452 struct dma_chan *chan = s->chan_tx;
1453 struct uart_port *port = &s->port;
1454 struct circ_buf *xmit = &port->state->xmit;
1455 struct scatterlist *sg = &s->sg_tx;
1456
1457 /*
1458 * DMA is idle now.
1459 * Port xmit buffer is already mapped, and it is one page... Just adjust
1460 * offsets and lengths. Since it is a circular buffer, we have to
1461 * transmit till the end, and then the rest. Take the port lock to get a
1462 * consistent xmit buffer state.
1463 */
1464 spin_lock_irq(&port->lock);
1465 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1466 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1467 sg->offset;
f354a381 1468 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1469 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1470 spin_unlock_irq(&port->lock);
1471
f354a381 1472 BUG_ON(!sg_dma_len(sg));
73a19e4c 1473
16052827 1474 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1475 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1476 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1477 if (!desc) {
1478 /* switch to PIO */
1479 sci_tx_dma_release(s, true);
1480 return;
1481 }
1482
1483 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1484
1485 spin_lock_irq(&port->lock);
1486 s->desc_tx = desc;
1487 desc->callback = sci_dma_tx_complete;
1488 desc->callback_param = s;
1489 spin_unlock_irq(&port->lock);
1490 s->cookie_tx = desc->tx_submit(desc);
1491 if (s->cookie_tx < 0) {
1492 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1493 /* switch to PIO */
1494 sci_tx_dma_release(s, true);
1495 return;
1496 }
1497
1498 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1499 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1500
1501 dma_async_issue_pending(chan);
1502}
1503#endif
1504
b129a8cc 1505static void sci_start_tx(struct uart_port *port)
1da177e4 1506{
3089f381 1507 struct sci_port *s = to_sci_port(port);
e108b2ca 1508 unsigned short ctrl;
1da177e4 1509
73a19e4c 1510#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1511 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1512 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1513 if (s->chan_tx)
1514 new = scr | 0x8000;
1515 else
1516 new = scr & ~0x8000;
1517 if (new != scr)
b12bb29f 1518 serial_port_out(port, SCSCR, new);
73a19e4c 1519 }
f43dc23d 1520
3089f381 1521 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1522 s->cookie_tx < 0) {
1523 s->cookie_tx = 0;
3089f381 1524 schedule_work(&s->work_tx);
49d4bcad 1525 }
73a19e4c 1526#endif
f43dc23d 1527
d1d4b10c 1528 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1529 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1530 ctrl = serial_port_in(port, SCSCR);
1531 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1532 }
1da177e4
LT		 1533}
1534
b129a8cc 1535static void sci_stop_tx(struct uart_port *port)
1da177e4 1536{
1da177e4
LT		 1537 unsigned short ctrl;
1538
1539 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1540 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1541
d1d4b10c 1542 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1543 ctrl &= ~0x8000;
f43dc23d 1544
8e698614 1545 ctrl &= ~SCSCR_TIE;
f43dc23d 1546
b12bb29f 1547 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1548}
1549
73a19e4c 1550static void sci_start_rx(struct uart_port *port)
1da177e4 1551{
1da177e4
LT		 1552 unsigned short ctrl;
1553
b12bb29f 1554 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1555
d1d4b10c 1556 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1557 ctrl &= ~0x4000;
f43dc23d 1558
b12bb29f 1559 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1560}
1561
1562static void sci_stop_rx(struct uart_port *port)
1563{
1da177e4
LT		 1564 unsigned short ctrl;
1565
b12bb29f 1566 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1567
d1d4b10c 1568 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1569 ctrl &= ~0x4000;
f43dc23d
PM		 1570
1571 ctrl &= ~port_rx_irq_mask(port);
1572
b12bb29f 1573 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1574}
1575
1576static void sci_enable_ms(struct uart_port *port)
1577{
d39ec6ce
PM		 1578 /*
1579 * Not supported by hardware, always a nop.
1580 */
1da177e4
LT		 1581}
1582
1583static void sci_break_ctl(struct uart_port *port, int break_state)
1584{
bbb4ce50 1585 struct sci_port *s = to_sci_port(port);
a4e02f6d 1586 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1587 unsigned short scscr, scsptr;
1588
a4e02f6d
SY		 1589 /* check wheter the port has SCSPTR */
1590 if (!reg->size) {
bbb4ce50
SY		 1591 /*
1592 * Not supported by hardware. Most parts couple break and rx
1593 * interrupts together, with break detection always enabled.
1594 */
a4e02f6d 1595 return;
bbb4ce50 1596 }
a4e02f6d
SY		 1597
1598 scsptr = serial_port_in(port, SCSPTR);
1599 scscr = serial_port_in(port, SCSCR);
1600
1601 if (break_state == -1) {
1602 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1603 scscr &= ~SCSCR_TE;
1604 } else {
1605 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1606 scscr |= SCSCR_TE;
1607 }
1608
1609 serial_port_out(port, SCSPTR, scsptr);
1610 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1611}
1612
73a19e4c
GL		 1613#ifdef CONFIG_SERIAL_SH_SCI_DMA
1614static bool filter(struct dma_chan *chan, void *slave)
1615{
1616 struct sh_dmae_slave *param = slave;
1617
1618 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1619 param->shdma_slave.slave_id);
73a19e4c 1620
d6fa5a4e 1621 chan->private = &param->shdma_slave;
937bb6e4 1622 return true;
73a19e4c
GL		 1623}
1624
1625static void rx_timer_fn(unsigned long arg)
1626{
1627 struct sci_port *s = (struct sci_port *)arg;
1628 struct uart_port *port = &s->port;
b12bb29f 1629 u16 scr = serial_port_in(port, SCSCR);
3089f381 1630
d1d4b10c 1631 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1632 scr &= ~0x4000;
ce6738b6 1633 enable_irq(s->cfg->irqs[1]);
3089f381 1634 }
b12bb29f 1635 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1636 dev_dbg(port->dev, "DMA Rx timed out\n");
1637 schedule_work(&s->work_rx);
1638}
1639
1640static void sci_request_dma(struct uart_port *port)
1641{
1642 struct sci_port *s = to_sci_port(port);
1643 struct sh_dmae_slave *param;
1644 struct dma_chan *chan;
1645 dma_cap_mask_t mask;
1646 int nent;
1647
937bb6e4
GL		 1648 dev_dbg(port->dev, "%s: port %d\n", __func__,
1649 port->line);
73a19e4c 1650
937bb6e4 1651 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1652 return;
1653
1654 dma_cap_zero(mask);
1655 dma_cap_set(DMA_SLAVE, mask);
1656
1657 param = &s->param_tx;
1658
1659 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1660 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1661
1662 s->cookie_tx = -EINVAL;
1663 chan = dma_request_channel(mask, filter, param);
1664 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1665 if (chan) {
1666 s->chan_tx = chan;
1667 sg_init_table(&s->sg_tx, 1);
1668 /* UART circular tx buffer is an aligned page. */
1669 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1670 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1671 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1672 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1673 if (!nent)
1674 sci_tx_dma_release(s, false);
1675 else
1676 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1677 sg_dma_len(&s->sg_tx),
1678 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1679
1680 s->sg_len_tx = nent;
1681
1682 INIT_WORK(&s->work_tx, work_fn_tx);
1683 }
1684
1685 param = &s->param_rx;
1686
1687 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1688 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1689
1690 chan = dma_request_channel(mask, filter, param);
1691 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1692 if (chan) {
1693 dma_addr_t dma[2];
1694 void *buf[2];
1695 int i;
1696
1697 s->chan_rx = chan;
1698
1699 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1700 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1701 &dma[0], GFP_KERNEL);
1702
1703 if (!buf[0]) {
1704 dev_warn(port->dev,
1705 "failed to allocate dma buffer, using PIO\n");
1706 sci_rx_dma_release(s, true);
1707 return;
1708 }
1709
1710 buf[1] = buf[0] + s->buf_len_rx;
1711 dma[1] = dma[0] + s->buf_len_rx;
1712
1713 for (i = 0; i < 2; i++) {
1714 struct scatterlist *sg = &s->sg_rx[i];
1715
1716 sg_init_table(sg, 1);
1717 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1718 (int)buf[i] & ~PAGE_MASK);
f354a381 1719 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1720 }
1721
1722 INIT_WORK(&s->work_rx, work_fn_rx);
1723 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1724
1725 sci_submit_rx(s);
1726 }
1727}
1728
1729static void sci_free_dma(struct uart_port *port)
1730{
1731 struct sci_port *s = to_sci_port(port);
1732
73a19e4c
GL		 1733 if (s->chan_tx)
1734 sci_tx_dma_release(s, false);
1735 if (s->chan_rx)
1736 sci_rx_dma_release(s, false);
1737}
27bd1075
PM		 1738#else
1739static inline void sci_request_dma(struct uart_port *port)
1740{
1741}
1742
1743static inline void sci_free_dma(struct uart_port *port)
1744{
1745}
73a19e4c
GL		 1746#endif
1747
1da177e4
LT		 1748static int sci_startup(struct uart_port *port)
1749{
a5660ada 1750 struct sci_port *s = to_sci_port(port);
073e84c9 1751 int ret;
1da177e4 1752
73a19e4c
GL		 1753 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1754
048be431
RW		 1755 pm_runtime_put_noidle(port->dev);
1756
23241d43 1757 sci_port_enable(s);
1da177e4 1758
073e84c9
PM		 1759 ret = sci_request_irq(s);
1760 if (unlikely(ret < 0))
1761 return ret;
1762
73a19e4c 1763 sci_request_dma(port);
073e84c9 1764
d656901b 1765 sci_start_tx(port);
73a19e4c 1766 sci_start_rx(port);
1da177e4
LT		 1767
1768 return 0;
1769}
1770
1771static void sci_shutdown(struct uart_port *port)
1772{
a5660ada 1773 struct sci_port *s = to_sci_port(port);
1da177e4 1774
73a19e4c
GL		 1775 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1776
1da177e4 1777 sci_stop_rx(port);
b129a8cc 1778 sci_stop_tx(port);
073e84c9 1779
73a19e4c 1780 sci_free_dma(port);
1da177e4
LT		 1781 sci_free_irq(s);
1782
23241d43 1783 sci_port_disable(s);
048be431
RW		 1784
1785 pm_runtime_get_noresume(port->dev);
1da177e4
LT		 1786}
1787
26c92f37
PM		 1788static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1789 unsigned long freq)
1790{
1791 switch (algo_id) {
1792 case SCBRR_ALGO_1:
1793 return ((freq + 16 * bps) / (16 * bps) - 1);
1794 case SCBRR_ALGO_2:
1795 return ((freq + 16 * bps) / (32 * bps) - 1);
1796 case SCBRR_ALGO_3:
1797 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1798 case SCBRR_ALGO_4:
1799 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1800 case SCBRR_ALGO_5:
1801 return (((freq * 1000 / 32) / bps) - 1);
1802 }
1803
1804 /* Warn, but use a safe default */
1805 WARN_ON(1);
e8183a6c 1806
26c92f37
PM		 1807 return ((freq + 16 * bps) / (32 * bps) - 1);
1808}
1809
1ba76220
MD		 1810static void sci_reset(struct uart_port *port)
1811{
0979e0e6 1812 struct plat_sci_reg *reg;
1ba76220
MD		 1813 unsigned int status;
1814
1815 do {
b12bb29f 1816 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1817 } while (!(status & SCxSR_TEND(port)));
1818
b12bb29f 1819 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1820
0979e0e6
PM		 1821 reg = sci_getreg(port, SCFCR);
1822 if (reg->size)
b12bb29f 1823 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1824}
1825
606d099c
AC		 1826static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1827 struct ktermios *old)
1da177e4 1828{
00b9de9c 1829 struct sci_port *s = to_sci_port(port);
0979e0e6 1830 struct plat_sci_reg *reg;
1ba76220 1831 unsigned int baud, smr_val, max_baud;
a2159b52 1832 int t = -1;
1da177e4 1833
154280fd
MD		 1834 /*
1835 * earlyprintk comes here early on with port->uartclk set to zero.
1836 * the clock framework is not up and running at this point so here
1837 * we assume that 115200 is the maximum baud rate. please note that
1838 * the baud rate is not programmed during earlyprintk - it is assumed
1839 * that the previous boot loader has enabled required clocks and
1840 * setup the baud rate generator hardware for us already.
1841 */
1842 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1843
154280fd
MD		 1844 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1845 if (likely(baud && port->uartclk))
ce6738b6 1846 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1847
23241d43 1848 sci_port_enable(s);
36003386 1849
1ba76220 1850 sci_reset(port);
1da177e4 1851
b12bb29f 1852 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1853
1da177e4
LT		 1854 if ((termios->c_cflag & CSIZE) == CS7)
1855 smr_val |= 0x40;
1856 if (termios->c_cflag & PARENB)
1857 smr_val |= 0x20;
1858 if (termios->c_cflag & PARODD)
1859 smr_val |= 0x30;
1860 if (termios->c_cflag & CSTOPB)
1861 smr_val |= 0x08;
1862
1863 uart_update_timeout(port, termios->c_cflag, baud);
1864
b12bb29f 1865 serial_port_out(port, SCSMR, smr_val);
1da177e4 1866
73a19e4c 1867 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1868 s->cfg->scscr);
73a19e4c 1869
1da177e4 1870 if (t > 0) {
e7c98dc7 1871 if (t >= 256) {
b12bb29f 1872 serial_port_out(port, SCSMR, (serial_port_in(port, SCSMR) & ~3) | 1);
1da177e4 1873 t >>= 2;
e7c98dc7 1874 } else
b12bb29f 1875 serial_port_out(port, SCSMR, serial_port_in(port, SCSMR) & ~3);
e7c98dc7 1876
b12bb29f 1877 serial_port_out(port, SCBRR, t);
1da177e4
LT		 1878 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1879 }
1880
d5701647 1881 sci_init_pins(port, termios->c_cflag);
0979e0e6 1882
73c3d53f
PM		 1883 reg = sci_getreg(port, SCFCR);
1884 if (reg->size) {
b12bb29f 1885 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1886
73c3d53f 1887 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1888 if (termios->c_cflag & CRTSCTS)
1889 ctrl |= SCFCR_MCE;
1890 else
1891 ctrl &= ~SCFCR_MCE;
faf02f8f 1892 }
73c3d53f
PM		 1893
1894 /*
1895 * As we've done a sci_reset() above, ensure we don't
1896 * interfere with the FIFOs while toggling MCE. As the
1897 * reset values could still be set, simply mask them out.
1898 */
1899 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1900
b12bb29f 1901 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1902 }
b7a76e4b 1903
b12bb29f 1904 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1905
3089f381
GL		 1906#ifdef CONFIG_SERIAL_SH_SCI_DMA
1907 /*
1908 * Calculate delay for 1.5 DMA buffers: see
1909 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1910 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1911 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1912 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1913 * sizes), but it has been found out experimentally, that this is not
1914 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1915 * as a minimum seem to work perfectly.
1916 */
1917 if (s->chan_rx) {
1918 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1919 port->fifosize / 2;
1920 dev_dbg(port->dev,
1921 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1922 s->rx_timeout * 1000 / HZ, port->timeout);
1923 if (s->rx_timeout < msecs_to_jiffies(20))
1924 s->rx_timeout = msecs_to_jiffies(20);
1925 }
1926#endif
1927
1da177e4 1928 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1929 sci_start_rx(port);
36003386 1930
23241d43 1931 sci_port_disable(s);
1da177e4
LT		 1932}
1933
1934static const char *sci_type(struct uart_port *port)
1935{
1936 switch (port->type) {
e7c98dc7
MT		 1937 case PORT_IRDA:
1938 return "irda";
1939 case PORT_SCI:
1940 return "sci";
1941 case PORT_SCIF:
1942 return "scif";
1943 case PORT_SCIFA:
1944 return "scifa";
d1d4b10c
GL		 1945 case PORT_SCIFB:
1946 return "scifb";
1da177e4
LT		 1947 }
1948
fa43972f 1949 return NULL;
1da177e4
LT		 1950}
1951
e2651647 1952static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1953{
e2651647
PM		 1954 /*
1955 * Pick an arbitrary size that encapsulates all of the base
1956 * registers by default. This can be optimized later, or derived
1957 * from platform resource data at such a time that ports begin to
1958 * behave more erratically.
1959 */
1960 return 64;
1da177e4
LT		 1961}
1962
f6e9495d
PM		 1963static int sci_remap_port(struct uart_port *port)
1964{
1965 unsigned long size = sci_port_size(port);
1966
1967 /*
1968 * Nothing to do if there's already an established membase.
1969 */
1970 if (port->membase)
1971 return 0;
1972
1973 if (port->flags & UPF_IOREMAP) {
1974 port->membase = ioremap_nocache(port->mapbase, size);
1975 if (unlikely(!port->membase)) {
1976 dev_err(port->dev, "can't remap port#%d\n", port->line);
1977 return -ENXIO;
1978 }
1979 } else {
1980 /*
1981 * For the simple (and majority of) cases where we don't
1982 * need to do any remapping, just cast the cookie
1983 * directly.
1984 */
1985 port->membase = (void __iomem *)port->mapbase;
1986 }
1987
1988 return 0;
1989}
1990
e2651647 1991static void sci_release_port(struct uart_port *port)
1da177e4 1992{
e2651647
PM		 1993 if (port->flags & UPF_IOREMAP) {
1994 iounmap(port->membase);
1995 port->membase = NULL;
1996 }
1997
1998 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1999}
2000
e2651647 2001static int sci_request_port(struct uart_port *port)
1da177e4 2002{
e2651647
PM		 2003 unsigned long size = sci_port_size(port);
2004 struct resource *res;
f6e9495d 2005 int ret;
1da177e4 2006
1020520e 2007 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2008 if (unlikely(res == NULL))
2009 return -EBUSY;
1da177e4 2010
f6e9495d
PM		 2011 ret = sci_remap_port(port);
2012 if (unlikely(ret != 0)) {
2013 release_resource(res);
2014 return ret;
7ff731ae 2015 }
e2651647
PM		 2016
2017 return 0;
2018}
2019
2020static void sci_config_port(struct uart_port *port, int flags)
2021{
2022 if (flags & UART_CONFIG_TYPE) {
2023 struct sci_port *sport = to_sci_port(port);
2024
2025 port->type = sport->cfg->type;
2026 sci_request_port(port);
2027 }
1da177e4
LT		 2028}
2029
2030static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2031{
a5660ada 2032 struct sci_port *s = to_sci_port(port);
1da177e4 2033
ce6738b6 2034 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 2035 return -EINVAL;
2036 if (ser->baud_base < 2400)
2037 /* No paper tape reader for Mitch.. */
2038 return -EINVAL;
2039
2040 return 0;
2041}
2042
2043static struct uart_ops sci_uart_ops = {
2044 .tx_empty = sci_tx_empty,
2045 .set_mctrl = sci_set_mctrl,
2046 .get_mctrl = sci_get_mctrl,
2047 .start_tx = sci_start_tx,
2048 .stop_tx = sci_stop_tx,
2049 .stop_rx = sci_stop_rx,
2050 .enable_ms = sci_enable_ms,
2051 .break_ctl = sci_break_ctl,
2052 .startup = sci_startup,
2053 .shutdown = sci_shutdown,
2054 .set_termios = sci_set_termios,
2055 .type = sci_type,
2056 .release_port = sci_release_port,
2057 .request_port = sci_request_port,
2058 .config_port = sci_config_port,
2059 .verify_port = sci_verify_port,
07d2a1a1
PM		 2060#ifdef CONFIG_CONSOLE_POLL
2061 .poll_get_char = sci_poll_get_char,
2062 .poll_put_char = sci_poll_put_char,
2063#endif
1da177e4
LT		 2064};
2065
c7ed1ab3
PM		 2066static int __devinit sci_init_single(struct platform_device *dev,
2067 struct sci_port *sci_port,
2068 unsigned int index,
2069 struct plat_sci_port *p)
e108b2ca 2070{
73a19e4c 2071 struct uart_port *port = &sci_port->port;
3127c6b2 2072 int ret;
e108b2ca 2073
50f0959a
PM		 2074 sci_port->cfg = p;
2075
73a19e4c
GL		 2076 port->ops = &sci_uart_ops;
2077 port->iotype = UPIO_MEM;
2078 port->line = index;
75136d48
MP		 2079
2080 switch (p->type) {
d1d4b10c
GL		 2081 case PORT_SCIFB:
2082 port->fifosize = 256;
2083 break;
75136d48 2084 case PORT_SCIFA:
73a19e4c 2085 port->fifosize = 64;
75136d48
MP		 2086 break;
2087 case PORT_SCIF:
73a19e4c 2088 port->fifosize = 16;
75136d48
MP		 2089 break;
2090 default:
73a19e4c 2091 port->fifosize = 1;
75136d48
MP		 2092 break;
2093 }
7b6fd3bf 2094
3127c6b2
PM		 2095 if (p->regtype == SCIx_PROBE_REGTYPE) {
2096 ret = sci_probe_regmap(p);
fc97114b 2097 if (unlikely(ret))
3127c6b2
PM		 2098 return ret;
2099 }
61a6976b 2100
7b6fd3bf 2101 if (dev) {
c7ed1ab3
PM		 2102 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2103 if (IS_ERR(sci_port->iclk)) {
2104 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2105 if (IS_ERR(sci_port->iclk)) {
2106 dev_err(&dev->dev, "can't get iclk\n");
2107 return PTR_ERR(sci_port->iclk);
2108 }
2109 }
2110
2111 /*
2112 * The function clock is optional, ignore it if we can't
2113 * find it.
2114 */
2115 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2116 if (IS_ERR(sci_port->fclk))
2117 sci_port->fclk = NULL;
2118
73a19e4c 2119 port->dev = &dev->dev;
5e50d2d6 2120
50f0959a
PM		 2121 sci_init_gpios(sci_port);
2122
5a50a01b 2123 pm_runtime_irq_safe(&dev->dev);
048be431 2124 pm_runtime_get_noresume(&dev->dev);
5e50d2d6 2125 pm_runtime_enable(&dev->dev);
7b6fd3bf 2126 }
e108b2ca 2127
7ed7e071
MD		 2128 sci_port->break_timer.data = (unsigned long)sci_port;
2129 sci_port->break_timer.function = sci_break_timer;
2130 init_timer(&sci_port->break_timer);
2131
debf9507
PM		 2132 /*
2133 * Establish some sensible defaults for the error detection.
2134 */
2135 if (!p->error_mask)
2136 p->error_mask = (p->type == PORT_SCI) ?
2137 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2138
2139 /*
2140 * Establish sensible defaults for the overrun detection, unless
2141 * the part has explicitly disabled support for it.
2142 */
2143 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2144 if (p->type == PORT_SCI)
2145 p->overrun_bit = 5;
2146 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2147 p->overrun_bit = 9;
2148 else
2149 p->overrun_bit = 0;
2150
2151 /*
2152 * Make the error mask inclusive of overrun detection, if
2153 * supported.
2154 */
2155 p->error_mask |= (1 << p->overrun_bit);
2156 }
2157
ce6738b6
PM		 2158 port->mapbase = p->mapbase;
2159 port->type = p->type;
f43dc23d 2160 port->flags = p->flags;
61a6976b 2161 port->regshift = p->regshift;
73a19e4c 2162
ce6738b6 2163 /*
61a6976b 2164 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2165 * for the multi-IRQ ports, which is where we are primarily
2166 * concerned with the shutdown path synchronization.
2167 *
2168 * For the muxed case there's nothing more to do.
2169 */
54aa89ea 2170 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2171 port->irqflags = 0;
73a19e4c 2172
61a6976b
PM		 2173 port->serial_in = sci_serial_in;
2174 port->serial_out = sci_serial_out;
2175
937bb6e4
GL		 2176 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2177 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2178 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2179
c7ed1ab3 2180 return 0;
e108b2ca
PM		 2181}
2182
6dae1421
LP		 2183static void sci_cleanup_single(struct sci_port *port)
2184{
2185 sci_free_gpios(port);
2186
2187 clk_put(port->iclk);
2188 clk_put(port->fclk);
2189
2190 pm_runtime_disable(port->port.dev);
2191}
2192
1da177e4 2193#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2194static void serial_console_putchar(struct uart_port *port, int ch)
2195{
2196 sci_poll_put_char(port, ch);
2197}
2198
1da177e4
LT		 2199/*
2200 * Print a string to the serial port trying not to disturb
2201 * any possible real use of the port...
2202 */
2203static void serial_console_write(struct console *co, const char *s,
2204 unsigned count)
2205{
906b17dc
PM		 2206 struct sci_port *sci_port = &sci_ports[co->index];
2207 struct uart_port *port = &sci_port->port;
973e5d52 2208 unsigned short bits;
07d2a1a1 2209
23241d43 2210 sci_port_enable(sci_port);
501b825d
MD		 2211
2212 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2213
2214 /* wait until fifo is empty and last bit has been transmitted */
2215 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2216 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2217 cpu_relax();
501b825d 2218
23241d43 2219 sci_port_disable(sci_port);
1da177e4
LT		 2220}
2221
7b6fd3bf 2222static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 2223{
dc8e6f5b 2224 struct sci_port *sci_port;
1da177e4
LT		 2225 struct uart_port *port;
2226 int baud = 115200;
2227 int bits = 8;
2228 int parity = 'n';
2229 int flow = 'n';
2230 int ret;
2231
e108b2ca 2232 /*
906b17dc 2233 * Refuse to handle any bogus ports.
1da177e4 2234 */
906b17dc 2235 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2236 return -ENODEV;
e108b2ca 2237
906b17dc
PM		 2238 sci_port = &sci_ports[co->index];
2239 port = &sci_port->port;
2240
b2267a6b
AC		 2241 /*
2242 * Refuse to handle uninitialized ports.
2243 */
2244 if (!port->ops)
2245 return -ENODEV;
2246
f6e9495d
PM		 2247 ret = sci_remap_port(port);
2248 if (unlikely(ret != 0))
2249 return ret;
e108b2ca 2250
23241d43 2251 sci_port_enable(sci_port);
b7a76e4b 2252
1da177e4
LT		 2253 if (options)
2254 uart_parse_options(options, &baud, &parity, &bits, &flow);
2255
1ba76220
MD		 2256 sci_port_disable(sci_port);
2257
ab7cfb55 2258 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2259}
2260
2261static struct console serial_console = {
2262 .name = "ttySC",
906b17dc 2263 .device = uart_console_device,
1da177e4
LT		 2264 .write = serial_console_write,
2265 .setup = serial_console_setup,
fa5da2f7 2266 .flags = CON_PRINTBUFFER,
1da177e4 2267 .index = -1,
906b17dc 2268 .data = &sci_uart_driver,
1da177e4
LT		 2269};
2270
7b6fd3bf
MD		 2271static struct console early_serial_console = {
2272 .name = "early_ttySC",
2273 .write = serial_console_write,
2274 .flags = CON_PRINTBUFFER,
906b17dc 2275 .index = -1,
7b6fd3bf 2276};
ecdf8a46 2277
7b6fd3bf
MD		 2278static char early_serial_buf[32];
2279
ecdf8a46
PM		 2280static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2281{
2282 struct plat_sci_port *cfg = pdev->dev.platform_data;
2283
2284 if (early_serial_console.data)
2285 return -EEXIST;
2286
2287 early_serial_console.index = pdev->id;
ecdf8a46 2288
906b17dc 2289 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2290
2291 serial_console_setup(&early_serial_console, early_serial_buf);
2292
2293 if (!strstr(early_serial_buf, "keep"))
2294 early_serial_console.flags |= CON_BOOT;
2295
2296 register_console(&early_serial_console);
2297 return 0;
2298}
6a8c9799 2299
1ba76220
MD		 2300#define uart_console(port) ((port)->cons->index == (port)->line)
2301
2302static int sci_runtime_suspend(struct device *dev)
2303{
2304 struct sci_port *sci_port = dev_get_drvdata(dev);
2305 struct uart_port *port = &sci_port->port;
2306
2307 if (uart_console(port)) {
0979e0e6
PM		 2308 struct plat_sci_reg *reg;
2309
b12bb29f
PM		 2310 sci_port->saved_smr = serial_port_in(port, SCSMR);
2311 sci_port->saved_brr = serial_port_in(port, SCBRR);
0979e0e6
PM		 2312
2313 reg = sci_getreg(port, SCFCR);
2314 if (reg->size)
b12bb29f 2315 sci_port->saved_fcr = serial_port_in(port, SCFCR);
0979e0e6
PM		 2316 else
2317 sci_port->saved_fcr = 0;
1ba76220
MD		 2318 }
2319 return 0;
2320}
2321
2322static int sci_runtime_resume(struct device *dev)
2323{
2324 struct sci_port *sci_port = dev_get_drvdata(dev);
2325 struct uart_port *port = &sci_port->port;
2326
2327 if (uart_console(port)) {
2328 sci_reset(port);
b12bb29f
PM		 2329 serial_port_out(port, SCSMR, sci_port->saved_smr);
2330 serial_port_out(port, SCBRR, sci_port->saved_brr);
0979e0e6
PM		 2331
2332 if (sci_port->saved_fcr)
b12bb29f 2333 serial_port_out(port, SCFCR, sci_port->saved_fcr);
0979e0e6 2334
b12bb29f 2335 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
1ba76220
MD		 2336 }
2337 return 0;
2338}
2339
6a8c9799
NI		 2340#define SCI_CONSOLE (&serial_console)
2341
ecdf8a46
PM		 2342#else
2343static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2344{
2345 return -EINVAL;
2346}
1da177e4 2347
6a8c9799 2348#define SCI_CONSOLE NULL
1ba76220
MD		 2349#define sci_runtime_suspend NULL
2350#define sci_runtime_resume NULL
6a8c9799
NI		 2351
2352#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2353
2354static char banner[] __initdata =
2355 KERN_INFO "SuperH SCI(F) driver initialized\n";
2356
2357static struct uart_driver sci_uart_driver = {
2358 .owner = THIS_MODULE,
2359 .driver_name = "sci",
1da177e4
LT		 2360 .dev_name = "ttySC",
2361 .major = SCI_MAJOR,
2362 .minor = SCI_MINOR_START,
e108b2ca 2363 .nr = SCI_NPORTS,
1da177e4
LT		 2364 .cons = SCI_CONSOLE,
2365};
2366
54507f6e 2367static int sci_remove(struct platform_device *dev)
e552de24 2368{
d535a230 2369 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2370
d535a230
PM		 2371 cpufreq_unregister_notifier(&port->freq_transition,
2372 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2373
d535a230
PM		 2374 uart_remove_one_port(&sci_uart_driver, &port->port);
2375
6dae1421 2376 sci_cleanup_single(port);
e552de24 2377
e552de24
MD		 2378 return 0;
2379}
2380
0ee70712
MD		 2381static int __devinit sci_probe_single(struct platform_device *dev,
2382 unsigned int index,
2383 struct plat_sci_port *p,
2384 struct sci_port *sciport)
2385{
0ee70712
MD		 2386 int ret;
2387
2388 /* Sanity check */
2389 if (unlikely(index >= SCI_NPORTS)) {
2390 dev_notice(&dev->dev, "Attempting to register port "
2391 "%d when only %d are available.\n",
2392 index+1, SCI_NPORTS);
2393 dev_notice(&dev->dev, "Consider bumping "
2394 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2395 return -EINVAL;
0ee70712
MD		 2396 }
2397
c7ed1ab3
PM		 2398 ret = sci_init_single(dev, sciport, index, p);
2399 if (ret)
2400 return ret;
0ee70712 2401
6dae1421
LP		 2402 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2403 if (ret) {
2404 sci_cleanup_single(sciport);
2405 return ret;
2406 }
2407
2408 return 0;
0ee70712
MD		 2409}
2410
e108b2ca 2411static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2412{
e108b2ca 2413 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2414 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2415 int ret;
d535a230 2416
ecdf8a46
PM		 2417 /*
2418 * If we've come here via earlyprintk initialization, head off to
2419 * the special early probe. We don't have sufficient device state
2420 * to make it beyond this yet.
2421 */
2422 if (is_early_platform_device(dev))
2423 return sci_probe_earlyprintk(dev);
7b6fd3bf 2424
d535a230 2425 platform_set_drvdata(dev, sp);
e552de24 2426
906b17dc 2427 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2428 if (ret)
6dae1421 2429 return ret;
e552de24 2430
d535a230 2431 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2432
d535a230
PM		 2433 ret = cpufreq_register_notifier(&sp->freq_transition,
2434 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2435 if (unlikely(ret < 0)) {
2436 sci_cleanup_single(sp);
2437 return ret;
2438 }
1da177e4
LT		 2439
2440#ifdef CONFIG_SH_STANDARD_BIOS
2441 sh_bios_gdb_detach();
2442#endif
2443
e108b2ca 2444 return 0;
1da177e4
LT		 2445}
2446
6daa79b3 2447static int sci_suspend(struct device *dev)
1da177e4 2448{
d535a230 2449 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2450
d535a230
PM		 2451 if (sport)
2452 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2453
e108b2ca
PM		 2454 return 0;
2455}
1da177e4 2456
6daa79b3 2457static int sci_resume(struct device *dev)
e108b2ca 2458{
d535a230 2459 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2460
d535a230
PM		 2461 if (sport)
2462 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2463
2464 return 0;
2465}
2466
47145210 2467static const struct dev_pm_ops sci_dev_pm_ops = {
1ba76220
MD		 2468 .runtime_suspend = sci_runtime_suspend,
2469 .runtime_resume = sci_runtime_resume,
6daa79b3
PM		 2470 .suspend = sci_suspend,
2471 .resume = sci_resume,
2472};
2473
e108b2ca
PM		 2474static struct platform_driver sci_driver = {
2475 .probe = sci_probe,
b9e39c89 2476 .remove = sci_remove,
e108b2ca
PM		 2477 .driver = {
2478 .name = "sh-sci",
2479 .owner = THIS_MODULE,
6daa79b3 2480 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2481 },
2482};
2483
2484static int __init sci_init(void)
2485{
2486 int ret;
2487
2488 printk(banner);
2489
e108b2ca
PM		 2490 ret = uart_register_driver(&sci_uart_driver);
2491 if (likely(ret == 0)) {
2492 ret = platform_driver_register(&sci_driver);
2493 if (unlikely(ret))
2494 uart_unregister_driver(&sci_uart_driver);
2495 }
2496
2497 return ret;
2498}
2499
2500static void __exit sci_exit(void)
2501{
2502 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2503 uart_unregister_driver(&sci_uart_driver);
2504}
2505
7b6fd3bf
MD		 2506#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2507early_platform_init_buffer("earlyprintk", &sci_driver,
2508 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2509#endif
1da177e4
LT		 2510module_init(sci_init);
2511module_exit(sci_exit);
2512
e108b2ca 2513MODULE_LICENSE("GPL");
e169c139 2514MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2515MODULE_AUTHOR("Paul Mundt");
2516MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux kernel - Deliverables
This page took 0.832991 seconds and 5 git commands to generate.