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serial: sh-sci: Make sci_regmap[] const
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 struct dma_async_tx_descriptor *desc_tx;
108 struct dma_async_tx_descriptor *desc_rx[2];
109 dma_cookie_t cookie_tx;
110 dma_cookie_t cookie_rx[2];
111 dma_cookie_t active_rx;
112 struct scatterlist sg_tx;
113 unsigned int sg_len_tx;
114 struct scatterlist sg_rx[2];
115 size_t buf_len_rx;
116 struct sh_dmae_slave param_tx;
117 struct sh_dmae_slave param_rx;
118 struct work_struct work_tx;
119 struct work_struct work_rx;
120 struct timer_list rx_timer;
3089f381 121 unsigned int rx_timeout;
73a19e4c 122#endif
e552de24 123
d535a230 124 struct notifier_block freq_transition;
e108b2ca
PM		 125};
126
1da177e4 127/* Function prototypes */
d535a230 128static void sci_start_tx(struct uart_port *port);
b129a8cc 129static void sci_stop_tx(struct uart_port *port);
d535a230 130static void sci_start_rx(struct uart_port *port);
1da177e4 131
e108b2ca 132#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 133
e108b2ca
PM		 134static struct sci_port sci_ports[SCI_NPORTS];
135static struct uart_driver sci_uart_driver;
1da177e4 136
e7c98dc7
MT		 137static inline struct sci_port *
138to_sci_port(struct uart_port *uart)
139{
140 return container_of(uart, struct sci_port, port);
141}
142
61a6976b
PM		 143struct plat_sci_reg {
144 u8 offset, size;
145};
146
147/* Helper for invalidating specific entries of an inherited map. */
148#define sci_reg_invalid { .offset = 0, .size = 0 }
149
d3184e68 150static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 151 [SCIx_PROBE_REGTYPE] = {
152 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
153 },
154
155 /*
156 * Common SCI definitions, dependent on the port's regshift
157 * value.
158 */
159 [SCIx_SCI_REGTYPE] = {
160 [SCSMR] = { 0x00, 8 },
161 [SCBRR] = { 0x01, 8 },
162 [SCSCR] = { 0x02, 8 },
163 [SCxTDR] = { 0x03, 8 },
164 [SCxSR] = { 0x04, 8 },
165 [SCxRDR] = { 0x05, 8 },
166 [SCFCR] = sci_reg_invalid,
167 [SCFDR] = sci_reg_invalid,
168 [SCTFDR] = sci_reg_invalid,
169 [SCRFDR] = sci_reg_invalid,
170 [SCSPTR] = sci_reg_invalid,
171 [SCLSR] = sci_reg_invalid,
f303b364 172 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 173 [SCPCR] = sci_reg_invalid,
174 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 175 },
176
177 /*
178 * Common definitions for legacy IrDA ports, dependent on
179 * regshift value.
180 */
181 [SCIx_IRDA_REGTYPE] = {
182 [SCSMR] = { 0x00, 8 },
183 [SCBRR] = { 0x01, 8 },
184 [SCSCR] = { 0x02, 8 },
185 [SCxTDR] = { 0x03, 8 },
186 [SCxSR] = { 0x04, 8 },
187 [SCxRDR] = { 0x05, 8 },
188 [SCFCR] = { 0x06, 8 },
189 [SCFDR] = { 0x07, 16 },
190 [SCTFDR] = sci_reg_invalid,
191 [SCRFDR] = sci_reg_invalid,
192 [SCSPTR] = sci_reg_invalid,
193 [SCLSR] = sci_reg_invalid,
f303b364 194 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 195 [SCPCR] = sci_reg_invalid,
196 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 197 },
198
199 /*
200 * Common SCIFA definitions.
201 */
202 [SCIx_SCIFA_REGTYPE] = {
203 [SCSMR] = { 0x00, 16 },
204 [SCBRR] = { 0x04, 8 },
205 [SCSCR] = { 0x08, 16 },
206 [SCxTDR] = { 0x20, 8 },
207 [SCxSR] = { 0x14, 16 },
208 [SCxRDR] = { 0x24, 8 },
209 [SCFCR] = { 0x18, 16 },
210 [SCFDR] = { 0x1c, 16 },
211 [SCTFDR] = sci_reg_invalid,
212 [SCRFDR] = sci_reg_invalid,
213 [SCSPTR] = sci_reg_invalid,
214 [SCLSR] = sci_reg_invalid,
f303b364 215 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 216 [SCPCR] = { 0x30, 16 },
217 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 218 },
219
220 /*
221 * Common SCIFB definitions.
222 */
223 [SCIx_SCIFB_REGTYPE] = {
224 [SCSMR] = { 0x00, 16 },
225 [SCBRR] = { 0x04, 8 },
226 [SCSCR] = { 0x08, 16 },
227 [SCxTDR] = { 0x40, 8 },
228 [SCxSR] = { 0x14, 16 },
229 [SCxRDR] = { 0x60, 8 },
230 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 231 [SCFDR] = sci_reg_invalid,
232 [SCTFDR] = { 0x38, 16 },
233 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 234 [SCSPTR] = sci_reg_invalid,
235 [SCLSR] = sci_reg_invalid,
f303b364 236 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 237 [SCPCR] = { 0x30, 16 },
238 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 239 },
240
3af1f8a4
PE		 241 /*
242 * Common SH-2(A) SCIF definitions for ports with FIFO data
243 * count registers.
244 */
245 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x0c, 8 },
250 [SCxSR] = { 0x10, 16 },
251 [SCxRDR] = { 0x14, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCFDR] = { 0x1c, 16 },
254 [SCTFDR] = sci_reg_invalid,
255 [SCRFDR] = sci_reg_invalid,
256 [SCSPTR] = { 0x20, 16 },
257 [SCLSR] = { 0x24, 16 },
f303b364 258 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 259 [SCPCR] = sci_reg_invalid,
260 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 261 },
262
61a6976b
PM		 263 /*
264 * Common SH-3 SCIF definitions.
265 */
266 [SCIx_SH3_SCIF_REGTYPE] = {
267 [SCSMR] = { 0x00, 8 },
268 [SCBRR] = { 0x02, 8 },
269 [SCSCR] = { 0x04, 8 },
270 [SCxTDR] = { 0x06, 8 },
271 [SCxSR] = { 0x08, 16 },
272 [SCxRDR] = { 0x0a, 8 },
273 [SCFCR] = { 0x0c, 8 },
274 [SCFDR] = { 0x0e, 16 },
275 [SCTFDR] = sci_reg_invalid,
276 [SCRFDR] = sci_reg_invalid,
277 [SCSPTR] = sci_reg_invalid,
278 [SCLSR] = sci_reg_invalid,
f303b364 279 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 280 [SCPCR] = sci_reg_invalid,
281 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 282 },
283
284 /*
285 * Common SH-4(A) SCIF(B) definitions.
286 */
287 [SCIx_SH4_SCIF_REGTYPE] = {
288 [SCSMR] = { 0x00, 16 },
289 [SCBRR] = { 0x04, 8 },
290 [SCSCR] = { 0x08, 16 },
291 [SCxTDR] = { 0x0c, 8 },
292 [SCxSR] = { 0x10, 16 },
293 [SCxRDR] = { 0x14, 8 },
294 [SCFCR] = { 0x18, 16 },
295 [SCFDR] = { 0x1c, 16 },
296 [SCTFDR] = sci_reg_invalid,
297 [SCRFDR] = sci_reg_invalid,
298 [SCSPTR] = { 0x20, 16 },
299 [SCLSR] = { 0x24, 16 },
f303b364 300 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 301 [SCPCR] = sci_reg_invalid,
302 [SCPDR] = sci_reg_invalid,
f303b364
UH		 303 },
304
305 /*
306 * Common HSCIF definitions.
307 */
308 [SCIx_HSCIF_REGTYPE] = {
309 [SCSMR] = { 0x00, 16 },
310 [SCBRR] = { 0x04, 8 },
311 [SCSCR] = { 0x08, 16 },
312 [SCxTDR] = { 0x0c, 8 },
313 [SCxSR] = { 0x10, 16 },
314 [SCxRDR] = { 0x14, 8 },
315 [SCFCR] = { 0x18, 16 },
316 [SCFDR] = { 0x1c, 16 },
317 [SCTFDR] = sci_reg_invalid,
318 [SCRFDR] = sci_reg_invalid,
319 [SCSPTR] = { 0x20, 16 },
320 [SCLSR] = { 0x24, 16 },
321 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 322 [SCPCR] = sci_reg_invalid,
323 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 324 },
325
326 /*
327 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
328 * register.
329 */
330 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
331 [SCSMR] = { 0x00, 16 },
332 [SCBRR] = { 0x04, 8 },
333 [SCSCR] = { 0x08, 16 },
334 [SCxTDR] = { 0x0c, 8 },
335 [SCxSR] = { 0x10, 16 },
336 [SCxRDR] = { 0x14, 8 },
337 [SCFCR] = { 0x18, 16 },
338 [SCFDR] = { 0x1c, 16 },
339 [SCTFDR] = sci_reg_invalid,
340 [SCRFDR] = sci_reg_invalid,
341 [SCSPTR] = sci_reg_invalid,
342 [SCLSR] = { 0x24, 16 },
f303b364 343 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 344 [SCPCR] = sci_reg_invalid,
345 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 346 },
347
348 /*
349 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
350 * count registers.
351 */
352 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
353 [SCSMR] = { 0x00, 16 },
354 [SCBRR] = { 0x04, 8 },
355 [SCSCR] = { 0x08, 16 },
356 [SCxTDR] = { 0x0c, 8 },
357 [SCxSR] = { 0x10, 16 },
358 [SCxRDR] = { 0x14, 8 },
359 [SCFCR] = { 0x18, 16 },
360 [SCFDR] = { 0x1c, 16 },
361 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
362 [SCRFDR] = { 0x20, 16 },
363 [SCSPTR] = { 0x24, 16 },
364 [SCLSR] = { 0x28, 16 },
f303b364 365 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 366 [SCPCR] = sci_reg_invalid,
367 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 368 },
369
370 /*
371 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
372 * registers.
373 */
374 [SCIx_SH7705_SCIF_REGTYPE] = {
375 [SCSMR] = { 0x00, 16 },
376 [SCBRR] = { 0x04, 8 },
377 [SCSCR] = { 0x08, 16 },
378 [SCxTDR] = { 0x20, 8 },
379 [SCxSR] = { 0x14, 16 },
380 [SCxRDR] = { 0x24, 8 },
381 [SCFCR] = { 0x18, 16 },
382 [SCFDR] = { 0x1c, 16 },
383 [SCTFDR] = sci_reg_invalid,
384 [SCRFDR] = sci_reg_invalid,
385 [SCSPTR] = sci_reg_invalid,
386 [SCLSR] = sci_reg_invalid,
f303b364 387 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 388 [SCPCR] = sci_reg_invalid,
389 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 390 },
391};
392
72b294cf
PM		 393#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
394
61a6976b
PM		 395/*
396 * The "offset" here is rather misleading, in that it refers to an enum
397 * value relative to the port mapping rather than the fixed offset
398 * itself, which needs to be manually retrieved from the platform's
399 * register map for the given port.
400 */
401static unsigned int sci_serial_in(struct uart_port *p, int offset)
402{
d3184e68 403 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 404
405 if (reg->size == 8)
406 return ioread8(p->membase + (reg->offset << p->regshift));
407 else if (reg->size == 16)
408 return ioread16(p->membase + (reg->offset << p->regshift));
409 else
410 WARN(1, "Invalid register access\n");
411
412 return 0;
413}
414
415static void sci_serial_out(struct uart_port *p, int offset, int value)
416{
d3184e68 417 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 418
419 if (reg->size == 8)
420 iowrite8(value, p->membase + (reg->offset << p->regshift));
421 else if (reg->size == 16)
422 iowrite16(value, p->membase + (reg->offset << p->regshift));
423 else
424 WARN(1, "Invalid register access\n");
425}
426
61a6976b
PM		 427static int sci_probe_regmap(struct plat_sci_port *cfg)
428{
429 switch (cfg->type) {
430 case PORT_SCI:
431 cfg->regtype = SCIx_SCI_REGTYPE;
432 break;
433 case PORT_IRDA:
434 cfg->regtype = SCIx_IRDA_REGTYPE;
435 break;
436 case PORT_SCIFA:
437 cfg->regtype = SCIx_SCIFA_REGTYPE;
438 break;
439 case PORT_SCIFB:
440 cfg->regtype = SCIx_SCIFB_REGTYPE;
441 break;
442 case PORT_SCIF:
443 /*
444 * The SH-4 is a bit of a misnomer here, although that's
445 * where this particular port layout originated. This
446 * configuration (or some slight variation thereof)
447 * remains the dominant model for all SCIFs.
448 */
449 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
450 break;
f303b364
UH		 451 case PORT_HSCIF:
452 cfg->regtype = SCIx_HSCIF_REGTYPE;
453 break;
61a6976b 454 default:
6c13d5d2 455 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 456 return -EINVAL;
457 }
458
459 return 0;
460}
461
23241d43
PM		 462static void sci_port_enable(struct sci_port *sci_port)
463{
464 if (!sci_port->port.dev)
465 return;
466
467 pm_runtime_get_sync(sci_port->port.dev);
468
b016b646 469 clk_prepare_enable(sci_port->iclk);
23241d43 470 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 471 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 472}
473
474static void sci_port_disable(struct sci_port *sci_port)
475{
476 if (!sci_port->port.dev)
477 return;
478
caec7038
LP		 479 /* Cancel the break timer to ensure that the timer handler will not try
480 * to access the hardware with clocks and power disabled. Reset the
481 * break flag to make the break debouncing state machine ready for the
482 * next break.
483 */
484 del_timer_sync(&sci_port->break_timer);
485 sci_port->break_flag = 0;
486
b016b646
LP		 487 clk_disable_unprepare(sci_port->fclk);
488 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 489
490 pm_runtime_put_sync(sci_port->port.dev);
491}
492
a1b5b43f
GU		 493static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
494{
495 if (port->type == PORT_SCI) {
496 /* Just store the mask */
497 serial_port_out(port, SCxSR, mask);
498 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
499 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
500 /* Only clear the status bits we want to clear */
501 serial_port_out(port, SCxSR,
502 serial_port_in(port, SCxSR) & mask);
503 } else {
504 /* Store the mask, clear parity/framing errors */
505 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
506 }
507}
508
07d2a1a1 509#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 510
511#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 512static int sci_poll_get_char(struct uart_port *port)
1da177e4 513{
1da177e4
LT		 514 unsigned short status;
515 int c;
516
e108b2ca 517 do {
b12bb29f 518 status = serial_port_in(port, SCxSR);
1da177e4 519 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 520 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 521 continue;
522 }
3f255eb3
JW		 523 break;
524 } while (1);
525
526 if (!(status & SCxSR_RDxF(port)))
527 return NO_POLL_CHAR;
07d2a1a1 528
b12bb29f 529 c = serial_port_in(port, SCxRDR);
07d2a1a1 530
e7c98dc7 531 /* Dummy read */
b12bb29f 532 serial_port_in(port, SCxSR);
a1b5b43f 533 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 534
535 return c;
536}
1f6fd5c9 537#endif
1da177e4 538
07d2a1a1 539static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 540{
1da177e4
LT		 541 unsigned short status;
542
1da177e4 543 do {
b12bb29f 544 status = serial_port_in(port, SCxSR);
1da177e4
LT		 545 } while (!(status & SCxSR_TDxE(port)));
546
b12bb29f 547 serial_port_out(port, SCxTDR, c);
a1b5b43f 548 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 549}
07d2a1a1 550#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 551
61a6976b 552static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 553{
61a6976b 554 struct sci_port *s = to_sci_port(port);
d3184e68 555 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 556
61a6976b
PM		 557 /*
558 * Use port-specific handler if provided.
559 */
560 if (s->cfg->ops && s->cfg->ops->init_pins) {
561 s->cfg->ops->init_pins(port, cflag);
562 return;
1da177e4 563 }
41504c39 564
61a6976b
PM		 565 /*
566 * For the generic path SCSPTR is necessary. Bail out if that's
567 * unavailable, too.
568 */
569 if (!reg->size)
570 return;
41504c39 571
faf02f8f
PM		 572 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
573 ((!(cflag & CRTSCTS)))) {
574 unsigned short status;
575
b12bb29f 576 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 577 status &= ~SCSPTR_CTSIO;
578 status |= SCSPTR_RTSIO;
b12bb29f 579 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 580 }
d5701647 581}
e108b2ca 582
72b294cf 583static int sci_txfill(struct uart_port *port)
e108b2ca 584{
d3184e68 585 const struct plat_sci_reg *reg;
e108b2ca 586
72b294cf
PM		 587 reg = sci_getreg(port, SCTFDR);
588 if (reg->size)
63f7ad11 589 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 590
72b294cf
PM		 591 reg = sci_getreg(port, SCFDR);
592 if (reg->size)
b12bb29f 593 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 594
b12bb29f 595 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 596}
597
73a19e4c
GL		 598static int sci_txroom(struct uart_port *port)
599{
72b294cf 600 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 601}
602
603static int sci_rxfill(struct uart_port *port)
e108b2ca 604{
d3184e68 605 const struct plat_sci_reg *reg;
72b294cf
PM		 606
607 reg = sci_getreg(port, SCRFDR);
608 if (reg->size)
63f7ad11 609 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 610
611 reg = sci_getreg(port, SCFDR);
612 if (reg->size)
b12bb29f 613 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 614
b12bb29f 615 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 616}
617
514820eb
PM		 618/*
619 * SCI helper for checking the state of the muxed port/RXD pins.
620 */
621static inline int sci_rxd_in(struct uart_port *port)
622{
623 struct sci_port *s = to_sci_port(port);
624
625 if (s->cfg->port_reg <= 0)
626 return 1;
627
0dd4d5cb 628 /* Cast for ARM damage */
e2afca69 629 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 630}
631
1da177e4
LT		 632/* ********************************************************************** *
633 * the interrupt related routines *
634 * ********************************************************************** */
635
636static void sci_transmit_chars(struct uart_port *port)
637{
ebd2c8f6 638 struct circ_buf *xmit = &port->state->xmit;
1da177e4 639 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 640 unsigned short status;
641 unsigned short ctrl;
e108b2ca 642 int count;
1da177e4 643
b12bb29f 644 status = serial_port_in(port, SCxSR);
1da177e4 645 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 646 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 647 if (uart_circ_empty(xmit))
8e698614 648 ctrl &= ~SCSCR_TIE;
e7c98dc7 649 else
8e698614 650 ctrl |= SCSCR_TIE;
b12bb29f 651 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 652 return;
653 }
654
72b294cf 655 count = sci_txroom(port);
1da177e4
LT		 656
657 do {
658 unsigned char c;
659
660 if (port->x_char) {
661 c = port->x_char;
662 port->x_char = 0;
663 } else if (!uart_circ_empty(xmit) && !stopped) {
664 c = xmit->buf[xmit->tail];
665 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
666 } else {
667 break;
668 }
669
b12bb29f 670 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 671
672 port->icount.tx++;
673 } while (--count > 0);
674
a1b5b43f 675 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 676
677 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
678 uart_write_wakeup(port);
679 if (uart_circ_empty(xmit)) {
b129a8cc 680 sci_stop_tx(port);
1da177e4 681 } else {
b12bb29f 682 ctrl = serial_port_in(port, SCSCR);
1da177e4 683
1a22f08d 684 if (port->type != PORT_SCI) {
b12bb29f 685 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 686 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 687 }
1da177e4 688
8e698614 689 ctrl |= SCSCR_TIE;
b12bb29f 690 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 691 }
692}
693
694/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 695#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 696
94c8b6db 697static void sci_receive_chars(struct uart_port *port)
1da177e4 698{
e7c98dc7 699 struct sci_port *sci_port = to_sci_port(port);
227434f8 700 struct tty_port *tport = &port->state->port;
1da177e4
LT		 701 int i, count, copied = 0;
702 unsigned short status;
33f0f88f 703 unsigned char flag;
1da177e4 704
b12bb29f 705 status = serial_port_in(port, SCxSR);
1da177e4
LT		 706 if (!(status & SCxSR_RDxF(port)))
707 return;
708
709 while (1) {
1da177e4 710 /* Don't copy more bytes than there is room for in the buffer */
227434f8 711 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 712
713 /* If for any reason we can't copy more data, we're done! */
714 if (count == 0)
715 break;
716
717 if (port->type == PORT_SCI) {
b12bb29f 718 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 719 if (uart_handle_sysrq_char(port, c) ||
720 sci_port->break_flag)
1da177e4 721 count = 0;
e7c98dc7 722 else
92a19f9c 723 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 724 } else {
e7c98dc7 725 for (i = 0; i < count; i++) {
b12bb29f 726 char c = serial_port_in(port, SCxRDR);
d97fbbed 727
b12bb29f 728 status = serial_port_in(port, SCxSR);
1da177e4
LT		 729#if defined(CONFIG_CPU_SH3)
730 /* Skip "chars" during break */
e108b2ca 731 if (sci_port->break_flag) {
1da177e4
LT		 732 if ((c == 0) &&
733 (status & SCxSR_FER(port))) {
734 count--; i--;
735 continue;
736 }
e108b2ca 737
1da177e4 738 /* Nonzero => end-of-break */
762c69e3 739 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 740 sci_port->break_flag = 0;
741
1da177e4
LT		 742 if (STEPFN(c)) {
743 count--; i--;
744 continue;
745 }
746 }
747#endif /* CONFIG_CPU_SH3 */
7d12e780 748 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 749 count--; i--;
750 continue;
751 }
752
753 /* Store data and status */
73a19e4c 754 if (status & SCxSR_FER(port)) {
33f0f88f 755 flag = TTY_FRAME;
d97fbbed 756 port->icount.frame++;
762c69e3 757 dev_notice(port->dev, "frame error\n");
73a19e4c 758 } else if (status & SCxSR_PER(port)) {
33f0f88f 759 flag = TTY_PARITY;
d97fbbed 760 port->icount.parity++;
762c69e3 761 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 762 } else
763 flag = TTY_NORMAL;
762c69e3 764
92a19f9c 765 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 766 }
767 }
768
b12bb29f 769 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 770 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 771
1da177e4
LT		 772 copied += count;
773 port->icount.rx += count;
774 }
775
776 if (copied) {
777 /* Tell the rest of the system the news. New characters! */
2e124b4a 778 tty_flip_buffer_push(tport);
1da177e4 779 } else {
b12bb29f 780 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 781 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 782 }
783}
784
785#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 786
787/*
788 * The sci generates interrupts during the break,
1da177e4
LT		 789 * 1 per millisecond or so during the break period, for 9600 baud.
790 * So dont bother disabling interrupts.
791 * But dont want more than 1 break event.
792 * Use a kernel timer to periodically poll the rx line until
793 * the break is finished.
794 */
94c8b6db 795static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 796{
bc9b3f5c 797 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 798}
94c8b6db 799
1da177e4
LT		 800/* Ensure that two consecutive samples find the break over. */
801static void sci_break_timer(unsigned long data)
802{
e108b2ca
PM		 803 struct sci_port *port = (struct sci_port *)data;
804
805 if (sci_rxd_in(&port->port) == 0) {
1da177e4 806 port->break_flag = 1;
e108b2ca
PM		 807 sci_schedule_break_timer(port);
808 } else if (port->break_flag == 1) {
1da177e4
LT		 809 /* break is over. */
810 port->break_flag = 2;
e108b2ca
PM		 811 sci_schedule_break_timer(port);
812 } else
813 port->break_flag = 0;
1da177e4
LT		 814}
815
94c8b6db 816static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 817{
818 int copied = 0;
b12bb29f 819 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 820 struct tty_port *tport = &port->state->port;
debf9507 821 struct sci_port *s = to_sci_port(port);
1da177e4 822
3ae988d9 823 /* Handle overruns */
75c249fd 824 if (status & s->overrun_mask) {
3ae988d9 825 port->icount.overrun++;
d97fbbed 826
3ae988d9
LP		 827 /* overrun error */
828 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
829 copied++;
762c69e3 830
9b971cd2 831 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 832 }
833
e108b2ca 834 if (status & SCxSR_FER(port)) {
1da177e4
LT		 835 if (sci_rxd_in(port) == 0) {
836 /* Notify of BREAK */
e7c98dc7 837 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 838
839 if (!sci_port->break_flag) {
d97fbbed
PM		 840 port->icount.brk++;
841
e108b2ca
PM		 842 sci_port->break_flag = 1;
843 sci_schedule_break_timer(sci_port);
844
1da177e4 845 /* Do sysrq handling. */
e108b2ca 846 if (uart_handle_break(port))
1da177e4 847 return 0;
762c69e3
PM		 848
849 dev_dbg(port->dev, "BREAK detected\n");
850
92a19f9c 851 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 852 copied++;
853 }
854
e108b2ca 855 } else {
1da177e4 856 /* frame error */
d97fbbed
PM		 857 port->icount.frame++;
858
92a19f9c 859 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 860 copied++;
762c69e3
PM		 861
862 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 863 }
864 }
865
e108b2ca 866 if (status & SCxSR_PER(port)) {
1da177e4 867 /* parity error */
d97fbbed
PM		 868 port->icount.parity++;
869
92a19f9c 870 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 871 copied++;
762c69e3 872
9b971cd2 873 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 874 }
875
33f0f88f 876 if (copied)
2e124b4a 877 tty_flip_buffer_push(tport);
1da177e4
LT		 878
879 return copied;
880}
881
94c8b6db 882static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 883{
92a19f9c 884 struct tty_port *tport = &port->state->port;
debf9507 885 struct sci_port *s = to_sci_port(port);
d3184e68 886 const struct plat_sci_reg *reg;
2e0842a1 887 int copied = 0;
75c249fd 888 u16 status;
d830fa45 889
2e0842a1 890 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 891 if (!reg->size)
d830fa45
PM		 892 return 0;
893
2e0842a1 894 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 895 if (status & s->overrun_mask) {
896 status &= ~s->overrun_mask;
2e0842a1 897 serial_port_out(port, s->overrun_reg, status);
d830fa45 898
d97fbbed
PM		 899 port->icount.overrun++;
900
92a19f9c 901 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 902 tty_flip_buffer_push(tport);
d830fa45 903
51b31f1c 904 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 905 copied++;
906 }
907
908 return copied;
909}
910
94c8b6db 911static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 912{
913 int copied = 0;
b12bb29f 914 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 915 struct tty_port *tport = &port->state->port;
a5660ada 916 struct sci_port *s = to_sci_port(port);
1da177e4 917
0b3d4ef6
PM		 918 if (uart_handle_break(port))
919 return 0;
920
b7a76e4b 921 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 922#if defined(CONFIG_CPU_SH3)
923 /* Debounce break */
924 s->break_flag = 1;
925#endif
d97fbbed
PM		 926
927 port->icount.brk++;
928
1da177e4 929 /* Notify of BREAK */
92a19f9c 930 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 931 copied++;
762c69e3
PM		 932
933 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 934 }
935
33f0f88f 936 if (copied)
2e124b4a 937 tty_flip_buffer_push(tport);
e108b2ca 938
d830fa45
PM		 939 copied += sci_handle_fifo_overrun(port);
940
1da177e4
LT		 941 return copied;
942}
943
73a19e4c 944static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 945{
73a19e4c
GL		 946#ifdef CONFIG_SERIAL_SH_SCI_DMA
947 struct uart_port *port = ptr;
948 struct sci_port *s = to_sci_port(port);
949
950 if (s->chan_rx) {
b12bb29f
PM		 951 u16 scr = serial_port_in(port, SCSCR);
952 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 953
954 /* Disable future Rx interrupts */
d1d4b10c 955 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 956 disable_irq_nosync(irq);
26de4f1b 957 scr |= SCSCR_RDRQE;
3089f381 958 } else {
f43dc23d 959 scr &= ~SCSCR_RIE;
3089f381 960 }
b12bb29f 961 serial_port_out(port, SCSCR, scr);
73a19e4c 962 /* Clear current interrupt */
54af5001
GU		 963 serial_port_out(port, SCxSR,
964 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
3089f381
GL		 965 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
966 jiffies, s->rx_timeout);
967 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 968
969 return IRQ_HANDLED;
970 }
971#endif
972
1da177e4
LT		 973 /* I think sci_receive_chars has to be called irrespective
974 * of whether the I_IXOFF is set, otherwise, how is the interrupt
975 * to be disabled?
976 */
73a19e4c 977 sci_receive_chars(ptr);
1da177e4
LT		 978
979 return IRQ_HANDLED;
980}
981
7d12e780 982static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 983{
984 struct uart_port *port = ptr;
fd78a76a 985 unsigned long flags;
1da177e4 986
fd78a76a 987 spin_lock_irqsave(&port->lock, flags);
1da177e4 988 sci_transmit_chars(port);
fd78a76a 989 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 990
991 return IRQ_HANDLED;
992}
993
7d12e780 994static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 995{
996 struct uart_port *port = ptr;
997
998 /* Handle errors */
999 if (port->type == PORT_SCI) {
1000 if (sci_handle_errors(port)) {
1001 /* discard character in rx buffer */
b12bb29f 1002 serial_port_in(port, SCxSR);
a1b5b43f 1003 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 1004 }
1005 } else {
d830fa45 1006 sci_handle_fifo_overrun(port);
7d12e780 1007 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 1008 }
1009
a1b5b43f 1010 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 1011
1012 /* Kick the transmission */
7d12e780 1013 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 1014
1015 return IRQ_HANDLED;
1016}
1017
7d12e780 1018static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 1019{
1020 struct uart_port *port = ptr;
1021
1022 /* Handle BREAKs */
1023 sci_handle_breaks(port);
a1b5b43f 1024 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 1025
1026 return IRQ_HANDLED;
1027}
1028
f43dc23d
PM		 1029static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1030{
1031 /*
1032 * Not all ports (such as SCIFA) will support REIE. Rather than
1033 * special-casing the port type, we check the port initialization
1034 * IRQ enable mask to see whether the IRQ is desired at all. If
1035 * it's unset, it's logically inferred that there's no point in
1036 * testing for it.
1037 */
ce6738b6 1038 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 1039}
1040
7d12e780 1041static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 1042{
cb772fe7 1043 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
a8884e34 1044 struct uart_port *port = ptr;
73a19e4c 1045 struct sci_port *s = to_sci_port(port);
a8884e34 1046 irqreturn_t ret = IRQ_NONE;
1da177e4 1047
b12bb29f
PM		 1048 ssr_status = serial_port_in(port, SCxSR);
1049 scr_status = serial_port_in(port, SCSCR);
2e0842a1 1050 if (s->overrun_reg == SCxSR)
cb772fe7 1051 orer_status = ssr_status;
2e0842a1
GU		 1052 else {
1053 if (sci_getreg(port, s->overrun_reg)->size)
1054 orer_status = serial_port_in(port, s->overrun_reg);
cb772fe7
NI		 1055 }
1056
f43dc23d 1057 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 1058
1059 /* Tx Interrupt */
f43dc23d 1060 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 1061 !s->chan_tx)
a8884e34 1062 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 1063
73a19e4c
GL		 1064 /*
1065 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1066 * DR flags
1067 */
1068 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
8b6ff84c
HN		 1069 (scr_status & SCSCR_RIE)) {
1070 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1071 sci_handle_fifo_overrun(port);
a8884e34 1072 ret = sci_rx_interrupt(irq, ptr);
8b6ff84c 1073 }
f43dc23d 1074
1da177e4 1075 /* Error Interrupt */
dd4da3a5 1076 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1077 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1078
1da177e4 1079 /* Break Interrupt */
dd4da3a5 1080 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1081 ret = sci_br_interrupt(irq, ptr);
1da177e4 1082
8b6ff84c 1083 /* Overrun Interrupt */
75c249fd 1084 if (orer_status & s->overrun_mask)
cb772fe7 1085 sci_handle_fifo_overrun(port);
8b6ff84c 1086
a8884e34 1087 return ret;
1da177e4
LT		 1088}
1089
1da177e4 1090/*
25985edc 1091 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1092 * ports' baud rate when the peripheral clock changes.
1093 */
e108b2ca
PM		 1094static int sci_notifier(struct notifier_block *self,
1095 unsigned long phase, void *p)
1da177e4 1096{
e552de24
MD		 1097 struct sci_port *sci_port;
1098 unsigned long flags;
1da177e4 1099
d535a230
PM		 1100 sci_port = container_of(self, struct sci_port, freq_transition);
1101
0b443ead 1102 if (phase == CPUFREQ_POSTCHANGE) {
d535a230 1103 struct uart_port *port = &sci_port->port;
073e84c9 1104
d535a230
PM		 1105 spin_lock_irqsave(&port->lock, flags);
1106 port->uartclk = clk_get_rate(sci_port->iclk);
1107 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1108 }
1da177e4 1109
1da177e4
LT		 1110 return NOTIFY_OK;
1111}
501b825d 1112
d56a91e8 1113static const struct sci_irq_desc {
9174fc8f
PM		 1114 const char *desc;
1115 irq_handler_t handler;
1116} sci_irq_desc[] = {
1117 /*
1118 * Split out handlers, the default case.
1119 */
1120 [SCIx_ERI_IRQ] = {
1121 .desc = "rx err",
1122 .handler = sci_er_interrupt,
1123 },
1124
1125 [SCIx_RXI_IRQ] = {
1126 .desc = "rx full",
1127 .handler = sci_rx_interrupt,
1128 },
1129
1130 [SCIx_TXI_IRQ] = {
1131 .desc = "tx empty",
1132 .handler = sci_tx_interrupt,
1133 },
1134
1135 [SCIx_BRI_IRQ] = {
1136 .desc = "break",
1137 .handler = sci_br_interrupt,
1138 },
1139
1140 /*
1141 * Special muxed handler.
1142 */
1143 [SCIx_MUX_IRQ] = {
1144 .desc = "mux",
1145 .handler = sci_mpxed_interrupt,
1146 },
1147};
1148
1da177e4
LT		 1149static int sci_request_irq(struct sci_port *port)
1150{
9174fc8f
PM		 1151 struct uart_port *up = &port->port;
1152 int i, j, ret = 0;
1153
1154 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
d56a91e8 1155 const struct sci_irq_desc *desc;
1fcc91a6 1156 int irq;
9174fc8f
PM		 1157
1158 if (SCIx_IRQ_IS_MUXED(port)) {
1159 i = SCIx_MUX_IRQ;
1160 irq = up->irq;
0e8963de 1161 } else {
1fcc91a6 1162 irq = port->irqs[i];
9174fc8f 1163
0e8963de
PM		 1164 /*
1165 * Certain port types won't support all of the
1166 * available interrupt sources.
1167 */
1fcc91a6 1168 if (unlikely(irq < 0))
0e8963de
PM		 1169 continue;
1170 }
1171
9174fc8f
PM		 1172 desc = sci_irq_desc + i;
1173 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1174 dev_name(up->dev), desc->desc);
1175 if (!port->irqstr[j]) {
1176 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1177 desc->desc);
1178 goto out_nomem;
1da177e4 1179 }
9174fc8f
PM		 1180
1181 ret = request_irq(irq, desc->handler, up->irqflags,
1182 port->irqstr[j], port);
1183 if (unlikely(ret)) {
1184 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1185 goto out_noirq;
1da177e4
LT		 1186 }
1187 }
1188
1189 return 0;
9174fc8f
PM		 1190
1191out_noirq:
1192 while (--i >= 0)
1fcc91a6 1193 free_irq(port->irqs[i], port);
9174fc8f
PM		 1194
1195out_nomem:
1196 while (--j >= 0)
1197 kfree(port->irqstr[j]);
1198
1199 return ret;
1da177e4
LT		 1200}
1201
1202static void sci_free_irq(struct sci_port *port)
1203{
1204 int i;
1205
9174fc8f
PM		 1206 /*
1207 * Intentionally in reverse order so we iterate over the muxed
1208 * IRQ first.
1209 */
1210 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1211 int irq = port->irqs[i];
0e8963de
PM		 1212
1213 /*
1214 * Certain port types won't support all of the available
1215 * interrupt sources.
1216 */
1fcc91a6 1217 if (unlikely(irq < 0))
0e8963de
PM		 1218 continue;
1219
1fcc91a6 1220 free_irq(port->irqs[i], port);
9174fc8f 1221 kfree(port->irqstr[i]);
1da177e4 1222
9174fc8f
PM		 1223 if (SCIx_IRQ_IS_MUXED(port)) {
1224 /* If there's only one IRQ, we're done. */
1225 return;
1da177e4
LT		 1226 }
1227 }
1228}
1229
1230static unsigned int sci_tx_empty(struct uart_port *port)
1231{
b12bb29f 1232 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1233 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1234
1235 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1236}
1237
cdf7c42f
PM		 1238/*
1239 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1240 * CTS/RTS is supported in hardware by at least one port and controlled
1241 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1242 * handled via the ->init_pins() op, which is a bit of a one-way street,
1243 * lacking any ability to defer pin control -- this will later be
1244 * converted over to the GPIO framework).
dc7e3ef7
PM		 1245 *
1246 * Other modes (such as loopback) are supported generically on certain
1247 * port types, but not others. For these it's sufficient to test for the
1248 * existence of the support register and simply ignore the port type.
cdf7c42f 1249 */
1da177e4
LT		 1250static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1251{
dc7e3ef7 1252 if (mctrl & TIOCM_LOOP) {
d3184e68 1253 const struct plat_sci_reg *reg;
dc7e3ef7
PM		 1254
1255 /*
1256 * Standard loopback mode for SCFCR ports.
1257 */
1258 reg = sci_getreg(port, SCFCR);
1259 if (reg->size)
26de4f1b
GU		 1260 serial_port_out(port, SCFCR,
1261 serial_port_in(port, SCFCR) |
1262 SCFCR_LOOP);
dc7e3ef7 1263 }
1da177e4
LT		 1264}
1265
1266static unsigned int sci_get_mctrl(struct uart_port *port)
1267{
cdf7c42f
PM		 1268 /*
1269 * CTS/RTS is handled in hardware when supported, while nothing
1270 * else is wired up. Keep it simple and simply assert DSR/CAR.
1271 */
1272 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1273}
1274
73a19e4c
GL		 1275#ifdef CONFIG_SERIAL_SH_SCI_DMA
1276static void sci_dma_tx_complete(void *arg)
1277{
1278 struct sci_port *s = arg;
1279 struct uart_port *port = &s->port;
1280 struct circ_buf *xmit = &port->state->xmit;
1281 unsigned long flags;
1282
1283 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1284
1285 spin_lock_irqsave(&port->lock, flags);
1286
f354a381 1287 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1288 xmit->tail &= UART_XMIT_SIZE - 1;
1289
f354a381 1290 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1291
1292 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1293 s->desc_tx = NULL;
1294
73a19e4c
GL		 1295 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1296 uart_write_wakeup(port);
1297
3089f381 1298 if (!uart_circ_empty(xmit)) {
49d4bcad 1299 s->cookie_tx = 0;
73a19e4c 1300 schedule_work(&s->work_tx);
49d4bcad
YT		 1301 } else {
1302 s->cookie_tx = -EINVAL;
1303 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1304 u16 ctrl = serial_port_in(port, SCSCR);
1305 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1306 }
3089f381
GL		 1307 }
1308
1309 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1310}
1311
1312/* Locking: called with port lock held */
92a19f9c 1313static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1314{
1315 struct uart_port *port = &s->port;
227434f8 1316 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1317 int i, active, room;
1318
227434f8 1319 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1320
1321 if (s->active_rx == s->cookie_rx[0]) {
1322 active = 0;
1323 } else if (s->active_rx == s->cookie_rx[1]) {
1324 active = 1;
1325 } else {
1326 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1327 return 0;
1328 }
1329
1330 if (room < count)
e2afca69 1331 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1332 count - room);
1333 if (!room)
1334 return room;
1335
1336 for (i = 0; i < room; i++)
92a19f9c 1337 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1338 TTY_NORMAL);
1339
1340 port->icount.rx += room;
1341
1342 return room;
1343}
1344
1345static void sci_dma_rx_complete(void *arg)
1346{
1347 struct sci_port *s = arg;
1348 struct uart_port *port = &s->port;
73a19e4c
GL		 1349 unsigned long flags;
1350 int count;
1351
9b971cd2
JP		 1352 dev_dbg(port->dev, "%s(%d) active #%d\n",
1353 __func__, port->line, s->active_rx);
73a19e4c
GL		 1354
1355 spin_lock_irqsave(&port->lock, flags);
1356
92a19f9c 1357 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1358
3089f381 1359 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1360
1361 spin_unlock_irqrestore(&port->lock, flags);
1362
1363 if (count)
2e124b4a 1364 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1365
1366 schedule_work(&s->work_rx);
1367}
1368
73a19e4c
GL		 1369static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1370{
1371 struct dma_chan *chan = s->chan_rx;
1372 struct uart_port *port = &s->port;
73a19e4c
GL		 1373
1374 s->chan_rx = NULL;
1375 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1376 dma_release_channel(chan);
85b8e3ff
GL		 1377 if (sg_dma_address(&s->sg_rx[0]))
1378 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1379 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1380 if (enable_pio)
1381 sci_start_rx(port);
1382}
1383
1384static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1385{
1386 struct dma_chan *chan = s->chan_tx;
1387 struct uart_port *port = &s->port;
73a19e4c
GL		 1388
1389 s->chan_tx = NULL;
1390 s->cookie_tx = -EINVAL;
1391 dma_release_channel(chan);
1392 if (enable_pio)
1393 sci_start_tx(port);
1394}
1395
1396static void sci_submit_rx(struct sci_port *s)
1397{
1398 struct dma_chan *chan = s->chan_rx;
1399 int i;
1400
1401 for (i = 0; i < 2; i++) {
1402 struct scatterlist *sg = &s->sg_rx[i];
1403 struct dma_async_tx_descriptor *desc;
1404
16052827 1405 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1406 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1407
1408 if (desc) {
1409 s->desc_rx[i] = desc;
1410 desc->callback = sci_dma_rx_complete;
1411 desc->callback_param = s;
1412 s->cookie_rx[i] = desc->tx_submit(desc);
1413 }
1414
1415 if (!desc || s->cookie_rx[i] < 0) {
1416 if (i) {
1417 async_tx_ack(s->desc_rx[0]);
1418 s->cookie_rx[0] = -EINVAL;
1419 }
1420 if (desc) {
1421 async_tx_ack(desc);
1422 s->cookie_rx[i] = -EINVAL;
1423 }
1424 dev_warn(s->port.dev,
1425 "failed to re-start DMA, using PIO\n");
1426 sci_rx_dma_release(s, true);
1427 return;
1428 }
9b971cd2
JP		 1429 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1430 __func__, s->cookie_rx[i], i);
73a19e4c
GL		 1431 }
1432
1433 s->active_rx = s->cookie_rx[0];
1434
1435 dma_async_issue_pending(chan);
1436}
1437
1438static void work_fn_rx(struct work_struct *work)
1439{
1440 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1441 struct uart_port *port = &s->port;
1442 struct dma_async_tx_descriptor *desc;
1443 int new;
1444
1445 if (s->active_rx == s->cookie_rx[0]) {
1446 new = 0;
1447 } else if (s->active_rx == s->cookie_rx[1]) {
1448 new = 1;
1449 } else {
1450 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1451 return;
1452 }
1453 desc = s->desc_rx[new];
1454
1455 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1456 DMA_COMPLETE) {
73a19e4c 1457 /* Handle incomplete DMA receive */
73a19e4c 1458 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1459 struct shdma_desc *sh_desc = container_of(desc,
1460 struct shdma_desc, async_tx);
73a19e4c
GL		 1461 unsigned long flags;
1462 int count;
1463
2bcd90d5 1464 dmaengine_terminate_all(chan);
e2afca69 1465 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1466 sh_desc->partial, sh_desc->cookie);
1467
1468 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1469 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1470 spin_unlock_irqrestore(&port->lock, flags);
1471
1472 if (count)
2e124b4a 1473 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1474
1475 sci_submit_rx(s);
1476
1477 return;
1478 }
1479
1480 s->cookie_rx[new] = desc->tx_submit(desc);
1481 if (s->cookie_rx[new] < 0) {
1482 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1483 sci_rx_dma_release(s, true);
1484 return;
1485 }
1486
73a19e4c 1487 s->active_rx = s->cookie_rx[!new];
3089f381 1488
9b971cd2
JP		 1489 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1490 __func__, s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1491}
1492
1493static void work_fn_tx(struct work_struct *work)
1494{
1495 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1496 struct dma_async_tx_descriptor *desc;
1497 struct dma_chan *chan = s->chan_tx;
1498 struct uart_port *port = &s->port;
1499 struct circ_buf *xmit = &port->state->xmit;
1500 struct scatterlist *sg = &s->sg_tx;
1501
1502 /*
1503 * DMA is idle now.
1504 * Port xmit buffer is already mapped, and it is one page... Just adjust
1505 * offsets and lengths. Since it is a circular buffer, we have to
1506 * transmit till the end, and then the rest. Take the port lock to get a
1507 * consistent xmit buffer state.
1508 */
1509 spin_lock_irq(&port->lock);
1510 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1511 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1512 sg->offset;
f354a381 1513 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1514 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1515 spin_unlock_irq(&port->lock);
1516
f354a381 1517 BUG_ON(!sg_dma_len(sg));
73a19e4c 1518
16052827 1519 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1520 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1521 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1522 if (!desc) {
1523 /* switch to PIO */
1524 sci_tx_dma_release(s, true);
1525 return;
1526 }
1527
1528 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1529
1530 spin_lock_irq(&port->lock);
1531 s->desc_tx = desc;
1532 desc->callback = sci_dma_tx_complete;
1533 desc->callback_param = s;
1534 spin_unlock_irq(&port->lock);
1535 s->cookie_tx = desc->tx_submit(desc);
1536 if (s->cookie_tx < 0) {
1537 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1538 /* switch to PIO */
1539 sci_tx_dma_release(s, true);
1540 return;
1541 }
1542
9b971cd2
JP		 1543 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1544 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c
GL		 1545
1546 dma_async_issue_pending(chan);
1547}
1548#endif
1549
b129a8cc 1550static void sci_start_tx(struct uart_port *port)
1da177e4 1551{
3089f381 1552 struct sci_port *s = to_sci_port(port);
e108b2ca 1553 unsigned short ctrl;
1da177e4 1554
73a19e4c 1555#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1556 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1557 u16 new, scr = serial_port_in(port, SCSCR);
3089f381 1558 if (s->chan_tx)
26de4f1b 1559 new = scr | SCSCR_TDRQE;
3089f381 1560 else
26de4f1b 1561 new = scr & ~SCSCR_TDRQE;
3089f381 1562 if (new != scr)
b12bb29f 1563 serial_port_out(port, SCSCR, new);
73a19e4c 1564 }
f43dc23d 1565
3089f381 1566 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1567 s->cookie_tx < 0) {
1568 s->cookie_tx = 0;
3089f381 1569 schedule_work(&s->work_tx);
49d4bcad 1570 }
73a19e4c 1571#endif
f43dc23d 1572
d1d4b10c 1573 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1574 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1575 ctrl = serial_port_in(port, SCSCR);
1576 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1577 }
1da177e4
LT		 1578}
1579
b129a8cc 1580static void sci_stop_tx(struct uart_port *port)
1da177e4 1581{
1da177e4
LT		 1582 unsigned short ctrl;
1583
1584 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1585 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1586
d1d4b10c 1587 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1588 ctrl &= ~SCSCR_TDRQE;
f43dc23d 1589
8e698614 1590 ctrl &= ~SCSCR_TIE;
f43dc23d 1591
b12bb29f 1592 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1593}
1594
73a19e4c 1595static void sci_start_rx(struct uart_port *port)
1da177e4 1596{
1da177e4
LT		 1597 unsigned short ctrl;
1598
b12bb29f 1599 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1600
d1d4b10c 1601 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1602 ctrl &= ~SCSCR_RDRQE;
f43dc23d 1603
b12bb29f 1604 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1605}
1606
1607static void sci_stop_rx(struct uart_port *port)
1608{
1da177e4
LT		 1609 unsigned short ctrl;
1610
b12bb29f 1611 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1612
d1d4b10c 1613 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1614 ctrl &= ~SCSCR_RDRQE;
f43dc23d
PM		 1615
1616 ctrl &= ~port_rx_irq_mask(port);
1617
b12bb29f 1618 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1619}
1620
1da177e4
LT		 1621static void sci_break_ctl(struct uart_port *port, int break_state)
1622{
bbb4ce50 1623 struct sci_port *s = to_sci_port(port);
d3184e68 1624 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1625 unsigned short scscr, scsptr;
1626
a4e02f6d
SY		 1627 /* check wheter the port has SCSPTR */
1628 if (!reg->size) {
bbb4ce50
SY		 1629 /*
1630 * Not supported by hardware. Most parts couple break and rx
1631 * interrupts together, with break detection always enabled.
1632 */
a4e02f6d 1633 return;
bbb4ce50 1634 }
a4e02f6d
SY		 1635
1636 scsptr = serial_port_in(port, SCSPTR);
1637 scscr = serial_port_in(port, SCSCR);
1638
1639 if (break_state == -1) {
1640 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1641 scscr &= ~SCSCR_TE;
1642 } else {
1643 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1644 scscr |= SCSCR_TE;
1645 }
1646
1647 serial_port_out(port, SCSPTR, scsptr);
1648 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1649}
1650
73a19e4c
GL		 1651#ifdef CONFIG_SERIAL_SH_SCI_DMA
1652static bool filter(struct dma_chan *chan, void *slave)
1653{
1654 struct sh_dmae_slave *param = slave;
1655
9b971cd2
JP		 1656 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1657 __func__, param->shdma_slave.slave_id);
73a19e4c 1658
d6fa5a4e 1659 chan->private = &param->shdma_slave;
937bb6e4 1660 return true;
73a19e4c
GL		 1661}
1662
1663static void rx_timer_fn(unsigned long arg)
1664{
1665 struct sci_port *s = (struct sci_port *)arg;
1666 struct uart_port *port = &s->port;
b12bb29f 1667 u16 scr = serial_port_in(port, SCSCR);
3089f381 1668
d1d4b10c 1669 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
26de4f1b 1670 scr &= ~SCSCR_RDRQE;
1fcc91a6 1671 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1672 }
b12bb29f 1673 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1674 dev_dbg(port->dev, "DMA Rx timed out\n");
1675 schedule_work(&s->work_rx);
1676}
1677
1678static void sci_request_dma(struct uart_port *port)
1679{
1680 struct sci_port *s = to_sci_port(port);
1681 struct sh_dmae_slave *param;
1682 struct dma_chan *chan;
1683 dma_cap_mask_t mask;
1684 int nent;
1685
9b971cd2 1686 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1687
937bb6e4 1688 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1689 return;
1690
1691 dma_cap_zero(mask);
1692 dma_cap_set(DMA_SLAVE, mask);
1693
1694 param = &s->param_tx;
1695
1696 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1697 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1698
1699 s->cookie_tx = -EINVAL;
1700 chan = dma_request_channel(mask, filter, param);
1701 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1702 if (chan) {
1703 s->chan_tx = chan;
1704 sg_init_table(&s->sg_tx, 1);
1705 /* UART circular tx buffer is an aligned page. */
e2afca69 1706 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1707 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1708 UART_XMIT_SIZE,
1709 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1710 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1711 if (!nent)
1712 sci_tx_dma_release(s, false);
1713 else
9b971cd2
JP		 1714 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1715 __func__,
e2afca69
LP		 1716 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1717 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1718
1719 s->sg_len_tx = nent;
1720
1721 INIT_WORK(&s->work_tx, work_fn_tx);
1722 }
1723
1724 param = &s->param_rx;
1725
1726 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1727 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1728
1729 chan = dma_request_channel(mask, filter, param);
1730 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1731 if (chan) {
1732 dma_addr_t dma[2];
1733 void *buf[2];
1734 int i;
1735
1736 s->chan_rx = chan;
1737
1738 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1739 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1740 &dma[0], GFP_KERNEL);
1741
1742 if (!buf[0]) {
1743 dev_warn(port->dev,
1744 "failed to allocate dma buffer, using PIO\n");
1745 sci_rx_dma_release(s, true);
1746 return;
1747 }
1748
1749 buf[1] = buf[0] + s->buf_len_rx;
1750 dma[1] = dma[0] + s->buf_len_rx;
1751
1752 for (i = 0; i < 2; i++) {
1753 struct scatterlist *sg = &s->sg_rx[i];
1754
1755 sg_init_table(sg, 1);
1756 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1757 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1758 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1759 }
1760
1761 INIT_WORK(&s->work_rx, work_fn_rx);
1762 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1763
1764 sci_submit_rx(s);
1765 }
1766}
1767
1768static void sci_free_dma(struct uart_port *port)
1769{
1770 struct sci_port *s = to_sci_port(port);
1771
73a19e4c
GL		 1772 if (s->chan_tx)
1773 sci_tx_dma_release(s, false);
1774 if (s->chan_rx)
1775 sci_rx_dma_release(s, false);
1776}
27bd1075
PM		 1777#else
1778static inline void sci_request_dma(struct uart_port *port)
1779{
1780}
1781
1782static inline void sci_free_dma(struct uart_port *port)
1783{
1784}
73a19e4c
GL		 1785#endif
1786
1da177e4
LT		 1787static int sci_startup(struct uart_port *port)
1788{
a5660ada 1789 struct sci_port *s = to_sci_port(port);
33b48e16 1790 unsigned long flags;
073e84c9 1791 int ret;
1da177e4 1792
73a19e4c
GL		 1793 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1794
073e84c9
PM		 1795 ret = sci_request_irq(s);
1796 if (unlikely(ret < 0))
1797 return ret;
1798
73a19e4c 1799 sci_request_dma(port);
073e84c9 1800
33b48e16 1801 spin_lock_irqsave(&port->lock, flags);
d656901b 1802 sci_start_tx(port);
73a19e4c 1803 sci_start_rx(port);
33b48e16 1804 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1805
1806 return 0;
1807}
1808
1809static void sci_shutdown(struct uart_port *port)
1810{
a5660ada 1811 struct sci_port *s = to_sci_port(port);
33b48e16 1812 unsigned long flags;
1da177e4 1813
73a19e4c
GL		 1814 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1815
33b48e16 1816 spin_lock_irqsave(&port->lock, flags);
1da177e4 1817 sci_stop_rx(port);
b129a8cc 1818 sci_stop_tx(port);
33b48e16 1819 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1820
73a19e4c 1821 sci_free_dma(port);
1da177e4 1822 sci_free_irq(s);
1da177e4
LT		 1823}
1824
ec09c5eb 1825static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1826 unsigned long freq)
1827{
ec09c5eb
LP		 1828 if (s->sampling_rate)
1829 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1830
26c92f37
PM		 1831 /* Warn, but use a safe default */
1832 WARN_ON(1);
e8183a6c 1833
26c92f37
PM		 1834 return ((freq + 16 * bps) / (32 * bps) - 1);
1835}
1836
730c4e78
NI		 1837/* calculate frame length from SMR */
1838static int sci_baud_calc_frame_len(unsigned int smr_val)
1839{
1840 int len = 10;
1841
1842 if (smr_val & SCSMR_CHR)
1843 len--;
1844 if (smr_val & SCSMR_PE)
1845 len++;
1846 if (smr_val & SCSMR_STOP)
1847 len++;
1848
1849 return len;
1850}
1851
1852
f303b364
UH		 1853/* calculate sample rate, BRR, and clock select for HSCIF */
1854static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1855 int *brr, unsigned int *srr,
730c4e78 1856 unsigned int *cks, int frame_len)
f303b364 1857{
730c4e78 1858 int sr, c, br, err, recv_margin;
f303b364 1859 int min_err = 1000; /* 100% */
730c4e78 1860 int recv_max_margin = 0;
f303b364
UH		 1861
1862 /* Find the combination of sample rate and clock select with the
1863 smallest deviation from the desired baud rate. */
1864 for (sr = 8; sr <= 32; sr++) {
1865 for (c = 0; c <= 3; c++) {
1866 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1867 br = DIV_ROUND_CLOSEST(freq, (sr *
1868 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1869 br = clamp(br, 0, 255);
b7d66397
NI		 1870 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1871 (1 << (2 * c + 1)) / 1000)) -
1872 1000;
730c4e78
NI		 1873 /* Calc recv margin
1874 * M: Receive margin (%)
1875 * N: Ratio of bit rate to clock (N = sampling rate)
1876 * D: Clock duty (D = 0 to 1.0)
1877 * L: Frame length (L = 9 to 12)
1878 * F: Absolute value of clock frequency deviation
1879 *
1880 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1881 * (|D - 0.5| / N * (1 + F))|
1882 * NOTE: Usually, treat D for 0.5, F is 0 by this
1883 * calculation.
1884 */
1885 recv_margin = abs((500 -
1886 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1887 if (abs(min_err) > abs(err)) {
f303b364 1888 min_err = err;
730c4e78
NI		 1889 recv_max_margin = recv_margin;
1890 } else if ((min_err == err) &&
1891 (recv_margin > recv_max_margin))
1892 recv_max_margin = recv_margin;
1893 else
1894 continue;
1895
1896 *brr = br;
1897 *srr = sr - 1;
1898 *cks = c;
f303b364
UH		 1899 }
1900 }
1901
1902 if (min_err == 1000) {
1903 WARN_ON(1);
1904 /* use defaults */
1905 *brr = 255;
1906 *srr = 15;
1907 *cks = 0;
1908 }
1909}
1910
1ba76220
MD		 1911static void sci_reset(struct uart_port *port)
1912{
d3184e68 1913 const struct plat_sci_reg *reg;
1ba76220
MD		 1914 unsigned int status;
1915
1916 do {
b12bb29f 1917 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1918 } while (!(status & SCxSR_TEND(port)));
1919
b12bb29f 1920 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1921
0979e0e6
PM		 1922 reg = sci_getreg(port, SCFCR);
1923 if (reg->size)
b12bb29f 1924 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1925}
1926
606d099c
AC		 1927static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1928 struct ktermios *old)
1da177e4 1929{
00b9de9c 1930 struct sci_port *s = to_sci_port(port);
d3184e68 1931 const struct plat_sci_reg *reg;
730c4e78 1932 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1933 int t = -1;
d4759ded 1934 unsigned int srr = 15;
1da177e4 1935
730c4e78
NI		 1936 if ((termios->c_cflag & CSIZE) == CS7)
1937 smr_val |= SCSMR_CHR;
1938 if (termios->c_cflag & PARENB)
1939 smr_val |= SCSMR_PE;
1940 if (termios->c_cflag & PARODD)
1941 smr_val |= SCSMR_PE | SCSMR_ODD;
1942 if (termios->c_cflag & CSTOPB)
1943 smr_val |= SCSMR_STOP;
1944
154280fd
MD		 1945 /*
1946 * earlyprintk comes here early on with port->uartclk set to zero.
1947 * the clock framework is not up and running at this point so here
1948 * we assume that 115200 is the maximum baud rate. please note that
1949 * the baud rate is not programmed during earlyprintk - it is assumed
1950 * that the previous boot loader has enabled required clocks and
1951 * setup the baud rate generator hardware for us already.
1952 */
1953 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1954
154280fd 1955 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1956 if (likely(baud && port->uartclk)) {
ec09c5eb 1957 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1958 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1959 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1960 &cks, frame_len);
f303b364 1961 } else {
ec09c5eb 1962 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1963 for (cks = 0; t >= 256 && cks <= 3; cks++)
1964 t >>= 2;
1965 }
1966 }
e108b2ca 1967
23241d43 1968 sci_port_enable(s);
36003386 1969
1ba76220 1970 sci_reset(port);
1da177e4 1971
2944a331 1972 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 1973
1974 uart_update_timeout(port, termios->c_cflag, baud);
1975
9d482cc3
TY		 1976 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1977 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1978
4ffc3cdb 1979 if (t >= 0) {
26de4f1b 1980 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1981 serial_port_out(port, SCBRR, t);
f303b364
UH		 1982 reg = sci_getreg(port, HSSRR);
1983 if (reg->size)
1984 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1985 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1986 } else
1987 serial_port_out(port, SCSMR, smr_val);
1da177e4 1988
d5701647 1989 sci_init_pins(port, termios->c_cflag);
0979e0e6 1990
73c3d53f
PM		 1991 reg = sci_getreg(port, SCFCR);
1992 if (reg->size) {
b12bb29f 1993 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1994
73c3d53f 1995 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1996 if (termios->c_cflag & CRTSCTS)
1997 ctrl |= SCFCR_MCE;
1998 else
1999 ctrl &= ~SCFCR_MCE;
faf02f8f 2000 }
73c3d53f
PM		 2001
2002 /*
2003 * As we've done a sci_reset() above, ensure we don't
2004 * interfere with the FIFOs while toggling MCE. As the
2005 * reset values could still be set, simply mask them out.
2006 */
2007 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2008
b12bb29f 2009 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2010 }
b7a76e4b 2011
b12bb29f 2012 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2013
3089f381
GL		 2014#ifdef CONFIG_SERIAL_SH_SCI_DMA
2015 /*
5f6d8515 2016 * Calculate delay for 2 DMA buffers (4 FIFO).
b933bd32 2017 * See serial_core.c::uart_update_timeout(). With 10
5f6d8515 2018 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
3089f381 2019 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
5f6d8515
NI		 2020 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
2021 * sizes), but when performing a faster transfer, value obtained by
2022 * this formula is may not enough. Therefore, if value is smaller than
2023 * 20msec, this sets 20msec as timeout of DMA.
3089f381
GL		 2024 */
2025 if (s->chan_rx) {
5f6d8515
NI		 2026 unsigned int bits;
2027
2028 /* byte size and parity */
2029 switch (termios->c_cflag & CSIZE) {
2030 case CS5:
2031 bits = 7;
2032 break;
2033 case CS6:
2034 bits = 8;
2035 break;
2036 case CS7:
2037 bits = 9;
2038 break;
2039 default:
2040 bits = 10;
2041 break;
2042 }
2043
2044 if (termios->c_cflag & CSTOPB)
2045 bits++;
2046 if (termios->c_cflag & PARENB)
2047 bits++;
2048 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2049 (baud / 10), 10);
9b971cd2 2050 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2051 s->rx_timeout * 1000 / HZ, port->timeout);
2052 if (s->rx_timeout < msecs_to_jiffies(20))
2053 s->rx_timeout = msecs_to_jiffies(20);
2054 }
2055#endif
2056
1da177e4 2057 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2058 sci_start_rx(port);
36003386 2059
23241d43 2060 sci_port_disable(s);
1da177e4
LT		 2061}
2062
0174e5ca
TK		 2063static void sci_pm(struct uart_port *port, unsigned int state,
2064 unsigned int oldstate)
2065{
2066 struct sci_port *sci_port = to_sci_port(port);
2067
2068 switch (state) {
d3dfe5d9 2069 case UART_PM_STATE_OFF:
0174e5ca
TK		 2070 sci_port_disable(sci_port);
2071 break;
2072 default:
2073 sci_port_enable(sci_port);
2074 break;
2075 }
2076}
2077
1da177e4
LT		 2078static const char *sci_type(struct uart_port *port)
2079{
2080 switch (port->type) {
e7c98dc7
MT		 2081 case PORT_IRDA:
2082 return "irda";
2083 case PORT_SCI:
2084 return "sci";
2085 case PORT_SCIF:
2086 return "scif";
2087 case PORT_SCIFA:
2088 return "scifa";
d1d4b10c
GL		 2089 case PORT_SCIFB:
2090 return "scifb";
f303b364
UH		 2091 case PORT_HSCIF:
2092 return "hscif";
1da177e4
LT		 2093 }
2094
fa43972f 2095 return NULL;
1da177e4
LT		 2096}
2097
f6e9495d
PM		 2098static int sci_remap_port(struct uart_port *port)
2099{
e4d6f911 2100 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2101
2102 /*
2103 * Nothing to do if there's already an established membase.
2104 */
2105 if (port->membase)
2106 return 0;
2107
2108 if (port->flags & UPF_IOREMAP) {
e4d6f911 2109 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2110 if (unlikely(!port->membase)) {
2111 dev_err(port->dev, "can't remap port#%d\n", port->line);
2112 return -ENXIO;
2113 }
2114 } else {
2115 /*
2116 * For the simple (and majority of) cases where we don't
2117 * need to do any remapping, just cast the cookie
2118 * directly.
2119 */
3af4e960 2120 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2121 }
2122
2123 return 0;
2124}
2125
e2651647 2126static void sci_release_port(struct uart_port *port)
1da177e4 2127{
e4d6f911
YS		 2128 struct sci_port *sport = to_sci_port(port);
2129
e2651647
PM		 2130 if (port->flags & UPF_IOREMAP) {
2131 iounmap(port->membase);
2132 port->membase = NULL;
2133 }
2134
e4d6f911 2135 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2136}
2137
e2651647 2138static int sci_request_port(struct uart_port *port)
1da177e4 2139{
e2651647 2140 struct resource *res;
e4d6f911 2141 struct sci_port *sport = to_sci_port(port);
f6e9495d 2142 int ret;
1da177e4 2143
e4d6f911
YS		 2144 res = request_mem_region(port->mapbase, sport->reg_size,
2145 dev_name(port->dev));
2146 if (unlikely(res == NULL)) {
2147 dev_err(port->dev, "request_mem_region failed.");
e2651647 2148 return -EBUSY;
e4d6f911 2149 }
1da177e4 2150
f6e9495d
PM		 2151 ret = sci_remap_port(port);
2152 if (unlikely(ret != 0)) {
2153 release_resource(res);
2154 return ret;
7ff731ae 2155 }
e2651647
PM		 2156
2157 return 0;
2158}
2159
2160static void sci_config_port(struct uart_port *port, int flags)
2161{
2162 if (flags & UART_CONFIG_TYPE) {
2163 struct sci_port *sport = to_sci_port(port);
2164
2165 port->type = sport->cfg->type;
2166 sci_request_port(port);
2167 }
1da177e4
LT		 2168}
2169
2170static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2171{
1da177e4
LT		 2172 if (ser->baud_base < 2400)
2173 /* No paper tape reader for Mitch.. */
2174 return -EINVAL;
2175
2176 return 0;
2177}
2178
2179static struct uart_ops sci_uart_ops = {
2180 .tx_empty = sci_tx_empty,
2181 .set_mctrl = sci_set_mctrl,
2182 .get_mctrl = sci_get_mctrl,
2183 .start_tx = sci_start_tx,
2184 .stop_tx = sci_stop_tx,
2185 .stop_rx = sci_stop_rx,
1da177e4
LT		 2186 .break_ctl = sci_break_ctl,
2187 .startup = sci_startup,
2188 .shutdown = sci_shutdown,
2189 .set_termios = sci_set_termios,
0174e5ca 2190 .pm = sci_pm,
1da177e4
LT		 2191 .type = sci_type,
2192 .release_port = sci_release_port,
2193 .request_port = sci_request_port,
2194 .config_port = sci_config_port,
2195 .verify_port = sci_verify_port,
07d2a1a1
PM		 2196#ifdef CONFIG_CONSOLE_POLL
2197 .poll_get_char = sci_poll_get_char,
2198 .poll_put_char = sci_poll_put_char,
2199#endif
1da177e4
LT		 2200};
2201
9671f099 2202static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2203 struct sci_port *sci_port, unsigned int index,
2204 struct plat_sci_port *p, bool early)
e108b2ca 2205{
73a19e4c 2206 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2207 const struct resource *res;
2208 unsigned int i;
3127c6b2 2209 int ret;
e108b2ca 2210
50f0959a
PM		 2211 sci_port->cfg = p;
2212
73a19e4c
GL		 2213 port->ops = &sci_uart_ops;
2214 port->iotype = UPIO_MEM;
2215 port->line = index;
75136d48 2216
89b5c1ab
LP		 2217 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2218 if (res == NULL)
2219 return -ENOMEM;
1fcc91a6 2220
89b5c1ab 2221 port->mapbase = res->start;
e4d6f911 2222 sci_port->reg_size = resource_size(res);
1fcc91a6 2223
89b5c1ab
LP		 2224 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2225 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2226
89b5c1ab
LP		 2227 /* The SCI generates several interrupts. They can be muxed together or
2228 * connected to different interrupt lines. In the muxed case only one
2229 * interrupt resource is specified. In the non-muxed case three or four
2230 * interrupt resources are specified, as the BRI interrupt is optional.
2231 */
2232 if (sci_port->irqs[0] < 0)
2233 return -ENXIO;
1fcc91a6 2234
89b5c1ab
LP		 2235 if (sci_port->irqs[1] < 0) {
2236 sci_port->irqs[1] = sci_port->irqs[0];
2237 sci_port->irqs[2] = sci_port->irqs[0];
2238 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2239 }
2240
b545e4f4
LP		 2241 if (p->regtype == SCIx_PROBE_REGTYPE) {
2242 ret = sci_probe_regmap(p);
2243 if (unlikely(ret))
2244 return ret;
2245 }
2246
75136d48 2247 switch (p->type) {
d1d4b10c
GL		 2248 case PORT_SCIFB:
2249 port->fifosize = 256;
2e0842a1 2250 sci_port->overrun_reg = SCxSR;
75c249fd 2251 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2252 sci_port->sampling_rate = 16;
d1d4b10c 2253 break;
f303b364
UH		 2254 case PORT_HSCIF:
2255 port->fifosize = 128;
2e0842a1 2256 sci_port->overrun_reg = SCLSR;
75c249fd 2257 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2258 sci_port->sampling_rate = 0;
f303b364 2259 break;
75136d48 2260 case PORT_SCIFA:
73a19e4c 2261 port->fifosize = 64;
2e0842a1 2262 sci_port->overrun_reg = SCxSR;
75c249fd 2263 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2264 sci_port->sampling_rate = 16;
75136d48
MP		 2265 break;
2266 case PORT_SCIF:
73a19e4c 2267 port->fifosize = 16;
ec09c5eb 2268 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2269 sci_port->overrun_reg = SCxSR;
75c249fd 2270 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2271 sci_port->sampling_rate = 16;
ec09c5eb 2272 } else {
2e0842a1 2273 sci_port->overrun_reg = SCLSR;
75c249fd 2274 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2275 sci_port->sampling_rate = 32;
ec09c5eb 2276 }
75136d48
MP		 2277 break;
2278 default:
73a19e4c 2279 port->fifosize = 1;
2e0842a1 2280 sci_port->overrun_reg = SCxSR;
75c249fd 2281 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2282 sci_port->sampling_rate = 32;
75136d48
MP		 2283 break;
2284 }
7b6fd3bf 2285
878fbb91
LP		 2286 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2287 * match the SoC datasheet, this should be investigated. Let platform
2288 * data override the sampling rate for now.
ec09c5eb 2289 */
f84b6bdc
GU		 2290 if (p->sampling_rate)
2291 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2292
1fcc91a6 2293 if (!early) {
c7ed1ab3
PM		 2294 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2295 if (IS_ERR(sci_port->iclk)) {
2296 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2297 if (IS_ERR(sci_port->iclk)) {
2298 dev_err(&dev->dev, "can't get iclk\n");
2299 return PTR_ERR(sci_port->iclk);
2300 }
2301 }
2302
2303 /*
2304 * The function clock is optional, ignore it if we can't
2305 * find it.
2306 */
2307 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2308 if (IS_ERR(sci_port->fclk))
2309 sci_port->fclk = NULL;
2310
73a19e4c 2311 port->dev = &dev->dev;
5e50d2d6
MD		 2312
2313 pm_runtime_enable(&dev->dev);
7b6fd3bf 2314 }
e108b2ca 2315
7ed7e071
MD		 2316 sci_port->break_timer.data = (unsigned long)sci_port;
2317 sci_port->break_timer.function = sci_break_timer;
2318 init_timer(&sci_port->break_timer);
2319
debf9507
PM		 2320 /*
2321 * Establish some sensible defaults for the error detection.
2322 */
5da0f468
GU		 2323 if (p->type == PORT_SCI) {
2324 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2325 sci_port->error_clear = SCI_ERROR_CLEAR;
2326 } else {
2327 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2328 sci_port->error_clear = SCIF_ERROR_CLEAR;
2329 }
debf9507 2330
3ae988d9
LP		 2331 /*
2332 * Make the error mask inclusive of overrun detection, if
2333 * supported.
2334 */
5da0f468 2335 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2336 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2337 sci_port->error_clear &= ~sci_port->overrun_mask;
2338 }
debf9507 2339
ce6738b6 2340 port->type = p->type;
b6e4a3f1 2341 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2342 port->regshift = p->regshift;
73a19e4c 2343
ce6738b6 2344 /*
61a6976b 2345 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2346 * for the multi-IRQ ports, which is where we are primarily
2347 * concerned with the shutdown path synchronization.
2348 *
2349 * For the muxed case there's nothing more to do.
2350 */
1fcc91a6 2351 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2352 port->irqflags = 0;
73a19e4c 2353
61a6976b
PM		 2354 port->serial_in = sci_serial_in;
2355 port->serial_out = sci_serial_out;
2356
937bb6e4
GL		 2357 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2358 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2359 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2360
c7ed1ab3 2361 return 0;
e108b2ca
PM		 2362}
2363
6dae1421
LP		 2364static void sci_cleanup_single(struct sci_port *port)
2365{
6dae1421
LP		 2366 clk_put(port->iclk);
2367 clk_put(port->fclk);
2368
2369 pm_runtime_disable(port->port.dev);
2370}
2371
1da177e4 2372#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2373static void serial_console_putchar(struct uart_port *port, int ch)
2374{
2375 sci_poll_put_char(port, ch);
2376}
2377
1da177e4
LT		 2378/*
2379 * Print a string to the serial port trying not to disturb
2380 * any possible real use of the port...
2381 */
2382static void serial_console_write(struct console *co, const char *s,
2383 unsigned count)
2384{
906b17dc
PM		 2385 struct sci_port *sci_port = &sci_ports[co->index];
2386 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2387 unsigned short bits, ctrl;
2388 unsigned long flags;
2389 int locked = 1;
2390
2391 local_irq_save(flags);
2392 if (port->sysrq)
2393 locked = 0;
2394 else if (oops_in_progress)
2395 locked = spin_trylock(&port->lock);
2396 else
2397 spin_lock(&port->lock);
2398
2399 /* first save the SCSCR then disable the interrupts */
2400 ctrl = serial_port_in(port, SCSCR);
2401 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2402
501b825d 2403 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2404
2405 /* wait until fifo is empty and last bit has been transmitted */
2406 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2407 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2408 cpu_relax();
40f70c03
SK		 2409
2410 /* restore the SCSCR */
2411 serial_port_out(port, SCSCR, ctrl);
2412
2413 if (locked)
2414 spin_unlock(&port->lock);
2415 local_irq_restore(flags);
1da177e4
LT		 2416}
2417
9671f099 2418static int serial_console_setup(struct console *co, char *options)
1da177e4 2419{
dc8e6f5b 2420 struct sci_port *sci_port;
1da177e4
LT		 2421 struct uart_port *port;
2422 int baud = 115200;
2423 int bits = 8;
2424 int parity = 'n';
2425 int flow = 'n';
2426 int ret;
2427
e108b2ca 2428 /*
906b17dc 2429 * Refuse to handle any bogus ports.
1da177e4 2430 */
906b17dc 2431 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2432 return -ENODEV;
e108b2ca 2433
906b17dc
PM		 2434 sci_port = &sci_ports[co->index];
2435 port = &sci_port->port;
2436
b2267a6b
AC		 2437 /*
2438 * Refuse to handle uninitialized ports.
2439 */
2440 if (!port->ops)
2441 return -ENODEV;
2442
f6e9495d
PM		 2443 ret = sci_remap_port(port);
2444 if (unlikely(ret != 0))
2445 return ret;
e108b2ca 2446
1da177e4
LT		 2447 if (options)
2448 uart_parse_options(options, &baud, &parity, &bits, &flow);
2449
ab7cfb55 2450 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2451}
2452
2453static struct console serial_console = {
2454 .name = "ttySC",
906b17dc 2455 .device = uart_console_device,
1da177e4
LT		 2456 .write = serial_console_write,
2457 .setup = serial_console_setup,
fa5da2f7 2458 .flags = CON_PRINTBUFFER,
1da177e4 2459 .index = -1,
906b17dc 2460 .data = &sci_uart_driver,
1da177e4
LT		 2461};
2462
7b6fd3bf
MD		 2463static struct console early_serial_console = {
2464 .name = "early_ttySC",
2465 .write = serial_console_write,
2466 .flags = CON_PRINTBUFFER,
906b17dc 2467 .index = -1,
7b6fd3bf 2468};
ecdf8a46 2469
7b6fd3bf
MD		 2470static char early_serial_buf[32];
2471
9671f099 2472static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2473{
574de559 2474 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2475
2476 if (early_serial_console.data)
2477 return -EEXIST;
2478
2479 early_serial_console.index = pdev->id;
ecdf8a46 2480
1fcc91a6 2481 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2482
2483 serial_console_setup(&early_serial_console, early_serial_buf);
2484
2485 if (!strstr(early_serial_buf, "keep"))
2486 early_serial_console.flags |= CON_BOOT;
2487
2488 register_console(&early_serial_console);
2489 return 0;
2490}
6a8c9799
NI		 2491
2492#define SCI_CONSOLE (&serial_console)
2493
ecdf8a46 2494#else
9671f099 2495static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2496{
2497 return -EINVAL;
2498}
1da177e4 2499
6a8c9799
NI		 2500#define SCI_CONSOLE NULL
2501
2502#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2503
6c13d5d2 2504static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2505
2506static struct uart_driver sci_uart_driver = {
2507 .owner = THIS_MODULE,
2508 .driver_name = "sci",
1da177e4
LT		 2509 .dev_name = "ttySC",
2510 .major = SCI_MAJOR,
2511 .minor = SCI_MINOR_START,
e108b2ca 2512 .nr = SCI_NPORTS,
1da177e4
LT		 2513 .cons = SCI_CONSOLE,
2514};
2515
54507f6e 2516static int sci_remove(struct platform_device *dev)
e552de24 2517{
d535a230 2518 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2519
d535a230
PM		 2520 cpufreq_unregister_notifier(&port->freq_transition,
2521 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2522
d535a230
PM		 2523 uart_remove_one_port(&sci_uart_driver, &port->port);
2524
6dae1421 2525 sci_cleanup_single(port);
e552de24 2526
e552de24
MD		 2527 return 0;
2528}
2529
20bdcab8
BH		 2530struct sci_port_info {
2531 unsigned int type;
2532 unsigned int regtype;
2533};
2534
2535static const struct of_device_id of_sci_match[] = {
2536 {
2537 .compatible = "renesas,scif",
ff43da00 2538 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2539 .type = PORT_SCIF,
2540 .regtype = SCIx_SH4_SCIF_REGTYPE,
2541 },
2542 }, {
2543 .compatible = "renesas,scifa",
ff43da00 2544 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2545 .type = PORT_SCIFA,
2546 .regtype = SCIx_SCIFA_REGTYPE,
2547 },
2548 }, {
2549 .compatible = "renesas,scifb",
ff43da00 2550 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2551 .type = PORT_SCIFB,
2552 .regtype = SCIx_SCIFB_REGTYPE,
2553 },
2554 }, {
2555 .compatible = "renesas,hscif",
ff43da00 2556 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2557 .type = PORT_HSCIF,
2558 .regtype = SCIx_HSCIF_REGTYPE,
2559 },
e1d0be61
YS		 2560 }, {
2561 .compatible = "renesas,sci",
2562 .data = &(const struct sci_port_info) {
2563 .type = PORT_SCI,
2564 .regtype = SCIx_SCI_REGTYPE,
2565 },
20bdcab8
BH		 2566 }, {
2567 /* Terminator */
2568 },
2569};
2570MODULE_DEVICE_TABLE(of, of_sci_match);
2571
2572static struct plat_sci_port *
2573sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2574{
2575 struct device_node *np = pdev->dev.of_node;
2576 const struct of_device_id *match;
2577 const struct sci_port_info *info;
2578 struct plat_sci_port *p;
2579 int id;
2580
2581 if (!IS_ENABLED(CONFIG_OF) || !np)
2582 return NULL;
2583
2584 match = of_match_node(of_sci_match, pdev->dev.of_node);
2585 if (!match)
2586 return NULL;
2587
2588 info = match->data;
2589
2590 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2591 if (!p) {
2592 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2593 return NULL;
2594 }
2595
2596 /* Get the line number for the aliases node. */
2597 id = of_alias_get_id(np, "serial");
2598 if (id < 0) {
2599 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2600 return NULL;
2601 }
2602
2603 *dev_id = id;
2604
2605 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2606 p->type = info->type;
2607 p->regtype = info->regtype;
2608 p->scscr = SCSCR_RE | SCSCR_TE;
2609
2610 return p;
2611}
2612
9671f099 2613static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2614 unsigned int index,
2615 struct plat_sci_port *p,
2616 struct sci_port *sciport)
2617{
0ee70712
MD		 2618 int ret;
2619
2620 /* Sanity check */
2621 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2622 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2623 index+1, SCI_NPORTS);
9b971cd2 2624 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2625 return -EINVAL;
0ee70712
MD		 2626 }
2627
1fcc91a6 2628 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2629 if (ret)
2630 return ret;
0ee70712 2631
6dae1421
LP		 2632 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2633 if (ret) {
2634 sci_cleanup_single(sciport);
2635 return ret;
2636 }
2637
2638 return 0;
0ee70712
MD		 2639}
2640
9671f099 2641static int sci_probe(struct platform_device *dev)
1da177e4 2642{
20bdcab8
BH		 2643 struct plat_sci_port *p;
2644 struct sci_port *sp;
2645 unsigned int dev_id;
ecdf8a46 2646 int ret;
d535a230 2647
ecdf8a46
PM		 2648 /*
2649 * If we've come here via earlyprintk initialization, head off to
2650 * the special early probe. We don't have sufficient device state
2651 * to make it beyond this yet.
2652 */
2653 if (is_early_platform_device(dev))
2654 return sci_probe_earlyprintk(dev);
7b6fd3bf 2655
20bdcab8
BH		 2656 if (dev->dev.of_node) {
2657 p = sci_parse_dt(dev, &dev_id);
2658 if (p == NULL)
2659 return -EINVAL;
2660 } else {
2661 p = dev->dev.platform_data;
2662 if (p == NULL) {
2663 dev_err(&dev->dev, "no platform data supplied\n");
2664 return -EINVAL;
2665 }
2666
2667 dev_id = dev->id;
2668 }
2669
2670 sp = &sci_ports[dev_id];
d535a230 2671 platform_set_drvdata(dev, sp);
e552de24 2672
20bdcab8 2673 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2674 if (ret)
6dae1421 2675 return ret;
e552de24 2676
d535a230 2677 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2678
d535a230
PM		 2679 ret = cpufreq_register_notifier(&sp->freq_transition,
2680 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2681 if (unlikely(ret < 0)) {
bf13c9a8 2682 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2683 sci_cleanup_single(sp);
2684 return ret;
2685 }
1da177e4
LT		 2686
2687#ifdef CONFIG_SH_STANDARD_BIOS
2688 sh_bios_gdb_detach();
2689#endif
2690
e108b2ca 2691 return 0;
1da177e4
LT		 2692}
2693
cb876341 2694static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2695{
d535a230 2696 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2697
d535a230
PM		 2698 if (sport)
2699 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2700
e108b2ca
PM		 2701 return 0;
2702}
1da177e4 2703
cb876341 2704static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2705{
d535a230 2706 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2707
d535a230
PM		 2708 if (sport)
2709 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2710
2711 return 0;
2712}
2713
cb876341 2714static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2715
e108b2ca
PM		 2716static struct platform_driver sci_driver = {
2717 .probe = sci_probe,
b9e39c89 2718 .remove = sci_remove,
e108b2ca
PM		 2719 .driver = {
2720 .name = "sh-sci",
6daa79b3 2721 .pm = &sci_dev_pm_ops,
20bdcab8 2722 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2723 },
2724};
2725
2726static int __init sci_init(void)
2727{
2728 int ret;
2729
6c13d5d2 2730 pr_info("%s\n", banner);
e108b2ca 2731
e108b2ca
PM		 2732 ret = uart_register_driver(&sci_uart_driver);
2733 if (likely(ret == 0)) {
2734 ret = platform_driver_register(&sci_driver);
2735 if (unlikely(ret))
2736 uart_unregister_driver(&sci_uart_driver);
2737 }
2738
2739 return ret;
2740}
2741
2742static void __exit sci_exit(void)
2743{
2744 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2745 uart_unregister_driver(&sci_uart_driver);
2746}
2747
7b6fd3bf
MD		 2748#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2749early_platform_init_buffer("earlyprintk", &sci_driver,
2750 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2751#endif
1da177e4
LT		 2752module_init(sci_init);
2753module_exit(sci_exit);
2754
e108b2ca 2755MODULE_LICENSE("GPL");
e169c139 2756MODULE_ALIAS("platform:sh-sci");
7f405f9c 2757MODULE_AUTHOR("Paul Mundt");
f303b364 2758MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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