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TTY: move low_latency to tty_port
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
4dc4c516 28#include <linux/sh_dma.h>
1da177e4
LT		 29#include <linux/timer.h>
30#include <linux/interrupt.h>
31#include <linux/tty.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/sysrq.h>
1da177e4
LT		 37#include <linux/ioport.h>
38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/console.h>
e108b2ca 42#include <linux/platform_device.h>
96de1a8f 43#include <linux/serial_sci.h>
1da177e4 44#include <linux/notifier.h>
5e50d2d6 45#include <linux/pm_runtime.h>
1da177e4 46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
73a19e4c 50#include <linux/dmaengine.h>
5beabc7f 51#include <linux/dma-mapping.h>
73a19e4c 52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
50f0959a 54#include <linux/gpio.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
e108b2ca
PM		 62struct sci_port {
63 struct uart_port port;
64
ce6738b6
PM		 65 /* Platform configuration */
66 struct plat_sci_port *cfg;
e108b2ca 67
e108b2ca
PM		 68 /* Break timer */
69 struct timer_list break_timer;
70 int break_flag;
1534a3b3 71
501b825d
MD		 72 /* Interface clock */
73 struct clk *iclk;
c7ed1ab3
PM		 74 /* Function clock */
75 struct clk *fclk;
edad1f20 76
9174fc8f 77 char *irqstr[SCIx_NR_IRQS];
50f0959a 78 char *gpiostr[SCIx_NR_FNS];
9174fc8f 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
e108b2ca
PM		 102};
103
1da177e4 104/* Function prototypes */
d535a230 105static void sci_start_tx(struct uart_port *port);
b129a8cc 106static void sci_stop_tx(struct uart_port *port);
d535a230 107static void sci_start_rx(struct uart_port *port);
1da177e4 108
e108b2ca 109#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 110
e108b2ca
PM		 111static struct sci_port sci_ports[SCI_NPORTS];
112static struct uart_driver sci_uart_driver;
1da177e4 113
e7c98dc7
MT		 114static inline struct sci_port *
115to_sci_port(struct uart_port *uart)
116{
117 return container_of(uart, struct sci_port, port);
118}
119
61a6976b
PM		 120struct plat_sci_reg {
121 u8 offset, size;
122};
123
124/* Helper for invalidating specific entries of an inherited map. */
125#define sci_reg_invalid { .offset = 0, .size = 0 }
126
127static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
130 },
131
132 /*
133 * Common SCI definitions, dependent on the port's regshift
134 * value.
135 */
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
149 },
150
151 /*
152 * Common definitions for legacy IrDA ports, dependent on
153 * regshift value.
154 */
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
168 },
169
170 /*
171 * Common SCIFA definitions.
172 */
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 },
187
188 /*
189 * Common SCIFB definitions.
190 */
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 199 [SCFDR] = sci_reg_invalid,
200 [SCTFDR] = { 0x38, 16 },
201 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
204 },
205
3af1f8a4
PE		 206 /*
207 * Common SH-2(A) SCIF definitions for ports with FIFO data
208 * count registers.
209 */
210 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
211 [SCSMR] = { 0x00, 16 },
212 [SCBRR] = { 0x04, 8 },
213 [SCSCR] = { 0x08, 16 },
214 [SCxTDR] = { 0x0c, 8 },
215 [SCxSR] = { 0x10, 16 },
216 [SCxRDR] = { 0x14, 8 },
217 [SCFCR] = { 0x18, 16 },
218 [SCFDR] = { 0x1c, 16 },
219 [SCTFDR] = sci_reg_invalid,
220 [SCRFDR] = sci_reg_invalid,
221 [SCSPTR] = { 0x20, 16 },
222 [SCLSR] = { 0x24, 16 },
223 },
224
61a6976b
PM		 225 /*
226 * Common SH-3 SCIF definitions.
227 */
228 [SCIx_SH3_SCIF_REGTYPE] = {
229 [SCSMR] = { 0x00, 8 },
230 [SCBRR] = { 0x02, 8 },
231 [SCSCR] = { 0x04, 8 },
232 [SCxTDR] = { 0x06, 8 },
233 [SCxSR] = { 0x08, 16 },
234 [SCxRDR] = { 0x0a, 8 },
235 [SCFCR] = { 0x0c, 8 },
236 [SCFDR] = { 0x0e, 16 },
237 [SCTFDR] = sci_reg_invalid,
238 [SCRFDR] = sci_reg_invalid,
239 [SCSPTR] = sci_reg_invalid,
240 [SCLSR] = sci_reg_invalid,
241 },
242
243 /*
244 * Common SH-4(A) SCIF(B) definitions.
245 */
246 [SCIx_SH4_SCIF_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = { 0x20, 16 },
258 [SCLSR] = { 0x24, 16 },
259 },
260
261 /*
262 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
263 * register.
264 */
265 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = { 0x24, 16 },
278 },
279
280 /*
281 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
282 * count registers.
283 */
284 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x0c, 8 },
289 [SCxSR] = { 0x10, 16 },
290 [SCxRDR] = { 0x14, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
294 [SCRFDR] = { 0x20, 16 },
295 [SCSPTR] = { 0x24, 16 },
296 [SCLSR] = { 0x28, 16 },
297 },
298
299 /*
300 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
301 * registers.
302 */
303 [SCIx_SH7705_SCIF_REGTYPE] = {
304 [SCSMR] = { 0x00, 16 },
305 [SCBRR] = { 0x04, 8 },
306 [SCSCR] = { 0x08, 16 },
307 [SCxTDR] = { 0x20, 8 },
308 [SCxSR] = { 0x14, 16 },
309 [SCxRDR] = { 0x24, 8 },
310 [SCFCR] = { 0x18, 16 },
311 [SCFDR] = { 0x1c, 16 },
312 [SCTFDR] = sci_reg_invalid,
313 [SCRFDR] = sci_reg_invalid,
314 [SCSPTR] = sci_reg_invalid,
315 [SCLSR] = sci_reg_invalid,
316 },
317};
318
72b294cf
PM		 319#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
320
61a6976b
PM		 321/*
322 * The "offset" here is rather misleading, in that it refers to an enum
323 * value relative to the port mapping rather than the fixed offset
324 * itself, which needs to be manually retrieved from the platform's
325 * register map for the given port.
326 */
327static unsigned int sci_serial_in(struct uart_port *p, int offset)
328{
72b294cf 329 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 330
331 if (reg->size == 8)
332 return ioread8(p->membase + (reg->offset << p->regshift));
333 else if (reg->size == 16)
334 return ioread16(p->membase + (reg->offset << p->regshift));
335 else
336 WARN(1, "Invalid register access\n");
337
338 return 0;
339}
340
341static void sci_serial_out(struct uart_port *p, int offset, int value)
342{
72b294cf 343 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 344
345 if (reg->size == 8)
346 iowrite8(value, p->membase + (reg->offset << p->regshift));
347 else if (reg->size == 16)
348 iowrite16(value, p->membase + (reg->offset << p->regshift));
349 else
350 WARN(1, "Invalid register access\n");
351}
352
61a6976b
PM		 353static int sci_probe_regmap(struct plat_sci_port *cfg)
354{
355 switch (cfg->type) {
356 case PORT_SCI:
357 cfg->regtype = SCIx_SCI_REGTYPE;
358 break;
359 case PORT_IRDA:
360 cfg->regtype = SCIx_IRDA_REGTYPE;
361 break;
362 case PORT_SCIFA:
363 cfg->regtype = SCIx_SCIFA_REGTYPE;
364 break;
365 case PORT_SCIFB:
366 cfg->regtype = SCIx_SCIFB_REGTYPE;
367 break;
368 case PORT_SCIF:
369 /*
370 * The SH-4 is a bit of a misnomer here, although that's
371 * where this particular port layout originated. This
372 * configuration (or some slight variation thereof)
373 * remains the dominant model for all SCIFs.
374 */
375 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
376 break;
377 default:
378 printk(KERN_ERR "Can't probe register map for given port\n");
379 return -EINVAL;
380 }
381
382 return 0;
383}
384
23241d43
PM		 385static void sci_port_enable(struct sci_port *sci_port)
386{
387 if (!sci_port->port.dev)
388 return;
389
390 pm_runtime_get_sync(sci_port->port.dev);
391
392 clk_enable(sci_port->iclk);
393 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
394 clk_enable(sci_port->fclk);
395}
396
397static void sci_port_disable(struct sci_port *sci_port)
398{
399 if (!sci_port->port.dev)
400 return;
401
402 clk_disable(sci_port->fclk);
403 clk_disable(sci_port->iclk);
404
405 pm_runtime_put_sync(sci_port->port.dev);
406}
407
07d2a1a1 408#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 409
410#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 411static int sci_poll_get_char(struct uart_port *port)
1da177e4 412{
1da177e4
LT		 413 unsigned short status;
414 int c;
415
e108b2ca 416 do {
b12bb29f 417 status = serial_port_in(port, SCxSR);
1da177e4 418 if (status & SCxSR_ERRORS(port)) {
b12bb29f 419 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 420 continue;
421 }
3f255eb3
JW		 422 break;
423 } while (1);
424
425 if (!(status & SCxSR_RDxF(port)))
426 return NO_POLL_CHAR;
07d2a1a1 427
b12bb29f 428 c = serial_port_in(port, SCxRDR);
07d2a1a1 429
e7c98dc7 430 /* Dummy read */
b12bb29f
PM		 431 serial_port_in(port, SCxSR);
432 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 433
434 return c;
435}
1f6fd5c9 436#endif
1da177e4 437
07d2a1a1 438static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 439{
1da177e4
LT		 440 unsigned short status;
441
1da177e4 442 do {
b12bb29f 443 status = serial_port_in(port, SCxSR);
1da177e4
LT		 444 } while (!(status & SCxSR_TDxE(port)));
445
b12bb29f
PM		 446 serial_port_out(port, SCxTDR, c);
447 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 448}
07d2a1a1 449#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 450
61a6976b 451static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 452{
61a6976b
PM		 453 struct sci_port *s = to_sci_port(port);
454 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 455
61a6976b
PM		 456 /*
457 * Use port-specific handler if provided.
458 */
459 if (s->cfg->ops && s->cfg->ops->init_pins) {
460 s->cfg->ops->init_pins(port, cflag);
461 return;
1da177e4 462 }
41504c39 463
61a6976b
PM		 464 /*
465 * For the generic path SCSPTR is necessary. Bail out if that's
466 * unavailable, too.
467 */
468 if (!reg->size)
469 return;
41504c39 470
faf02f8f
PM		 471 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
472 ((!(cflag & CRTSCTS)))) {
473 unsigned short status;
474
b12bb29f 475 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 476 status &= ~SCSPTR_CTSIO;
477 status |= SCSPTR_RTSIO;
b12bb29f 478 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 479 }
d5701647 480}
e108b2ca 481
72b294cf 482static int sci_txfill(struct uart_port *port)
e108b2ca 483{
72b294cf 484 struct plat_sci_reg *reg;
e108b2ca 485
72b294cf
PM		 486 reg = sci_getreg(port, SCTFDR);
487 if (reg->size)
63f7ad11 488 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 489
72b294cf
PM		 490 reg = sci_getreg(port, SCFDR);
491 if (reg->size)
b12bb29f 492 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 493
b12bb29f 494 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 495}
496
73a19e4c
GL		 497static int sci_txroom(struct uart_port *port)
498{
72b294cf 499 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 500}
501
502static int sci_rxfill(struct uart_port *port)
e108b2ca 503{
72b294cf
PM		 504 struct plat_sci_reg *reg;
505
506 reg = sci_getreg(port, SCRFDR);
507 if (reg->size)
63f7ad11 508 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 509
510 reg = sci_getreg(port, SCFDR);
511 if (reg->size)
b12bb29f 512 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 513
b12bb29f 514 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 515}
516
514820eb
PM		 517/*
518 * SCI helper for checking the state of the muxed port/RXD pins.
519 */
520static inline int sci_rxd_in(struct uart_port *port)
521{
522 struct sci_port *s = to_sci_port(port);
523
524 if (s->cfg->port_reg <= 0)
525 return 1;
526
0dd4d5cb
PM		 527 /* Cast for ARM damage */
528 return !!__raw_readb((void __iomem *)s->cfg->port_reg);
514820eb
PM		 529}
530
1da177e4
LT		 531/* ********************************************************************** *
532 * the interrupt related routines *
533 * ********************************************************************** */
534
535static void sci_transmit_chars(struct uart_port *port)
536{
ebd2c8f6 537 struct circ_buf *xmit = &port->state->xmit;
1da177e4 538 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 539 unsigned short status;
540 unsigned short ctrl;
e108b2ca 541 int count;
1da177e4 542
b12bb29f 543 status = serial_port_in(port, SCxSR);
1da177e4 544 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 545 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 546 if (uart_circ_empty(xmit))
8e698614 547 ctrl &= ~SCSCR_TIE;
e7c98dc7 548 else
8e698614 549 ctrl |= SCSCR_TIE;
b12bb29f 550 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 551 return;
552 }
553
72b294cf 554 count = sci_txroom(port);
1da177e4
LT		 555
556 do {
557 unsigned char c;
558
559 if (port->x_char) {
560 c = port->x_char;
561 port->x_char = 0;
562 } else if (!uart_circ_empty(xmit) && !stopped) {
563 c = xmit->buf[xmit->tail];
564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
565 } else {
566 break;
567 }
568
b12bb29f 569 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 570
571 port->icount.tx++;
572 } while (--count > 0);
573
b12bb29f 574 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 575
576 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
577 uart_write_wakeup(port);
578 if (uart_circ_empty(xmit)) {
b129a8cc 579 sci_stop_tx(port);
1da177e4 580 } else {
b12bb29f 581 ctrl = serial_port_in(port, SCSCR);
1da177e4 582
1a22f08d 583 if (port->type != PORT_SCI) {
b12bb29f
PM		 584 serial_port_in(port, SCxSR); /* Dummy read */
585 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 586 }
1da177e4 587
8e698614 588 ctrl |= SCSCR_TIE;
b12bb29f 589 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 590 }
591}
592
593/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 594#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 595
94c8b6db 596static void sci_receive_chars(struct uart_port *port)
1da177e4 597{
e7c98dc7 598 struct sci_port *sci_port = to_sci_port(port);
227434f8
JS		 599 struct tty_port *tport = &port->state->port;
600 struct tty_struct *tty = tport->tty;
1da177e4
LT		 601 int i, count, copied = 0;
602 unsigned short status;
33f0f88f 603 unsigned char flag;
1da177e4 604
b12bb29f 605 status = serial_port_in(port, SCxSR);
1da177e4
LT		 606 if (!(status & SCxSR_RDxF(port)))
607 return;
608
609 while (1) {
1da177e4 610 /* Don't copy more bytes than there is room for in the buffer */
227434f8 611 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 612
613 /* If for any reason we can't copy more data, we're done! */
614 if (count == 0)
615 break;
616
617 if (port->type == PORT_SCI) {
b12bb29f 618 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 619 if (uart_handle_sysrq_char(port, c) ||
620 sci_port->break_flag)
1da177e4 621 count = 0;
e7c98dc7 622 else
92a19f9c 623 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 624 } else {
e7c98dc7 625 for (i = 0; i < count; i++) {
b12bb29f 626 char c = serial_port_in(port, SCxRDR);
d97fbbed 627
b12bb29f 628 status = serial_port_in(port, SCxSR);
1da177e4
LT		 629#if defined(CONFIG_CPU_SH3)
630 /* Skip "chars" during break */
e108b2ca 631 if (sci_port->break_flag) {
1da177e4
LT		 632 if ((c == 0) &&
633 (status & SCxSR_FER(port))) {
634 count--; i--;
635 continue;
636 }
e108b2ca 637
1da177e4 638 /* Nonzero => end-of-break */
762c69e3 639 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 640 sci_port->break_flag = 0;
641
1da177e4
LT		 642 if (STEPFN(c)) {
643 count--; i--;
644 continue;
645 }
646 }
647#endif /* CONFIG_CPU_SH3 */
7d12e780 648 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 649 count--; i--;
650 continue;
651 }
652
653 /* Store data and status */
73a19e4c 654 if (status & SCxSR_FER(port)) {
33f0f88f 655 flag = TTY_FRAME;
d97fbbed 656 port->icount.frame++;
762c69e3 657 dev_notice(port->dev, "frame error\n");
73a19e4c 658 } else if (status & SCxSR_PER(port)) {
33f0f88f 659 flag = TTY_PARITY;
d97fbbed 660 port->icount.parity++;
762c69e3 661 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 662 } else
663 flag = TTY_NORMAL;
762c69e3 664
92a19f9c 665 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 666 }
667 }
668
b12bb29f
PM		 669 serial_port_in(port, SCxSR); /* dummy read */
670 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 671
1da177e4
LT		 672 copied += count;
673 port->icount.rx += count;
674 }
675
676 if (copied) {
677 /* Tell the rest of the system the news. New characters! */
678 tty_flip_buffer_push(tty);
679 } else {
b12bb29f
PM		 680 serial_port_in(port, SCxSR); /* dummy read */
681 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 682 }
683}
684
685#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 686
687/*
688 * The sci generates interrupts during the break,
1da177e4
LT		 689 * 1 per millisecond or so during the break period, for 9600 baud.
690 * So dont bother disabling interrupts.
691 * But dont want more than 1 break event.
692 * Use a kernel timer to periodically poll the rx line until
693 * the break is finished.
694 */
94c8b6db 695static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 696{
bc9b3f5c 697 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 698}
94c8b6db 699
1da177e4
LT		 700/* Ensure that two consecutive samples find the break over. */
701static void sci_break_timer(unsigned long data)
702{
e108b2ca
PM		 703 struct sci_port *port = (struct sci_port *)data;
704
23241d43 705 sci_port_enable(port);
5e50d2d6 706
e108b2ca 707 if (sci_rxd_in(&port->port) == 0) {
1da177e4 708 port->break_flag = 1;
e108b2ca
PM		 709 sci_schedule_break_timer(port);
710 } else if (port->break_flag == 1) {
1da177e4
LT		 711 /* break is over. */
712 port->break_flag = 2;
e108b2ca
PM		 713 sci_schedule_break_timer(port);
714 } else
715 port->break_flag = 0;
5e50d2d6 716
23241d43 717 sci_port_disable(port);
1da177e4
LT		 718}
719
94c8b6db 720static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 721{
722 int copied = 0;
b12bb29f 723 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c
JS		 724 struct tty_port *tport = &port->state->port;
725 struct tty_struct *tty = tport->tty;
debf9507 726 struct sci_port *s = to_sci_port(port);
1da177e4 727
debf9507
PM		 728 /*
729 * Handle overruns, if supported.
730 */
731 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
732 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 733 port->icount.overrun++;
734
debf9507 735 /* overrun error */
92a19f9c 736 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
debf9507 737 copied++;
762c69e3 738
debf9507
PM		 739 dev_notice(port->dev, "overrun error");
740 }
1da177e4
LT		 741 }
742
e108b2ca 743 if (status & SCxSR_FER(port)) {
1da177e4
LT		 744 if (sci_rxd_in(port) == 0) {
745 /* Notify of BREAK */
e7c98dc7 746 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 747
748 if (!sci_port->break_flag) {
d97fbbed
PM		 749 port->icount.brk++;
750
e108b2ca
PM		 751 sci_port->break_flag = 1;
752 sci_schedule_break_timer(sci_port);
753
1da177e4 754 /* Do sysrq handling. */
e108b2ca 755 if (uart_handle_break(port))
1da177e4 756 return 0;
762c69e3
PM		 757
758 dev_dbg(port->dev, "BREAK detected\n");
759
92a19f9c 760 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 761 copied++;
762 }
763
e108b2ca 764 } else {
1da177e4 765 /* frame error */
d97fbbed
PM		 766 port->icount.frame++;
767
92a19f9c 768 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 769 copied++;
762c69e3
PM		 770
771 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 772 }
773 }
774
e108b2ca 775 if (status & SCxSR_PER(port)) {
1da177e4 776 /* parity error */
d97fbbed
PM		 777 port->icount.parity++;
778
92a19f9c 779 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 780 copied++;
762c69e3
PM		 781
782 dev_notice(port->dev, "parity error");
1da177e4
LT		 783 }
784
33f0f88f 785 if (copied)
1da177e4 786 tty_flip_buffer_push(tty);
1da177e4
LT		 787
788 return copied;
789}
790
94c8b6db 791static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 792{
92a19f9c
JS		 793 struct tty_port *tport = &port->state->port;
794 struct tty_struct *tty = tport->tty;
debf9507 795 struct sci_port *s = to_sci_port(port);
4b8c59a3 796 struct plat_sci_reg *reg;
d830fa45
PM		 797 int copied = 0;
798
4b8c59a3
PM		 799 reg = sci_getreg(port, SCLSR);
800 if (!reg->size)
d830fa45
PM		 801 return 0;
802
b12bb29f
PM		 803 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
804 serial_port_out(port, SCLSR, 0);
d830fa45 805
d97fbbed
PM		 806 port->icount.overrun++;
807
92a19f9c 808 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
d830fa45
PM		 809 tty_flip_buffer_push(tty);
810
811 dev_notice(port->dev, "overrun error\n");
812 copied++;
813 }
814
815 return copied;
816}
817
94c8b6db 818static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 819{
820 int copied = 0;
b12bb29f 821 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c
JS		 822 struct tty_port *tport = &port->state->port;
823 struct tty_struct *tty = tport->tty;
a5660ada 824 struct sci_port *s = to_sci_port(port);
1da177e4 825
0b3d4ef6
PM		 826 if (uart_handle_break(port))
827 return 0;
828
b7a76e4b 829 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 830#if defined(CONFIG_CPU_SH3)
831 /* Debounce break */
832 s->break_flag = 1;
833#endif
d97fbbed
PM		 834
835 port->icount.brk++;
836
1da177e4 837 /* Notify of BREAK */
92a19f9c 838 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 839 copied++;
762c69e3
PM		 840
841 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 842 }
843
33f0f88f 844 if (copied)
1da177e4 845 tty_flip_buffer_push(tty);
e108b2ca 846
d830fa45
PM		 847 copied += sci_handle_fifo_overrun(port);
848
1da177e4
LT		 849 return copied;
850}
851
73a19e4c 852static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 853{
73a19e4c
GL		 854#ifdef CONFIG_SERIAL_SH_SCI_DMA
855 struct uart_port *port = ptr;
856 struct sci_port *s = to_sci_port(port);
857
858 if (s->chan_rx) {
b12bb29f
PM		 859 u16 scr = serial_port_in(port, SCSCR);
860 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 861
862 /* Disable future Rx interrupts */
d1d4b10c 863 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 864 disable_irq_nosync(irq);
865 scr |= 0x4000;
866 } else {
f43dc23d 867 scr &= ~SCSCR_RIE;
3089f381 868 }
b12bb29f 869 serial_port_out(port, SCSCR, scr);
73a19e4c 870 /* Clear current interrupt */
b12bb29f 871 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 872 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
873 jiffies, s->rx_timeout);
874 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 875
876 return IRQ_HANDLED;
877 }
878#endif
879
1da177e4
LT		 880 /* I think sci_receive_chars has to be called irrespective
881 * of whether the I_IXOFF is set, otherwise, how is the interrupt
882 * to be disabled?
883 */
73a19e4c 884 sci_receive_chars(ptr);
1da177e4
LT		 885
886 return IRQ_HANDLED;
887}
888
7d12e780 889static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 890{
891 struct uart_port *port = ptr;
fd78a76a 892 unsigned long flags;
1da177e4 893
fd78a76a 894 spin_lock_irqsave(&port->lock, flags);
1da177e4 895 sci_transmit_chars(port);
fd78a76a 896 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 897
898 return IRQ_HANDLED;
899}
900
7d12e780 901static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 902{
903 struct uart_port *port = ptr;
904
905 /* Handle errors */
906 if (port->type == PORT_SCI) {
907 if (sci_handle_errors(port)) {
908 /* discard character in rx buffer */
b12bb29f
PM		 909 serial_port_in(port, SCxSR);
910 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 911 }
912 } else {
d830fa45 913 sci_handle_fifo_overrun(port);
7d12e780 914 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 915 }
916
b12bb29f 917 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 918
919 /* Kick the transmission */
7d12e780 920 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 921
922 return IRQ_HANDLED;
923}
924
7d12e780 925static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 926{
927 struct uart_port *port = ptr;
928
929 /* Handle BREAKs */
930 sci_handle_breaks(port);
b12bb29f 931 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 932
933 return IRQ_HANDLED;
934}
935
f43dc23d
PM		 936static inline unsigned long port_rx_irq_mask(struct uart_port *port)
937{
938 /*
939 * Not all ports (such as SCIFA) will support REIE. Rather than
940 * special-casing the port type, we check the port initialization
941 * IRQ enable mask to see whether the IRQ is desired at all. If
942 * it's unset, it's logically inferred that there's no point in
943 * testing for it.
944 */
ce6738b6 945 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 946}
947
7d12e780 948static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 949{
44e18e9e 950 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 951 struct uart_port *port = ptr;
73a19e4c 952 struct sci_port *s = to_sci_port(port);
a8884e34 953 irqreturn_t ret = IRQ_NONE;
1da177e4 954
b12bb29f
PM		 955 ssr_status = serial_port_in(port, SCxSR);
956 scr_status = serial_port_in(port, SCSCR);
f43dc23d 957 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 958
959 /* Tx Interrupt */
f43dc23d 960 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 961 !s->chan_tx)
a8884e34 962 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 963
73a19e4c
GL		 964 /*
965 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
966 * DR flags
967 */
968 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 969 (scr_status & SCSCR_RIE))
a8884e34 970 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 971
1da177e4 972 /* Error Interrupt */
dd4da3a5 973 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 974 ret = sci_er_interrupt(irq, ptr);
f43dc23d 975
1da177e4 976 /* Break Interrupt */
dd4da3a5 977 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 978 ret = sci_br_interrupt(irq, ptr);
1da177e4 979
a8884e34 980 return ret;
1da177e4
LT		 981}
982
1da177e4 983/*
25985edc 984 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 985 * ports' baud rate when the peripheral clock changes.
986 */
e108b2ca
PM		 987static int sci_notifier(struct notifier_block *self,
988 unsigned long phase, void *p)
1da177e4 989{
e552de24
MD		 990 struct sci_port *sci_port;
991 unsigned long flags;
1da177e4 992
d535a230
PM		 993 sci_port = container_of(self, struct sci_port, freq_transition);
994
1da177e4 995 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 996 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 997 struct uart_port *port = &sci_port->port;
073e84c9 998
d535a230
PM		 999 spin_lock_irqsave(&port->lock, flags);
1000 port->uartclk = clk_get_rate(sci_port->iclk);
1001 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1002 }
1da177e4 1003
1da177e4
LT		 1004 return NOTIFY_OK;
1005}
501b825d 1006
9174fc8f
PM		 1007static struct sci_irq_desc {
1008 const char *desc;
1009 irq_handler_t handler;
1010} sci_irq_desc[] = {
1011 /*
1012 * Split out handlers, the default case.
1013 */
1014 [SCIx_ERI_IRQ] = {
1015 .desc = "rx err",
1016 .handler = sci_er_interrupt,
1017 },
1018
1019 [SCIx_RXI_IRQ] = {
1020 .desc = "rx full",
1021 .handler = sci_rx_interrupt,
1022 },
1023
1024 [SCIx_TXI_IRQ] = {
1025 .desc = "tx empty",
1026 .handler = sci_tx_interrupt,
1027 },
1028
1029 [SCIx_BRI_IRQ] = {
1030 .desc = "break",
1031 .handler = sci_br_interrupt,
1032 },
1033
1034 /*
1035 * Special muxed handler.
1036 */
1037 [SCIx_MUX_IRQ] = {
1038 .desc = "mux",
1039 .handler = sci_mpxed_interrupt,
1040 },
1041};
1042
1da177e4
LT		 1043static int sci_request_irq(struct sci_port *port)
1044{
9174fc8f
PM		 1045 struct uart_port *up = &port->port;
1046 int i, j, ret = 0;
1047
1048 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1049 struct sci_irq_desc *desc;
1050 unsigned int irq;
1051
1052 if (SCIx_IRQ_IS_MUXED(port)) {
1053 i = SCIx_MUX_IRQ;
1054 irq = up->irq;
0e8963de 1055 } else {
9174fc8f
PM		 1056 irq = port->cfg->irqs[i];
1057
0e8963de
PM		 1058 /*
1059 * Certain port types won't support all of the
1060 * available interrupt sources.
1061 */
1062 if (unlikely(!irq))
1063 continue;
1064 }
1065
9174fc8f
PM		 1066 desc = sci_irq_desc + i;
1067 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1068 dev_name(up->dev), desc->desc);
1069 if (!port->irqstr[j]) {
1070 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1071 desc->desc);
1072 goto out_nomem;
1da177e4 1073 }
9174fc8f
PM		 1074
1075 ret = request_irq(irq, desc->handler, up->irqflags,
1076 port->irqstr[j], port);
1077 if (unlikely(ret)) {
1078 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1079 goto out_noirq;
1da177e4
LT		 1080 }
1081 }
1082
1083 return 0;
9174fc8f
PM		 1084
1085out_noirq:
1086 while (--i >= 0)
1087 free_irq(port->cfg->irqs[i], port);
1088
1089out_nomem:
1090 while (--j >= 0)
1091 kfree(port->irqstr[j]);
1092
1093 return ret;
1da177e4
LT		 1094}
1095
1096static void sci_free_irq(struct sci_port *port)
1097{
1098 int i;
1099
9174fc8f
PM		 1100 /*
1101 * Intentionally in reverse order so we iterate over the muxed
1102 * IRQ first.
1103 */
1104 for (i = 0; i < SCIx_NR_IRQS; i++) {
0e8963de
PM		 1105 unsigned int irq = port->cfg->irqs[i];
1106
1107 /*
1108 * Certain port types won't support all of the available
1109 * interrupt sources.
1110 */
1111 if (unlikely(!irq))
1112 continue;
1113
9174fc8f
PM		 1114 free_irq(port->cfg->irqs[i], port);
1115 kfree(port->irqstr[i]);
1da177e4 1116
9174fc8f
PM		 1117 if (SCIx_IRQ_IS_MUXED(port)) {
1118 /* If there's only one IRQ, we're done. */
1119 return;
1da177e4
LT		 1120 }
1121 }
1122}
1123
50f0959a
PM		 1124static const char *sci_gpio_names[SCIx_NR_FNS] = {
1125 "sck", "rxd", "txd", "cts", "rts",
1126};
1127
1128static const char *sci_gpio_str(unsigned int index)
1129{
1130 return sci_gpio_names[index];
1131}
1132
9671f099 1133static void sci_init_gpios(struct sci_port *port)
50f0959a
PM		 1134{
1135 struct uart_port *up = &port->port;
1136 int i;
1137
1138 if (!port->cfg)
1139 return;
1140
1141 for (i = 0; i < SCIx_NR_FNS; i++) {
1142 const char *desc;
1143 int ret;
1144
1145 if (!port->cfg->gpios[i])
1146 continue;
1147
1148 desc = sci_gpio_str(i);
1149
1150 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1151 dev_name(up->dev), desc);
1152
1153 /*
1154 * If we've failed the allocation, we can still continue
1155 * on with a NULL string.
1156 */
1157 if (!port->gpiostr[i])
1158 dev_notice(up->dev, "%s string allocation failure\n",
1159 desc);
1160
1161 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1162 if (unlikely(ret != 0)) {
1163 dev_notice(up->dev, "failed %s gpio request\n", desc);
1164
1165 /*
1166 * If we can't get the GPIO for whatever reason,
1167 * no point in keeping the verbose string around.
1168 */
1169 kfree(port->gpiostr[i]);
1170 }
1171 }
1172}
1173
1174static void sci_free_gpios(struct sci_port *port)
1175{
1176 int i;
1177
1178 for (i = 0; i < SCIx_NR_FNS; i++)
1179 if (port->cfg->gpios[i]) {
1180 gpio_free(port->cfg->gpios[i]);
1181 kfree(port->gpiostr[i]);
1182 }
1183}
1184
1da177e4
LT		 1185static unsigned int sci_tx_empty(struct uart_port *port)
1186{
b12bb29f 1187 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1188 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1189
1190 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1191}
1192
cdf7c42f
PM		 1193/*
1194 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1195 * CTS/RTS is supported in hardware by at least one port and controlled
1196 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1197 * handled via the ->init_pins() op, which is a bit of a one-way street,
1198 * lacking any ability to defer pin control -- this will later be
1199 * converted over to the GPIO framework).
dc7e3ef7
PM		 1200 *
1201 * Other modes (such as loopback) are supported generically on certain
1202 * port types, but not others. For these it's sufficient to test for the
1203 * existence of the support register and simply ignore the port type.
cdf7c42f 1204 */
1da177e4
LT		 1205static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1206{
dc7e3ef7
PM		 1207 if (mctrl & TIOCM_LOOP) {
1208 struct plat_sci_reg *reg;
1209
1210 /*
1211 * Standard loopback mode for SCFCR ports.
1212 */
1213 reg = sci_getreg(port, SCFCR);
1214 if (reg->size)
b12bb29f 1215 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1216 }
1da177e4
LT		 1217}
1218
1219static unsigned int sci_get_mctrl(struct uart_port *port)
1220{
cdf7c42f
PM		 1221 /*
1222 * CTS/RTS is handled in hardware when supported, while nothing
1223 * else is wired up. Keep it simple and simply assert DSR/CAR.
1224 */
1225 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1226}
1227
73a19e4c
GL		 1228#ifdef CONFIG_SERIAL_SH_SCI_DMA
1229static void sci_dma_tx_complete(void *arg)
1230{
1231 struct sci_port *s = arg;
1232 struct uart_port *port = &s->port;
1233 struct circ_buf *xmit = &port->state->xmit;
1234 unsigned long flags;
1235
1236 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1237
1238 spin_lock_irqsave(&port->lock, flags);
1239
f354a381 1240 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1241 xmit->tail &= UART_XMIT_SIZE - 1;
1242
f354a381 1243 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1244
1245 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1246 s->desc_tx = NULL;
1247
73a19e4c
GL		 1248 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1249 uart_write_wakeup(port);
1250
3089f381 1251 if (!uart_circ_empty(xmit)) {
49d4bcad 1252 s->cookie_tx = 0;
73a19e4c 1253 schedule_work(&s->work_tx);
49d4bcad
YT		 1254 } else {
1255 s->cookie_tx = -EINVAL;
1256 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1257 u16 ctrl = serial_port_in(port, SCSCR);
1258 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1259 }
3089f381
GL		 1260 }
1261
1262 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1263}
1264
1265/* Locking: called with port lock held */
92a19f9c 1266static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1267{
1268 struct uart_port *port = &s->port;
227434f8 1269 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1270 int i, active, room;
1271
227434f8 1272 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1273
1274 if (s->active_rx == s->cookie_rx[0]) {
1275 active = 0;
1276 } else if (s->active_rx == s->cookie_rx[1]) {
1277 active = 1;
1278 } else {
1279 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1280 return 0;
1281 }
1282
1283 if (room < count)
1284 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1285 count - room);
1286 if (!room)
1287 return room;
1288
1289 for (i = 0; i < room; i++)
92a19f9c 1290 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1291 TTY_NORMAL);
1292
1293 port->icount.rx += room;
1294
1295 return room;
1296}
1297
1298static void sci_dma_rx_complete(void *arg)
1299{
1300 struct sci_port *s = arg;
1301 struct uart_port *port = &s->port;
1302 struct tty_struct *tty = port->state->port.tty;
1303 unsigned long flags;
1304 int count;
1305
3089f381 1306 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1307
1308 spin_lock_irqsave(&port->lock, flags);
1309
92a19f9c 1310 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1311
3089f381 1312 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1313
1314 spin_unlock_irqrestore(&port->lock, flags);
1315
1316 if (count)
1317 tty_flip_buffer_push(tty);
1318
1319 schedule_work(&s->work_rx);
1320}
1321
73a19e4c
GL		 1322static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1323{
1324 struct dma_chan *chan = s->chan_rx;
1325 struct uart_port *port = &s->port;
73a19e4c
GL		 1326
1327 s->chan_rx = NULL;
1328 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1329 dma_release_channel(chan);
85b8e3ff
GL		 1330 if (sg_dma_address(&s->sg_rx[0]))
1331 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1332 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1333 if (enable_pio)
1334 sci_start_rx(port);
1335}
1336
1337static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1338{
1339 struct dma_chan *chan = s->chan_tx;
1340 struct uart_port *port = &s->port;
73a19e4c
GL		 1341
1342 s->chan_tx = NULL;
1343 s->cookie_tx = -EINVAL;
1344 dma_release_channel(chan);
1345 if (enable_pio)
1346 sci_start_tx(port);
1347}
1348
1349static void sci_submit_rx(struct sci_port *s)
1350{
1351 struct dma_chan *chan = s->chan_rx;
1352 int i;
1353
1354 for (i = 0; i < 2; i++) {
1355 struct scatterlist *sg = &s->sg_rx[i];
1356 struct dma_async_tx_descriptor *desc;
1357
16052827 1358 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1359 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1360
1361 if (desc) {
1362 s->desc_rx[i] = desc;
1363 desc->callback = sci_dma_rx_complete;
1364 desc->callback_param = s;
1365 s->cookie_rx[i] = desc->tx_submit(desc);
1366 }
1367
1368 if (!desc || s->cookie_rx[i] < 0) {
1369 if (i) {
1370 async_tx_ack(s->desc_rx[0]);
1371 s->cookie_rx[0] = -EINVAL;
1372 }
1373 if (desc) {
1374 async_tx_ack(desc);
1375 s->cookie_rx[i] = -EINVAL;
1376 }
1377 dev_warn(s->port.dev,
1378 "failed to re-start DMA, using PIO\n");
1379 sci_rx_dma_release(s, true);
1380 return;
1381 }
3089f381
GL		 1382 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1383 s->cookie_rx[i], i);
73a19e4c
GL		 1384 }
1385
1386 s->active_rx = s->cookie_rx[0];
1387
1388 dma_async_issue_pending(chan);
1389}
1390
1391static void work_fn_rx(struct work_struct *work)
1392{
1393 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1394 struct uart_port *port = &s->port;
1395 struct dma_async_tx_descriptor *desc;
1396 int new;
1397
1398 if (s->active_rx == s->cookie_rx[0]) {
1399 new = 0;
1400 } else if (s->active_rx == s->cookie_rx[1]) {
1401 new = 1;
1402 } else {
1403 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1404 return;
1405 }
1406 desc = s->desc_rx[new];
1407
1408 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1409 DMA_SUCCESS) {
1410 /* Handle incomplete DMA receive */
1411 struct tty_struct *tty = port->state->port.tty;
1412 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1413 struct shdma_desc *sh_desc = container_of(desc,
1414 struct shdma_desc, async_tx);
73a19e4c
GL		 1415 unsigned long flags;
1416 int count;
1417
05827630 1418 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1419 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1420 sh_desc->partial, sh_desc->cookie);
1421
1422 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1423 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1424 spin_unlock_irqrestore(&port->lock, flags);
1425
1426 if (count)
1427 tty_flip_buffer_push(tty);
1428
1429 sci_submit_rx(s);
1430
1431 return;
1432 }
1433
1434 s->cookie_rx[new] = desc->tx_submit(desc);
1435 if (s->cookie_rx[new] < 0) {
1436 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1437 sci_rx_dma_release(s, true);
1438 return;
1439 }
1440
73a19e4c 1441 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1442
1443 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1444 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1445}
1446
1447static void work_fn_tx(struct work_struct *work)
1448{
1449 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1450 struct dma_async_tx_descriptor *desc;
1451 struct dma_chan *chan = s->chan_tx;
1452 struct uart_port *port = &s->port;
1453 struct circ_buf *xmit = &port->state->xmit;
1454 struct scatterlist *sg = &s->sg_tx;
1455
1456 /*
1457 * DMA is idle now.
1458 * Port xmit buffer is already mapped, and it is one page... Just adjust
1459 * offsets and lengths. Since it is a circular buffer, we have to
1460 * transmit till the end, and then the rest. Take the port lock to get a
1461 * consistent xmit buffer state.
1462 */
1463 spin_lock_irq(&port->lock);
1464 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1465 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1466 sg->offset;
f354a381 1467 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1468 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1469 spin_unlock_irq(&port->lock);
1470
f354a381 1471 BUG_ON(!sg_dma_len(sg));
73a19e4c 1472
16052827 1473 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1474 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1475 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1476 if (!desc) {
1477 /* switch to PIO */
1478 sci_tx_dma_release(s, true);
1479 return;
1480 }
1481
1482 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1483
1484 spin_lock_irq(&port->lock);
1485 s->desc_tx = desc;
1486 desc->callback = sci_dma_tx_complete;
1487 desc->callback_param = s;
1488 spin_unlock_irq(&port->lock);
1489 s->cookie_tx = desc->tx_submit(desc);
1490 if (s->cookie_tx < 0) {
1491 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1492 /* switch to PIO */
1493 sci_tx_dma_release(s, true);
1494 return;
1495 }
1496
1497 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1498 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1499
1500 dma_async_issue_pending(chan);
1501}
1502#endif
1503
b129a8cc 1504static void sci_start_tx(struct uart_port *port)
1da177e4 1505{
3089f381 1506 struct sci_port *s = to_sci_port(port);
e108b2ca 1507 unsigned short ctrl;
1da177e4 1508
73a19e4c 1509#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1510 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1511 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1512 if (s->chan_tx)
1513 new = scr | 0x8000;
1514 else
1515 new = scr & ~0x8000;
1516 if (new != scr)
b12bb29f 1517 serial_port_out(port, SCSCR, new);
73a19e4c 1518 }
f43dc23d 1519
3089f381 1520 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1521 s->cookie_tx < 0) {
1522 s->cookie_tx = 0;
3089f381 1523 schedule_work(&s->work_tx);
49d4bcad 1524 }
73a19e4c 1525#endif
f43dc23d 1526
d1d4b10c 1527 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1528 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1529 ctrl = serial_port_in(port, SCSCR);
1530 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1531 }
1da177e4
LT		 1532}
1533
b129a8cc 1534static void sci_stop_tx(struct uart_port *port)
1da177e4 1535{
1da177e4
LT		 1536 unsigned short ctrl;
1537
1538 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1539 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1540
d1d4b10c 1541 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1542 ctrl &= ~0x8000;
f43dc23d 1543
8e698614 1544 ctrl &= ~SCSCR_TIE;
f43dc23d 1545
b12bb29f 1546 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1547}
1548
73a19e4c 1549static void sci_start_rx(struct uart_port *port)
1da177e4 1550{
1da177e4
LT		 1551 unsigned short ctrl;
1552
b12bb29f 1553 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1554
d1d4b10c 1555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1556 ctrl &= ~0x4000;
f43dc23d 1557
b12bb29f 1558 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1559}
1560
1561static void sci_stop_rx(struct uart_port *port)
1562{
1da177e4
LT		 1563 unsigned short ctrl;
1564
b12bb29f 1565 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1566
d1d4b10c 1567 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1568 ctrl &= ~0x4000;
f43dc23d
PM		 1569
1570 ctrl &= ~port_rx_irq_mask(port);
1571
b12bb29f 1572 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1573}
1574
1575static void sci_enable_ms(struct uart_port *port)
1576{
d39ec6ce
PM		 1577 /*
1578 * Not supported by hardware, always a nop.
1579 */
1da177e4
LT		 1580}
1581
1582static void sci_break_ctl(struct uart_port *port, int break_state)
1583{
bbb4ce50 1584 struct sci_port *s = to_sci_port(port);
a4e02f6d 1585 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1586 unsigned short scscr, scsptr;
1587
a4e02f6d
SY		 1588 /* check wheter the port has SCSPTR */
1589 if (!reg->size) {
bbb4ce50
SY		 1590 /*
1591 * Not supported by hardware. Most parts couple break and rx
1592 * interrupts together, with break detection always enabled.
1593 */
a4e02f6d 1594 return;
bbb4ce50 1595 }
a4e02f6d
SY		 1596
1597 scsptr = serial_port_in(port, SCSPTR);
1598 scscr = serial_port_in(port, SCSCR);
1599
1600 if (break_state == -1) {
1601 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1602 scscr &= ~SCSCR_TE;
1603 } else {
1604 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1605 scscr |= SCSCR_TE;
1606 }
1607
1608 serial_port_out(port, SCSPTR, scsptr);
1609 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1610}
1611
73a19e4c
GL		 1612#ifdef CONFIG_SERIAL_SH_SCI_DMA
1613static bool filter(struct dma_chan *chan, void *slave)
1614{
1615 struct sh_dmae_slave *param = slave;
1616
1617 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1618 param->shdma_slave.slave_id);
73a19e4c 1619
d6fa5a4e 1620 chan->private = &param->shdma_slave;
937bb6e4 1621 return true;
73a19e4c
GL		 1622}
1623
1624static void rx_timer_fn(unsigned long arg)
1625{
1626 struct sci_port *s = (struct sci_port *)arg;
1627 struct uart_port *port = &s->port;
b12bb29f 1628 u16 scr = serial_port_in(port, SCSCR);
3089f381 1629
d1d4b10c 1630 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1631 scr &= ~0x4000;
ce6738b6 1632 enable_irq(s->cfg->irqs[1]);
3089f381 1633 }
b12bb29f 1634 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1635 dev_dbg(port->dev, "DMA Rx timed out\n");
1636 schedule_work(&s->work_rx);
1637}
1638
1639static void sci_request_dma(struct uart_port *port)
1640{
1641 struct sci_port *s = to_sci_port(port);
1642 struct sh_dmae_slave *param;
1643 struct dma_chan *chan;
1644 dma_cap_mask_t mask;
1645 int nent;
1646
937bb6e4
GL		 1647 dev_dbg(port->dev, "%s: port %d\n", __func__,
1648 port->line);
73a19e4c 1649
937bb6e4 1650 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1651 return;
1652
1653 dma_cap_zero(mask);
1654 dma_cap_set(DMA_SLAVE, mask);
1655
1656 param = &s->param_tx;
1657
1658 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1659 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1660
1661 s->cookie_tx = -EINVAL;
1662 chan = dma_request_channel(mask, filter, param);
1663 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1664 if (chan) {
1665 s->chan_tx = chan;
1666 sg_init_table(&s->sg_tx, 1);
1667 /* UART circular tx buffer is an aligned page. */
1668 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1669 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1670 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1671 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1672 if (!nent)
1673 sci_tx_dma_release(s, false);
1674 else
1675 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1676 sg_dma_len(&s->sg_tx),
1677 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1678
1679 s->sg_len_tx = nent;
1680
1681 INIT_WORK(&s->work_tx, work_fn_tx);
1682 }
1683
1684 param = &s->param_rx;
1685
1686 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1687 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1688
1689 chan = dma_request_channel(mask, filter, param);
1690 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1691 if (chan) {
1692 dma_addr_t dma[2];
1693 void *buf[2];
1694 int i;
1695
1696 s->chan_rx = chan;
1697
1698 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1699 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1700 &dma[0], GFP_KERNEL);
1701
1702 if (!buf[0]) {
1703 dev_warn(port->dev,
1704 "failed to allocate dma buffer, using PIO\n");
1705 sci_rx_dma_release(s, true);
1706 return;
1707 }
1708
1709 buf[1] = buf[0] + s->buf_len_rx;
1710 dma[1] = dma[0] + s->buf_len_rx;
1711
1712 for (i = 0; i < 2; i++) {
1713 struct scatterlist *sg = &s->sg_rx[i];
1714
1715 sg_init_table(sg, 1);
1716 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1717 (int)buf[i] & ~PAGE_MASK);
f354a381 1718 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1719 }
1720
1721 INIT_WORK(&s->work_rx, work_fn_rx);
1722 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1723
1724 sci_submit_rx(s);
1725 }
1726}
1727
1728static void sci_free_dma(struct uart_port *port)
1729{
1730 struct sci_port *s = to_sci_port(port);
1731
73a19e4c
GL		 1732 if (s->chan_tx)
1733 sci_tx_dma_release(s, false);
1734 if (s->chan_rx)
1735 sci_rx_dma_release(s, false);
1736}
27bd1075
PM		 1737#else
1738static inline void sci_request_dma(struct uart_port *port)
1739{
1740}
1741
1742static inline void sci_free_dma(struct uart_port *port)
1743{
1744}
73a19e4c
GL		 1745#endif
1746
1da177e4
LT		 1747static int sci_startup(struct uart_port *port)
1748{
a5660ada 1749 struct sci_port *s = to_sci_port(port);
33b48e16 1750 unsigned long flags;
073e84c9 1751 int ret;
1da177e4 1752
73a19e4c
GL		 1753 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1754
073e84c9
PM		 1755 ret = sci_request_irq(s);
1756 if (unlikely(ret < 0))
1757 return ret;
1758
73a19e4c 1759 sci_request_dma(port);
073e84c9 1760
33b48e16 1761 spin_lock_irqsave(&port->lock, flags);
d656901b 1762 sci_start_tx(port);
73a19e4c 1763 sci_start_rx(port);
33b48e16 1764 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1765
1766 return 0;
1767}
1768
1769static void sci_shutdown(struct uart_port *port)
1770{
a5660ada 1771 struct sci_port *s = to_sci_port(port);
33b48e16 1772 unsigned long flags;
1da177e4 1773
73a19e4c
GL		 1774 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1775
33b48e16 1776 spin_lock_irqsave(&port->lock, flags);
1da177e4 1777 sci_stop_rx(port);
b129a8cc 1778 sci_stop_tx(port);
33b48e16 1779 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1780
73a19e4c 1781 sci_free_dma(port);
1da177e4 1782 sci_free_irq(s);
1da177e4
LT		 1783}
1784
26c92f37
PM		 1785static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1786 unsigned long freq)
1787{
1788 switch (algo_id) {
1789 case SCBRR_ALGO_1:
1790 return ((freq + 16 * bps) / (16 * bps) - 1);
1791 case SCBRR_ALGO_2:
1792 return ((freq + 16 * bps) / (32 * bps) - 1);
1793 case SCBRR_ALGO_3:
1794 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1795 case SCBRR_ALGO_4:
1796 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1797 case SCBRR_ALGO_5:
1798 return (((freq * 1000 / 32) / bps) - 1);
1799 }
1800
1801 /* Warn, but use a safe default */
1802 WARN_ON(1);
e8183a6c 1803
26c92f37
PM		 1804 return ((freq + 16 * bps) / (32 * bps) - 1);
1805}
1806
1ba76220
MD		 1807static void sci_reset(struct uart_port *port)
1808{
0979e0e6 1809 struct plat_sci_reg *reg;
1ba76220
MD		 1810 unsigned int status;
1811
1812 do {
b12bb29f 1813 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1814 } while (!(status & SCxSR_TEND(port)));
1815
b12bb29f 1816 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1817
0979e0e6
PM		 1818 reg = sci_getreg(port, SCFCR);
1819 if (reg->size)
b12bb29f 1820 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1821}
1822
606d099c
AC		 1823static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1824 struct ktermios *old)
1da177e4 1825{
00b9de9c 1826 struct sci_port *s = to_sci_port(port);
0979e0e6 1827 struct plat_sci_reg *reg;
9d482cc3 1828 unsigned int baud, smr_val, max_baud, cks;
a2159b52 1829 int t = -1;
1da177e4 1830
154280fd
MD		 1831 /*
1832 * earlyprintk comes here early on with port->uartclk set to zero.
1833 * the clock framework is not up and running at this point so here
1834 * we assume that 115200 is the maximum baud rate. please note that
1835 * the baud rate is not programmed during earlyprintk - it is assumed
1836 * that the previous boot loader has enabled required clocks and
1837 * setup the baud rate generator hardware for us already.
1838 */
1839 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1840
154280fd
MD		 1841 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1842 if (likely(baud && port->uartclk))
ce6738b6 1843 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1844
23241d43 1845 sci_port_enable(s);
36003386 1846
1ba76220 1847 sci_reset(port);
1da177e4 1848
b12bb29f 1849 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1850
1da177e4
LT		 1851 if ((termios->c_cflag & CSIZE) == CS7)
1852 smr_val |= 0x40;
1853 if (termios->c_cflag & PARENB)
1854 smr_val |= 0x20;
1855 if (termios->c_cflag & PARODD)
1856 smr_val |= 0x30;
1857 if (termios->c_cflag & CSTOPB)
1858 smr_val |= 0x08;
1859
1860 uart_update_timeout(port, termios->c_cflag, baud);
1861
9d482cc3
TY		 1862 for (cks = 0; t >= 256 && cks <= 3; cks++)
1863 t >>= 2;
1da177e4 1864
9d482cc3
TY		 1865 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1866 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1867
4ffc3cdb 1868 if (t >= 0) {
9d482cc3 1869 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1870 serial_port_out(port, SCBRR, t);
1da177e4 1871 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1872 } else
1873 serial_port_out(port, SCSMR, smr_val);
1da177e4 1874
d5701647 1875 sci_init_pins(port, termios->c_cflag);
0979e0e6 1876
73c3d53f
PM		 1877 reg = sci_getreg(port, SCFCR);
1878 if (reg->size) {
b12bb29f 1879 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1880
73c3d53f 1881 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1882 if (termios->c_cflag & CRTSCTS)
1883 ctrl |= SCFCR_MCE;
1884 else
1885 ctrl &= ~SCFCR_MCE;
faf02f8f 1886 }
73c3d53f
PM		 1887
1888 /*
1889 * As we've done a sci_reset() above, ensure we don't
1890 * interfere with the FIFOs while toggling MCE. As the
1891 * reset values could still be set, simply mask them out.
1892 */
1893 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1894
b12bb29f 1895 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1896 }
b7a76e4b 1897
b12bb29f 1898 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1899
3089f381
GL		 1900#ifdef CONFIG_SERIAL_SH_SCI_DMA
1901 /*
1902 * Calculate delay for 1.5 DMA buffers: see
1903 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1904 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1905 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1906 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1907 * sizes), but it has been found out experimentally, that this is not
1908 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1909 * as a minimum seem to work perfectly.
1910 */
1911 if (s->chan_rx) {
1912 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1913 port->fifosize / 2;
1914 dev_dbg(port->dev,
1915 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1916 s->rx_timeout * 1000 / HZ, port->timeout);
1917 if (s->rx_timeout < msecs_to_jiffies(20))
1918 s->rx_timeout = msecs_to_jiffies(20);
1919 }
1920#endif
1921
1da177e4 1922 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1923 sci_start_rx(port);
36003386 1924
23241d43 1925 sci_port_disable(s);
1da177e4
LT		 1926}
1927
0174e5ca
TK		 1928static void sci_pm(struct uart_port *port, unsigned int state,
1929 unsigned int oldstate)
1930{
1931 struct sci_port *sci_port = to_sci_port(port);
1932
1933 switch (state) {
1934 case 3:
1935 sci_port_disable(sci_port);
1936 break;
1937 default:
1938 sci_port_enable(sci_port);
1939 break;
1940 }
1941}
1942
1da177e4
LT		 1943static const char *sci_type(struct uart_port *port)
1944{
1945 switch (port->type) {
e7c98dc7
MT		 1946 case PORT_IRDA:
1947 return "irda";
1948 case PORT_SCI:
1949 return "sci";
1950 case PORT_SCIF:
1951 return "scif";
1952 case PORT_SCIFA:
1953 return "scifa";
d1d4b10c
GL		 1954 case PORT_SCIFB:
1955 return "scifb";
1da177e4
LT		 1956 }
1957
fa43972f 1958 return NULL;
1da177e4
LT		 1959}
1960
e2651647 1961static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1962{
e2651647
PM		 1963 /*
1964 * Pick an arbitrary size that encapsulates all of the base
1965 * registers by default. This can be optimized later, or derived
1966 * from platform resource data at such a time that ports begin to
1967 * behave more erratically.
1968 */
1969 return 64;
1da177e4
LT		 1970}
1971
f6e9495d
PM		 1972static int sci_remap_port(struct uart_port *port)
1973{
1974 unsigned long size = sci_port_size(port);
1975
1976 /*
1977 * Nothing to do if there's already an established membase.
1978 */
1979 if (port->membase)
1980 return 0;
1981
1982 if (port->flags & UPF_IOREMAP) {
1983 port->membase = ioremap_nocache(port->mapbase, size);
1984 if (unlikely(!port->membase)) {
1985 dev_err(port->dev, "can't remap port#%d\n", port->line);
1986 return -ENXIO;
1987 }
1988 } else {
1989 /*
1990 * For the simple (and majority of) cases where we don't
1991 * need to do any remapping, just cast the cookie
1992 * directly.
1993 */
1994 port->membase = (void __iomem *)port->mapbase;
1995 }
1996
1997 return 0;
1998}
1999
e2651647 2000static void sci_release_port(struct uart_port *port)
1da177e4 2001{
e2651647
PM		 2002 if (port->flags & UPF_IOREMAP) {
2003 iounmap(port->membase);
2004 port->membase = NULL;
2005 }
2006
2007 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2008}
2009
e2651647 2010static int sci_request_port(struct uart_port *port)
1da177e4 2011{
e2651647
PM		 2012 unsigned long size = sci_port_size(port);
2013 struct resource *res;
f6e9495d 2014 int ret;
1da177e4 2015
1020520e 2016 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2017 if (unlikely(res == NULL))
2018 return -EBUSY;
1da177e4 2019
f6e9495d
PM		 2020 ret = sci_remap_port(port);
2021 if (unlikely(ret != 0)) {
2022 release_resource(res);
2023 return ret;
7ff731ae 2024 }
e2651647
PM		 2025
2026 return 0;
2027}
2028
2029static void sci_config_port(struct uart_port *port, int flags)
2030{
2031 if (flags & UART_CONFIG_TYPE) {
2032 struct sci_port *sport = to_sci_port(port);
2033
2034 port->type = sport->cfg->type;
2035 sci_request_port(port);
2036 }
1da177e4
LT		 2037}
2038
2039static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2040{
a5660ada 2041 struct sci_port *s = to_sci_port(port);
1da177e4 2042
ce6738b6 2043 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 2044 return -EINVAL;
2045 if (ser->baud_base < 2400)
2046 /* No paper tape reader for Mitch.. */
2047 return -EINVAL;
2048
2049 return 0;
2050}
2051
2052static struct uart_ops sci_uart_ops = {
2053 .tx_empty = sci_tx_empty,
2054 .set_mctrl = sci_set_mctrl,
2055 .get_mctrl = sci_get_mctrl,
2056 .start_tx = sci_start_tx,
2057 .stop_tx = sci_stop_tx,
2058 .stop_rx = sci_stop_rx,
2059 .enable_ms = sci_enable_ms,
2060 .break_ctl = sci_break_ctl,
2061 .startup = sci_startup,
2062 .shutdown = sci_shutdown,
2063 .set_termios = sci_set_termios,
0174e5ca 2064 .pm = sci_pm,
1da177e4
LT		 2065 .type = sci_type,
2066 .release_port = sci_release_port,
2067 .request_port = sci_request_port,
2068 .config_port = sci_config_port,
2069 .verify_port = sci_verify_port,
07d2a1a1
PM		 2070#ifdef CONFIG_CONSOLE_POLL
2071 .poll_get_char = sci_poll_get_char,
2072 .poll_put_char = sci_poll_put_char,
2073#endif
1da177e4
LT		 2074};
2075
9671f099 2076static int sci_init_single(struct platform_device *dev,
c7ed1ab3
PM		 2077 struct sci_port *sci_port,
2078 unsigned int index,
2079 struct plat_sci_port *p)
e108b2ca 2080{
73a19e4c 2081 struct uart_port *port = &sci_port->port;
3127c6b2 2082 int ret;
e108b2ca 2083
50f0959a
PM		 2084 sci_port->cfg = p;
2085
73a19e4c
GL		 2086 port->ops = &sci_uart_ops;
2087 port->iotype = UPIO_MEM;
2088 port->line = index;
75136d48
MP		 2089
2090 switch (p->type) {
d1d4b10c
GL		 2091 case PORT_SCIFB:
2092 port->fifosize = 256;
2093 break;
75136d48 2094 case PORT_SCIFA:
73a19e4c 2095 port->fifosize = 64;
75136d48
MP		 2096 break;
2097 case PORT_SCIF:
73a19e4c 2098 port->fifosize = 16;
75136d48
MP		 2099 break;
2100 default:
73a19e4c 2101 port->fifosize = 1;
75136d48
MP		 2102 break;
2103 }
7b6fd3bf 2104
3127c6b2
PM		 2105 if (p->regtype == SCIx_PROBE_REGTYPE) {
2106 ret = sci_probe_regmap(p);
fc97114b 2107 if (unlikely(ret))
3127c6b2
PM		 2108 return ret;
2109 }
61a6976b 2110
7b6fd3bf 2111 if (dev) {
c7ed1ab3
PM		 2112 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2113 if (IS_ERR(sci_port->iclk)) {
2114 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2115 if (IS_ERR(sci_port->iclk)) {
2116 dev_err(&dev->dev, "can't get iclk\n");
2117 return PTR_ERR(sci_port->iclk);
2118 }
2119 }
2120
2121 /*
2122 * The function clock is optional, ignore it if we can't
2123 * find it.
2124 */
2125 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2126 if (IS_ERR(sci_port->fclk))
2127 sci_port->fclk = NULL;
2128
73a19e4c 2129 port->dev = &dev->dev;
5e50d2d6 2130
50f0959a
PM		 2131 sci_init_gpios(sci_port);
2132
5e50d2d6 2133 pm_runtime_enable(&dev->dev);
7b6fd3bf 2134 }
e108b2ca 2135
7ed7e071
MD		 2136 sci_port->break_timer.data = (unsigned long)sci_port;
2137 sci_port->break_timer.function = sci_break_timer;
2138 init_timer(&sci_port->break_timer);
2139
debf9507
PM		 2140 /*
2141 * Establish some sensible defaults for the error detection.
2142 */
2143 if (!p->error_mask)
2144 p->error_mask = (p->type == PORT_SCI) ?
2145 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2146
2147 /*
2148 * Establish sensible defaults for the overrun detection, unless
2149 * the part has explicitly disabled support for it.
2150 */
2151 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2152 if (p->type == PORT_SCI)
2153 p->overrun_bit = 5;
2154 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2155 p->overrun_bit = 9;
2156 else
2157 p->overrun_bit = 0;
2158
2159 /*
2160 * Make the error mask inclusive of overrun detection, if
2161 * supported.
2162 */
2163 p->error_mask |= (1 << p->overrun_bit);
2164 }
2165
ce6738b6
PM		 2166 port->mapbase = p->mapbase;
2167 port->type = p->type;
f43dc23d 2168 port->flags = p->flags;
61a6976b 2169 port->regshift = p->regshift;
73a19e4c 2170
ce6738b6 2171 /*
61a6976b 2172 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2173 * for the multi-IRQ ports, which is where we are primarily
2174 * concerned with the shutdown path synchronization.
2175 *
2176 * For the muxed case there's nothing more to do.
2177 */
54aa89ea 2178 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2179 port->irqflags = 0;
73a19e4c 2180
61a6976b
PM		 2181 port->serial_in = sci_serial_in;
2182 port->serial_out = sci_serial_out;
2183
937bb6e4
GL		 2184 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2185 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2186 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2187
c7ed1ab3 2188 return 0;
e108b2ca
PM		 2189}
2190
6dae1421
LP		 2191static void sci_cleanup_single(struct sci_port *port)
2192{
2193 sci_free_gpios(port);
2194
2195 clk_put(port->iclk);
2196 clk_put(port->fclk);
2197
2198 pm_runtime_disable(port->port.dev);
2199}
2200
1da177e4 2201#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2202static void serial_console_putchar(struct uart_port *port, int ch)
2203{
2204 sci_poll_put_char(port, ch);
2205}
2206
1da177e4
LT		 2207/*
2208 * Print a string to the serial port trying not to disturb
2209 * any possible real use of the port...
2210 */
2211static void serial_console_write(struct console *co, const char *s,
2212 unsigned count)
2213{
906b17dc
PM		 2214 struct sci_port *sci_port = &sci_ports[co->index];
2215 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2216 unsigned short bits, ctrl;
2217 unsigned long flags;
2218 int locked = 1;
2219
2220 local_irq_save(flags);
2221 if (port->sysrq)
2222 locked = 0;
2223 else if (oops_in_progress)
2224 locked = spin_trylock(&port->lock);
2225 else
2226 spin_lock(&port->lock);
2227
2228 /* first save the SCSCR then disable the interrupts */
2229 ctrl = serial_port_in(port, SCSCR);
2230 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2231
501b825d 2232 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2233
2234 /* wait until fifo is empty and last bit has been transmitted */
2235 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2236 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2237 cpu_relax();
40f70c03
SK		 2238
2239 /* restore the SCSCR */
2240 serial_port_out(port, SCSCR, ctrl);
2241
2242 if (locked)
2243 spin_unlock(&port->lock);
2244 local_irq_restore(flags);
1da177e4
LT		 2245}
2246
9671f099 2247static int serial_console_setup(struct console *co, char *options)
1da177e4 2248{
dc8e6f5b 2249 struct sci_port *sci_port;
1da177e4
LT		 2250 struct uart_port *port;
2251 int baud = 115200;
2252 int bits = 8;
2253 int parity = 'n';
2254 int flow = 'n';
2255 int ret;
2256
e108b2ca 2257 /*
906b17dc 2258 * Refuse to handle any bogus ports.
1da177e4 2259 */
906b17dc 2260 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2261 return -ENODEV;
e108b2ca 2262
906b17dc
PM		 2263 sci_port = &sci_ports[co->index];
2264 port = &sci_port->port;
2265
b2267a6b
AC		 2266 /*
2267 * Refuse to handle uninitialized ports.
2268 */
2269 if (!port->ops)
2270 return -ENODEV;
2271
f6e9495d
PM		 2272 ret = sci_remap_port(port);
2273 if (unlikely(ret != 0))
2274 return ret;
e108b2ca 2275
1da177e4
LT		 2276 if (options)
2277 uart_parse_options(options, &baud, &parity, &bits, &flow);
2278
ab7cfb55 2279 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2280}
2281
2282static struct console serial_console = {
2283 .name = "ttySC",
906b17dc 2284 .device = uart_console_device,
1da177e4
LT		 2285 .write = serial_console_write,
2286 .setup = serial_console_setup,
fa5da2f7 2287 .flags = CON_PRINTBUFFER,
1da177e4 2288 .index = -1,
906b17dc 2289 .data = &sci_uart_driver,
1da177e4
LT		 2290};
2291
7b6fd3bf
MD		 2292static struct console early_serial_console = {
2293 .name = "early_ttySC",
2294 .write = serial_console_write,
2295 .flags = CON_PRINTBUFFER,
906b17dc 2296 .index = -1,
7b6fd3bf 2297};
ecdf8a46 2298
7b6fd3bf
MD		 2299static char early_serial_buf[32];
2300
9671f099 2301static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2302{
2303 struct plat_sci_port *cfg = pdev->dev.platform_data;
2304
2305 if (early_serial_console.data)
2306 return -EEXIST;
2307
2308 early_serial_console.index = pdev->id;
ecdf8a46 2309
906b17dc 2310 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2311
2312 serial_console_setup(&early_serial_console, early_serial_buf);
2313
2314 if (!strstr(early_serial_buf, "keep"))
2315 early_serial_console.flags |= CON_BOOT;
2316
2317 register_console(&early_serial_console);
2318 return 0;
2319}
6a8c9799
NI		 2320
2321#define SCI_CONSOLE (&serial_console)
2322
ecdf8a46 2323#else
9671f099 2324static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2325{
2326 return -EINVAL;
2327}
1da177e4 2328
6a8c9799
NI		 2329#define SCI_CONSOLE NULL
2330
2331#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2332
2333static char banner[] __initdata =
2334 KERN_INFO "SuperH SCI(F) driver initialized\n";
2335
2336static struct uart_driver sci_uart_driver = {
2337 .owner = THIS_MODULE,
2338 .driver_name = "sci",
1da177e4
LT		 2339 .dev_name = "ttySC",
2340 .major = SCI_MAJOR,
2341 .minor = SCI_MINOR_START,
e108b2ca 2342 .nr = SCI_NPORTS,
1da177e4
LT		 2343 .cons = SCI_CONSOLE,
2344};
2345
54507f6e 2346static int sci_remove(struct platform_device *dev)
e552de24 2347{
d535a230 2348 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2349
d535a230
PM		 2350 cpufreq_unregister_notifier(&port->freq_transition,
2351 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2352
d535a230
PM		 2353 uart_remove_one_port(&sci_uart_driver, &port->port);
2354
6dae1421 2355 sci_cleanup_single(port);
e552de24 2356
e552de24
MD		 2357 return 0;
2358}
2359
9671f099 2360static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2361 unsigned int index,
2362 struct plat_sci_port *p,
2363 struct sci_port *sciport)
2364{
0ee70712
MD		 2365 int ret;
2366
2367 /* Sanity check */
2368 if (unlikely(index >= SCI_NPORTS)) {
2369 dev_notice(&dev->dev, "Attempting to register port "
2370 "%d when only %d are available.\n",
2371 index+1, SCI_NPORTS);
2372 dev_notice(&dev->dev, "Consider bumping "
2373 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2374 return -EINVAL;
0ee70712
MD		 2375 }
2376
c7ed1ab3
PM		 2377 ret = sci_init_single(dev, sciport, index, p);
2378 if (ret)
2379 return ret;
0ee70712 2380
6dae1421
LP		 2381 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2382 if (ret) {
2383 sci_cleanup_single(sciport);
2384 return ret;
2385 }
2386
2387 return 0;
0ee70712
MD		 2388}
2389
9671f099 2390static int sci_probe(struct platform_device *dev)
1da177e4 2391{
e108b2ca 2392 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2393 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2394 int ret;
d535a230 2395
ecdf8a46
PM		 2396 /*
2397 * If we've come here via earlyprintk initialization, head off to
2398 * the special early probe. We don't have sufficient device state
2399 * to make it beyond this yet.
2400 */
2401 if (is_early_platform_device(dev))
2402 return sci_probe_earlyprintk(dev);
7b6fd3bf 2403
d535a230 2404 platform_set_drvdata(dev, sp);
e552de24 2405
906b17dc 2406 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2407 if (ret)
6dae1421 2408 return ret;
e552de24 2409
d535a230 2410 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2411
d535a230
PM		 2412 ret = cpufreq_register_notifier(&sp->freq_transition,
2413 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2414 if (unlikely(ret < 0)) {
2415 sci_cleanup_single(sp);
2416 return ret;
2417 }
1da177e4
LT		 2418
2419#ifdef CONFIG_SH_STANDARD_BIOS
2420 sh_bios_gdb_detach();
2421#endif
2422
e108b2ca 2423 return 0;
1da177e4
LT		 2424}
2425
6daa79b3 2426static int sci_suspend(struct device *dev)
1da177e4 2427{
d535a230 2428 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2429
d535a230
PM		 2430 if (sport)
2431 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2432
e108b2ca
PM		 2433 return 0;
2434}
1da177e4 2435
6daa79b3 2436static int sci_resume(struct device *dev)
e108b2ca 2437{
d535a230 2438 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2439
d535a230
PM		 2440 if (sport)
2441 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2442
2443 return 0;
2444}
2445
47145210 2446static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2447 .suspend = sci_suspend,
2448 .resume = sci_resume,
2449};
2450
e108b2ca
PM		 2451static struct platform_driver sci_driver = {
2452 .probe = sci_probe,
b9e39c89 2453 .remove = sci_remove,
e108b2ca
PM		 2454 .driver = {
2455 .name = "sh-sci",
2456 .owner = THIS_MODULE,
6daa79b3 2457 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2458 },
2459};
2460
2461static int __init sci_init(void)
2462{
2463 int ret;
2464
2465 printk(banner);
2466
e108b2ca
PM		 2467 ret = uart_register_driver(&sci_uart_driver);
2468 if (likely(ret == 0)) {
2469 ret = platform_driver_register(&sci_driver);
2470 if (unlikely(ret))
2471 uart_unregister_driver(&sci_uart_driver);
2472 }
2473
2474 return ret;
2475}
2476
2477static void __exit sci_exit(void)
2478{
2479 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2480 uart_unregister_driver(&sci_uart_driver);
2481}
2482
7b6fd3bf
MD		 2483#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2484early_platform_init_buffer("earlyprintk", &sci_driver,
2485 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2486#endif
1da177e4
LT		 2487module_init(sci_init);
2488module_exit(sci_exit);
2489
e108b2ca 2490MODULE_LICENSE("GPL");
e169c139 2491MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2492MODULE_AUTHOR("Paul Mundt");
2493MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux kernel - Deliverables
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