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serial: sh-sci: Generalize overrun handling.
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
1da177e4
LT		 28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
e108b2ca 41#include <linux/platform_device.h>
96de1a8f 42#include <linux/serial_sci.h>
1da177e4 43#include <linux/notifier.h>
5e50d2d6 44#include <linux/pm_runtime.h>
1da177e4 45#include <linux/cpufreq.h>
85f094ec 46#include <linux/clk.h>
fa5da2f7 47#include <linux/ctype.h>
7ff731ae 48#include <linux/err.h>
73a19e4c
GL		 49#include <linux/dmaengine.h>
50#include <linux/scatterlist.h>
5a0e3ad6 51#include <linux/slab.h>
85f094ec
PM		 52
53#ifdef CONFIG_SUPERH
1da177e4
LT		 54#include <asm/sh_bios.h>
55#endif
56
1da177e4
LT		 57#include "sh-sci.h"
58
e108b2ca
PM		 59struct sci_port {
60 struct uart_port port;
61
ce6738b6
PM		 62 /* Platform configuration */
63 struct plat_sci_port *cfg;
e108b2ca 64
e108b2ca
PM		 65 /* Port enable callback */
66 void (*enable)(struct uart_port *port);
67
68 /* Port disable callback */
69 void (*disable)(struct uart_port *port);
70
71 /* Break timer */
72 struct timer_list break_timer;
73 int break_flag;
1534a3b3 74
501b825d
MD		 75 /* Interface clock */
76 struct clk *iclk;
c7ed1ab3
PM		 77 /* Function clock */
78 struct clk *fclk;
edad1f20 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
e108b2ca
PM		 102};
103
1da177e4 104/* Function prototypes */
d535a230 105static void sci_start_tx(struct uart_port *port);
b129a8cc 106static void sci_stop_tx(struct uart_port *port);
d535a230 107static void sci_start_rx(struct uart_port *port);
1da177e4 108
e108b2ca 109#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 110
e108b2ca
PM		 111static struct sci_port sci_ports[SCI_NPORTS];
112static struct uart_driver sci_uart_driver;
1da177e4 113
e7c98dc7
MT		 114static inline struct sci_port *
115to_sci_port(struct uart_port *uart)
116{
117 return container_of(uart, struct sci_port, port);
118}
119
07d2a1a1 120#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 121
122#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 123static int sci_poll_get_char(struct uart_port *port)
1da177e4 124{
1da177e4
LT		 125 unsigned short status;
126 int c;
127
e108b2ca 128 do {
1da177e4
LT		 129 status = sci_in(port, SCxSR);
130 if (status & SCxSR_ERRORS(port)) {
94c8b6db 131 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 132 continue;
133 }
3f255eb3
JW		 134 break;
135 } while (1);
136
137 if (!(status & SCxSR_RDxF(port)))
138 return NO_POLL_CHAR;
07d2a1a1 139
1da177e4 140 c = sci_in(port, SCxRDR);
07d2a1a1 141
e7c98dc7
MT		 142 /* Dummy read */
143 sci_in(port, SCxSR);
1da177e4 144 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 145
146 return c;
147}
1f6fd5c9 148#endif
1da177e4 149
07d2a1a1 150static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 151{
1da177e4
LT		 152 unsigned short status;
153
1da177e4
LT		 154 do {
155 status = sci_in(port, SCxSR);
156 } while (!(status & SCxSR_TDxE(port)));
157
272966c0 158 sci_out(port, SCxTDR, c);
dd0a3e77 159 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 160}
07d2a1a1 161#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 162
ab7cfb55 163#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
d5701647 164static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
e108b2ca 165{
d5701647
PM		 166 if (port->mapbase == 0xA4400000) {
167 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
168 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
169 } else if (port->mapbase == 0xA4410000)
170 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
9465a54f 171}
31a49c4b 172#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
d5701647 173static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
3ea6bc3d 174{
3ea6bc3d
MB		 175 unsigned short data;
176
177 if (cflag & CRTSCTS) {
178 /* enable RTS/CTS */
179 if (port->mapbase == 0xa4430000) { /* SCIF0 */
180 /* Clear PTCR bit 9-2; enable all scif pins but sck */
d5701647
PM		 181 data = __raw_readw(PORT_PTCR);
182 __raw_writew((data & 0xfc03), PORT_PTCR);
3ea6bc3d
MB		 183 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
184 /* Clear PVCR bit 9-2 */
d5701647
PM		 185 data = __raw_readw(PORT_PVCR);
186 __raw_writew((data & 0xfc03), PORT_PVCR);
3ea6bc3d 187 }
3ea6bc3d
MB		 188 } else {
189 if (port->mapbase == 0xa4430000) { /* SCIF0 */
190 /* Clear PTCR bit 5-2; enable only tx and rx */
d5701647
PM		 191 data = __raw_readw(PORT_PTCR);
192 __raw_writew((data & 0xffc3), PORT_PTCR);
3ea6bc3d
MB		 193 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
194 /* Clear PVCR bit 5-2 */
d5701647
PM		 195 data = __raw_readw(PORT_PVCR);
196 __raw_writew((data & 0xffc3), PORT_PVCR);
3ea6bc3d
MB		 197 }
198 }
3ea6bc3d 199}
b7a76e4b 200#elif defined(CONFIG_CPU_SH3)
e108b2ca 201/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
d5701647 202static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 203{
b7a76e4b
PM		 204 unsigned short data;
205
206 /* We need to set SCPCR to enable RTS/CTS */
d5701647 207 data = __raw_readw(SCPCR);
b7a76e4b 208 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
d5701647 209 __raw_writew(data & 0x0fcf, SCPCR);
1da177e4 210
d5701647 211 if (!(cflag & CRTSCTS)) {
1da177e4 212 /* We need to set SCPCR to enable RTS/CTS */
d5701647 213 data = __raw_readw(SCPCR);
1da177e4
LT		 214 /* Clear out SCP7MD1,0, SCP4MD1,0,
215 Set SCP6MD1,0 = {01} (output) */
d5701647 216 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
1da177e4 217
32b53076 218 data = __raw_readb(SCPDR);
1da177e4 219 /* Set /RTS2 (bit6) = 0 */
32b53076 220 __raw_writeb(data & 0xbf, SCPDR);
1da177e4 221 }
1da177e4 222}
41504c39 223#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
d5701647 224static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
41504c39 225{
346b7463 226 unsigned short data;
41504c39 227
346b7463 228 if (port->mapbase == 0xffe00000) {
d5701647 229 data = __raw_readw(PSCR);
346b7463 230 data &= ~0x03cf;
d5701647 231 if (!(cflag & CRTSCTS))
346b7463 232 data |= 0x0340;
41504c39 233
d5701647 234 __raw_writew(data, PSCR);
41504c39 235 }
178dd0cd 236}
c01f0f1a
YS		 237#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
238 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
7d740a06 239 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 240 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 241 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 242 defined(CONFIG_CPU_SUBTYPE_SHX3)
d5701647
PM		 243static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
244{
245 if (!(cflag & CRTSCTS))
246 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
247}
b0c50ad7 248#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
d5701647
PM		 249static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
250{
251 if (!(cflag & CRTSCTS))
252 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
253}
b7a76e4b 254#else
d5701647
PM		 255static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
256{
257 /* Nothing to do */
1da177e4 258}
e108b2ca
PM		 259#endif
260
32351a28
PM		 261#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
262 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 263 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
264 defined(CONFIG_CPU_SUBTYPE_SH7786)
73a19e4c 265static int scif_txfill(struct uart_port *port)
e108b2ca 266{
73a19e4c 267 return sci_in(port, SCTFDR) & 0xff;
e108b2ca
PM		 268}
269
73a19e4c 270static int scif_txroom(struct uart_port *port)
e108b2ca 271{
73a19e4c 272 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca
PM		 273}
274
73a19e4c 275static int scif_rxfill(struct uart_port *port)
e108b2ca 276{
cae167d3 277 return sci_in(port, SCRFDR) & 0xff;
e108b2ca 278}
c63847a3 279#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
73a19e4c 280static int scif_txfill(struct uart_port *port)
c63847a3 281{
73a19e4c
GL		 282 if (port->mapbase == 0xffe00000 ||
283 port->mapbase == 0xffe08000)
e7c98dc7 284 /* SCIF0/1*/
73a19e4c
GL		 285 return sci_in(port, SCTFDR) & 0xff;
286 else
e7c98dc7 287 /* SCIF2 */
73a19e4c 288 return sci_in(port, SCFDR) >> 8;
c63847a3
NI		 289}
290
73a19e4c
GL		 291static int scif_txroom(struct uart_port *port)
292{
293 if (port->mapbase == 0xffe00000 ||
294 port->mapbase == 0xffe08000)
295 /* SCIF0/1*/
296 return SCIF_TXROOM_MAX - scif_txfill(port);
297 else
298 /* SCIF2 */
299 return SCIF2_TXROOM_MAX - scif_txfill(port);
c63847a3
NI		 300}
301
73a19e4c 302static int scif_rxfill(struct uart_port *port)
c63847a3 303{
e7c98dc7
MT		 304 if ((port->mapbase == 0xffe00000) ||
305 (port->mapbase == 0xffe08000)) {
306 /* SCIF0/1*/
c63847a3 307 return sci_in(port, SCRFDR) & 0xff;
e7c98dc7
MT		 308 } else {
309 /* SCIF2 */
c63847a3 310 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
e7c98dc7 311 }
c63847a3 312}
d1d4b10c
GL		 313#elif defined(CONFIG_ARCH_SH7372)
314static int scif_txfill(struct uart_port *port)
315{
316 if (port->type == PORT_SCIFA)
317 return sci_in(port, SCFDR) >> 8;
318 else
319 return sci_in(port, SCTFDR);
320}
321
322static int scif_txroom(struct uart_port *port)
323{
324 return port->fifosize - scif_txfill(port);
325}
326
327static int scif_rxfill(struct uart_port *port)
328{
329 if (port->type == PORT_SCIFA)
330 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
331 else
332 return sci_in(port, SCRFDR);
333}
e108b2ca 334#else
73a19e4c 335static int scif_txfill(struct uart_port *port)
e108b2ca 336{
73a19e4c 337 return sci_in(port, SCFDR) >> 8;
e108b2ca 338}
1da177e4 339
73a19e4c 340static int scif_txroom(struct uart_port *port)
e108b2ca 341{
73a19e4c 342 return SCIF_TXROOM_MAX - scif_txfill(port);
e108b2ca 343}
1da177e4 344
73a19e4c 345static int scif_rxfill(struct uart_port *port)
e108b2ca
PM		 346{
347 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
348}
1da177e4 349#endif
1da177e4 350
73a19e4c 351static int sci_txfill(struct uart_port *port)
e108b2ca 352{
73a19e4c 353 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 354}
355
73a19e4c
GL		 356static int sci_txroom(struct uart_port *port)
357{
358 return !sci_txfill(port);
359}
360
361static int sci_rxfill(struct uart_port *port)
e108b2ca 362{
e7c98dc7 363 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 364}
365
1da177e4
LT		 366/* ********************************************************************** *
367 * the interrupt related routines *
368 * ********************************************************************** */
369
370static void sci_transmit_chars(struct uart_port *port)
371{
ebd2c8f6 372 struct circ_buf *xmit = &port->state->xmit;
1da177e4 373 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 374 unsigned short status;
375 unsigned short ctrl;
e108b2ca 376 int count;
1da177e4
LT		 377
378 status = sci_in(port, SCxSR);
379 if (!(status & SCxSR_TDxE(port))) {
1da177e4 380 ctrl = sci_in(port, SCSCR);
e7c98dc7 381 if (uart_circ_empty(xmit))
8e698614 382 ctrl &= ~SCSCR_TIE;
e7c98dc7 383 else
8e698614 384 ctrl |= SCSCR_TIE;
1da177e4 385 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 386 return;
387 }
388
1a22f08d 389 if (port->type == PORT_SCI)
e108b2ca 390 count = sci_txroom(port);
1a22f08d
YS		 391 else
392 count = scif_txroom(port);
1da177e4
LT		 393
394 do {
395 unsigned char c;
396
397 if (port->x_char) {
398 c = port->x_char;
399 port->x_char = 0;
400 } else if (!uart_circ_empty(xmit) && !stopped) {
401 c = xmit->buf[xmit->tail];
402 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
403 } else {
404 break;
405 }
406
407 sci_out(port, SCxTDR, c);
408
409 port->icount.tx++;
410 } while (--count > 0);
411
412 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
413
414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
415 uart_write_wakeup(port);
416 if (uart_circ_empty(xmit)) {
b129a8cc 417 sci_stop_tx(port);
1da177e4 418 } else {
1da177e4
LT		 419 ctrl = sci_in(port, SCSCR);
420
1a22f08d 421 if (port->type != PORT_SCI) {
1da177e4
LT		 422 sci_in(port, SCxSR); /* Dummy read */
423 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
424 }
1da177e4 425
8e698614 426 ctrl |= SCSCR_TIE;
1da177e4 427 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 428 }
429}
430
431/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 432#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 433
94c8b6db 434static void sci_receive_chars(struct uart_port *port)
1da177e4 435{
e7c98dc7 436 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 437 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 438 int i, count, copied = 0;
439 unsigned short status;
33f0f88f 440 unsigned char flag;
1da177e4
LT		 441
442 status = sci_in(port, SCxSR);
443 if (!(status & SCxSR_RDxF(port)))
444 return;
445
446 while (1) {
1a22f08d 447 if (port->type == PORT_SCI)
73a19e4c 448 count = sci_rxfill(port);
1a22f08d 449 else
73a19e4c 450 count = scif_rxfill(port);
1da177e4
LT		 451
452 /* Don't copy more bytes than there is room for in the buffer */
33f0f88f 453 count = tty_buffer_request_room(tty, count);
1da177e4
LT		 454
455 /* If for any reason we can't copy more data, we're done! */
456 if (count == 0)
457 break;
458
459 if (port->type == PORT_SCI) {
460 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 461 if (uart_handle_sysrq_char(port, c) ||
462 sci_port->break_flag)
1da177e4 463 count = 0;
e7c98dc7 464 else
e108b2ca 465 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 466 } else {
e7c98dc7 467 for (i = 0; i < count; i++) {
1da177e4
LT		 468 char c = sci_in(port, SCxRDR);
469 status = sci_in(port, SCxSR);
470#if defined(CONFIG_CPU_SH3)
471 /* Skip "chars" during break */
e108b2ca 472 if (sci_port->break_flag) {
1da177e4
LT		 473 if ((c == 0) &&
474 (status & SCxSR_FER(port))) {
475 count--; i--;
476 continue;
477 }
e108b2ca 478
1da177e4 479 /* Nonzero => end-of-break */
762c69e3 480 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 481 sci_port->break_flag = 0;
482
1da177e4
LT		 483 if (STEPFN(c)) {
484 count--; i--;
485 continue;
486 }
487 }
488#endif /* CONFIG_CPU_SH3 */
7d12e780 489 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 490 count--; i--;
491 continue;
492 }
493
494 /* Store data and status */
73a19e4c 495 if (status & SCxSR_FER(port)) {
33f0f88f 496 flag = TTY_FRAME;
762c69e3 497 dev_notice(port->dev, "frame error\n");
73a19e4c 498 } else if (status & SCxSR_PER(port)) {
33f0f88f 499 flag = TTY_PARITY;
762c69e3 500 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 501 } else
502 flag = TTY_NORMAL;
762c69e3 503
33f0f88f 504 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 505 }
506 }
507
508 sci_in(port, SCxSR); /* dummy read */
509 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
510
1da177e4
LT		 511 copied += count;
512 port->icount.rx += count;
513 }
514
515 if (copied) {
516 /* Tell the rest of the system the news. New characters! */
517 tty_flip_buffer_push(tty);
518 } else {
519 sci_in(port, SCxSR); /* dummy read */
520 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
521 }
522}
523
524#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 525
526/*
527 * The sci generates interrupts during the break,
1da177e4
LT		 528 * 1 per millisecond or so during the break period, for 9600 baud.
529 * So dont bother disabling interrupts.
530 * But dont want more than 1 break event.
531 * Use a kernel timer to periodically poll the rx line until
532 * the break is finished.
533 */
94c8b6db 534static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 535{
bc9b3f5c 536 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 537}
94c8b6db 538
1da177e4
LT		 539/* Ensure that two consecutive samples find the break over. */
540static void sci_break_timer(unsigned long data)
541{
e108b2ca
PM		 542 struct sci_port *port = (struct sci_port *)data;
543
5e50d2d6
MD		 544 if (port->enable)
545 port->enable(&port->port);
546
e108b2ca 547 if (sci_rxd_in(&port->port) == 0) {
1da177e4 548 port->break_flag = 1;
e108b2ca
PM		 549 sci_schedule_break_timer(port);
550 } else if (port->break_flag == 1) {
1da177e4
LT		 551 /* break is over. */
552 port->break_flag = 2;
e108b2ca
PM		 553 sci_schedule_break_timer(port);
554 } else
555 port->break_flag = 0;
5e50d2d6
MD		 556
557 if (port->disable)
558 port->disable(&port->port);
1da177e4
LT		 559}
560
94c8b6db 561static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 562{
563 int copied = 0;
564 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 565 struct tty_struct *tty = port->state->port.tty;
debf9507 566 struct sci_port *s = to_sci_port(port);
1da177e4 567
debf9507
PM		 568 /*
569 * Handle overruns, if supported.
570 */
571 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
572 if (status & (1 << s->cfg->overrun_bit)) {
573 /* overrun error */
574 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
575 copied++;
762c69e3 576
debf9507
PM		 577 dev_notice(port->dev, "overrun error");
578 }
1da177e4
LT		 579 }
580
e108b2ca 581 if (status & SCxSR_FER(port)) {
1da177e4
LT		 582 if (sci_rxd_in(port) == 0) {
583 /* Notify of BREAK */
e7c98dc7 584 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 585
586 if (!sci_port->break_flag) {
587 sci_port->break_flag = 1;
588 sci_schedule_break_timer(sci_port);
589
1da177e4 590 /* Do sysrq handling. */
e108b2ca 591 if (uart_handle_break(port))
1da177e4 592 return 0;
762c69e3
PM		 593
594 dev_dbg(port->dev, "BREAK detected\n");
595
e108b2ca 596 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 597 copied++;
598 }
599
e108b2ca 600 } else {
1da177e4 601 /* frame error */
e108b2ca 602 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 603 copied++;
762c69e3
PM		 604
605 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 606 }
607 }
608
e108b2ca 609 if (status & SCxSR_PER(port)) {
1da177e4 610 /* parity error */
e108b2ca
PM		 611 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
612 copied++;
762c69e3
PM		 613
614 dev_notice(port->dev, "parity error");
1da177e4
LT		 615 }
616
33f0f88f 617 if (copied)
1da177e4 618 tty_flip_buffer_push(tty);
1da177e4
LT		 619
620 return copied;
621}
622
94c8b6db 623static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 624{
ebd2c8f6 625 struct tty_struct *tty = port->state->port.tty;
debf9507 626 struct sci_port *s = to_sci_port(port);
d830fa45
PM		 627 int copied = 0;
628
debf9507
PM		 629 /*
630 * XXX: Technically not limited to non-SCIFs, it's simply the
631 * SCLSR check that is for the moment SCIF-specific. This
632 * probably wants to be revisited for SCIFA/B as well as for
633 * factoring in SCI overrun detection.
634 */
d830fa45
PM		 635 if (port->type != PORT_SCIF)
636 return 0;
637
debf9507 638 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
d830fa45
PM		 639 sci_out(port, SCLSR, 0);
640
641 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
642 tty_flip_buffer_push(tty);
643
644 dev_notice(port->dev, "overrun error\n");
645 copied++;
646 }
647
648 return copied;
649}
650
94c8b6db 651static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 652{
653 int copied = 0;
654 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 655 struct tty_struct *tty = port->state->port.tty;
a5660ada 656 struct sci_port *s = to_sci_port(port);
1da177e4 657
0b3d4ef6
PM		 658 if (uart_handle_break(port))
659 return 0;
660
b7a76e4b 661 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 662#if defined(CONFIG_CPU_SH3)
663 /* Debounce break */
664 s->break_flag = 1;
665#endif
666 /* Notify of BREAK */
e108b2ca 667 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 668 copied++;
762c69e3
PM		 669
670 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 671 }
672
33f0f88f 673 if (copied)
1da177e4 674 tty_flip_buffer_push(tty);
e108b2ca 675
d830fa45
PM		 676 copied += sci_handle_fifo_overrun(port);
677
1da177e4
LT		 678 return copied;
679}
680
73a19e4c 681static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 682{
73a19e4c
GL		 683#ifdef CONFIG_SERIAL_SH_SCI_DMA
684 struct uart_port *port = ptr;
685 struct sci_port *s = to_sci_port(port);
686
687 if (s->chan_rx) {
73a19e4c
GL		 688 u16 scr = sci_in(port, SCSCR);
689 u16 ssr = sci_in(port, SCxSR);
690
691 /* Disable future Rx interrupts */
d1d4b10c 692 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 693 disable_irq_nosync(irq);
694 scr |= 0x4000;
695 } else {
f43dc23d 696 scr &= ~SCSCR_RIE;
3089f381
GL		 697 }
698 sci_out(port, SCSCR, scr);
73a19e4c
GL		 699 /* Clear current interrupt */
700 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 701 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
702 jiffies, s->rx_timeout);
703 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 704
705 return IRQ_HANDLED;
706 }
707#endif
708
1da177e4
LT		 709 /* I think sci_receive_chars has to be called irrespective
710 * of whether the I_IXOFF is set, otherwise, how is the interrupt
711 * to be disabled?
712 */
73a19e4c 713 sci_receive_chars(ptr);
1da177e4
LT		 714
715 return IRQ_HANDLED;
716}
717
7d12e780 718static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 719{
720 struct uart_port *port = ptr;
fd78a76a 721 unsigned long flags;
1da177e4 722
fd78a76a 723 spin_lock_irqsave(&port->lock, flags);
1da177e4 724 sci_transmit_chars(port);
fd78a76a 725 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 726
727 return IRQ_HANDLED;
728}
729
7d12e780 730static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 731{
732 struct uart_port *port = ptr;
733
734 /* Handle errors */
735 if (port->type == PORT_SCI) {
736 if (sci_handle_errors(port)) {
737 /* discard character in rx buffer */
738 sci_in(port, SCxSR);
739 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
740 }
741 } else {
d830fa45 742 sci_handle_fifo_overrun(port);
7d12e780 743 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 744 }
745
746 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
747
748 /* Kick the transmission */
7d12e780 749 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 750
751 return IRQ_HANDLED;
752}
753
7d12e780 754static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 755{
756 struct uart_port *port = ptr;
757
758 /* Handle BREAKs */
759 sci_handle_breaks(port);
760 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
761
762 return IRQ_HANDLED;
763}
764
f43dc23d
PM		 765static inline unsigned long port_rx_irq_mask(struct uart_port *port)
766{
767 /*
768 * Not all ports (such as SCIFA) will support REIE. Rather than
769 * special-casing the port type, we check the port initialization
770 * IRQ enable mask to see whether the IRQ is desired at all. If
771 * it's unset, it's logically inferred that there's no point in
772 * testing for it.
773 */
ce6738b6 774 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 775}
776
7d12e780 777static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 778{
44e18e9e 779 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 780 struct uart_port *port = ptr;
73a19e4c 781 struct sci_port *s = to_sci_port(port);
a8884e34 782 irqreturn_t ret = IRQ_NONE;
1da177e4 783
e7c98dc7
MT		 784 ssr_status = sci_in(port, SCxSR);
785 scr_status = sci_in(port, SCSCR);
f43dc23d 786 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 787
788 /* Tx Interrupt */
f43dc23d 789 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 790 !s->chan_tx)
a8884e34 791 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 792
73a19e4c
GL		 793 /*
794 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
795 * DR flags
796 */
797 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 798 (scr_status & SCSCR_RIE))
a8884e34 799 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 800
1da177e4 801 /* Error Interrupt */
dd4da3a5 802 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 803 ret = sci_er_interrupt(irq, ptr);
f43dc23d 804
1da177e4 805 /* Break Interrupt */
dd4da3a5 806 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 807 ret = sci_br_interrupt(irq, ptr);
1da177e4 808
a8884e34 809 return ret;
1da177e4
LT		 810}
811
1da177e4 812/*
25985edc 813 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 814 * ports' baud rate when the peripheral clock changes.
815 */
e108b2ca
PM		 816static int sci_notifier(struct notifier_block *self,
817 unsigned long phase, void *p)
1da177e4 818{
e552de24
MD		 819 struct sci_port *sci_port;
820 unsigned long flags;
1da177e4 821
d535a230
PM		 822 sci_port = container_of(self, struct sci_port, freq_transition);
823
1da177e4 824 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 825 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 826 struct uart_port *port = &sci_port->port;
073e84c9 827
d535a230
PM		 828 spin_lock_irqsave(&port->lock, flags);
829 port->uartclk = clk_get_rate(sci_port->iclk);
830 spin_unlock_irqrestore(&port->lock, flags);
e552de24 831 }
1da177e4 832
1da177e4
LT		 833 return NOTIFY_OK;
834}
501b825d
MD		 835
836static void sci_clk_enable(struct uart_port *port)
837{
838 struct sci_port *sci_port = to_sci_port(port);
839
5e50d2d6
MD		 840 pm_runtime_get_sync(port->dev);
841
c7ed1ab3
PM		 842 clk_enable(sci_port->iclk);
843 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
844 clk_enable(sci_port->fclk);
501b825d
MD		 845}
846
847static void sci_clk_disable(struct uart_port *port)
848{
849 struct sci_port *sci_port = to_sci_port(port);
850
c7ed1ab3
PM		 851 clk_disable(sci_port->fclk);
852 clk_disable(sci_port->iclk);
5e50d2d6
MD		 853
854 pm_runtime_put_sync(port->dev);
501b825d 855}
1da177e4
LT		 856
857static int sci_request_irq(struct sci_port *port)
858{
859 int i;
7d12e780 860 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
1da177e4
LT		 861 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
862 sci_br_interrupt,
863 };
864 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
865 "SCI Transmit Data Empty", "SCI Break" };
866
ce6738b6
PM		 867 if (port->cfg->irqs[0] == port->cfg->irqs[1]) {
868 if (unlikely(!port->cfg->irqs[0]))
1da177e4 869 return -ENODEV;
e108b2ca 870
ce6738b6 871 if (request_irq(port->cfg->irqs[0], sci_mpxed_interrupt,
35f3c518 872 IRQF_DISABLED, "sci", port)) {
762c69e3 873 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 874 return -ENODEV;
875 }
876 } else {
877 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
ce6738b6 878 if (unlikely(!port->cfg->irqs[i]))
1da177e4 879 continue;
762c69e3 880
ce6738b6 881 if (request_irq(port->cfg->irqs[i], handlers[i],
35f3c518 882 IRQF_DISABLED, desc[i], port)) {
762c69e3 883 dev_err(port->port.dev, "Can't allocate IRQ\n");
1da177e4
LT		 884 return -ENODEV;
885 }
886 }
887 }
888
889 return 0;
890}
891
892static void sci_free_irq(struct sci_port *port)
893{
894 int i;
895
ce6738b6
PM		 896 if (port->cfg->irqs[0] == port->cfg->irqs[1])
897 free_irq(port->cfg->irqs[0], port);
762c69e3 898 else {
ce6738b6
PM		 899 for (i = 0; i < ARRAY_SIZE(port->cfg->irqs); i++) {
900 if (!port->cfg->irqs[i])
1da177e4
LT		 901 continue;
902
ce6738b6 903 free_irq(port->cfg->irqs[i], port);
1da177e4
LT		 904 }
905 }
906}
907
908static unsigned int sci_tx_empty(struct uart_port *port)
909{
b1516803 910 unsigned short status = sci_in(port, SCxSR);
73a19e4c
GL		 911 unsigned short in_tx_fifo = scif_txfill(port);
912
913 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 914}
915
916static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
917{
918 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
919 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
920 /* If you have signals for DTR and DCD, please implement here. */
921}
922
923static unsigned int sci_get_mctrl(struct uart_port *port)
924{
73a19e4c 925 /* This routine is used for getting signals of: DTR, DCD, DSR, RI,
1da177e4
LT		 926 and CTS/RTS */
927
928 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
929}
930
73a19e4c
GL		 931#ifdef CONFIG_SERIAL_SH_SCI_DMA
932static void sci_dma_tx_complete(void *arg)
933{
934 struct sci_port *s = arg;
935 struct uart_port *port = &s->port;
936 struct circ_buf *xmit = &port->state->xmit;
937 unsigned long flags;
938
939 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
940
941 spin_lock_irqsave(&port->lock, flags);
942
f354a381 943 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 944 xmit->tail &= UART_XMIT_SIZE - 1;
945
f354a381 946 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 947
948 async_tx_ack(s->desc_tx);
949 s->cookie_tx = -EINVAL;
950 s->desc_tx = NULL;
951
73a19e4c
GL		 952 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
953 uart_write_wakeup(port);
954
3089f381 955 if (!uart_circ_empty(xmit)) {
73a19e4c 956 schedule_work(&s->work_tx);
d1d4b10c 957 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 958 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 959 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 960 }
961
962 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 963}
964
965/* Locking: called with port lock held */
966static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
967 size_t count)
968{
969 struct uart_port *port = &s->port;
970 int i, active, room;
971
972 room = tty_buffer_request_room(tty, count);
973
974 if (s->active_rx == s->cookie_rx[0]) {
975 active = 0;
976 } else if (s->active_rx == s->cookie_rx[1]) {
977 active = 1;
978 } else {
979 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
980 return 0;
981 }
982
983 if (room < count)
984 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
985 count - room);
986 if (!room)
987 return room;
988
989 for (i = 0; i < room; i++)
990 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
991 TTY_NORMAL);
992
993 port->icount.rx += room;
994
995 return room;
996}
997
998static void sci_dma_rx_complete(void *arg)
999{
1000 struct sci_port *s = arg;
1001 struct uart_port *port = &s->port;
1002 struct tty_struct *tty = port->state->port.tty;
1003 unsigned long flags;
1004 int count;
1005
3089f381 1006 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1007
1008 spin_lock_irqsave(&port->lock, flags);
1009
1010 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1011
3089f381 1012 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1013
1014 spin_unlock_irqrestore(&port->lock, flags);
1015
1016 if (count)
1017 tty_flip_buffer_push(tty);
1018
1019 schedule_work(&s->work_rx);
1020}
1021
73a19e4c
GL		 1022static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1023{
1024 struct dma_chan *chan = s->chan_rx;
1025 struct uart_port *port = &s->port;
73a19e4c
GL		 1026
1027 s->chan_rx = NULL;
1028 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1029 dma_release_channel(chan);
85b8e3ff
GL		 1030 if (sg_dma_address(&s->sg_rx[0]))
1031 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1032 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1033 if (enable_pio)
1034 sci_start_rx(port);
1035}
1036
1037static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1038{
1039 struct dma_chan *chan = s->chan_tx;
1040 struct uart_port *port = &s->port;
73a19e4c
GL		 1041
1042 s->chan_tx = NULL;
1043 s->cookie_tx = -EINVAL;
1044 dma_release_channel(chan);
1045 if (enable_pio)
1046 sci_start_tx(port);
1047}
1048
1049static void sci_submit_rx(struct sci_port *s)
1050{
1051 struct dma_chan *chan = s->chan_rx;
1052 int i;
1053
1054 for (i = 0; i < 2; i++) {
1055 struct scatterlist *sg = &s->sg_rx[i];
1056 struct dma_async_tx_descriptor *desc;
1057
1058 desc = chan->device->device_prep_slave_sg(chan,
1059 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1060
1061 if (desc) {
1062 s->desc_rx[i] = desc;
1063 desc->callback = sci_dma_rx_complete;
1064 desc->callback_param = s;
1065 s->cookie_rx[i] = desc->tx_submit(desc);
1066 }
1067
1068 if (!desc || s->cookie_rx[i] < 0) {
1069 if (i) {
1070 async_tx_ack(s->desc_rx[0]);
1071 s->cookie_rx[0] = -EINVAL;
1072 }
1073 if (desc) {
1074 async_tx_ack(desc);
1075 s->cookie_rx[i] = -EINVAL;
1076 }
1077 dev_warn(s->port.dev,
1078 "failed to re-start DMA, using PIO\n");
1079 sci_rx_dma_release(s, true);
1080 return;
1081 }
3089f381
GL		 1082 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1083 s->cookie_rx[i], i);
73a19e4c
GL		 1084 }
1085
1086 s->active_rx = s->cookie_rx[0];
1087
1088 dma_async_issue_pending(chan);
1089}
1090
1091static void work_fn_rx(struct work_struct *work)
1092{
1093 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1094 struct uart_port *port = &s->port;
1095 struct dma_async_tx_descriptor *desc;
1096 int new;
1097
1098 if (s->active_rx == s->cookie_rx[0]) {
1099 new = 0;
1100 } else if (s->active_rx == s->cookie_rx[1]) {
1101 new = 1;
1102 } else {
1103 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1104 return;
1105 }
1106 desc = s->desc_rx[new];
1107
1108 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1109 DMA_SUCCESS) {
1110 /* Handle incomplete DMA receive */
1111 struct tty_struct *tty = port->state->port.tty;
1112 struct dma_chan *chan = s->chan_rx;
1113 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1114 async_tx);
1115 unsigned long flags;
1116 int count;
1117
05827630 1118 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1119 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1120 sh_desc->partial, sh_desc->cookie);
1121
1122 spin_lock_irqsave(&port->lock, flags);
1123 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1124 spin_unlock_irqrestore(&port->lock, flags);
1125
1126 if (count)
1127 tty_flip_buffer_push(tty);
1128
1129 sci_submit_rx(s);
1130
1131 return;
1132 }
1133
1134 s->cookie_rx[new] = desc->tx_submit(desc);
1135 if (s->cookie_rx[new] < 0) {
1136 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1137 sci_rx_dma_release(s, true);
1138 return;
1139 }
1140
73a19e4c 1141 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1142
1143 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1144 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1145}
1146
1147static void work_fn_tx(struct work_struct *work)
1148{
1149 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1150 struct dma_async_tx_descriptor *desc;
1151 struct dma_chan *chan = s->chan_tx;
1152 struct uart_port *port = &s->port;
1153 struct circ_buf *xmit = &port->state->xmit;
1154 struct scatterlist *sg = &s->sg_tx;
1155
1156 /*
1157 * DMA is idle now.
1158 * Port xmit buffer is already mapped, and it is one page... Just adjust
1159 * offsets and lengths. Since it is a circular buffer, we have to
1160 * transmit till the end, and then the rest. Take the port lock to get a
1161 * consistent xmit buffer state.
1162 */
1163 spin_lock_irq(&port->lock);
1164 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1165 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1166 sg->offset;
f354a381 1167 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1168 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1169 spin_unlock_irq(&port->lock);
1170
f354a381 1171 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1172
1173 desc = chan->device->device_prep_slave_sg(chan,
1174 sg, s->sg_len_tx, DMA_TO_DEVICE,
1175 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1176 if (!desc) {
1177 /* switch to PIO */
1178 sci_tx_dma_release(s, true);
1179 return;
1180 }
1181
1182 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1183
1184 spin_lock_irq(&port->lock);
1185 s->desc_tx = desc;
1186 desc->callback = sci_dma_tx_complete;
1187 desc->callback_param = s;
1188 spin_unlock_irq(&port->lock);
1189 s->cookie_tx = desc->tx_submit(desc);
1190 if (s->cookie_tx < 0) {
1191 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1192 /* switch to PIO */
1193 sci_tx_dma_release(s, true);
1194 return;
1195 }
1196
1197 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1198 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1199
1200 dma_async_issue_pending(chan);
1201}
1202#endif
1203
b129a8cc 1204static void sci_start_tx(struct uart_port *port)
1da177e4 1205{
3089f381 1206 struct sci_port *s = to_sci_port(port);
e108b2ca 1207 unsigned short ctrl;
1da177e4 1208
73a19e4c 1209#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1211 u16 new, scr = sci_in(port, SCSCR);
1212 if (s->chan_tx)
1213 new = scr | 0x8000;
1214 else
1215 new = scr & ~0x8000;
1216 if (new != scr)
1217 sci_out(port, SCSCR, new);
73a19e4c 1218 }
f43dc23d 1219
3089f381
GL		 1220 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1221 s->cookie_tx < 0)
1222 schedule_work(&s->work_tx);
73a19e4c 1223#endif
f43dc23d 1224
d1d4b10c 1225 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1226 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1227 ctrl = sci_in(port, SCSCR);
f43dc23d 1228 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1229 }
1da177e4
LT		 1230}
1231
b129a8cc 1232static void sci_stop_tx(struct uart_port *port)
1da177e4 1233{
1da177e4
LT		 1234 unsigned short ctrl;
1235
1236 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1237 ctrl = sci_in(port, SCSCR);
f43dc23d 1238
d1d4b10c 1239 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1240 ctrl &= ~0x8000;
f43dc23d 1241
8e698614 1242 ctrl &= ~SCSCR_TIE;
f43dc23d 1243
1da177e4 1244 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1245}
1246
73a19e4c 1247static void sci_start_rx(struct uart_port *port)
1da177e4 1248{
1da177e4
LT		 1249 unsigned short ctrl;
1250
f43dc23d 1251 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1252
d1d4b10c 1253 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1254 ctrl &= ~0x4000;
f43dc23d 1255
1da177e4 1256 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1257}
1258
1259static void sci_stop_rx(struct uart_port *port)
1260{
1da177e4
LT		 1261 unsigned short ctrl;
1262
1da177e4 1263 ctrl = sci_in(port, SCSCR);
f43dc23d 1264
d1d4b10c 1265 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1266 ctrl &= ~0x4000;
f43dc23d
PM		 1267
1268 ctrl &= ~port_rx_irq_mask(port);
1269
1da177e4 1270 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1271}
1272
1273static void sci_enable_ms(struct uart_port *port)
1274{
1275 /* Nothing here yet .. */
1276}
1277
1278static void sci_break_ctl(struct uart_port *port, int break_state)
1279{
1280 /* Nothing here yet .. */
1281}
1282
73a19e4c
GL		 1283#ifdef CONFIG_SERIAL_SH_SCI_DMA
1284static bool filter(struct dma_chan *chan, void *slave)
1285{
1286 struct sh_dmae_slave *param = slave;
1287
1288 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1289 param->slave_id);
1290
1291 if (param->dma_dev == chan->device->dev) {
1292 chan->private = param;
1293 return true;
1294 } else {
1295 return false;
1296 }
1297}
1298
1299static void rx_timer_fn(unsigned long arg)
1300{
1301 struct sci_port *s = (struct sci_port *)arg;
1302 struct uart_port *port = &s->port;
73a19e4c 1303 u16 scr = sci_in(port, SCSCR);
3089f381 1304
d1d4b10c 1305 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1306 scr &= ~0x4000;
ce6738b6 1307 enable_irq(s->cfg->irqs[1]);
3089f381 1308 }
f43dc23d 1309 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1310 dev_dbg(port->dev, "DMA Rx timed out\n");
1311 schedule_work(&s->work_rx);
1312}
1313
1314static void sci_request_dma(struct uart_port *port)
1315{
1316 struct sci_port *s = to_sci_port(port);
1317 struct sh_dmae_slave *param;
1318 struct dma_chan *chan;
1319 dma_cap_mask_t mask;
1320 int nent;
1321
1322 dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
ce6738b6 1323 port->line, s->cfg->dma_dev);
73a19e4c 1324
ce6738b6 1325 if (!s->cfg->dma_dev)
73a19e4c
GL		 1326 return;
1327
1328 dma_cap_zero(mask);
1329 dma_cap_set(DMA_SLAVE, mask);
1330
1331 param = &s->param_tx;
1332
1333 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6
PM		 1334 param->slave_id = s->cfg->dma_slave_tx;
1335 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1336
1337 s->cookie_tx = -EINVAL;
1338 chan = dma_request_channel(mask, filter, param);
1339 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1340 if (chan) {
1341 s->chan_tx = chan;
1342 sg_init_table(&s->sg_tx, 1);
1343 /* UART circular tx buffer is an aligned page. */
1344 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1345 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1346 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1347 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1348 if (!nent)
1349 sci_tx_dma_release(s, false);
1350 else
1351 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1352 sg_dma_len(&s->sg_tx),
1353 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1354
1355 s->sg_len_tx = nent;
1356
1357 INIT_WORK(&s->work_tx, work_fn_tx);
1358 }
1359
1360 param = &s->param_rx;
1361
1362 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6
PM		 1363 param->slave_id = s->cfg->dma_slave_rx;
1364 param->dma_dev = s->cfg->dma_dev;
73a19e4c
GL		 1365
1366 chan = dma_request_channel(mask, filter, param);
1367 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1368 if (chan) {
1369 dma_addr_t dma[2];
1370 void *buf[2];
1371 int i;
1372
1373 s->chan_rx = chan;
1374
1375 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1376 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1377 &dma[0], GFP_KERNEL);
1378
1379 if (!buf[0]) {
1380 dev_warn(port->dev,
1381 "failed to allocate dma buffer, using PIO\n");
1382 sci_rx_dma_release(s, true);
1383 return;
1384 }
1385
1386 buf[1] = buf[0] + s->buf_len_rx;
1387 dma[1] = dma[0] + s->buf_len_rx;
1388
1389 for (i = 0; i < 2; i++) {
1390 struct scatterlist *sg = &s->sg_rx[i];
1391
1392 sg_init_table(sg, 1);
1393 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1394 (int)buf[i] & ~PAGE_MASK);
f354a381 1395 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1396 }
1397
1398 INIT_WORK(&s->work_rx, work_fn_rx);
1399 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1400
1401 sci_submit_rx(s);
1402 }
1403}
1404
1405static void sci_free_dma(struct uart_port *port)
1406{
1407 struct sci_port *s = to_sci_port(port);
1408
ce6738b6 1409 if (!s->cfg->dma_dev)
73a19e4c
GL		 1410 return;
1411
1412 if (s->chan_tx)
1413 sci_tx_dma_release(s, false);
1414 if (s->chan_rx)
1415 sci_rx_dma_release(s, false);
1416}
27bd1075
PM		 1417#else
1418static inline void sci_request_dma(struct uart_port *port)
1419{
1420}
1421
1422static inline void sci_free_dma(struct uart_port *port)
1423{
1424}
73a19e4c
GL		 1425#endif
1426
1da177e4
LT		 1427static int sci_startup(struct uart_port *port)
1428{
a5660ada 1429 struct sci_port *s = to_sci_port(port);
073e84c9 1430 int ret;
1da177e4 1431
73a19e4c
GL		 1432 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1433
e108b2ca
PM		 1434 if (s->enable)
1435 s->enable(port);
1da177e4 1436
073e84c9
PM		 1437 ret = sci_request_irq(s);
1438 if (unlikely(ret < 0))
1439 return ret;
1440
73a19e4c 1441 sci_request_dma(port);
073e84c9 1442
d656901b 1443 sci_start_tx(port);
73a19e4c 1444 sci_start_rx(port);
1da177e4
LT		 1445
1446 return 0;
1447}
1448
1449static void sci_shutdown(struct uart_port *port)
1450{
a5660ada 1451 struct sci_port *s = to_sci_port(port);
1da177e4 1452
73a19e4c
GL		 1453 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1454
1da177e4 1455 sci_stop_rx(port);
b129a8cc 1456 sci_stop_tx(port);
073e84c9 1457
73a19e4c 1458 sci_free_dma(port);
1da177e4
LT		 1459 sci_free_irq(s);
1460
e108b2ca
PM		 1461 if (s->disable)
1462 s->disable(port);
1da177e4
LT		 1463}
1464
26c92f37
PM		 1465static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1466 unsigned long freq)
1467{
1468 switch (algo_id) {
1469 case SCBRR_ALGO_1:
1470 return ((freq + 16 * bps) / (16 * bps) - 1);
1471 case SCBRR_ALGO_2:
1472 return ((freq + 16 * bps) / (32 * bps) - 1);
1473 case SCBRR_ALGO_3:
1474 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1475 case SCBRR_ALGO_4:
1476 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1477 case SCBRR_ALGO_5:
1478 return (((freq * 1000 / 32) / bps) - 1);
1479 }
1480
1481 /* Warn, but use a safe default */
1482 WARN_ON(1);
e8183a6c 1483
26c92f37
PM		 1484 return ((freq + 16 * bps) / (32 * bps) - 1);
1485}
1486
606d099c
AC		 1487static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1488 struct ktermios *old)
1da177e4 1489{
00b9de9c 1490 struct sci_port *s = to_sci_port(port);
154280fd 1491 unsigned int status, baud, smr_val, max_baud;
a2159b52 1492 int t = -1;
3089f381 1493 u16 scfcr = 0;
1da177e4 1494
154280fd
MD		 1495 /*
1496 * earlyprintk comes here early on with port->uartclk set to zero.
1497 * the clock framework is not up and running at this point so here
1498 * we assume that 115200 is the maximum baud rate. please note that
1499 * the baud rate is not programmed during earlyprintk - it is assumed
1500 * that the previous boot loader has enabled required clocks and
1501 * setup the baud rate generator hardware for us already.
1502 */
1503 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1504
154280fd
MD		 1505 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1506 if (likely(baud && port->uartclk))
ce6738b6 1507 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1508
36003386
AC		 1509 if (s->enable)
1510 s->enable(port);
1511
1da177e4
LT		 1512 do {
1513 status = sci_in(port, SCxSR);
1514 } while (!(status & SCxSR_TEND(port)));
1515
1516 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1517
1a22f08d 1518 if (port->type != PORT_SCI)
3089f381 1519 sci_out(port, SCFCR, scfcr | SCFCR_RFRST | SCFCR_TFRST);
1da177e4
LT		 1520
1521 smr_val = sci_in(port, SCSMR) & 3;
e8183a6c 1522
1da177e4
LT		 1523 if ((termios->c_cflag & CSIZE) == CS7)
1524 smr_val |= 0x40;
1525 if (termios->c_cflag & PARENB)
1526 smr_val |= 0x20;
1527 if (termios->c_cflag & PARODD)
1528 smr_val |= 0x30;
1529 if (termios->c_cflag & CSTOPB)
1530 smr_val |= 0x08;
1531
1532 uart_update_timeout(port, termios->c_cflag, baud);
1533
1534 sci_out(port, SCSMR, smr_val);
1535
73a19e4c 1536 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1537 s->cfg->scscr);
73a19e4c 1538
1da177e4 1539 if (t > 0) {
e7c98dc7 1540 if (t >= 256) {
1da177e4
LT		 1541 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1542 t >>= 2;
e7c98dc7 1543 } else
1da177e4 1544 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1545
1da177e4
LT		 1546 sci_out(port, SCBRR, t);
1547 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1548 }
1549
d5701647 1550 sci_init_pins(port, termios->c_cflag);
3089f381 1551 sci_out(port, SCFCR, scfcr | ((termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0));
b7a76e4b 1552
ce6738b6 1553 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1554
3089f381
GL		 1555#ifdef CONFIG_SERIAL_SH_SCI_DMA
1556 /*
1557 * Calculate delay for 1.5 DMA buffers: see
1558 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1559 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1560 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1561 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1562 * sizes), but it has been found out experimentally, that this is not
1563 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1564 * as a minimum seem to work perfectly.
1565 */
1566 if (s->chan_rx) {
1567 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1568 port->fifosize / 2;
1569 dev_dbg(port->dev,
1570 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1571 s->rx_timeout * 1000 / HZ, port->timeout);
1572 if (s->rx_timeout < msecs_to_jiffies(20))
1573 s->rx_timeout = msecs_to_jiffies(20);
1574 }
1575#endif
1576
1da177e4 1577 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1578 sci_start_rx(port);
36003386
AC		 1579
1580 if (s->disable)
1581 s->disable(port);
1da177e4
LT		 1582}
1583
1584static const char *sci_type(struct uart_port *port)
1585{
1586 switch (port->type) {
e7c98dc7
MT		 1587 case PORT_IRDA:
1588 return "irda";
1589 case PORT_SCI:
1590 return "sci";
1591 case PORT_SCIF:
1592 return "scif";
1593 case PORT_SCIFA:
1594 return "scifa";
d1d4b10c
GL		 1595 case PORT_SCIFB:
1596 return "scifb";
1da177e4
LT		 1597 }
1598
fa43972f 1599 return NULL;
1da177e4
LT		 1600}
1601
e2651647 1602static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1603{
e2651647
PM		 1604 /*
1605 * Pick an arbitrary size that encapsulates all of the base
1606 * registers by default. This can be optimized later, or derived
1607 * from platform resource data at such a time that ports begin to
1608 * behave more erratically.
1609 */
1610 return 64;
1da177e4
LT		 1611}
1612
f6e9495d
PM		 1613static int sci_remap_port(struct uart_port *port)
1614{
1615 unsigned long size = sci_port_size(port);
1616
1617 /*
1618 * Nothing to do if there's already an established membase.
1619 */
1620 if (port->membase)
1621 return 0;
1622
1623 if (port->flags & UPF_IOREMAP) {
1624 port->membase = ioremap_nocache(port->mapbase, size);
1625 if (unlikely(!port->membase)) {
1626 dev_err(port->dev, "can't remap port#%d\n", port->line);
1627 return -ENXIO;
1628 }
1629 } else {
1630 /*
1631 * For the simple (and majority of) cases where we don't
1632 * need to do any remapping, just cast the cookie
1633 * directly.
1634 */
1635 port->membase = (void __iomem *)port->mapbase;
1636 }
1637
1638 return 0;
1639}
1640
e2651647 1641static void sci_release_port(struct uart_port *port)
1da177e4 1642{
e2651647
PM		 1643 if (port->flags & UPF_IOREMAP) {
1644 iounmap(port->membase);
1645 port->membase = NULL;
1646 }
1647
1648 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1649}
1650
e2651647 1651static int sci_request_port(struct uart_port *port)
1da177e4 1652{
e2651647
PM		 1653 unsigned long size = sci_port_size(port);
1654 struct resource *res;
f6e9495d 1655 int ret;
1da177e4 1656
1020520e 1657 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 1658 if (unlikely(res == NULL))
1659 return -EBUSY;
1da177e4 1660
f6e9495d
PM		 1661 ret = sci_remap_port(port);
1662 if (unlikely(ret != 0)) {
1663 release_resource(res);
1664 return ret;
7ff731ae 1665 }
e2651647
PM		 1666
1667 return 0;
1668}
1669
1670static void sci_config_port(struct uart_port *port, int flags)
1671{
1672 if (flags & UART_CONFIG_TYPE) {
1673 struct sci_port *sport = to_sci_port(port);
1674
1675 port->type = sport->cfg->type;
1676 sci_request_port(port);
1677 }
1da177e4
LT		 1678}
1679
1680static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1681{
a5660ada 1682 struct sci_port *s = to_sci_port(port);
1da177e4 1683
ce6738b6 1684 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1685 return -EINVAL;
1686 if (ser->baud_base < 2400)
1687 /* No paper tape reader for Mitch.. */
1688 return -EINVAL;
1689
1690 return 0;
1691}
1692
1693static struct uart_ops sci_uart_ops = {
1694 .tx_empty = sci_tx_empty,
1695 .set_mctrl = sci_set_mctrl,
1696 .get_mctrl = sci_get_mctrl,
1697 .start_tx = sci_start_tx,
1698 .stop_tx = sci_stop_tx,
1699 .stop_rx = sci_stop_rx,
1700 .enable_ms = sci_enable_ms,
1701 .break_ctl = sci_break_ctl,
1702 .startup = sci_startup,
1703 .shutdown = sci_shutdown,
1704 .set_termios = sci_set_termios,
1705 .type = sci_type,
1706 .release_port = sci_release_port,
1707 .request_port = sci_request_port,
1708 .config_port = sci_config_port,
1709 .verify_port = sci_verify_port,
07d2a1a1
PM		 1710#ifdef CONFIG_CONSOLE_POLL
1711 .poll_get_char = sci_poll_get_char,
1712 .poll_put_char = sci_poll_put_char,
1713#endif
1da177e4
LT		 1714};
1715
c7ed1ab3
PM		 1716static int __devinit sci_init_single(struct platform_device *dev,
1717 struct sci_port *sci_port,
1718 unsigned int index,
1719 struct plat_sci_port *p)
e108b2ca 1720{
73a19e4c 1721 struct uart_port *port = &sci_port->port;
e108b2ca 1722
73a19e4c
GL		 1723 port->ops = &sci_uart_ops;
1724 port->iotype = UPIO_MEM;
1725 port->line = index;
75136d48
MP		 1726
1727 switch (p->type) {
d1d4b10c
GL		 1728 case PORT_SCIFB:
1729 port->fifosize = 256;
1730 break;
75136d48 1731 case PORT_SCIFA:
73a19e4c 1732 port->fifosize = 64;
75136d48
MP		 1733 break;
1734 case PORT_SCIF:
73a19e4c 1735 port->fifosize = 16;
75136d48
MP		 1736 break;
1737 default:
73a19e4c 1738 port->fifosize = 1;
75136d48
MP		 1739 break;
1740 }
7b6fd3bf
MD		 1741
1742 if (dev) {
c7ed1ab3
PM		 1743 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1744 if (IS_ERR(sci_port->iclk)) {
1745 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1746 if (IS_ERR(sci_port->iclk)) {
1747 dev_err(&dev->dev, "can't get iclk\n");
1748 return PTR_ERR(sci_port->iclk);
1749 }
1750 }
1751
1752 /*
1753 * The function clock is optional, ignore it if we can't
1754 * find it.
1755 */
1756 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1757 if (IS_ERR(sci_port->fclk))
1758 sci_port->fclk = NULL;
1759
7b6fd3bf
MD		 1760 sci_port->enable = sci_clk_enable;
1761 sci_port->disable = sci_clk_disable;
73a19e4c 1762 port->dev = &dev->dev;
5e50d2d6
MD		 1763
1764 pm_runtime_enable(&dev->dev);
7b6fd3bf 1765 }
e108b2ca 1766
7ed7e071
MD		 1767 sci_port->break_timer.data = (unsigned long)sci_port;
1768 sci_port->break_timer.function = sci_break_timer;
1769 init_timer(&sci_port->break_timer);
1770
debf9507
PM		 1771 /*
1772 * Establish some sensible defaults for the error detection.
1773 */
1774 if (!p->error_mask)
1775 p->error_mask = (p->type == PORT_SCI) ?
1776 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1777
1778 /*
1779 * Establish sensible defaults for the overrun detection, unless
1780 * the part has explicitly disabled support for it.
1781 */
1782 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1783 if (p->type == PORT_SCI)
1784 p->overrun_bit = 5;
1785 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1786 p->overrun_bit = 9;
1787 else
1788 p->overrun_bit = 0;
1789
1790 /*
1791 * Make the error mask inclusive of overrun detection, if
1792 * supported.
1793 */
1794 p->error_mask |= (1 << p->overrun_bit);
1795 }
1796
ce6738b6 1797 sci_port->cfg = p;
7ed7e071 1798
ce6738b6
PM		 1799 port->mapbase = p->mapbase;
1800 port->type = p->type;
f43dc23d 1801 port->flags = p->flags;
73a19e4c 1802
ce6738b6
PM		 1803 /*
1804 * The UART port needs an IRQ value, so we peg this to the TX IRQ
1805 * for the multi-IRQ ports, which is where we are primarily
1806 * concerned with the shutdown path synchronization.
1807 *
1808 * For the muxed case there's nothing more to do.
1809 */
54aa89ea 1810 port->irq = p->irqs[SCIx_RXI_IRQ];
73a19e4c 1811
ce6738b6
PM		 1812 if (p->dma_dev)
1813 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1814 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 1815
c7ed1ab3 1816 return 0;
e108b2ca
PM		 1817}
1818
1da177e4 1819#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 1820static void serial_console_putchar(struct uart_port *port, int ch)
1821{
1822 sci_poll_put_char(port, ch);
1823}
1824
1da177e4
LT		 1825/*
1826 * Print a string to the serial port trying not to disturb
1827 * any possible real use of the port...
1828 */
1829static void serial_console_write(struct console *co, const char *s,
1830 unsigned count)
1831{
906b17dc
PM		 1832 struct sci_port *sci_port = &sci_ports[co->index];
1833 struct uart_port *port = &sci_port->port;
973e5d52 1834 unsigned short bits;
07d2a1a1 1835
501b825d
MD		 1836 if (sci_port->enable)
1837 sci_port->enable(port);
1838
1839 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 1840
1841 /* wait until fifo is empty and last bit has been transmitted */
1842 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1843 while ((sci_in(port, SCxSR) & bits) != bits)
1844 cpu_relax();
501b825d 1845
345e5a76 1846 if (sci_port->disable)
501b825d 1847 sci_port->disable(port);
1da177e4
LT		 1848}
1849
7b6fd3bf 1850static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 1851{
dc8e6f5b 1852 struct sci_port *sci_port;
1da177e4
LT		 1853 struct uart_port *port;
1854 int baud = 115200;
1855 int bits = 8;
1856 int parity = 'n';
1857 int flow = 'n';
1858 int ret;
1859
e108b2ca 1860 /*
906b17dc 1861 * Refuse to handle any bogus ports.
1da177e4 1862 */
906b17dc 1863 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 1864 return -ENODEV;
e108b2ca 1865
906b17dc
PM		 1866 sci_port = &sci_ports[co->index];
1867 port = &sci_port->port;
1868
b2267a6b
AC		 1869 /*
1870 * Refuse to handle uninitialized ports.
1871 */
1872 if (!port->ops)
1873 return -ENODEV;
1874
f6e9495d
PM		 1875 ret = sci_remap_port(port);
1876 if (unlikely(ret != 0))
1877 return ret;
e108b2ca 1878
dc8e6f5b
MD		 1879 if (sci_port->enable)
1880 sci_port->enable(port);
b7a76e4b 1881
1da177e4
LT		 1882 if (options)
1883 uart_parse_options(options, &baud, &parity, &bits, &flow);
1884
501b825d 1885 /* TODO: disable clock */
ab7cfb55 1886 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 1887}
1888
1889static struct console serial_console = {
1890 .name = "ttySC",
906b17dc 1891 .device = uart_console_device,
1da177e4
LT		 1892 .write = serial_console_write,
1893 .setup = serial_console_setup,
fa5da2f7 1894 .flags = CON_PRINTBUFFER,
1da177e4 1895 .index = -1,
906b17dc 1896 .data = &sci_uart_driver,
1da177e4
LT		 1897};
1898
7b6fd3bf
MD		 1899static struct console early_serial_console = {
1900 .name = "early_ttySC",
1901 .write = serial_console_write,
1902 .flags = CON_PRINTBUFFER,
906b17dc 1903 .index = -1,
7b6fd3bf 1904};
ecdf8a46 1905
7b6fd3bf
MD		 1906static char early_serial_buf[32];
1907
ecdf8a46
PM		 1908static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
1909{
1910 struct plat_sci_port *cfg = pdev->dev.platform_data;
1911
1912 if (early_serial_console.data)
1913 return -EEXIST;
1914
1915 early_serial_console.index = pdev->id;
ecdf8a46 1916
906b17dc 1917 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 1918
1919 serial_console_setup(&early_serial_console, early_serial_buf);
1920
1921 if (!strstr(early_serial_buf, "keep"))
1922 early_serial_console.flags |= CON_BOOT;
1923
1924 register_console(&early_serial_console);
1925 return 0;
1926}
6a8c9799
NI		 1927
1928#define SCI_CONSOLE (&serial_console)
1929
ecdf8a46
PM		 1930#else
1931static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
1932{
1933 return -EINVAL;
1934}
1da177e4 1935
6a8c9799
NI		 1936#define SCI_CONSOLE NULL
1937
1938#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 1939
1940static char banner[] __initdata =
1941 KERN_INFO "SuperH SCI(F) driver initialized\n";
1942
1943static struct uart_driver sci_uart_driver = {
1944 .owner = THIS_MODULE,
1945 .driver_name = "sci",
1da177e4
LT		 1946 .dev_name = "ttySC",
1947 .major = SCI_MAJOR,
1948 .minor = SCI_MINOR_START,
e108b2ca 1949 .nr = SCI_NPORTS,
1da177e4
LT		 1950 .cons = SCI_CONSOLE,
1951};
1952
54507f6e 1953static int sci_remove(struct platform_device *dev)
e552de24 1954{
d535a230 1955 struct sci_port *port = platform_get_drvdata(dev);
e552de24 1956
d535a230
PM		 1957 cpufreq_unregister_notifier(&port->freq_transition,
1958 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 1959
d535a230
PM		 1960 uart_remove_one_port(&sci_uart_driver, &port->port);
1961
1962 clk_put(port->iclk);
1963 clk_put(port->fclk);
e552de24 1964
5e50d2d6 1965 pm_runtime_disable(&dev->dev);
e552de24
MD		 1966 return 0;
1967}
1968
0ee70712
MD		 1969static int __devinit sci_probe_single(struct platform_device *dev,
1970 unsigned int index,
1971 struct plat_sci_port *p,
1972 struct sci_port *sciport)
1973{
0ee70712
MD		 1974 int ret;
1975
1976 /* Sanity check */
1977 if (unlikely(index >= SCI_NPORTS)) {
1978 dev_notice(&dev->dev, "Attempting to register port "
1979 "%d when only %d are available.\n",
1980 index+1, SCI_NPORTS);
1981 dev_notice(&dev->dev, "Consider bumping "
1982 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1983 return 0;
1984 }
1985
c7ed1ab3
PM		 1986 ret = sci_init_single(dev, sciport, index, p);
1987 if (ret)
1988 return ret;
0ee70712 1989
d535a230 1990 return uart_add_one_port(&sci_uart_driver, &sciport->port);
0ee70712
MD		 1991}
1992
e108b2ca 1993static int __devinit sci_probe(struct platform_device *dev)
1da177e4 1994{
e108b2ca 1995 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 1996 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 1997 int ret;
d535a230 1998
ecdf8a46
PM		 1999 /*
2000 * If we've come here via earlyprintk initialization, head off to
2001 * the special early probe. We don't have sufficient device state
2002 * to make it beyond this yet.
2003 */
2004 if (is_early_platform_device(dev))
2005 return sci_probe_earlyprintk(dev);
7b6fd3bf 2006
d535a230 2007 platform_set_drvdata(dev, sp);
e552de24 2008
906b17dc 2009 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230
PM		 2010 if (ret)
2011 goto err_unreg;
e552de24 2012
d535a230 2013 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2014
d535a230
PM		 2015 ret = cpufreq_register_notifier(&sp->freq_transition,
2016 CPUFREQ_TRANSITION_NOTIFIER);
2017 if (unlikely(ret < 0))
2018 goto err_unreg;
1da177e4
LT		 2019
2020#ifdef CONFIG_SH_STANDARD_BIOS
2021 sh_bios_gdb_detach();
2022#endif
2023
e108b2ca 2024 return 0;
7ff731ae
PM		 2025
2026err_unreg:
e552de24 2027 sci_remove(dev);
7ff731ae 2028 return ret;
1da177e4
LT		 2029}
2030
6daa79b3 2031static int sci_suspend(struct device *dev)
1da177e4 2032{
d535a230 2033 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2034
d535a230
PM		 2035 if (sport)
2036 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2037
e108b2ca
PM		 2038 return 0;
2039}
1da177e4 2040
6daa79b3 2041static int sci_resume(struct device *dev)
e108b2ca 2042{
d535a230 2043 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2044
d535a230
PM		 2045 if (sport)
2046 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2047
2048 return 0;
2049}
2050
47145210 2051static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2052 .suspend = sci_suspend,
2053 .resume = sci_resume,
2054};
2055
e108b2ca
PM		 2056static struct platform_driver sci_driver = {
2057 .probe = sci_probe,
b9e39c89 2058 .remove = sci_remove,
e108b2ca
PM		 2059 .driver = {
2060 .name = "sh-sci",
2061 .owner = THIS_MODULE,
6daa79b3 2062 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2063 },
2064};
2065
2066static int __init sci_init(void)
2067{
2068 int ret;
2069
2070 printk(banner);
2071
e108b2ca
PM		 2072 ret = uart_register_driver(&sci_uart_driver);
2073 if (likely(ret == 0)) {
2074 ret = platform_driver_register(&sci_driver);
2075 if (unlikely(ret))
2076 uart_unregister_driver(&sci_uart_driver);
2077 }
2078
2079 return ret;
2080}
2081
2082static void __exit sci_exit(void)
2083{
2084 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2085 uart_unregister_driver(&sci_uart_driver);
2086}
2087
7b6fd3bf
MD		 2088#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2089early_platform_init_buffer("earlyprintk", &sci_driver,
2090 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2091#endif
1da177e4
LT		 2092module_init(sci_init);
2093module_exit(sci_exit);
2094
e108b2ca 2095MODULE_LICENSE("GPL");
e169c139 2096MODULE_ALIAS("platform:sh-sci");
Linux kernel - Deliverables
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