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serial: sh-sci: Pause DMA engine and get DMA status again
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
501b825d
MD		 95 /* Interface clock */
96 struct clk *iclk;
c7ed1ab3
PM		 97 /* Function clock */
98 struct clk *fclk;
edad1f20 99
1fcc91a6 100 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 101 char *irqstr[SCIx_NR_IRQS];
102
73a19e4c
GL		 103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
f43dc23d 105
73a19e4c 106#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
79904420
GU		 110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
73a19e4c 112 struct scatterlist sg_rx[2];
7b39d901 113 void *rx_buf[2];
73a19e4c
GL		 114 size_t buf_len_rx;
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
73a19e4c 118 struct timer_list rx_timer;
3089f381 119 unsigned int rx_timeout;
73a19e4c 120#endif
e552de24 121
d535a230 122 struct notifier_block freq_transition;
e108b2ca
PM		 123};
124
e108b2ca 125#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 126
e108b2ca
PM		 127static struct sci_port sci_ports[SCI_NPORTS];
128static struct uart_driver sci_uart_driver;
1da177e4 129
e7c98dc7
MT		 130static inline struct sci_port *
131to_sci_port(struct uart_port *uart)
132{
133 return container_of(uart, struct sci_port, port);
134}
135
61a6976b
PM		 136struct plat_sci_reg {
137 u8 offset, size;
138};
139
140/* Helper for invalidating specific entries of an inherited map. */
141#define sci_reg_invalid { .offset = 0, .size = 0 }
142
d3184e68 143static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 144 [SCIx_PROBE_REGTYPE] = {
145 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
146 },
147
148 /*
149 * Common SCI definitions, dependent on the port's regshift
150 * value.
151 */
152 [SCIx_SCI_REGTYPE] = {
153 [SCSMR] = { 0x00, 8 },
154 [SCBRR] = { 0x01, 8 },
155 [SCSCR] = { 0x02, 8 },
156 [SCxTDR] = { 0x03, 8 },
157 [SCxSR] = { 0x04, 8 },
158 [SCxRDR] = { 0x05, 8 },
159 [SCFCR] = sci_reg_invalid,
160 [SCFDR] = sci_reg_invalid,
161 [SCTFDR] = sci_reg_invalid,
162 [SCRFDR] = sci_reg_invalid,
163 [SCSPTR] = sci_reg_invalid,
164 [SCLSR] = sci_reg_invalid,
f303b364 165 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 166 [SCPCR] = sci_reg_invalid,
167 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 168 },
169
170 /*
171 * Common definitions for legacy IrDA ports, dependent on
172 * regshift value.
173 */
174 [SCIx_IRDA_REGTYPE] = {
175 [SCSMR] = { 0x00, 8 },
176 [SCBRR] = { 0x01, 8 },
177 [SCSCR] = { 0x02, 8 },
178 [SCxTDR] = { 0x03, 8 },
179 [SCxSR] = { 0x04, 8 },
180 [SCxRDR] = { 0x05, 8 },
181 [SCFCR] = { 0x06, 8 },
182 [SCFDR] = { 0x07, 16 },
183 [SCTFDR] = sci_reg_invalid,
184 [SCRFDR] = sci_reg_invalid,
185 [SCSPTR] = sci_reg_invalid,
186 [SCLSR] = sci_reg_invalid,
f303b364 187 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 188 [SCPCR] = sci_reg_invalid,
189 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 190 },
191
192 /*
193 * Common SCIFA definitions.
194 */
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
f303b364 208 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 209 [SCPCR] = { 0x30, 16 },
210 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 211 },
212
213 /*
214 * Common SCIFB definitions.
215 */
216 [SCIx_SCIFB_REGTYPE] = {
217 [SCSMR] = { 0x00, 16 },
218 [SCBRR] = { 0x04, 8 },
219 [SCSCR] = { 0x08, 16 },
220 [SCxTDR] = { 0x40, 8 },
221 [SCxSR] = { 0x14, 16 },
222 [SCxRDR] = { 0x60, 8 },
223 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 224 [SCFDR] = sci_reg_invalid,
225 [SCTFDR] = { 0x38, 16 },
226 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 227 [SCSPTR] = sci_reg_invalid,
228 [SCLSR] = sci_reg_invalid,
f303b364 229 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
61a6976b
PM		 232 },
233
3af1f8a4
PE		 234 /*
235 * Common SH-2(A) SCIF definitions for ports with FIFO data
236 * count registers.
237 */
238 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
239 [SCSMR] = { 0x00, 16 },
240 [SCBRR] = { 0x04, 8 },
241 [SCSCR] = { 0x08, 16 },
242 [SCxTDR] = { 0x0c, 8 },
243 [SCxSR] = { 0x10, 16 },
244 [SCxRDR] = { 0x14, 8 },
245 [SCFCR] = { 0x18, 16 },
246 [SCFDR] = { 0x1c, 16 },
247 [SCTFDR] = sci_reg_invalid,
248 [SCRFDR] = sci_reg_invalid,
249 [SCSPTR] = { 0x20, 16 },
250 [SCLSR] = { 0x24, 16 },
f303b364 251 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 252 [SCPCR] = sci_reg_invalid,
253 [SCPDR] = sci_reg_invalid,
3af1f8a4
PE		 254 },
255
61a6976b
PM		 256 /*
257 * Common SH-3 SCIF definitions.
258 */
259 [SCIx_SH3_SCIF_REGTYPE] = {
260 [SCSMR] = { 0x00, 8 },
261 [SCBRR] = { 0x02, 8 },
262 [SCSCR] = { 0x04, 8 },
263 [SCxTDR] = { 0x06, 8 },
264 [SCxSR] = { 0x08, 16 },
265 [SCxRDR] = { 0x0a, 8 },
266 [SCFCR] = { 0x0c, 8 },
267 [SCFDR] = { 0x0e, 16 },
268 [SCTFDR] = sci_reg_invalid,
269 [SCRFDR] = sci_reg_invalid,
270 [SCSPTR] = sci_reg_invalid,
271 [SCLSR] = sci_reg_invalid,
f303b364 272 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 273 [SCPCR] = sci_reg_invalid,
274 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 275 },
276
277 /*
278 * Common SH-4(A) SCIF(B) definitions.
279 */
280 [SCIx_SH4_SCIF_REGTYPE] = {
281 [SCSMR] = { 0x00, 16 },
282 [SCBRR] = { 0x04, 8 },
283 [SCSCR] = { 0x08, 16 },
284 [SCxTDR] = { 0x0c, 8 },
285 [SCxSR] = { 0x10, 16 },
286 [SCxRDR] = { 0x14, 8 },
287 [SCFCR] = { 0x18, 16 },
288 [SCFDR] = { 0x1c, 16 },
289 [SCTFDR] = sci_reg_invalid,
290 [SCRFDR] = sci_reg_invalid,
291 [SCSPTR] = { 0x20, 16 },
292 [SCLSR] = { 0x24, 16 },
f303b364 293 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 294 [SCPCR] = sci_reg_invalid,
295 [SCPDR] = sci_reg_invalid,
f303b364
UH		 296 },
297
298 /*
299 * Common HSCIF definitions.
300 */
301 [SCIx_HSCIF_REGTYPE] = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x04, 8 },
304 [SCSCR] = { 0x08, 16 },
305 [SCxTDR] = { 0x0c, 8 },
306 [SCxSR] = { 0x10, 16 },
307 [SCxRDR] = { 0x14, 8 },
308 [SCFCR] = { 0x18, 16 },
309 [SCFDR] = { 0x1c, 16 },
310 [SCTFDR] = sci_reg_invalid,
311 [SCRFDR] = sci_reg_invalid,
312 [SCSPTR] = { 0x20, 16 },
313 [SCLSR] = { 0x24, 16 },
314 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 315 [SCPCR] = sci_reg_invalid,
316 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 317 },
318
319 /*
320 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
321 * register.
322 */
323 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
324 [SCSMR] = { 0x00, 16 },
325 [SCBRR] = { 0x04, 8 },
326 [SCSCR] = { 0x08, 16 },
327 [SCxTDR] = { 0x0c, 8 },
328 [SCxSR] = { 0x10, 16 },
329 [SCxRDR] = { 0x14, 8 },
330 [SCFCR] = { 0x18, 16 },
331 [SCFDR] = { 0x1c, 16 },
332 [SCTFDR] = sci_reg_invalid,
333 [SCRFDR] = sci_reg_invalid,
334 [SCSPTR] = sci_reg_invalid,
335 [SCLSR] = { 0x24, 16 },
f303b364 336 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 337 [SCPCR] = sci_reg_invalid,
338 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 339 },
340
341 /*
342 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
343 * count registers.
344 */
345 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
346 [SCSMR] = { 0x00, 16 },
347 [SCBRR] = { 0x04, 8 },
348 [SCSCR] = { 0x08, 16 },
349 [SCxTDR] = { 0x0c, 8 },
350 [SCxSR] = { 0x10, 16 },
351 [SCxRDR] = { 0x14, 8 },
352 [SCFCR] = { 0x18, 16 },
353 [SCFDR] = { 0x1c, 16 },
354 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
355 [SCRFDR] = { 0x20, 16 },
356 [SCSPTR] = { 0x24, 16 },
357 [SCLSR] = { 0x28, 16 },
f303b364 358 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 359 [SCPCR] = sci_reg_invalid,
360 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 361 },
362
363 /*
364 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
365 * registers.
366 */
367 [SCIx_SH7705_SCIF_REGTYPE] = {
368 [SCSMR] = { 0x00, 16 },
369 [SCBRR] = { 0x04, 8 },
370 [SCSCR] = { 0x08, 16 },
371 [SCxTDR] = { 0x20, 8 },
372 [SCxSR] = { 0x14, 16 },
373 [SCxRDR] = { 0x24, 8 },
374 [SCFCR] = { 0x18, 16 },
375 [SCFDR] = { 0x1c, 16 },
376 [SCTFDR] = sci_reg_invalid,
377 [SCRFDR] = sci_reg_invalid,
378 [SCSPTR] = sci_reg_invalid,
379 [SCLSR] = sci_reg_invalid,
f303b364 380 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 381 [SCPCR] = sci_reg_invalid,
382 [SCPDR] = sci_reg_invalid,
61a6976b
PM		 383 },
384};
385
72b294cf
PM		 386#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
387
61a6976b
PM		 388/*
389 * The "offset" here is rather misleading, in that it refers to an enum
390 * value relative to the port mapping rather than the fixed offset
391 * itself, which needs to be manually retrieved from the platform's
392 * register map for the given port.
393 */
394static unsigned int sci_serial_in(struct uart_port *p, int offset)
395{
d3184e68 396 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 397
398 if (reg->size == 8)
399 return ioread8(p->membase + (reg->offset << p->regshift));
400 else if (reg->size == 16)
401 return ioread16(p->membase + (reg->offset << p->regshift));
402 else
403 WARN(1, "Invalid register access\n");
404
405 return 0;
406}
407
408static void sci_serial_out(struct uart_port *p, int offset, int value)
409{
d3184e68 410 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 411
412 if (reg->size == 8)
413 iowrite8(value, p->membase + (reg->offset << p->regshift));
414 else if (reg->size == 16)
415 iowrite16(value, p->membase + (reg->offset << p->regshift));
416 else
417 WARN(1, "Invalid register access\n");
418}
419
61a6976b
PM		 420static int sci_probe_regmap(struct plat_sci_port *cfg)
421{
422 switch (cfg->type) {
423 case PORT_SCI:
424 cfg->regtype = SCIx_SCI_REGTYPE;
425 break;
426 case PORT_IRDA:
427 cfg->regtype = SCIx_IRDA_REGTYPE;
428 break;
429 case PORT_SCIFA:
430 cfg->regtype = SCIx_SCIFA_REGTYPE;
431 break;
432 case PORT_SCIFB:
433 cfg->regtype = SCIx_SCIFB_REGTYPE;
434 break;
435 case PORT_SCIF:
436 /*
437 * The SH-4 is a bit of a misnomer here, although that's
438 * where this particular port layout originated. This
439 * configuration (or some slight variation thereof)
440 * remains the dominant model for all SCIFs.
441 */
442 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
443 break;
f303b364
UH		 444 case PORT_HSCIF:
445 cfg->regtype = SCIx_HSCIF_REGTYPE;
446 break;
61a6976b 447 default:
6c13d5d2 448 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 449 return -EINVAL;
450 }
451
452 return 0;
453}
454
23241d43
PM		 455static void sci_port_enable(struct sci_port *sci_port)
456{
457 if (!sci_port->port.dev)
458 return;
459
460 pm_runtime_get_sync(sci_port->port.dev);
461
b016b646 462 clk_prepare_enable(sci_port->iclk);
23241d43 463 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 464 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 465}
466
467static void sci_port_disable(struct sci_port *sci_port)
468{
469 if (!sci_port->port.dev)
470 return;
471
caec7038
LP		 472 /* Cancel the break timer to ensure that the timer handler will not try
473 * to access the hardware with clocks and power disabled. Reset the
474 * break flag to make the break debouncing state machine ready for the
475 * next break.
476 */
477 del_timer_sync(&sci_port->break_timer);
478 sci_port->break_flag = 0;
479
b016b646
LP		 480 clk_disable_unprepare(sci_port->fclk);
481 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 482
483 pm_runtime_put_sync(sci_port->port.dev);
484}
485
e1910fcd
GU		 486static inline unsigned long port_rx_irq_mask(struct uart_port *port)
487{
488 /*
489 * Not all ports (such as SCIFA) will support REIE. Rather than
490 * special-casing the port type, we check the port initialization
491 * IRQ enable mask to see whether the IRQ is desired at all. If
492 * it's unset, it's logically inferred that there's no point in
493 * testing for it.
494 */
495 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
496}
497
498static void sci_start_tx(struct uart_port *port)
499{
500 struct sci_port *s = to_sci_port(port);
501 unsigned short ctrl;
502
503#ifdef CONFIG_SERIAL_SH_SCI_DMA
504 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
505 u16 new, scr = serial_port_in(port, SCSCR);
506 if (s->chan_tx)
507 new = scr | SCSCR_TDRQE;
508 else
509 new = scr & ~SCSCR_TDRQE;
510 if (new != scr)
511 serial_port_out(port, SCSCR, new);
512 }
513
514 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
515 dma_submit_error(s->cookie_tx)) {
516 s->cookie_tx = 0;
517 schedule_work(&s->work_tx);
518 }
519#endif
520
521 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
522 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
523 ctrl = serial_port_in(port, SCSCR);
524 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
525 }
526}
527
528static void sci_stop_tx(struct uart_port *port)
529{
530 unsigned short ctrl;
531
532 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
533 ctrl = serial_port_in(port, SCSCR);
534
535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
536 ctrl &= ~SCSCR_TDRQE;
537
538 ctrl &= ~SCSCR_TIE;
539
540 serial_port_out(port, SCSCR, ctrl);
541}
542
543static void sci_start_rx(struct uart_port *port)
544{
545 unsigned short ctrl;
546
547 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
548
549 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
550 ctrl &= ~SCSCR_RDRQE;
551
552 serial_port_out(port, SCSCR, ctrl);
553}
554
555static void sci_stop_rx(struct uart_port *port)
556{
557 unsigned short ctrl;
558
559 ctrl = serial_port_in(port, SCSCR);
560
561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
562 ctrl &= ~SCSCR_RDRQE;
563
564 ctrl &= ~port_rx_irq_mask(port);
565
566 serial_port_out(port, SCSCR, ctrl);
567}
568
a1b5b43f
GU		 569static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
570{
571 if (port->type == PORT_SCI) {
572 /* Just store the mask */
573 serial_port_out(port, SCxSR, mask);
574 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
575 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
576 /* Only clear the status bits we want to clear */
577 serial_port_out(port, SCxSR,
578 serial_port_in(port, SCxSR) & mask);
579 } else {
580 /* Store the mask, clear parity/framing errors */
581 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
582 }
583}
584
07d2a1a1 585#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 586
587#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 588static int sci_poll_get_char(struct uart_port *port)
1da177e4 589{
1da177e4
LT		 590 unsigned short status;
591 int c;
592
e108b2ca 593 do {
b12bb29f 594 status = serial_port_in(port, SCxSR);
1da177e4 595 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 596 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 597 continue;
598 }
3f255eb3
JW		 599 break;
600 } while (1);
601
602 if (!(status & SCxSR_RDxF(port)))
603 return NO_POLL_CHAR;
07d2a1a1 604
b12bb29f 605 c = serial_port_in(port, SCxRDR);
07d2a1a1 606
e7c98dc7 607 /* Dummy read */
b12bb29f 608 serial_port_in(port, SCxSR);
a1b5b43f 609 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 610
611 return c;
612}
1f6fd5c9 613#endif
1da177e4 614
07d2a1a1 615static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 616{
1da177e4
LT		 617 unsigned short status;
618
1da177e4 619 do {
b12bb29f 620 status = serial_port_in(port, SCxSR);
1da177e4
LT		 621 } while (!(status & SCxSR_TDxE(port)));
622
b12bb29f 623 serial_port_out(port, SCxTDR, c);
a1b5b43f 624 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 625}
07d2a1a1 626#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 627
61a6976b 628static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 629{
61a6976b 630 struct sci_port *s = to_sci_port(port);
d3184e68 631 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 632
61a6976b
PM		 633 /*
634 * Use port-specific handler if provided.
635 */
636 if (s->cfg->ops && s->cfg->ops->init_pins) {
637 s->cfg->ops->init_pins(port, cflag);
638 return;
1da177e4 639 }
41504c39 640
61a6976b
PM		 641 /*
642 * For the generic path SCSPTR is necessary. Bail out if that's
643 * unavailable, too.
644 */
645 if (!reg->size)
646 return;
41504c39 647
faf02f8f
PM		 648 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
649 ((!(cflag & CRTSCTS)))) {
650 unsigned short status;
651
b12bb29f 652 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 653 status &= ~SCSPTR_CTSIO;
654 status |= SCSPTR_RTSIO;
b12bb29f 655 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 656 }
d5701647 657}
e108b2ca 658
72b294cf 659static int sci_txfill(struct uart_port *port)
e108b2ca 660{
d3184e68 661 const struct plat_sci_reg *reg;
e108b2ca 662
72b294cf
PM		 663 reg = sci_getreg(port, SCTFDR);
664 if (reg->size)
63f7ad11 665 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 666
72b294cf
PM		 667 reg = sci_getreg(port, SCFDR);
668 if (reg->size)
b12bb29f 669 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 670
b12bb29f 671 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 672}
673
73a19e4c
GL		 674static int sci_txroom(struct uart_port *port)
675{
72b294cf 676 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 677}
678
679static int sci_rxfill(struct uart_port *port)
e108b2ca 680{
d3184e68 681 const struct plat_sci_reg *reg;
72b294cf
PM		 682
683 reg = sci_getreg(port, SCRFDR);
684 if (reg->size)
63f7ad11 685 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 686
687 reg = sci_getreg(port, SCFDR);
688 if (reg->size)
b12bb29f 689 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 690
b12bb29f 691 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 692}
693
514820eb
PM		 694/*
695 * SCI helper for checking the state of the muxed port/RXD pins.
696 */
697static inline int sci_rxd_in(struct uart_port *port)
698{
699 struct sci_port *s = to_sci_port(port);
700
701 if (s->cfg->port_reg <= 0)
702 return 1;
703
0dd4d5cb 704 /* Cast for ARM damage */
e2afca69 705 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 706}
707
1da177e4
LT		 708/* ********************************************************************** *
709 * the interrupt related routines *
710 * ********************************************************************** */
711
712static void sci_transmit_chars(struct uart_port *port)
713{
ebd2c8f6 714 struct circ_buf *xmit = &port->state->xmit;
1da177e4 715 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 716 unsigned short status;
717 unsigned short ctrl;
e108b2ca 718 int count;
1da177e4 719
b12bb29f 720 status = serial_port_in(port, SCxSR);
1da177e4 721 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 722 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 723 if (uart_circ_empty(xmit))
8e698614 724 ctrl &= ~SCSCR_TIE;
e7c98dc7 725 else
8e698614 726 ctrl |= SCSCR_TIE;
b12bb29f 727 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 728 return;
729 }
730
72b294cf 731 count = sci_txroom(port);
1da177e4
LT		 732
733 do {
734 unsigned char c;
735
736 if (port->x_char) {
737 c = port->x_char;
738 port->x_char = 0;
739 } else if (!uart_circ_empty(xmit) && !stopped) {
740 c = xmit->buf[xmit->tail];
741 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
742 } else {
743 break;
744 }
745
b12bb29f 746 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 747
748 port->icount.tx++;
749 } while (--count > 0);
750
a1b5b43f 751 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 752
753 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
754 uart_write_wakeup(port);
755 if (uart_circ_empty(xmit)) {
b129a8cc 756 sci_stop_tx(port);
1da177e4 757 } else {
b12bb29f 758 ctrl = serial_port_in(port, SCSCR);
1da177e4 759
1a22f08d 760 if (port->type != PORT_SCI) {
b12bb29f 761 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 762 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 763 }
1da177e4 764
8e698614 765 ctrl |= SCSCR_TIE;
b12bb29f 766 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 767 }
768}
769
770/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 771#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 772
94c8b6db 773static void sci_receive_chars(struct uart_port *port)
1da177e4 774{
e7c98dc7 775 struct sci_port *sci_port = to_sci_port(port);
227434f8 776 struct tty_port *tport = &port->state->port;
1da177e4
LT		 777 int i, count, copied = 0;
778 unsigned short status;
33f0f88f 779 unsigned char flag;
1da177e4 780
b12bb29f 781 status = serial_port_in(port, SCxSR);
1da177e4
LT		 782 if (!(status & SCxSR_RDxF(port)))
783 return;
784
785 while (1) {
1da177e4 786 /* Don't copy more bytes than there is room for in the buffer */
227434f8 787 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 788
789 /* If for any reason we can't copy more data, we're done! */
790 if (count == 0)
791 break;
792
793 if (port->type == PORT_SCI) {
b12bb29f 794 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 795 if (uart_handle_sysrq_char(port, c) ||
796 sci_port->break_flag)
1da177e4 797 count = 0;
e7c98dc7 798 else
92a19f9c 799 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 800 } else {
e7c98dc7 801 for (i = 0; i < count; i++) {
b12bb29f 802 char c = serial_port_in(port, SCxRDR);
d97fbbed 803
b12bb29f 804 status = serial_port_in(port, SCxSR);
1da177e4
LT		 805#if defined(CONFIG_CPU_SH3)
806 /* Skip "chars" during break */
e108b2ca 807 if (sci_port->break_flag) {
1da177e4
LT		 808 if ((c == 0) &&
809 (status & SCxSR_FER(port))) {
810 count--; i--;
811 continue;
812 }
e108b2ca 813
1da177e4 814 /* Nonzero => end-of-break */
762c69e3 815 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 816 sci_port->break_flag = 0;
817
1da177e4
LT		 818 if (STEPFN(c)) {
819 count--; i--;
820 continue;
821 }
822 }
823#endif /* CONFIG_CPU_SH3 */
7d12e780 824 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 825 count--; i--;
826 continue;
827 }
828
829 /* Store data and status */
73a19e4c 830 if (status & SCxSR_FER(port)) {
33f0f88f 831 flag = TTY_FRAME;
d97fbbed 832 port->icount.frame++;
762c69e3 833 dev_notice(port->dev, "frame error\n");
73a19e4c 834 } else if (status & SCxSR_PER(port)) {
33f0f88f 835 flag = TTY_PARITY;
d97fbbed 836 port->icount.parity++;
762c69e3 837 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 838 } else
839 flag = TTY_NORMAL;
762c69e3 840
92a19f9c 841 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 842 }
843 }
844
b12bb29f 845 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 846 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 847
1da177e4
LT		 848 copied += count;
849 port->icount.rx += count;
850 }
851
852 if (copied) {
853 /* Tell the rest of the system the news. New characters! */
2e124b4a 854 tty_flip_buffer_push(tport);
1da177e4 855 } else {
b12bb29f 856 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 857 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 858 }
859}
860
861#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 862
863/*
864 * The sci generates interrupts during the break,
1da177e4
LT		 865 * 1 per millisecond or so during the break period, for 9600 baud.
866 * So dont bother disabling interrupts.
867 * But dont want more than 1 break event.
868 * Use a kernel timer to periodically poll the rx line until
869 * the break is finished.
870 */
94c8b6db 871static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 872{
bc9b3f5c 873 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 874}
94c8b6db 875
1da177e4
LT		 876/* Ensure that two consecutive samples find the break over. */
877static void sci_break_timer(unsigned long data)
878{
e108b2ca
PM		 879 struct sci_port *port = (struct sci_port *)data;
880
881 if (sci_rxd_in(&port->port) == 0) {
1da177e4 882 port->break_flag = 1;
e108b2ca
PM		 883 sci_schedule_break_timer(port);
884 } else if (port->break_flag == 1) {
1da177e4
LT		 885 /* break is over. */
886 port->break_flag = 2;
e108b2ca
PM		 887 sci_schedule_break_timer(port);
888 } else
889 port->break_flag = 0;
1da177e4
LT		 890}
891
94c8b6db 892static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 893{
894 int copied = 0;
b12bb29f 895 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 896 struct tty_port *tport = &port->state->port;
debf9507 897 struct sci_port *s = to_sci_port(port);
1da177e4 898
3ae988d9 899 /* Handle overruns */
75c249fd 900 if (status & s->overrun_mask) {
3ae988d9 901 port->icount.overrun++;
d97fbbed 902
3ae988d9
LP		 903 /* overrun error */
904 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
905 copied++;
762c69e3 906
9b971cd2 907 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 908 }
909
e108b2ca 910 if (status & SCxSR_FER(port)) {
1da177e4
LT		 911 if (sci_rxd_in(port) == 0) {
912 /* Notify of BREAK */
e7c98dc7 913 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 914
915 if (!sci_port->break_flag) {
d97fbbed
PM		 916 port->icount.brk++;
917
e108b2ca
PM		 918 sci_port->break_flag = 1;
919 sci_schedule_break_timer(sci_port);
920
1da177e4 921 /* Do sysrq handling. */
e108b2ca 922 if (uart_handle_break(port))
1da177e4 923 return 0;
762c69e3
PM		 924
925 dev_dbg(port->dev, "BREAK detected\n");
926
92a19f9c 927 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 928 copied++;
929 }
930
e108b2ca 931 } else {
1da177e4 932 /* frame error */
d97fbbed
PM		 933 port->icount.frame++;
934
92a19f9c 935 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 936 copied++;
762c69e3
PM		 937
938 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 939 }
940 }
941
e108b2ca 942 if (status & SCxSR_PER(port)) {
1da177e4 943 /* parity error */
d97fbbed
PM		 944 port->icount.parity++;
945
92a19f9c 946 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 947 copied++;
762c69e3 948
9b971cd2 949 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 950 }
951
33f0f88f 952 if (copied)
2e124b4a 953 tty_flip_buffer_push(tport);
1da177e4
LT		 954
955 return copied;
956}
957
94c8b6db 958static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 959{
92a19f9c 960 struct tty_port *tport = &port->state->port;
debf9507 961 struct sci_port *s = to_sci_port(port);
d3184e68 962 const struct plat_sci_reg *reg;
2e0842a1 963 int copied = 0;
75c249fd 964 u16 status;
d830fa45 965
2e0842a1 966 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 967 if (!reg->size)
d830fa45
PM		 968 return 0;
969
2e0842a1 970 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 971 if (status & s->overrun_mask) {
972 status &= ~s->overrun_mask;
2e0842a1 973 serial_port_out(port, s->overrun_reg, status);
d830fa45 974
d97fbbed
PM		 975 port->icount.overrun++;
976
92a19f9c 977 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 978 tty_flip_buffer_push(tport);
d830fa45 979
51b31f1c 980 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 981 copied++;
982 }
983
984 return copied;
985}
986
94c8b6db 987static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 988{
989 int copied = 0;
b12bb29f 990 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 991 struct tty_port *tport = &port->state->port;
a5660ada 992 struct sci_port *s = to_sci_port(port);
1da177e4 993
0b3d4ef6
PM		 994 if (uart_handle_break(port))
995 return 0;
996
b7a76e4b 997 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 998#if defined(CONFIG_CPU_SH3)
999 /* Debounce break */
1000 s->break_flag = 1;
1001#endif
d97fbbed
PM		 1002
1003 port->icount.brk++;
1004
1da177e4 1005 /* Notify of BREAK */
92a19f9c 1006 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1007 copied++;
762c69e3
PM		 1008
1009 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1010 }
1011
33f0f88f 1012 if (copied)
2e124b4a 1013 tty_flip_buffer_push(tport);
e108b2ca 1014
d830fa45
PM		 1015 copied += sci_handle_fifo_overrun(port);
1016
1da177e4
LT		 1017 return copied;
1018}
1019
73a19e4c 1020#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1021static void sci_dma_tx_complete(void *arg)
1022{
1023 struct sci_port *s = arg;
1024 struct uart_port *port = &s->port;
1025 struct circ_buf *xmit = &port->state->xmit;
1026 unsigned long flags;
73a19e4c 1027
e1910fcd 1028 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1029
e1910fcd 1030 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1031
e1910fcd
GU		 1032 xmit->tail += s->tx_dma_len;
1033 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1034
e1910fcd 1035 port->icount.tx += s->tx_dma_len;
1da177e4 1036
e1910fcd
GU		 1037 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1038 uart_write_wakeup(port);
1da177e4 1039
e1910fcd
GU		 1040 if (!uart_circ_empty(xmit)) {
1041 s->cookie_tx = 0;
1042 schedule_work(&s->work_tx);
1043 } else {
1044 s->cookie_tx = -EINVAL;
1045 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1046 u16 ctrl = serial_port_in(port, SCSCR);
1047 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1048 }
1049 }
1da177e4 1050
fd78a76a 1051 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1052}
1053
e1910fcd
GU		 1054/* Locking: called with port lock held */
1055static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1056{
e1910fcd
GU		 1057 struct uart_port *port = &s->port;
1058 struct tty_port *tport = &port->state->port;
1059 int copied;
1da177e4 1060
e1910fcd
GU		 1061 copied = tty_insert_flip_string(tport, buf, count);
1062 if (copied < count) {
1063 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1064 count - copied);
1065 port->icount.buf_overrun++;
1da177e4
LT		 1066 }
1067
e1910fcd 1068 port->icount.rx += copied;
1da177e4 1069
e1910fcd 1070 return copied;
1da177e4
LT		 1071}
1072
e1910fcd 1073static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1074{
e1910fcd 1075 unsigned int i;
1da177e4 1076
e1910fcd
GU		 1077 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1078 if (s->active_rx == s->cookie_rx[i])
1079 return i;
1da177e4 1080
e1910fcd
GU		 1081 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1082 s->active_rx);
1083 return -1;
1da177e4
LT		 1084}
1085
e1910fcd 1086static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1087{
e1910fcd
GU		 1088 struct dma_chan *chan = s->chan_rx;
1089 struct uart_port *port = &s->port;
1090 unsigned long flags;
1091
1092 spin_lock_irqsave(&port->lock, flags);
1093 s->chan_rx = NULL;
1094 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1095 spin_unlock_irqrestore(&port->lock, flags);
1096 dmaengine_terminate_all(chan);
1097 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1098 sg_dma_address(&s->sg_rx[0]));
1099 dma_release_channel(chan);
1100 if (enable_pio)
1101 sci_start_rx(port);
f43dc23d
PM		 1102}
1103
e1910fcd 1104static void sci_dma_rx_complete(void *arg)
1da177e4 1105{
e1910fcd 1106 struct sci_port *s = arg;
1d3db608 1107 struct dma_chan *chan = s->chan_rx;
e1910fcd 1108 struct uart_port *port = &s->port;
67f462b0 1109 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1110 unsigned long flags;
1111 int active, count = 0;
1da177e4 1112
e1910fcd
GU		 1113 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1114 s->active_rx);
cb772fe7 1115
e1910fcd 1116 spin_lock_irqsave(&port->lock, flags);
1da177e4 1117
e1910fcd
GU		 1118 active = sci_dma_rx_find_active(s);
1119 if (active >= 0)
1120 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1121
e1910fcd 1122 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1123
e1910fcd
GU		 1124 if (count)
1125 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1126
67f462b0
GU		 1127 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1128 DMA_DEV_TO_MEM,
1129 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1130 if (!desc)
1131 goto fail;
1132
1133 desc->callback = sci_dma_rx_complete;
1134 desc->callback_param = s;
1135 s->cookie_rx[active] = dmaengine_submit(desc);
1136 if (dma_submit_error(s->cookie_rx[active]))
1137 goto fail;
1138
1139 s->active_rx = s->cookie_rx[!active];
1140
1d3db608
MHF		 1141 dma_async_issue_pending(chan);
1142
67f462b0
GU		 1143 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1144 __func__, s->cookie_rx[active], active, s->active_rx);
1145 spin_unlock_irqrestore(&port->lock, flags);
1146 return;
1147
1148fail:
1149 spin_unlock_irqrestore(&port->lock, flags);
1150 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1151 sci_rx_dma_release(s, true);
1da177e4
LT		 1152}
1153
e1910fcd 1154static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1155{
e1910fcd
GU		 1156 struct dma_chan *chan = s->chan_tx;
1157 struct uart_port *port = &s->port;
e552de24 1158 unsigned long flags;
1da177e4 1159
e1910fcd
GU		 1160 spin_lock_irqsave(&port->lock, flags);
1161 s->chan_tx = NULL;
1162 s->cookie_tx = -EINVAL;
1163 spin_unlock_irqrestore(&port->lock, flags);
1164 dmaengine_terminate_all(chan);
1165 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1166 DMA_TO_DEVICE);
1167 dma_release_channel(chan);
1168 if (enable_pio)
1169 sci_start_tx(port);
1170}
d535a230 1171
e1910fcd
GU		 1172static void sci_submit_rx(struct sci_port *s)
1173{
1174 struct dma_chan *chan = s->chan_rx;
1175 int i;
073e84c9 1176
e1910fcd
GU		 1177 for (i = 0; i < 2; i++) {
1178 struct scatterlist *sg = &s->sg_rx[i];
1179 struct dma_async_tx_descriptor *desc;
1da177e4 1180
e1910fcd
GU		 1181 desc = dmaengine_prep_slave_sg(chan,
1182 sg, 1, DMA_DEV_TO_MEM,
1183 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1184 if (!desc)
1185 goto fail;
501b825d 1186
e1910fcd
GU		 1187 desc->callback = sci_dma_rx_complete;
1188 desc->callback_param = s;
1189 s->cookie_rx[i] = dmaengine_submit(desc);
1190 if (dma_submit_error(s->cookie_rx[i]))
1191 goto fail;
9174fc8f 1192
e1910fcd
GU		 1193 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1194 s->cookie_rx[i], i);
1195 }
9174fc8f 1196
e1910fcd 1197 s->active_rx = s->cookie_rx[0];
9174fc8f 1198
e1910fcd
GU		 1199 dma_async_issue_pending(chan);
1200 return;
9174fc8f 1201
e1910fcd
GU		 1202fail:
1203 if (i)
1204 dmaengine_terminate_all(chan);
1205 for (i = 0; i < 2; i++)
1206 s->cookie_rx[i] = -EINVAL;
1207 s->active_rx = -EINVAL;
1208 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1209 sci_rx_dma_release(s, true);
1210}
9174fc8f 1211
e1910fcd 1212static void work_fn_tx(struct work_struct *work)
1da177e4 1213{
e1910fcd
GU		 1214 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1215 struct dma_async_tx_descriptor *desc;
1216 struct dma_chan *chan = s->chan_tx;
1217 struct uart_port *port = &s->port;
1218 struct circ_buf *xmit = &port->state->xmit;
1219 dma_addr_t buf;
1da177e4 1220
9174fc8f 1221 /*
e1910fcd
GU		 1222 * DMA is idle now.
1223 * Port xmit buffer is already mapped, and it is one page... Just adjust
1224 * offsets and lengths. Since it is a circular buffer, we have to
1225 * transmit till the end, and then the rest. Take the port lock to get a
1226 * consistent xmit buffer state.
9174fc8f 1227 */
e1910fcd
GU		 1228 spin_lock_irq(&port->lock);
1229 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1230 s->tx_dma_len = min_t(unsigned int,
1231 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1232 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1233 spin_unlock_irq(&port->lock);
0e8963de 1234
e1910fcd
GU		 1235 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1236 DMA_MEM_TO_DEV,
1237 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1238 if (!desc) {
1239 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1240 /* switch to PIO */
1241 sci_tx_dma_release(s, true);
1242 return;
1243 }
0e8963de 1244
e1910fcd
GU		 1245 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1246 DMA_TO_DEVICE);
1da177e4 1247
e1910fcd
GU		 1248 spin_lock_irq(&port->lock);
1249 desc->callback = sci_dma_tx_complete;
1250 desc->callback_param = s;
1251 spin_unlock_irq(&port->lock);
1252 s->cookie_tx = dmaengine_submit(desc);
1253 if (dma_submit_error(s->cookie_tx)) {
1254 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1255 /* switch to PIO */
1256 sci_tx_dma_release(s, true);
1257 return;
1da177e4 1258 }
1da177e4 1259
e1910fcd
GU		 1260 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1261 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1262
e1910fcd 1263 dma_async_issue_pending(chan);
1da177e4
LT		 1264}
1265
e1910fcd 1266static bool filter(struct dma_chan *chan, void *slave)
1da177e4 1267{
e1910fcd 1268 struct sh_dmae_slave *param = slave;
dc7e3ef7 1269
e1910fcd
GU		 1270 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1271 __func__, param->shdma_slave.slave_id);
1272
1273 chan->private = &param->shdma_slave;
1274 return true;
1da177e4
LT		 1275}
1276
e1910fcd 1277static void rx_timer_fn(unsigned long arg)
1da177e4 1278{
e1910fcd 1279 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1280 struct dma_chan *chan = s->chan_rx;
e1910fcd 1281 struct uart_port *port = &s->port;
67f462b0
GU		 1282 struct dma_tx_state state;
1283 enum dma_status status;
1284 unsigned long flags;
1285 unsigned int read;
1286 int active, count;
1287 u16 scr;
1288
1289 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1290
67f462b0 1291 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0
GU		 1292
1293 active = sci_dma_rx_find_active(s);
1294 if (active < 0) {
1295 spin_unlock_irqrestore(&port->lock, flags);
1296 return;
1297 }
1298
1299 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1300 if (status == DMA_COMPLETE) {
67f462b0
GU		 1301 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1302 s->active_rx, active);
3b963042
MHF		 1303 spin_unlock_irqrestore(&port->lock, flags);
1304
1305 /* Let packet complete handler take care of the packet */
1306 return;
1307 }
67f462b0 1308
e7327c09
MHF		 1309 dmaengine_pause(chan);
1310
1311 /*
1312 * sometimes DMA transfer doesn't stop even if it is stopped and
1313 * data keeps on coming until transaction is complete so check
1314 * for DMA_COMPLETE again
1315 * Let packet complete handler take care of the packet
1316 */
1317 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1318 if (status == DMA_COMPLETE) {
1319 spin_unlock_irqrestore(&port->lock, flags);
1320 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1321 return;
1322 }
1323
67f462b0
GU		 1324 /* Handle incomplete DMA receive */
1325 dmaengine_terminate_all(s->chan_rx);
1326 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1327 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1328 s->active_rx);
1329
1330 if (read) {
1331 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1332 if (count)
1333 tty_flip_buffer_push(&port->state->port);
1334 }
1335
756981be
GU		 1336 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1337 sci_submit_rx(s);
371cfed3
MHF		 1338
1339 /* Direct new serial port interrupts back to CPU */
1340 scr = serial_port_in(port, SCSCR);
1341 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1342 scr &= ~SCSCR_RDRQE;
1343 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1344 }
1345 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1346
1347 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1348}
1349
e1910fcd 1350static void sci_request_dma(struct uart_port *port)
73a19e4c 1351{
e1910fcd
GU		 1352 struct sci_port *s = to_sci_port(port);
1353 struct sh_dmae_slave *param;
1354 struct dma_chan *chan;
1355 dma_cap_mask_t mask;
73a19e4c 1356
e1910fcd 1357 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1358
e1910fcd
GU		 1359 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1360 return;
73a19e4c 1361
e1910fcd
GU		 1362 dma_cap_zero(mask);
1363 dma_cap_set(DMA_SLAVE, mask);
73a19e4c 1364
e1910fcd 1365 param = &s->param_tx;
73a19e4c 1366
e1910fcd
GU		 1367 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1368 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c 1369
e1910fcd
GU		 1370 s->cookie_tx = -EINVAL;
1371 chan = dma_request_channel(mask, filter, param);
1372 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1373 if (chan) {
1374 s->chan_tx = chan;
1375 /* UART circular tx buffer is an aligned page. */
1376 s->tx_dma_addr = dma_map_single(chan->device->dev,
1377 port->state->xmit.buf,
1378 UART_XMIT_SIZE,
1379 DMA_TO_DEVICE);
1380 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1381 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1382 dma_release_channel(chan);
1383 s->chan_tx = NULL;
1384 } else {
1385 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1386 __func__, UART_XMIT_SIZE,
1387 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1388 }
e1910fcd
GU		 1389
1390 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1391 }
1392
e1910fcd 1393 param = &s->param_rx;
73a19e4c 1394
e1910fcd
GU		 1395 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1396 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c 1397
e1910fcd
GU		 1398 chan = dma_request_channel(mask, filter, param);
1399 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1400 if (chan) {
1401 unsigned int i;
1402 dma_addr_t dma;
1403 void *buf;
73a19e4c 1404
e1910fcd 1405 s->chan_rx = chan;
73a19e4c 1406
e1910fcd
GU		 1407 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1408 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1409 &dma, GFP_KERNEL);
1410 if (!buf) {
1411 dev_warn(port->dev,
1412 "Failed to allocate Rx dma buffer, using PIO\n");
1413 dma_release_channel(chan);
1414 s->chan_rx = NULL;
e1910fcd
GU		 1415 return;
1416 }
73a19e4c 1417
e1910fcd
GU		 1418 for (i = 0; i < 2; i++) {
1419 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1420
e1910fcd
GU		 1421 sg_init_table(sg, 1);
1422 s->rx_buf[i] = buf;
1423 sg_dma_address(sg) = dma;
1424 sg->length = s->buf_len_rx;
0533502d 1425
e1910fcd
GU		 1426 buf += s->buf_len_rx;
1427 dma += s->buf_len_rx;
1428 }
1429
e1910fcd
GU		 1430 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1431
756981be
GU		 1432 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1433 sci_submit_rx(s);
e1910fcd 1434 }
0533502d
GU		 1435}
1436
e1910fcd 1437static void sci_free_dma(struct uart_port *port)
73a19e4c 1438{
e1910fcd 1439 struct sci_port *s = to_sci_port(port);
73a19e4c 1440
e1910fcd
GU		 1441 if (s->chan_tx)
1442 sci_tx_dma_release(s, false);
1443 if (s->chan_rx)
1444 sci_rx_dma_release(s, false);
1445}
1446#else
1447static inline void sci_request_dma(struct uart_port *port)
1448{
1449}
73a19e4c 1450
e1910fcd
GU		 1451static inline void sci_free_dma(struct uart_port *port)
1452{
1453}
1454#endif
73a19e4c 1455
e1910fcd
GU		 1456static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1457{
1458#ifdef CONFIG_SERIAL_SH_SCI_DMA
1459 struct uart_port *port = ptr;
1460 struct sci_port *s = to_sci_port(port);
73a19e4c 1461
e1910fcd
GU		 1462 if (s->chan_rx) {
1463 u16 scr = serial_port_in(port, SCSCR);
1464 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1465
e1910fcd
GU		 1466 /* Disable future Rx interrupts */
1467 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1468 disable_irq_nosync(irq);
1469 scr |= SCSCR_RDRQE;
1470 } else {
1471 scr &= ~SCSCR_RIE;
756981be 1472 sci_submit_rx(s);
e1910fcd
GU		 1473 }
1474 serial_port_out(port, SCSCR, scr);
1475 /* Clear current interrupt */
1476 serial_port_out(port, SCxSR,
1477 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1478 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1479 jiffies, s->rx_timeout);
1480 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1481
e1910fcd
GU		 1482 return IRQ_HANDLED;
1483 }
1484#endif
73a19e4c 1485
e1910fcd
GU		 1486 /* I think sci_receive_chars has to be called irrespective
1487 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1488 * to be disabled?
1489 */
1490 sci_receive_chars(ptr);
1491
1492 return IRQ_HANDLED;
73a19e4c
GL		 1493}
1494
e1910fcd 1495static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1496{
e1910fcd 1497 struct uart_port *port = ptr;
04928b79 1498 unsigned long flags;
73a19e4c 1499
04928b79 1500 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1501 sci_transmit_chars(port);
04928b79 1502 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1503
1504 return IRQ_HANDLED;
73a19e4c
GL		 1505}
1506
e1910fcd 1507static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1508{
e1910fcd
GU		 1509 struct uart_port *port = ptr;
1510 struct sci_port *s = to_sci_port(port);
73a19e4c 1511
e1910fcd
GU		 1512 /* Handle errors */
1513 if (port->type == PORT_SCI) {
1514 if (sci_handle_errors(port)) {
1515 /* discard character in rx buffer */
1516 serial_port_in(port, SCxSR);
1517 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1518 }
1519 } else {
1520 sci_handle_fifo_overrun(port);
1521 if (!s->chan_rx)
1522 sci_receive_chars(ptr);
1523 }
1524
1525 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1526
1527 /* Kick the transmission */
1528 if (!s->chan_tx)
1529 sci_tx_interrupt(irq, ptr);
1530
1531 return IRQ_HANDLED;
73a19e4c
GL		 1532}
1533
e1910fcd 1534static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1535{
e1910fcd 1536 struct uart_port *port = ptr;
73a19e4c 1537
e1910fcd
GU		 1538 /* Handle BREAKs */
1539 sci_handle_breaks(port);
1540 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1541
e1910fcd
GU		 1542 return IRQ_HANDLED;
1543}
73a19e4c 1544
e1910fcd
GU		 1545static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1546{
1547 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1548 struct uart_port *port = ptr;
1549 struct sci_port *s = to_sci_port(port);
1550 irqreturn_t ret = IRQ_NONE;
73a19e4c 1551
e1910fcd
GU		 1552 ssr_status = serial_port_in(port, SCxSR);
1553 scr_status = serial_port_in(port, SCSCR);
1554 if (s->overrun_reg == SCxSR)
1555 orer_status = ssr_status;
1556 else {
1557 if (sci_getreg(port, s->overrun_reg)->size)
1558 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1559 }
1560
e1910fcd 1561 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1562
e1910fcd
GU		 1563 /* Tx Interrupt */
1564 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1565 !s->chan_tx)
1566 ret = sci_tx_interrupt(irq, ptr);
658daa95 1567
e1910fcd
GU		 1568 /*
1569 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1570 * DR flags
1571 */
1572 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1573 (scr_status & SCSCR_RIE))
1574 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1575
e1910fcd
GU		 1576 /* Error Interrupt */
1577 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1578 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1579
e1910fcd
GU		 1580 /* Break Interrupt */
1581 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1582 ret = sci_br_interrupt(irq, ptr);
1583
1584 /* Overrun Interrupt */
1585 if (orer_status & s->overrun_mask) {
1586 sci_handle_fifo_overrun(port);
1587 ret = IRQ_HANDLED;
73a19e4c 1588 }
73a19e4c 1589
e1910fcd
GU		 1590 return ret;
1591}
73a19e4c 1592
e1910fcd
GU		 1593/*
1594 * Here we define a transition notifier so that we can update all of our
1595 * ports' baud rate when the peripheral clock changes.
1596 */
1597static int sci_notifier(struct notifier_block *self,
1598 unsigned long phase, void *p)
1599{
1600 struct sci_port *sci_port;
1601 unsigned long flags;
73a19e4c 1602
e1910fcd 1603 sci_port = container_of(self, struct sci_port, freq_transition);
73a19e4c 1604
e1910fcd
GU		 1605 if (phase == CPUFREQ_POSTCHANGE) {
1606 struct uart_port *port = &sci_port->port;
73a19e4c 1607
e1910fcd
GU		 1608 spin_lock_irqsave(&port->lock, flags);
1609 port->uartclk = clk_get_rate(sci_port->iclk);
1610 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1611 }
1612
e1910fcd
GU		 1613 return NOTIFY_OK;
1614}
73a19e4c 1615
e1910fcd
GU		 1616static const struct sci_irq_desc {
1617 const char *desc;
1618 irq_handler_t handler;
1619} sci_irq_desc[] = {
1620 /*
1621 * Split out handlers, the default case.
1622 */
1623 [SCIx_ERI_IRQ] = {
1624 .desc = "rx err",
1625 .handler = sci_er_interrupt,
1626 },
3089f381 1627
e1910fcd
GU		 1628 [SCIx_RXI_IRQ] = {
1629 .desc = "rx full",
1630 .handler = sci_rx_interrupt,
1631 },
47aceb92 1632
e1910fcd
GU		 1633 [SCIx_TXI_IRQ] = {
1634 .desc = "tx empty",
1635 .handler = sci_tx_interrupt,
1636 },
73a19e4c 1637
e1910fcd
GU		 1638 [SCIx_BRI_IRQ] = {
1639 .desc = "break",
1640 .handler = sci_br_interrupt,
1641 },
73a19e4c
GL		 1642
1643 /*
e1910fcd 1644 * Special muxed handler.
73a19e4c 1645 */
e1910fcd
GU		 1646 [SCIx_MUX_IRQ] = {
1647 .desc = "mux",
1648 .handler = sci_mpxed_interrupt,
1649 },
1650};
73a19e4c 1651
e1910fcd
GU		 1652static int sci_request_irq(struct sci_port *port)
1653{
1654 struct uart_port *up = &port->port;
1655 int i, j, ret = 0;
73a19e4c 1656
e1910fcd
GU		 1657 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1658 const struct sci_irq_desc *desc;
1659 int irq;
73a19e4c 1660
e1910fcd
GU		 1661 if (SCIx_IRQ_IS_MUXED(port)) {
1662 i = SCIx_MUX_IRQ;
1663 irq = up->irq;
1664 } else {
1665 irq = port->irqs[i];
1666
1667 /*
1668 * Certain port types won't support all of the
1669 * available interrupt sources.
1670 */
1671 if (unlikely(irq < 0))
1672 continue;
1673 }
1674
1675 desc = sci_irq_desc + i;
1676 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1677 dev_name(up->dev), desc->desc);
1678 if (!port->irqstr[j])
1679 goto out_nomem;
1680
1681 ret = request_irq(irq, desc->handler, up->irqflags,
1682 port->irqstr[j], port);
1683 if (unlikely(ret)) {
1684 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1685 goto out_noirq;
1686 }
73a19e4c
GL		 1687 }
1688
e1910fcd 1689 return 0;
1da177e4 1690
e1910fcd
GU		 1691out_noirq:
1692 while (--i >= 0)
1693 free_irq(port->irqs[i], port);
f43dc23d 1694
e1910fcd
GU		 1695out_nomem:
1696 while (--j >= 0)
1697 kfree(port->irqstr[j]);
f43dc23d 1698
e1910fcd 1699 return ret;
1da177e4
LT		 1700}
1701
e1910fcd 1702static void sci_free_irq(struct sci_port *port)
1da177e4 1703{
e1910fcd 1704 int i;
1da177e4 1705
e1910fcd
GU		 1706 /*
1707 * Intentionally in reverse order so we iterate over the muxed
1708 * IRQ first.
1709 */
1710 for (i = 0; i < SCIx_NR_IRQS; i++) {
1711 int irq = port->irqs[i];
f43dc23d 1712
e1910fcd
GU		 1713 /*
1714 * Certain port types won't support all of the available
1715 * interrupt sources.
1716 */
1717 if (unlikely(irq < 0))
1718 continue;
f43dc23d 1719
e1910fcd
GU		 1720 free_irq(port->irqs[i], port);
1721 kfree(port->irqstr[i]);
f43dc23d 1722
e1910fcd
GU		 1723 if (SCIx_IRQ_IS_MUXED(port)) {
1724 /* If there's only one IRQ, we're done. */
1725 return;
1726 }
1727 }
1da177e4
LT		 1728}
1729
e1910fcd 1730static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1731{
e1910fcd
GU		 1732 unsigned short status = serial_port_in(port, SCxSR);
1733 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1734
e1910fcd 1735 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1736}
1737
e1910fcd
GU		 1738/*
1739 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1740 * CTS/RTS is supported in hardware by at least one port and controlled
1741 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1742 * handled via the ->init_pins() op, which is a bit of a one-way street,
1743 * lacking any ability to defer pin control -- this will later be
1744 * converted over to the GPIO framework).
1745 *
1746 * Other modes (such as loopback) are supported generically on certain
1747 * port types, but not others. For these it's sufficient to test for the
1748 * existence of the support register and simply ignore the port type.
1749 */
1750static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1751{
e1910fcd
GU		 1752 if (mctrl & TIOCM_LOOP) {
1753 const struct plat_sci_reg *reg;
f43dc23d 1754
e1910fcd
GU		 1755 /*
1756 * Standard loopback mode for SCFCR ports.
1757 */
1758 reg = sci_getreg(port, SCFCR);
1759 if (reg->size)
1760 serial_port_out(port, SCFCR,
1761 serial_port_in(port, SCFCR) |
1762 SCFCR_LOOP);
1763 }
1764}
f43dc23d 1765
e1910fcd
GU		 1766static unsigned int sci_get_mctrl(struct uart_port *port)
1767{
1768 /*
1769 * CTS/RTS is handled in hardware when supported, while nothing
1770 * else is wired up. Keep it simple and simply assert DSR/CAR.
1771 */
1772 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1773}
1774
1da177e4
LT		 1775static void sci_break_ctl(struct uart_port *port, int break_state)
1776{
bbb4ce50 1777 struct sci_port *s = to_sci_port(port);
d3184e68 1778 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1779 unsigned short scscr, scsptr;
1780
a4e02f6d
SY		 1781 /* check wheter the port has SCSPTR */
1782 if (!reg->size) {
bbb4ce50
SY		 1783 /*
1784 * Not supported by hardware. Most parts couple break and rx
1785 * interrupts together, with break detection always enabled.
1786 */
a4e02f6d 1787 return;
bbb4ce50 1788 }
a4e02f6d
SY		 1789
1790 scsptr = serial_port_in(port, SCSPTR);
1791 scscr = serial_port_in(port, SCSCR);
1792
1793 if (break_state == -1) {
1794 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1795 scscr &= ~SCSCR_TE;
1796 } else {
1797 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1798 scscr |= SCSCR_TE;
1799 }
1800
1801 serial_port_out(port, SCSPTR, scsptr);
1802 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1803}
1804
1805static int sci_startup(struct uart_port *port)
1806{
a5660ada 1807 struct sci_port *s = to_sci_port(port);
33b48e16 1808 unsigned long flags;
073e84c9 1809 int ret;
1da177e4 1810
73a19e4c
GL		 1811 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1812
073e84c9
PM		 1813 ret = sci_request_irq(s);
1814 if (unlikely(ret < 0))
1815 return ret;
1816
73a19e4c 1817 sci_request_dma(port);
073e84c9 1818
33b48e16 1819 spin_lock_irqsave(&port->lock, flags);
d656901b 1820 sci_start_tx(port);
73a19e4c 1821 sci_start_rx(port);
33b48e16 1822 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1823
1824 return 0;
1825}
1826
1827static void sci_shutdown(struct uart_port *port)
1828{
a5660ada 1829 struct sci_port *s = to_sci_port(port);
33b48e16 1830 unsigned long flags;
1da177e4 1831
73a19e4c
GL		 1832 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1833
33b48e16 1834 spin_lock_irqsave(&port->lock, flags);
1da177e4 1835 sci_stop_rx(port);
b129a8cc 1836 sci_stop_tx(port);
33b48e16 1837 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1838
9ab76556
AM		 1839#ifdef CONFIG_SERIAL_SH_SCI_DMA
1840 if (s->chan_rx) {
1841 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1842 port->line);
1843 del_timer_sync(&s->rx_timer);
1844 }
1845#endif
1846
73a19e4c 1847 sci_free_dma(port);
1da177e4 1848 sci_free_irq(s);
1da177e4
LT		 1849}
1850
ec09c5eb 1851static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1852 unsigned long freq)
1853{
ec09c5eb
LP		 1854 if (s->sampling_rate)
1855 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1856
26c92f37
PM		 1857 /* Warn, but use a safe default */
1858 WARN_ON(1);
e8183a6c 1859
26c92f37
PM		 1860 return ((freq + 16 * bps) / (32 * bps) - 1);
1861}
1862
730c4e78
NI		 1863/* calculate frame length from SMR */
1864static int sci_baud_calc_frame_len(unsigned int smr_val)
1865{
1866 int len = 10;
1867
1868 if (smr_val & SCSMR_CHR)
1869 len--;
1870 if (smr_val & SCSMR_PE)
1871 len++;
1872 if (smr_val & SCSMR_STOP)
1873 len++;
1874
1875 return len;
1876}
1877
1878
f303b364
UH		 1879/* calculate sample rate, BRR, and clock select for HSCIF */
1880static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1881 int *brr, unsigned int *srr,
730c4e78 1882 unsigned int *cks, int frame_len)
f303b364 1883{
730c4e78 1884 int sr, c, br, err, recv_margin;
f303b364 1885 int min_err = 1000; /* 100% */
730c4e78 1886 int recv_max_margin = 0;
f303b364
UH		 1887
1888 /* Find the combination of sample rate and clock select with the
1889 smallest deviation from the desired baud rate. */
1890 for (sr = 8; sr <= 32; sr++) {
1891 for (c = 0; c <= 3; c++) {
1892 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1893 br = DIV_ROUND_CLOSEST(freq, (sr *
1894 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1895 br = clamp(br, 0, 255);
b7d66397
NI		 1896 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1897 (1 << (2 * c + 1)) / 1000)) -
1898 1000;
730c4e78
NI		 1899 /* Calc recv margin
1900 * M: Receive margin (%)
1901 * N: Ratio of bit rate to clock (N = sampling rate)
1902 * D: Clock duty (D = 0 to 1.0)
1903 * L: Frame length (L = 9 to 12)
1904 * F: Absolute value of clock frequency deviation
1905 *
1906 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1907 * (|D - 0.5| / N * (1 + F))|
1908 * NOTE: Usually, treat D for 0.5, F is 0 by this
1909 * calculation.
1910 */
1911 recv_margin = abs((500 -
1912 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1913 if (abs(min_err) > abs(err)) {
f303b364 1914 min_err = err;
730c4e78
NI		 1915 recv_max_margin = recv_margin;
1916 } else if ((min_err == err) &&
1917 (recv_margin > recv_max_margin))
1918 recv_max_margin = recv_margin;
1919 else
1920 continue;
1921
1922 *brr = br;
1923 *srr = sr - 1;
1924 *cks = c;
f303b364
UH		 1925 }
1926 }
1927
1928 if (min_err == 1000) {
1929 WARN_ON(1);
1930 /* use defaults */
1931 *brr = 255;
1932 *srr = 15;
1933 *cks = 0;
1934 }
1935}
1936
1ba76220
MD		 1937static void sci_reset(struct uart_port *port)
1938{
d3184e68 1939 const struct plat_sci_reg *reg;
1ba76220
MD		 1940 unsigned int status;
1941
1942 do {
b12bb29f 1943 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1944 } while (!(status & SCxSR_TEND(port)));
1945
b12bb29f 1946 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1947
0979e0e6
PM		 1948 reg = sci_getreg(port, SCFCR);
1949 if (reg->size)
b12bb29f 1950 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1951}
1952
606d099c
AC		 1953static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1954 struct ktermios *old)
1da177e4 1955{
00b9de9c 1956 struct sci_port *s = to_sci_port(port);
d3184e68 1957 const struct plat_sci_reg *reg;
730c4e78 1958 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1959 int t = -1;
d4759ded 1960 unsigned int srr = 15;
1da177e4 1961
730c4e78
NI		 1962 if ((termios->c_cflag & CSIZE) == CS7)
1963 smr_val |= SCSMR_CHR;
1964 if (termios->c_cflag & PARENB)
1965 smr_val |= SCSMR_PE;
1966 if (termios->c_cflag & PARODD)
1967 smr_val |= SCSMR_PE | SCSMR_ODD;
1968 if (termios->c_cflag & CSTOPB)
1969 smr_val |= SCSMR_STOP;
1970
154280fd
MD		 1971 /*
1972 * earlyprintk comes here early on with port->uartclk set to zero.
1973 * the clock framework is not up and running at this point so here
1974 * we assume that 115200 is the maximum baud rate. please note that
1975 * the baud rate is not programmed during earlyprintk - it is assumed
1976 * that the previous boot loader has enabled required clocks and
1977 * setup the baud rate generator hardware for us already.
1978 */
1979 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1980
154280fd 1981 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1982 if (likely(baud && port->uartclk)) {
ec09c5eb 1983 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1984 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1985 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1986 &cks, frame_len);
f303b364 1987 } else {
ec09c5eb 1988 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1989 for (cks = 0; t >= 256 && cks <= 3; cks++)
1990 t >>= 2;
1991 }
1992 }
e108b2ca 1993
23241d43 1994 sci_port_enable(s);
36003386 1995
1ba76220 1996 sci_reset(port);
1da177e4 1997
2944a331 1998 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 1999
2000 uart_update_timeout(port, termios->c_cflag, baud);
2001
9d482cc3
TY		 2002 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2003 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 2004
4ffc3cdb 2005 if (t >= 0) {
26de4f1b 2006 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 2007 serial_port_out(port, SCBRR, t);
f303b364
UH		 2008 reg = sci_getreg(port, HSSRR);
2009 if (reg->size)
2010 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 2011 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 2012 } else
2013 serial_port_out(port, SCSMR, smr_val);
1da177e4 2014
d5701647 2015 sci_init_pins(port, termios->c_cflag);
0979e0e6 2016
73c3d53f
PM		 2017 reg = sci_getreg(port, SCFCR);
2018 if (reg->size) {
b12bb29f 2019 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2020
73c3d53f 2021 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2022 if (termios->c_cflag & CRTSCTS)
2023 ctrl |= SCFCR_MCE;
2024 else
2025 ctrl &= ~SCFCR_MCE;
faf02f8f 2026 }
73c3d53f
PM		 2027
2028 /*
2029 * As we've done a sci_reset() above, ensure we don't
2030 * interfere with the FIFOs while toggling MCE. As the
2031 * reset values could still be set, simply mask them out.
2032 */
2033 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2034
b12bb29f 2035 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2036 }
b7a76e4b 2037
b12bb29f 2038 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2039
3089f381
GL		 2040#ifdef CONFIG_SERIAL_SH_SCI_DMA
2041 /*
5f6d8515 2042 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2043 * See serial_core.c::uart_update_timeout().
2044 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2045 * function calculates 1 jiffie for the data plus 5 jiffies for the
2046 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2047 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2048 * value obtained by this formula is too small. Therefore, if the value
2049 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2050 */
2051 if (s->chan_rx) {
5f6d8515
NI		 2052 unsigned int bits;
2053
2054 /* byte size and parity */
2055 switch (termios->c_cflag & CSIZE) {
2056 case CS5:
2057 bits = 7;
2058 break;
2059 case CS6:
2060 bits = 8;
2061 break;
2062 case CS7:
2063 bits = 9;
2064 break;
2065 default:
2066 bits = 10;
2067 break;
2068 }
2069
2070 if (termios->c_cflag & CSTOPB)
2071 bits++;
2072 if (termios->c_cflag & PARENB)
2073 bits++;
2074 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2075 (baud / 10), 10);
9b971cd2 2076 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2077 s->rx_timeout * 1000 / HZ, port->timeout);
2078 if (s->rx_timeout < msecs_to_jiffies(20))
2079 s->rx_timeout = msecs_to_jiffies(20);
2080 }
2081#endif
2082
1da177e4 2083 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2084 sci_start_rx(port);
36003386 2085
23241d43 2086 sci_port_disable(s);
1da177e4
LT		 2087}
2088
0174e5ca
TK		 2089static void sci_pm(struct uart_port *port, unsigned int state,
2090 unsigned int oldstate)
2091{
2092 struct sci_port *sci_port = to_sci_port(port);
2093
2094 switch (state) {
d3dfe5d9 2095 case UART_PM_STATE_OFF:
0174e5ca
TK		 2096 sci_port_disable(sci_port);
2097 break;
2098 default:
2099 sci_port_enable(sci_port);
2100 break;
2101 }
2102}
2103
1da177e4
LT		 2104static const char *sci_type(struct uart_port *port)
2105{
2106 switch (port->type) {
e7c98dc7
MT		 2107 case PORT_IRDA:
2108 return "irda";
2109 case PORT_SCI:
2110 return "sci";
2111 case PORT_SCIF:
2112 return "scif";
2113 case PORT_SCIFA:
2114 return "scifa";
d1d4b10c
GL		 2115 case PORT_SCIFB:
2116 return "scifb";
f303b364
UH		 2117 case PORT_HSCIF:
2118 return "hscif";
1da177e4
LT		 2119 }
2120
fa43972f 2121 return NULL;
1da177e4
LT		 2122}
2123
f6e9495d
PM		 2124static int sci_remap_port(struct uart_port *port)
2125{
e4d6f911 2126 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2127
2128 /*
2129 * Nothing to do if there's already an established membase.
2130 */
2131 if (port->membase)
2132 return 0;
2133
2134 if (port->flags & UPF_IOREMAP) {
e4d6f911 2135 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2136 if (unlikely(!port->membase)) {
2137 dev_err(port->dev, "can't remap port#%d\n", port->line);
2138 return -ENXIO;
2139 }
2140 } else {
2141 /*
2142 * For the simple (and majority of) cases where we don't
2143 * need to do any remapping, just cast the cookie
2144 * directly.
2145 */
3af4e960 2146 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2147 }
2148
2149 return 0;
2150}
2151
e2651647 2152static void sci_release_port(struct uart_port *port)
1da177e4 2153{
e4d6f911
YS		 2154 struct sci_port *sport = to_sci_port(port);
2155
e2651647
PM		 2156 if (port->flags & UPF_IOREMAP) {
2157 iounmap(port->membase);
2158 port->membase = NULL;
2159 }
2160
e4d6f911 2161 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2162}
2163
e2651647 2164static int sci_request_port(struct uart_port *port)
1da177e4 2165{
e2651647 2166 struct resource *res;
e4d6f911 2167 struct sci_port *sport = to_sci_port(port);
f6e9495d 2168 int ret;
1da177e4 2169
e4d6f911
YS		 2170 res = request_mem_region(port->mapbase, sport->reg_size,
2171 dev_name(port->dev));
2172 if (unlikely(res == NULL)) {
2173 dev_err(port->dev, "request_mem_region failed.");
e2651647 2174 return -EBUSY;
e4d6f911 2175 }
1da177e4 2176
f6e9495d
PM		 2177 ret = sci_remap_port(port);
2178 if (unlikely(ret != 0)) {
2179 release_resource(res);
2180 return ret;
7ff731ae 2181 }
e2651647
PM		 2182
2183 return 0;
2184}
2185
2186static void sci_config_port(struct uart_port *port, int flags)
2187{
2188 if (flags & UART_CONFIG_TYPE) {
2189 struct sci_port *sport = to_sci_port(port);
2190
2191 port->type = sport->cfg->type;
2192 sci_request_port(port);
2193 }
1da177e4
LT		 2194}
2195
2196static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2197{
1da177e4
LT		 2198 if (ser->baud_base < 2400)
2199 /* No paper tape reader for Mitch.. */
2200 return -EINVAL;
2201
2202 return 0;
2203}
2204
2205static struct uart_ops sci_uart_ops = {
2206 .tx_empty = sci_tx_empty,
2207 .set_mctrl = sci_set_mctrl,
2208 .get_mctrl = sci_get_mctrl,
2209 .start_tx = sci_start_tx,
2210 .stop_tx = sci_stop_tx,
2211 .stop_rx = sci_stop_rx,
1da177e4
LT		 2212 .break_ctl = sci_break_ctl,
2213 .startup = sci_startup,
2214 .shutdown = sci_shutdown,
2215 .set_termios = sci_set_termios,
0174e5ca 2216 .pm = sci_pm,
1da177e4
LT		 2217 .type = sci_type,
2218 .release_port = sci_release_port,
2219 .request_port = sci_request_port,
2220 .config_port = sci_config_port,
2221 .verify_port = sci_verify_port,
07d2a1a1
PM		 2222#ifdef CONFIG_CONSOLE_POLL
2223 .poll_get_char = sci_poll_get_char,
2224 .poll_put_char = sci_poll_put_char,
2225#endif
1da177e4
LT		 2226};
2227
9671f099 2228static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2229 struct sci_port *sci_port, unsigned int index,
2230 struct plat_sci_port *p, bool early)
e108b2ca 2231{
73a19e4c 2232 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2233 const struct resource *res;
2234 unsigned int i;
3127c6b2 2235 int ret;
e108b2ca 2236
50f0959a
PM		 2237 sci_port->cfg = p;
2238
73a19e4c
GL		 2239 port->ops = &sci_uart_ops;
2240 port->iotype = UPIO_MEM;
2241 port->line = index;
75136d48 2242
89b5c1ab
LP		 2243 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2244 if (res == NULL)
2245 return -ENOMEM;
1fcc91a6 2246
89b5c1ab 2247 port->mapbase = res->start;
e4d6f911 2248 sci_port->reg_size = resource_size(res);
1fcc91a6 2249
89b5c1ab
LP		 2250 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2251 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2252
89b5c1ab
LP		 2253 /* The SCI generates several interrupts. They can be muxed together or
2254 * connected to different interrupt lines. In the muxed case only one
2255 * interrupt resource is specified. In the non-muxed case three or four
2256 * interrupt resources are specified, as the BRI interrupt is optional.
2257 */
2258 if (sci_port->irqs[0] < 0)
2259 return -ENXIO;
1fcc91a6 2260
89b5c1ab
LP		 2261 if (sci_port->irqs[1] < 0) {
2262 sci_port->irqs[1] = sci_port->irqs[0];
2263 sci_port->irqs[2] = sci_port->irqs[0];
2264 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2265 }
2266
b545e4f4
LP		 2267 if (p->regtype == SCIx_PROBE_REGTYPE) {
2268 ret = sci_probe_regmap(p);
2269 if (unlikely(ret))
2270 return ret;
2271 }
2272
75136d48 2273 switch (p->type) {
d1d4b10c
GL		 2274 case PORT_SCIFB:
2275 port->fifosize = 256;
2e0842a1 2276 sci_port->overrun_reg = SCxSR;
75c249fd 2277 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2278 sci_port->sampling_rate = 16;
d1d4b10c 2279 break;
f303b364
UH		 2280 case PORT_HSCIF:
2281 port->fifosize = 128;
2e0842a1 2282 sci_port->overrun_reg = SCLSR;
75c249fd 2283 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2284 sci_port->sampling_rate = 0;
f303b364 2285 break;
75136d48 2286 case PORT_SCIFA:
73a19e4c 2287 port->fifosize = 64;
2e0842a1 2288 sci_port->overrun_reg = SCxSR;
75c249fd 2289 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2290 sci_port->sampling_rate = 16;
75136d48
MP		 2291 break;
2292 case PORT_SCIF:
73a19e4c 2293 port->fifosize = 16;
ec09c5eb 2294 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2295 sci_port->overrun_reg = SCxSR;
75c249fd 2296 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2297 sci_port->sampling_rate = 16;
ec09c5eb 2298 } else {
2e0842a1 2299 sci_port->overrun_reg = SCLSR;
75c249fd 2300 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2301 sci_port->sampling_rate = 32;
ec09c5eb 2302 }
75136d48
MP		 2303 break;
2304 default:
73a19e4c 2305 port->fifosize = 1;
2e0842a1 2306 sci_port->overrun_reg = SCxSR;
75c249fd 2307 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2308 sci_port->sampling_rate = 32;
75136d48
MP		 2309 break;
2310 }
7b6fd3bf 2311
878fbb91
LP		 2312 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2313 * match the SoC datasheet, this should be investigated. Let platform
2314 * data override the sampling rate for now.
ec09c5eb 2315 */
f84b6bdc
GU		 2316 if (p->sampling_rate)
2317 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2318
1fcc91a6 2319 if (!early) {
c7ed1ab3
PM		 2320 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2321 if (IS_ERR(sci_port->iclk)) {
2322 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2323 if (IS_ERR(sci_port->iclk)) {
2324 dev_err(&dev->dev, "can't get iclk\n");
2325 return PTR_ERR(sci_port->iclk);
2326 }
2327 }
2328
2329 /*
2330 * The function clock is optional, ignore it if we can't
2331 * find it.
2332 */
2333 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2334 if (IS_ERR(sci_port->fclk))
2335 sci_port->fclk = NULL;
2336
73a19e4c 2337 port->dev = &dev->dev;
5e50d2d6
MD		 2338
2339 pm_runtime_enable(&dev->dev);
7b6fd3bf 2340 }
e108b2ca 2341
7ed7e071
MD		 2342 sci_port->break_timer.data = (unsigned long)sci_port;
2343 sci_port->break_timer.function = sci_break_timer;
2344 init_timer(&sci_port->break_timer);
2345
debf9507
PM		 2346 /*
2347 * Establish some sensible defaults for the error detection.
2348 */
5da0f468
GU		 2349 if (p->type == PORT_SCI) {
2350 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2351 sci_port->error_clear = SCI_ERROR_CLEAR;
2352 } else {
2353 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2354 sci_port->error_clear = SCIF_ERROR_CLEAR;
2355 }
debf9507 2356
3ae988d9
LP		 2357 /*
2358 * Make the error mask inclusive of overrun detection, if
2359 * supported.
2360 */
5da0f468 2361 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2362 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2363 sci_port->error_clear &= ~sci_port->overrun_mask;
2364 }
debf9507 2365
ce6738b6 2366 port->type = p->type;
b6e4a3f1 2367 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2368 port->regshift = p->regshift;
73a19e4c 2369
ce6738b6 2370 /*
61a6976b 2371 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2372 * for the multi-IRQ ports, which is where we are primarily
2373 * concerned with the shutdown path synchronization.
2374 *
2375 * For the muxed case there's nothing more to do.
2376 */
1fcc91a6 2377 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2378 port->irqflags = 0;
73a19e4c 2379
61a6976b
PM		 2380 port->serial_in = sci_serial_in;
2381 port->serial_out = sci_serial_out;
2382
937bb6e4
GL		 2383 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2384 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2385 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2386
c7ed1ab3 2387 return 0;
e108b2ca
PM		 2388}
2389
6dae1421
LP		 2390static void sci_cleanup_single(struct sci_port *port)
2391{
6dae1421
LP		 2392 clk_put(port->iclk);
2393 clk_put(port->fclk);
2394
2395 pm_runtime_disable(port->port.dev);
2396}
2397
1da177e4 2398#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2399static void serial_console_putchar(struct uart_port *port, int ch)
2400{
2401 sci_poll_put_char(port, ch);
2402}
2403
1da177e4
LT		 2404/*
2405 * Print a string to the serial port trying not to disturb
2406 * any possible real use of the port...
2407 */
2408static void serial_console_write(struct console *co, const char *s,
2409 unsigned count)
2410{
906b17dc
PM		 2411 struct sci_port *sci_port = &sci_ports[co->index];
2412 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2413 unsigned short bits, ctrl;
2414 unsigned long flags;
2415 int locked = 1;
2416
2417 local_irq_save(flags);
2418 if (port->sysrq)
2419 locked = 0;
2420 else if (oops_in_progress)
2421 locked = spin_trylock(&port->lock);
2422 else
2423 spin_lock(&port->lock);
2424
2425 /* first save the SCSCR then disable the interrupts */
2426 ctrl = serial_port_in(port, SCSCR);
2427 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2428
501b825d 2429 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2430
2431 /* wait until fifo is empty and last bit has been transmitted */
2432 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2433 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2434 cpu_relax();
40f70c03
SK		 2435
2436 /* restore the SCSCR */
2437 serial_port_out(port, SCSCR, ctrl);
2438
2439 if (locked)
2440 spin_unlock(&port->lock);
2441 local_irq_restore(flags);
1da177e4
LT		 2442}
2443
9671f099 2444static int serial_console_setup(struct console *co, char *options)
1da177e4 2445{
dc8e6f5b 2446 struct sci_port *sci_port;
1da177e4
LT		 2447 struct uart_port *port;
2448 int baud = 115200;
2449 int bits = 8;
2450 int parity = 'n';
2451 int flow = 'n';
2452 int ret;
2453
e108b2ca 2454 /*
906b17dc 2455 * Refuse to handle any bogus ports.
1da177e4 2456 */
906b17dc 2457 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2458 return -ENODEV;
e108b2ca 2459
906b17dc
PM		 2460 sci_port = &sci_ports[co->index];
2461 port = &sci_port->port;
2462
b2267a6b
AC		 2463 /*
2464 * Refuse to handle uninitialized ports.
2465 */
2466 if (!port->ops)
2467 return -ENODEV;
2468
f6e9495d
PM		 2469 ret = sci_remap_port(port);
2470 if (unlikely(ret != 0))
2471 return ret;
e108b2ca 2472
1da177e4
LT		 2473 if (options)
2474 uart_parse_options(options, &baud, &parity, &bits, &flow);
2475
ab7cfb55 2476 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2477}
2478
2479static struct console serial_console = {
2480 .name = "ttySC",
906b17dc 2481 .device = uart_console_device,
1da177e4
LT		 2482 .write = serial_console_write,
2483 .setup = serial_console_setup,
fa5da2f7 2484 .flags = CON_PRINTBUFFER,
1da177e4 2485 .index = -1,
906b17dc 2486 .data = &sci_uart_driver,
1da177e4
LT		 2487};
2488
7b6fd3bf
MD		 2489static struct console early_serial_console = {
2490 .name = "early_ttySC",
2491 .write = serial_console_write,
2492 .flags = CON_PRINTBUFFER,
906b17dc 2493 .index = -1,
7b6fd3bf 2494};
ecdf8a46 2495
7b6fd3bf
MD		 2496static char early_serial_buf[32];
2497
9671f099 2498static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2499{
574de559 2500 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2501
2502 if (early_serial_console.data)
2503 return -EEXIST;
2504
2505 early_serial_console.index = pdev->id;
ecdf8a46 2506
1fcc91a6 2507 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2508
2509 serial_console_setup(&early_serial_console, early_serial_buf);
2510
2511 if (!strstr(early_serial_buf, "keep"))
2512 early_serial_console.flags |= CON_BOOT;
2513
2514 register_console(&early_serial_console);
2515 return 0;
2516}
6a8c9799
NI		 2517
2518#define SCI_CONSOLE (&serial_console)
2519
ecdf8a46 2520#else
9671f099 2521static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2522{
2523 return -EINVAL;
2524}
1da177e4 2525
6a8c9799
NI		 2526#define SCI_CONSOLE NULL
2527
2528#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2529
6c13d5d2 2530static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2531
2532static struct uart_driver sci_uart_driver = {
2533 .owner = THIS_MODULE,
2534 .driver_name = "sci",
1da177e4
LT		 2535 .dev_name = "ttySC",
2536 .major = SCI_MAJOR,
2537 .minor = SCI_MINOR_START,
e108b2ca 2538 .nr = SCI_NPORTS,
1da177e4
LT		 2539 .cons = SCI_CONSOLE,
2540};
2541
54507f6e 2542static int sci_remove(struct platform_device *dev)
e552de24 2543{
d535a230 2544 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2545
d535a230
PM		 2546 cpufreq_unregister_notifier(&port->freq_transition,
2547 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2548
d535a230
PM		 2549 uart_remove_one_port(&sci_uart_driver, &port->port);
2550
6dae1421 2551 sci_cleanup_single(port);
e552de24 2552
e552de24
MD		 2553 return 0;
2554}
2555
20bdcab8
BH		 2556struct sci_port_info {
2557 unsigned int type;
2558 unsigned int regtype;
2559};
2560
2561static const struct of_device_id of_sci_match[] = {
2562 {
2563 .compatible = "renesas,scif",
ff43da00 2564 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2565 .type = PORT_SCIF,
2566 .regtype = SCIx_SH4_SCIF_REGTYPE,
2567 },
2568 }, {
2569 .compatible = "renesas,scifa",
ff43da00 2570 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2571 .type = PORT_SCIFA,
2572 .regtype = SCIx_SCIFA_REGTYPE,
2573 },
2574 }, {
2575 .compatible = "renesas,scifb",
ff43da00 2576 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2577 .type = PORT_SCIFB,
2578 .regtype = SCIx_SCIFB_REGTYPE,
2579 },
2580 }, {
2581 .compatible = "renesas,hscif",
ff43da00 2582 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2583 .type = PORT_HSCIF,
2584 .regtype = SCIx_HSCIF_REGTYPE,
2585 },
e1d0be61
YS		 2586 }, {
2587 .compatible = "renesas,sci",
2588 .data = &(const struct sci_port_info) {
2589 .type = PORT_SCI,
2590 .regtype = SCIx_SCI_REGTYPE,
2591 },
20bdcab8
BH		 2592 }, {
2593 /* Terminator */
2594 },
2595};
2596MODULE_DEVICE_TABLE(of, of_sci_match);
2597
2598static struct plat_sci_port *
2599sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2600{
2601 struct device_node *np = pdev->dev.of_node;
2602 const struct of_device_id *match;
2603 const struct sci_port_info *info;
2604 struct plat_sci_port *p;
2605 int id;
2606
2607 if (!IS_ENABLED(CONFIG_OF) || !np)
2608 return NULL;
2609
2610 match = of_match_node(of_sci_match, pdev->dev.of_node);
2611 if (!match)
2612 return NULL;
2613
2614 info = match->data;
2615
2616 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2617 if (!p)
20bdcab8 2618 return NULL;
20bdcab8
BH		 2619
2620 /* Get the line number for the aliases node. */
2621 id = of_alias_get_id(np, "serial");
2622 if (id < 0) {
2623 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2624 return NULL;
2625 }
2626
2627 *dev_id = id;
2628
2629 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2630 p->type = info->type;
2631 p->regtype = info->regtype;
2632 p->scscr = SCSCR_RE | SCSCR_TE;
2633
2634 return p;
2635}
2636
9671f099 2637static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2638 unsigned int index,
2639 struct plat_sci_port *p,
2640 struct sci_port *sciport)
2641{
0ee70712
MD		 2642 int ret;
2643
2644 /* Sanity check */
2645 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2646 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2647 index+1, SCI_NPORTS);
9b971cd2 2648 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2649 return -EINVAL;
0ee70712
MD		 2650 }
2651
1fcc91a6 2652 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2653 if (ret)
2654 return ret;
0ee70712 2655
6dae1421
LP		 2656 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2657 if (ret) {
2658 sci_cleanup_single(sciport);
2659 return ret;
2660 }
2661
2662 return 0;
0ee70712
MD		 2663}
2664
9671f099 2665static int sci_probe(struct platform_device *dev)
1da177e4 2666{
20bdcab8
BH		 2667 struct plat_sci_port *p;
2668 struct sci_port *sp;
2669 unsigned int dev_id;
ecdf8a46 2670 int ret;
d535a230 2671
ecdf8a46
PM		 2672 /*
2673 * If we've come here via earlyprintk initialization, head off to
2674 * the special early probe. We don't have sufficient device state
2675 * to make it beyond this yet.
2676 */
2677 if (is_early_platform_device(dev))
2678 return sci_probe_earlyprintk(dev);
7b6fd3bf 2679
20bdcab8
BH		 2680 if (dev->dev.of_node) {
2681 p = sci_parse_dt(dev, &dev_id);
2682 if (p == NULL)
2683 return -EINVAL;
2684 } else {
2685 p = dev->dev.platform_data;
2686 if (p == NULL) {
2687 dev_err(&dev->dev, "no platform data supplied\n");
2688 return -EINVAL;
2689 }
2690
2691 dev_id = dev->id;
2692 }
2693
2694 sp = &sci_ports[dev_id];
d535a230 2695 platform_set_drvdata(dev, sp);
e552de24 2696
20bdcab8 2697 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2698 if (ret)
6dae1421 2699 return ret;
e552de24 2700
d535a230 2701 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2702
d535a230
PM		 2703 ret = cpufreq_register_notifier(&sp->freq_transition,
2704 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2705 if (unlikely(ret < 0)) {
bf13c9a8 2706 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2707 sci_cleanup_single(sp);
2708 return ret;
2709 }
1da177e4
LT		 2710
2711#ifdef CONFIG_SH_STANDARD_BIOS
2712 sh_bios_gdb_detach();
2713#endif
2714
e108b2ca 2715 return 0;
1da177e4
LT		 2716}
2717
cb876341 2718static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2719{
d535a230 2720 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2721
d535a230
PM		 2722 if (sport)
2723 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2724
e108b2ca
PM		 2725 return 0;
2726}
1da177e4 2727
cb876341 2728static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2729{
d535a230 2730 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2731
d535a230
PM		 2732 if (sport)
2733 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2734
2735 return 0;
2736}
2737
cb876341 2738static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2739
e108b2ca
PM		 2740static struct platform_driver sci_driver = {
2741 .probe = sci_probe,
b9e39c89 2742 .remove = sci_remove,
e108b2ca
PM		 2743 .driver = {
2744 .name = "sh-sci",
6daa79b3 2745 .pm = &sci_dev_pm_ops,
20bdcab8 2746 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2747 },
2748};
2749
2750static int __init sci_init(void)
2751{
2752 int ret;
2753
6c13d5d2 2754 pr_info("%s\n", banner);
e108b2ca 2755
e108b2ca
PM		 2756 ret = uart_register_driver(&sci_uart_driver);
2757 if (likely(ret == 0)) {
2758 ret = platform_driver_register(&sci_driver);
2759 if (unlikely(ret))
2760 uart_unregister_driver(&sci_uart_driver);
2761 }
2762
2763 return ret;
2764}
2765
2766static void __exit sci_exit(void)
2767{
2768 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2769 uart_unregister_driver(&sci_uart_driver);
2770}
2771
7b6fd3bf
MD		 2772#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2773early_platform_init_buffer("earlyprintk", &sci_driver,
2774 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2775#endif
1da177e4
LT		 2776module_init(sci_init);
2777module_exit(sci_exit);
2778
e108b2ca 2779MODULE_LICENSE("GPL");
e169c139 2780MODULE_ALIAS("platform:sh-sci");
7f405f9c 2781MODULE_AUTHOR("Paul Mundt");
f303b364 2782MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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