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serial: sh-sci: Prepare for multiple sampling clock sources
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 5 * Copyright (C) 2015 Glider bvba
3ea6bc3d 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 15 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
0b3d4ef6
PM		 21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
1da177e4
LT		 24
25#undef DEBUG
26
8fb9631c
LP		 27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
1da177e4 35#include <linux/errno.h>
8fb9631c 36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
1da177e4 42#include <linux/notifier.h>
20bdcab8 43#include <linux/of.h>
8fb9631c 44#include <linux/platform_device.h>
5e50d2d6 45#include <linux/pm_runtime.h>
73a19e4c 46#include <linux/scatterlist.h>
8fb9631c
LP		 47#include <linux/serial.h>
48#include <linux/serial_sci.h>
49#include <linux/sh_dma.h>
5a0e3ad6 50#include <linux/slab.h>
8fb9631c
LP		 51#include <linux/string.h>
52#include <linux/sysrq.h>
53#include <linux/timer.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
85f094ec
PM		 56
57#ifdef CONFIG_SUPERH
1da177e4
LT		 58#include <asm/sh_bios.h>
59#endif
60
1da177e4
LT		 61#include "sh-sci.h"
62
89b5c1ab
LP		 63/* Offsets into the sci_port->irqs array */
64enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72};
73
74#define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
f4998e55
GU		 80enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
82 SCI_NUM_CLKS
83};
84
e108b2ca
PM		 85struct sci_port {
86 struct uart_port port;
87
ce6738b6
PM		 88 /* Platform configuration */
89 struct plat_sci_port *cfg;
2e0842a1 90 unsigned int overrun_reg;
75c249fd 91 unsigned int overrun_mask;
3ae988d9 92 unsigned int error_mask;
5da0f468 93 unsigned int error_clear;
ec09c5eb 94 unsigned int sampling_rate;
e4d6f911 95 resource_size_t reg_size;
e108b2ca 96
e108b2ca
PM		 97 /* Break timer */
98 struct timer_list break_timer;
99 int break_flag;
1534a3b3 100
f4998e55
GU		 101 /* Clocks */
102 struct clk *clks[SCI_NUM_CLKS];
103 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 104
1fcc91a6 105 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 106 char *irqstr[SCIx_NR_IRQS];
107
73a19e4c
GL		 108 struct dma_chan *chan_tx;
109 struct dma_chan *chan_rx;
f43dc23d 110
73a19e4c 111#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 112 dma_cookie_t cookie_tx;
113 dma_cookie_t cookie_rx[2];
114 dma_cookie_t active_rx;
79904420
GU		 115 dma_addr_t tx_dma_addr;
116 unsigned int tx_dma_len;
73a19e4c 117 struct scatterlist sg_rx[2];
7b39d901 118 void *rx_buf[2];
73a19e4c 119 size_t buf_len_rx;
73a19e4c 120 struct work_struct work_tx;
73a19e4c 121 struct timer_list rx_timer;
3089f381 122 unsigned int rx_timeout;
73a19e4c 123#endif
e552de24 124
d535a230 125 struct notifier_block freq_transition;
e108b2ca
PM		 126};
127
e108b2ca 128#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 129
e108b2ca
PM		 130static struct sci_port sci_ports[SCI_NPORTS];
131static struct uart_driver sci_uart_driver;
1da177e4 132
e7c98dc7
MT		 133static inline struct sci_port *
134to_sci_port(struct uart_port *uart)
135{
136 return container_of(uart, struct sci_port, port);
137}
138
61a6976b
PM		 139struct plat_sci_reg {
140 u8 offset, size;
141};
142
143/* Helper for invalidating specific entries of an inherited map. */
144#define sci_reg_invalid { .offset = 0, .size = 0 }
145
d3184e68 146static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 147 [SCIx_PROBE_REGTYPE] = {
148 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
149 },
150
151 /*
152 * Common SCI definitions, dependent on the port's regshift
153 * value.
154 */
155 [SCIx_SCI_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = sci_reg_invalid,
163 [SCFDR] = sci_reg_invalid,
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
f303b364 168 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 169 [SCPCR] = sci_reg_invalid,
170 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 171 [SCDL] = sci_reg_invalid,
172 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 173 },
174
175 /*
176 * Common definitions for legacy IrDA ports, dependent on
177 * regshift value.
178 */
179 [SCIx_IRDA_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 [SCFCR] = { 0x06, 8 },
187 [SCFDR] = { 0x07, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
f303b364 192 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 193 [SCPCR] = sci_reg_invalid,
194 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 195 [SCDL] = sci_reg_invalid,
196 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 197 },
198
199 /*
200 * Common SCIFA definitions.
201 */
202 [SCIx_SCIFA_REGTYPE] = {
203 [SCSMR] = { 0x00, 16 },
204 [SCBRR] = { 0x04, 8 },
205 [SCSCR] = { 0x08, 16 },
206 [SCxTDR] = { 0x20, 8 },
207 [SCxSR] = { 0x14, 16 },
208 [SCxRDR] = { 0x24, 8 },
209 [SCFCR] = { 0x18, 16 },
210 [SCFDR] = { 0x1c, 16 },
211 [SCTFDR] = sci_reg_invalid,
212 [SCRFDR] = sci_reg_invalid,
213 [SCSPTR] = sci_reg_invalid,
214 [SCLSR] = sci_reg_invalid,
f303b364 215 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 216 [SCPCR] = { 0x30, 16 },
217 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 218 [SCDL] = sci_reg_invalid,
219 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 220 },
221
222 /*
223 * Common SCIFB definitions.
224 */
225 [SCIx_SCIFB_REGTYPE] = {
226 [SCSMR] = { 0x00, 16 },
227 [SCBRR] = { 0x04, 8 },
228 [SCSCR] = { 0x08, 16 },
229 [SCxTDR] = { 0x40, 8 },
230 [SCxSR] = { 0x14, 16 },
231 [SCxRDR] = { 0x60, 8 },
232 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 233 [SCFDR] = sci_reg_invalid,
234 [SCTFDR] = { 0x38, 16 },
235 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 236 [SCSPTR] = sci_reg_invalid,
237 [SCLSR] = sci_reg_invalid,
f303b364 238 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 239 [SCPCR] = { 0x30, 16 },
240 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 241 [SCDL] = sci_reg_invalid,
242 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 243 },
244
3af1f8a4
PE		 245 /*
246 * Common SH-2(A) SCIF definitions for ports with FIFO data
247 * count registers.
248 */
249 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x0c, 8 },
254 [SCxSR] = { 0x10, 16 },
255 [SCxRDR] = { 0x14, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCFDR] = { 0x1c, 16 },
258 [SCTFDR] = sci_reg_invalid,
259 [SCRFDR] = sci_reg_invalid,
260 [SCSPTR] = { 0x20, 16 },
261 [SCLSR] = { 0x24, 16 },
f303b364 262 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 263 [SCPCR] = sci_reg_invalid,
264 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 265 [SCDL] = sci_reg_invalid,
266 [SCCKS] = sci_reg_invalid,
3af1f8a4
PE		 267 },
268
61a6976b
PM		 269 /*
270 * Common SH-3 SCIF definitions.
271 */
272 [SCIx_SH3_SCIF_REGTYPE] = {
273 [SCSMR] = { 0x00, 8 },
274 [SCBRR] = { 0x02, 8 },
275 [SCSCR] = { 0x04, 8 },
276 [SCxTDR] = { 0x06, 8 },
277 [SCxSR] = { 0x08, 16 },
278 [SCxRDR] = { 0x0a, 8 },
279 [SCFCR] = { 0x0c, 8 },
280 [SCFDR] = { 0x0e, 16 },
281 [SCTFDR] = sci_reg_invalid,
282 [SCRFDR] = sci_reg_invalid,
283 [SCSPTR] = sci_reg_invalid,
284 [SCLSR] = sci_reg_invalid,
f303b364 285 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 286 [SCPCR] = sci_reg_invalid,
287 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 288 [SCDL] = sci_reg_invalid,
289 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 290 },
291
292 /*
293 * Common SH-4(A) SCIF(B) definitions.
294 */
295 [SCIx_SH4_SCIF_REGTYPE] = {
296 [SCSMR] = { 0x00, 16 },
297 [SCBRR] = { 0x04, 8 },
298 [SCSCR] = { 0x08, 16 },
299 [SCxTDR] = { 0x0c, 8 },
300 [SCxSR] = { 0x10, 16 },
301 [SCxRDR] = { 0x14, 8 },
302 [SCFCR] = { 0x18, 16 },
303 [SCFDR] = { 0x1c, 16 },
304 [SCTFDR] = sci_reg_invalid,
305 [SCRFDR] = sci_reg_invalid,
306 [SCSPTR] = { 0x20, 16 },
307 [SCLSR] = { 0x24, 16 },
f303b364 308 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 309 [SCPCR] = sci_reg_invalid,
310 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 311 [SCDL] = sci_reg_invalid,
312 [SCCKS] = sci_reg_invalid,
313 },
314
315 /*
316 * Common SCIF definitions for ports with a Baud Rate Generator for
317 * External Clock (BRG).
318 */
319 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
320 [SCSMR] = { 0x00, 16 },
321 [SCBRR] = { 0x04, 8 },
322 [SCSCR] = { 0x08, 16 },
323 [SCxTDR] = { 0x0c, 8 },
324 [SCxSR] = { 0x10, 16 },
325 [SCxRDR] = { 0x14, 8 },
326 [SCFCR] = { 0x18, 16 },
327 [SCFDR] = { 0x1c, 16 },
328 [SCTFDR] = sci_reg_invalid,
329 [SCRFDR] = sci_reg_invalid,
330 [SCSPTR] = { 0x20, 16 },
331 [SCLSR] = { 0x24, 16 },
332 [HSSRR] = sci_reg_invalid,
333 [SCPCR] = sci_reg_invalid,
334 [SCPDR] = sci_reg_invalid,
335 [SCDL] = { 0x30, 16 },
336 [SCCKS] = { 0x34, 16 },
f303b364
UH		 337 },
338
339 /*
340 * Common HSCIF definitions.
341 */
342 [SCIx_HSCIF_REGTYPE] = {
343 [SCSMR] = { 0x00, 16 },
344 [SCBRR] = { 0x04, 8 },
345 [SCSCR] = { 0x08, 16 },
346 [SCxTDR] = { 0x0c, 8 },
347 [SCxSR] = { 0x10, 16 },
348 [SCxRDR] = { 0x14, 8 },
349 [SCFCR] = { 0x18, 16 },
350 [SCFDR] = { 0x1c, 16 },
351 [SCTFDR] = sci_reg_invalid,
352 [SCRFDR] = sci_reg_invalid,
353 [SCSPTR] = { 0x20, 16 },
354 [SCLSR] = { 0x24, 16 },
355 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 356 [SCPCR] = sci_reg_invalid,
357 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 358 [SCDL] = { 0x30, 16 },
359 [SCCKS] = { 0x34, 16 },
61a6976b
PM		 360 },
361
362 /*
363 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
364 * register.
365 */
366 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCTFDR] = sci_reg_invalid,
376 [SCRFDR] = sci_reg_invalid,
377 [SCSPTR] = sci_reg_invalid,
378 [SCLSR] = { 0x24, 16 },
f303b364 379 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 380 [SCPCR] = sci_reg_invalid,
381 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 382 [SCDL] = sci_reg_invalid,
383 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 384 },
385
386 /*
387 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
388 * count registers.
389 */
390 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
391 [SCSMR] = { 0x00, 16 },
392 [SCBRR] = { 0x04, 8 },
393 [SCSCR] = { 0x08, 16 },
394 [SCxTDR] = { 0x0c, 8 },
395 [SCxSR] = { 0x10, 16 },
396 [SCxRDR] = { 0x14, 8 },
397 [SCFCR] = { 0x18, 16 },
398 [SCFDR] = { 0x1c, 16 },
399 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
400 [SCRFDR] = { 0x20, 16 },
401 [SCSPTR] = { 0x24, 16 },
402 [SCLSR] = { 0x28, 16 },
f303b364 403 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 404 [SCPCR] = sci_reg_invalid,
405 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 406 [SCDL] = sci_reg_invalid,
407 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 408 },
409
410 /*
411 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
412 * registers.
413 */
414 [SCIx_SH7705_SCIF_REGTYPE] = {
415 [SCSMR] = { 0x00, 16 },
416 [SCBRR] = { 0x04, 8 },
417 [SCSCR] = { 0x08, 16 },
418 [SCxTDR] = { 0x20, 8 },
419 [SCxSR] = { 0x14, 16 },
420 [SCxRDR] = { 0x24, 8 },
421 [SCFCR] = { 0x18, 16 },
422 [SCFDR] = { 0x1c, 16 },
423 [SCTFDR] = sci_reg_invalid,
424 [SCRFDR] = sci_reg_invalid,
425 [SCSPTR] = sci_reg_invalid,
426 [SCLSR] = sci_reg_invalid,
f303b364 427 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 428 [SCPCR] = sci_reg_invalid,
429 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 430 [SCDL] = sci_reg_invalid,
431 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 432 },
433};
434
72b294cf
PM		 435#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
436
61a6976b
PM		 437/*
438 * The "offset" here is rather misleading, in that it refers to an enum
439 * value relative to the port mapping rather than the fixed offset
440 * itself, which needs to be manually retrieved from the platform's
441 * register map for the given port.
442 */
443static unsigned int sci_serial_in(struct uart_port *p, int offset)
444{
d3184e68 445 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 446
447 if (reg->size == 8)
448 return ioread8(p->membase + (reg->offset << p->regshift));
449 else if (reg->size == 16)
450 return ioread16(p->membase + (reg->offset << p->regshift));
451 else
452 WARN(1, "Invalid register access\n");
453
454 return 0;
455}
456
457static void sci_serial_out(struct uart_port *p, int offset, int value)
458{
d3184e68 459 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 460
461 if (reg->size == 8)
462 iowrite8(value, p->membase + (reg->offset << p->regshift));
463 else if (reg->size == 16)
464 iowrite16(value, p->membase + (reg->offset << p->regshift));
465 else
466 WARN(1, "Invalid register access\n");
467}
468
61a6976b
PM		 469static int sci_probe_regmap(struct plat_sci_port *cfg)
470{
471 switch (cfg->type) {
472 case PORT_SCI:
473 cfg->regtype = SCIx_SCI_REGTYPE;
474 break;
475 case PORT_IRDA:
476 cfg->regtype = SCIx_IRDA_REGTYPE;
477 break;
478 case PORT_SCIFA:
479 cfg->regtype = SCIx_SCIFA_REGTYPE;
480 break;
481 case PORT_SCIFB:
482 cfg->regtype = SCIx_SCIFB_REGTYPE;
483 break;
484 case PORT_SCIF:
485 /*
486 * The SH-4 is a bit of a misnomer here, although that's
487 * where this particular port layout originated. This
488 * configuration (or some slight variation thereof)
489 * remains the dominant model for all SCIFs.
490 */
491 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
492 break;
f303b364
UH		 493 case PORT_HSCIF:
494 cfg->regtype = SCIx_HSCIF_REGTYPE;
495 break;
61a6976b 496 default:
6c13d5d2 497 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 498 return -EINVAL;
499 }
500
501 return 0;
502}
503
23241d43
PM		 504static void sci_port_enable(struct sci_port *sci_port)
505{
f4998e55
GU		 506 unsigned int i;
507
23241d43
PM		 508 if (!sci_port->port.dev)
509 return;
510
511 pm_runtime_get_sync(sci_port->port.dev);
512
f4998e55
GU		 513 for (i = 0; i < SCI_NUM_CLKS; i++) {
514 clk_prepare_enable(sci_port->clks[i]);
515 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
516 }
517 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 518}
519
520static void sci_port_disable(struct sci_port *sci_port)
521{
f4998e55
GU		 522 unsigned int i;
523
23241d43
PM		 524 if (!sci_port->port.dev)
525 return;
526
caec7038
LP		 527 /* Cancel the break timer to ensure that the timer handler will not try
528 * to access the hardware with clocks and power disabled. Reset the
529 * break flag to make the break debouncing state machine ready for the
530 * next break.
531 */
532 del_timer_sync(&sci_port->break_timer);
533 sci_port->break_flag = 0;
534
f4998e55
GU		 535 for (i = SCI_NUM_CLKS; i-- > 0; )
536 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 537
538 pm_runtime_put_sync(sci_port->port.dev);
539}
540
e1910fcd
GU		 541static inline unsigned long port_rx_irq_mask(struct uart_port *port)
542{
543 /*
544 * Not all ports (such as SCIFA) will support REIE. Rather than
545 * special-casing the port type, we check the port initialization
546 * IRQ enable mask to see whether the IRQ is desired at all. If
547 * it's unset, it's logically inferred that there's no point in
548 * testing for it.
549 */
550 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
551}
552
553static void sci_start_tx(struct uart_port *port)
554{
555 struct sci_port *s = to_sci_port(port);
556 unsigned short ctrl;
557
558#ifdef CONFIG_SERIAL_SH_SCI_DMA
559 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
560 u16 new, scr = serial_port_in(port, SCSCR);
561 if (s->chan_tx)
562 new = scr | SCSCR_TDRQE;
563 else
564 new = scr & ~SCSCR_TDRQE;
565 if (new != scr)
566 serial_port_out(port, SCSCR, new);
567 }
568
569 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
570 dma_submit_error(s->cookie_tx)) {
571 s->cookie_tx = 0;
572 schedule_work(&s->work_tx);
573 }
574#endif
575
576 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
577 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
578 ctrl = serial_port_in(port, SCSCR);
579 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
580 }
581}
582
583static void sci_stop_tx(struct uart_port *port)
584{
585 unsigned short ctrl;
586
587 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
588 ctrl = serial_port_in(port, SCSCR);
589
590 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
591 ctrl &= ~SCSCR_TDRQE;
592
593 ctrl &= ~SCSCR_TIE;
594
595 serial_port_out(port, SCSCR, ctrl);
596}
597
598static void sci_start_rx(struct uart_port *port)
599{
600 unsigned short ctrl;
601
602 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
603
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
606
607 serial_port_out(port, SCSCR, ctrl);
608}
609
610static void sci_stop_rx(struct uart_port *port)
611{
612 unsigned short ctrl;
613
614 ctrl = serial_port_in(port, SCSCR);
615
616 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
617 ctrl &= ~SCSCR_RDRQE;
618
619 ctrl &= ~port_rx_irq_mask(port);
620
621 serial_port_out(port, SCSCR, ctrl);
622}
623
a1b5b43f
GU		 624static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
625{
626 if (port->type == PORT_SCI) {
627 /* Just store the mask */
628 serial_port_out(port, SCxSR, mask);
629 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
630 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
631 /* Only clear the status bits we want to clear */
632 serial_port_out(port, SCxSR,
633 serial_port_in(port, SCxSR) & mask);
634 } else {
635 /* Store the mask, clear parity/framing errors */
636 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
637 }
638}
639
07d2a1a1 640#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 641
642#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 643static int sci_poll_get_char(struct uart_port *port)
1da177e4 644{
1da177e4
LT		 645 unsigned short status;
646 int c;
647
e108b2ca 648 do {
b12bb29f 649 status = serial_port_in(port, SCxSR);
1da177e4 650 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 651 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 652 continue;
653 }
3f255eb3
JW		 654 break;
655 } while (1);
656
657 if (!(status & SCxSR_RDxF(port)))
658 return NO_POLL_CHAR;
07d2a1a1 659
b12bb29f 660 c = serial_port_in(port, SCxRDR);
07d2a1a1 661
e7c98dc7 662 /* Dummy read */
b12bb29f 663 serial_port_in(port, SCxSR);
a1b5b43f 664 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 665
666 return c;
667}
1f6fd5c9 668#endif
1da177e4 669
07d2a1a1 670static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 671{
1da177e4
LT		 672 unsigned short status;
673
1da177e4 674 do {
b12bb29f 675 status = serial_port_in(port, SCxSR);
1da177e4
LT		 676 } while (!(status & SCxSR_TDxE(port)));
677
b12bb29f 678 serial_port_out(port, SCxTDR, c);
a1b5b43f 679 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 680}
07d2a1a1 681#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 682
61a6976b 683static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 684{
61a6976b 685 struct sci_port *s = to_sci_port(port);
d3184e68 686 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 687
61a6976b
PM		 688 /*
689 * Use port-specific handler if provided.
690 */
691 if (s->cfg->ops && s->cfg->ops->init_pins) {
692 s->cfg->ops->init_pins(port, cflag);
693 return;
1da177e4 694 }
41504c39 695
61a6976b
PM		 696 /*
697 * For the generic path SCSPTR is necessary. Bail out if that's
698 * unavailable, too.
699 */
700 if (!reg->size)
701 return;
41504c39 702
faf02f8f
PM		 703 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
704 ((!(cflag & CRTSCTS)))) {
705 unsigned short status;
706
b12bb29f 707 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 708 status &= ~SCSPTR_CTSIO;
709 status |= SCSPTR_RTSIO;
b12bb29f 710 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 711 }
d5701647 712}
e108b2ca 713
72b294cf 714static int sci_txfill(struct uart_port *port)
e108b2ca 715{
d3184e68 716 const struct plat_sci_reg *reg;
e108b2ca 717
72b294cf
PM		 718 reg = sci_getreg(port, SCTFDR);
719 if (reg->size)
63f7ad11 720 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 721
72b294cf
PM		 722 reg = sci_getreg(port, SCFDR);
723 if (reg->size)
b12bb29f 724 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 725
b12bb29f 726 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 727}
728
73a19e4c
GL		 729static int sci_txroom(struct uart_port *port)
730{
72b294cf 731 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 732}
733
734static int sci_rxfill(struct uart_port *port)
e108b2ca 735{
d3184e68 736 const struct plat_sci_reg *reg;
72b294cf
PM		 737
738 reg = sci_getreg(port, SCRFDR);
739 if (reg->size)
63f7ad11 740 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 741
742 reg = sci_getreg(port, SCFDR);
743 if (reg->size)
b12bb29f 744 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 745
b12bb29f 746 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 747}
748
514820eb
PM		 749/*
750 * SCI helper for checking the state of the muxed port/RXD pins.
751 */
752static inline int sci_rxd_in(struct uart_port *port)
753{
754 struct sci_port *s = to_sci_port(port);
755
756 if (s->cfg->port_reg <= 0)
757 return 1;
758
0dd4d5cb 759 /* Cast for ARM damage */
e2afca69 760 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 761}
762
1da177e4
LT		 763/* ********************************************************************** *
764 * the interrupt related routines *
765 * ********************************************************************** */
766
767static void sci_transmit_chars(struct uart_port *port)
768{
ebd2c8f6 769 struct circ_buf *xmit = &port->state->xmit;
1da177e4 770 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 771 unsigned short status;
772 unsigned short ctrl;
e108b2ca 773 int count;
1da177e4 774
b12bb29f 775 status = serial_port_in(port, SCxSR);
1da177e4 776 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 777 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 778 if (uart_circ_empty(xmit))
8e698614 779 ctrl &= ~SCSCR_TIE;
e7c98dc7 780 else
8e698614 781 ctrl |= SCSCR_TIE;
b12bb29f 782 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 783 return;
784 }
785
72b294cf 786 count = sci_txroom(port);
1da177e4
LT		 787
788 do {
789 unsigned char c;
790
791 if (port->x_char) {
792 c = port->x_char;
793 port->x_char = 0;
794 } else if (!uart_circ_empty(xmit) && !stopped) {
795 c = xmit->buf[xmit->tail];
796 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
797 } else {
798 break;
799 }
800
b12bb29f 801 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 802
803 port->icount.tx++;
804 } while (--count > 0);
805
a1b5b43f 806 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 807
808 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
809 uart_write_wakeup(port);
810 if (uart_circ_empty(xmit)) {
b129a8cc 811 sci_stop_tx(port);
1da177e4 812 } else {
b12bb29f 813 ctrl = serial_port_in(port, SCSCR);
1da177e4 814
1a22f08d 815 if (port->type != PORT_SCI) {
b12bb29f 816 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 817 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 818 }
1da177e4 819
8e698614 820 ctrl |= SCSCR_TIE;
b12bb29f 821 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 822 }
823}
824
825/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 826#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 827
94c8b6db 828static void sci_receive_chars(struct uart_port *port)
1da177e4 829{
e7c98dc7 830 struct sci_port *sci_port = to_sci_port(port);
227434f8 831 struct tty_port *tport = &port->state->port;
1da177e4
LT		 832 int i, count, copied = 0;
833 unsigned short status;
33f0f88f 834 unsigned char flag;
1da177e4 835
b12bb29f 836 status = serial_port_in(port, SCxSR);
1da177e4
LT		 837 if (!(status & SCxSR_RDxF(port)))
838 return;
839
840 while (1) {
1da177e4 841 /* Don't copy more bytes than there is room for in the buffer */
227434f8 842 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 843
844 /* If for any reason we can't copy more data, we're done! */
845 if (count == 0)
846 break;
847
848 if (port->type == PORT_SCI) {
b12bb29f 849 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 850 if (uart_handle_sysrq_char(port, c) ||
851 sci_port->break_flag)
1da177e4 852 count = 0;
e7c98dc7 853 else
92a19f9c 854 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 855 } else {
e7c98dc7 856 for (i = 0; i < count; i++) {
b12bb29f 857 char c = serial_port_in(port, SCxRDR);
d97fbbed 858
b12bb29f 859 status = serial_port_in(port, SCxSR);
1da177e4
LT		 860#if defined(CONFIG_CPU_SH3)
861 /* Skip "chars" during break */
e108b2ca 862 if (sci_port->break_flag) {
1da177e4
LT		 863 if ((c == 0) &&
864 (status & SCxSR_FER(port))) {
865 count--; i--;
866 continue;
867 }
e108b2ca 868
1da177e4 869 /* Nonzero => end-of-break */
762c69e3 870 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 871 sci_port->break_flag = 0;
872
1da177e4
LT		 873 if (STEPFN(c)) {
874 count--; i--;
875 continue;
876 }
877 }
878#endif /* CONFIG_CPU_SH3 */
7d12e780 879 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 880 count--; i--;
881 continue;
882 }
883
884 /* Store data and status */
73a19e4c 885 if (status & SCxSR_FER(port)) {
33f0f88f 886 flag = TTY_FRAME;
d97fbbed 887 port->icount.frame++;
762c69e3 888 dev_notice(port->dev, "frame error\n");
73a19e4c 889 } else if (status & SCxSR_PER(port)) {
33f0f88f 890 flag = TTY_PARITY;
d97fbbed 891 port->icount.parity++;
762c69e3 892 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 893 } else
894 flag = TTY_NORMAL;
762c69e3 895
92a19f9c 896 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 897 }
898 }
899
b12bb29f 900 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 902
1da177e4
LT		 903 copied += count;
904 port->icount.rx += count;
905 }
906
907 if (copied) {
908 /* Tell the rest of the system the news. New characters! */
2e124b4a 909 tty_flip_buffer_push(tport);
1da177e4 910 } else {
b12bb29f 911 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 912 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 913 }
914}
915
916#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 917
918/*
919 * The sci generates interrupts during the break,
1da177e4
LT		 920 * 1 per millisecond or so during the break period, for 9600 baud.
921 * So dont bother disabling interrupts.
922 * But dont want more than 1 break event.
923 * Use a kernel timer to periodically poll the rx line until
924 * the break is finished.
925 */
94c8b6db 926static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 927{
bc9b3f5c 928 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 929}
94c8b6db 930
1da177e4
LT		 931/* Ensure that two consecutive samples find the break over. */
932static void sci_break_timer(unsigned long data)
933{
e108b2ca
PM		 934 struct sci_port *port = (struct sci_port *)data;
935
936 if (sci_rxd_in(&port->port) == 0) {
1da177e4 937 port->break_flag = 1;
e108b2ca
PM		 938 sci_schedule_break_timer(port);
939 } else if (port->break_flag == 1) {
1da177e4
LT		 940 /* break is over. */
941 port->break_flag = 2;
e108b2ca
PM		 942 sci_schedule_break_timer(port);
943 } else
944 port->break_flag = 0;
1da177e4
LT		 945}
946
94c8b6db 947static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 948{
949 int copied = 0;
b12bb29f 950 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 951 struct tty_port *tport = &port->state->port;
debf9507 952 struct sci_port *s = to_sci_port(port);
1da177e4 953
3ae988d9 954 /* Handle overruns */
75c249fd 955 if (status & s->overrun_mask) {
3ae988d9 956 port->icount.overrun++;
d97fbbed 957
3ae988d9
LP		 958 /* overrun error */
959 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
960 copied++;
762c69e3 961
9b971cd2 962 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 963 }
964
e108b2ca 965 if (status & SCxSR_FER(port)) {
1da177e4
LT		 966 if (sci_rxd_in(port) == 0) {
967 /* Notify of BREAK */
e7c98dc7 968 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 969
970 if (!sci_port->break_flag) {
d97fbbed
PM		 971 port->icount.brk++;
972
e108b2ca
PM		 973 sci_port->break_flag = 1;
974 sci_schedule_break_timer(sci_port);
975
1da177e4 976 /* Do sysrq handling. */
e108b2ca 977 if (uart_handle_break(port))
1da177e4 978 return 0;
762c69e3
PM		 979
980 dev_dbg(port->dev, "BREAK detected\n");
981
92a19f9c 982 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 983 copied++;
984 }
985
e108b2ca 986 } else {
1da177e4 987 /* frame error */
d97fbbed
PM		 988 port->icount.frame++;
989
92a19f9c 990 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 991 copied++;
762c69e3
PM		 992
993 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 994 }
995 }
996
e108b2ca 997 if (status & SCxSR_PER(port)) {
1da177e4 998 /* parity error */
d97fbbed
PM		 999 port->icount.parity++;
1000
92a19f9c 1001 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 1002 copied++;
762c69e3 1003
9b971cd2 1004 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 1005 }
1006
33f0f88f 1007 if (copied)
2e124b4a 1008 tty_flip_buffer_push(tport);
1da177e4
LT		 1009
1010 return copied;
1011}
1012
94c8b6db 1013static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 1014{
92a19f9c 1015 struct tty_port *tport = &port->state->port;
debf9507 1016 struct sci_port *s = to_sci_port(port);
d3184e68 1017 const struct plat_sci_reg *reg;
2e0842a1 1018 int copied = 0;
75c249fd 1019 u16 status;
d830fa45 1020
2e0842a1 1021 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 1022 if (!reg->size)
d830fa45
PM		 1023 return 0;
1024
2e0842a1 1025 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 1026 if (status & s->overrun_mask) {
1027 status &= ~s->overrun_mask;
2e0842a1 1028 serial_port_out(port, s->overrun_reg, status);
d830fa45 1029
d97fbbed
PM		 1030 port->icount.overrun++;
1031
92a19f9c 1032 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 1033 tty_flip_buffer_push(tport);
d830fa45 1034
51b31f1c 1035 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 1036 copied++;
1037 }
1038
1039 return copied;
1040}
1041
94c8b6db 1042static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 1043{
1044 int copied = 0;
b12bb29f 1045 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 1046 struct tty_port *tport = &port->state->port;
a5660ada 1047 struct sci_port *s = to_sci_port(port);
1da177e4 1048
0b3d4ef6
PM		 1049 if (uart_handle_break(port))
1050 return 0;
1051
b7a76e4b 1052 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 1053#if defined(CONFIG_CPU_SH3)
1054 /* Debounce break */
1055 s->break_flag = 1;
1056#endif
d97fbbed
PM		 1057
1058 port->icount.brk++;
1059
1da177e4 1060 /* Notify of BREAK */
92a19f9c 1061 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1062 copied++;
762c69e3
PM		 1063
1064 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1065 }
1066
33f0f88f 1067 if (copied)
2e124b4a 1068 tty_flip_buffer_push(tport);
e108b2ca 1069
d830fa45
PM		 1070 copied += sci_handle_fifo_overrun(port);
1071
1da177e4
LT		 1072 return copied;
1073}
1074
73a19e4c 1075#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1076static void sci_dma_tx_complete(void *arg)
1077{
1078 struct sci_port *s = arg;
1079 struct uart_port *port = &s->port;
1080 struct circ_buf *xmit = &port->state->xmit;
1081 unsigned long flags;
73a19e4c 1082
e1910fcd 1083 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1084
e1910fcd 1085 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1086
e1910fcd
GU		 1087 xmit->tail += s->tx_dma_len;
1088 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1089
e1910fcd 1090 port->icount.tx += s->tx_dma_len;
1da177e4 1091
e1910fcd
GU		 1092 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1093 uart_write_wakeup(port);
1da177e4 1094
e1910fcd
GU		 1095 if (!uart_circ_empty(xmit)) {
1096 s->cookie_tx = 0;
1097 schedule_work(&s->work_tx);
1098 } else {
1099 s->cookie_tx = -EINVAL;
1100 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1101 u16 ctrl = serial_port_in(port, SCSCR);
1102 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1103 }
1104 }
1da177e4 1105
fd78a76a 1106 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1107}
1108
e1910fcd
GU		 1109/* Locking: called with port lock held */
1110static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1111{
e1910fcd
GU		 1112 struct uart_port *port = &s->port;
1113 struct tty_port *tport = &port->state->port;
1114 int copied;
1da177e4 1115
e1910fcd
GU		 1116 copied = tty_insert_flip_string(tport, buf, count);
1117 if (copied < count) {
1118 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1119 count - copied);
1120 port->icount.buf_overrun++;
1da177e4
LT		 1121 }
1122
e1910fcd 1123 port->icount.rx += copied;
1da177e4 1124
e1910fcd 1125 return copied;
1da177e4
LT		 1126}
1127
e1910fcd 1128static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1129{
e1910fcd 1130 unsigned int i;
1da177e4 1131
e1910fcd
GU		 1132 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1133 if (s->active_rx == s->cookie_rx[i])
1134 return i;
1da177e4 1135
e1910fcd
GU		 1136 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1137 s->active_rx);
1138 return -1;
1da177e4
LT		 1139}
1140
e1910fcd 1141static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1142{
e1910fcd
GU		 1143 struct dma_chan *chan = s->chan_rx;
1144 struct uart_port *port = &s->port;
1145 unsigned long flags;
1146
1147 spin_lock_irqsave(&port->lock, flags);
1148 s->chan_rx = NULL;
1149 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1150 spin_unlock_irqrestore(&port->lock, flags);
1151 dmaengine_terminate_all(chan);
1152 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1153 sg_dma_address(&s->sg_rx[0]));
1154 dma_release_channel(chan);
1155 if (enable_pio)
1156 sci_start_rx(port);
f43dc23d
PM		 1157}
1158
e1910fcd 1159static void sci_dma_rx_complete(void *arg)
1da177e4 1160{
e1910fcd 1161 struct sci_port *s = arg;
1d3db608 1162 struct dma_chan *chan = s->chan_rx;
e1910fcd 1163 struct uart_port *port = &s->port;
67f462b0 1164 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1165 unsigned long flags;
1166 int active, count = 0;
1da177e4 1167
e1910fcd
GU		 1168 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1169 s->active_rx);
cb772fe7 1170
e1910fcd 1171 spin_lock_irqsave(&port->lock, flags);
1da177e4 1172
e1910fcd
GU		 1173 active = sci_dma_rx_find_active(s);
1174 if (active >= 0)
1175 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1176
e1910fcd 1177 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1178
e1910fcd
GU		 1179 if (count)
1180 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1181
67f462b0
GU		 1182 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1183 DMA_DEV_TO_MEM,
1184 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1185 if (!desc)
1186 goto fail;
1187
1188 desc->callback = sci_dma_rx_complete;
1189 desc->callback_param = s;
1190 s->cookie_rx[active] = dmaengine_submit(desc);
1191 if (dma_submit_error(s->cookie_rx[active]))
1192 goto fail;
1193
1194 s->active_rx = s->cookie_rx[!active];
1195
1d3db608
MHF		 1196 dma_async_issue_pending(chan);
1197
67f462b0
GU		 1198 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1199 __func__, s->cookie_rx[active], active, s->active_rx);
1200 spin_unlock_irqrestore(&port->lock, flags);
1201 return;
1202
1203fail:
1204 spin_unlock_irqrestore(&port->lock, flags);
1205 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1206 sci_rx_dma_release(s, true);
1da177e4
LT		 1207}
1208
e1910fcd 1209static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1210{
e1910fcd
GU		 1211 struct dma_chan *chan = s->chan_tx;
1212 struct uart_port *port = &s->port;
e552de24 1213 unsigned long flags;
1da177e4 1214
e1910fcd
GU		 1215 spin_lock_irqsave(&port->lock, flags);
1216 s->chan_tx = NULL;
1217 s->cookie_tx = -EINVAL;
1218 spin_unlock_irqrestore(&port->lock, flags);
1219 dmaengine_terminate_all(chan);
1220 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1221 DMA_TO_DEVICE);
1222 dma_release_channel(chan);
1223 if (enable_pio)
1224 sci_start_tx(port);
1225}
d535a230 1226
e1910fcd
GU		 1227static void sci_submit_rx(struct sci_port *s)
1228{
1229 struct dma_chan *chan = s->chan_rx;
1230 int i;
073e84c9 1231
e1910fcd
GU		 1232 for (i = 0; i < 2; i++) {
1233 struct scatterlist *sg = &s->sg_rx[i];
1234 struct dma_async_tx_descriptor *desc;
1da177e4 1235
e1910fcd
GU		 1236 desc = dmaengine_prep_slave_sg(chan,
1237 sg, 1, DMA_DEV_TO_MEM,
1238 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1239 if (!desc)
1240 goto fail;
501b825d 1241
e1910fcd
GU		 1242 desc->callback = sci_dma_rx_complete;
1243 desc->callback_param = s;
1244 s->cookie_rx[i] = dmaengine_submit(desc);
1245 if (dma_submit_error(s->cookie_rx[i]))
1246 goto fail;
9174fc8f 1247
e1910fcd
GU		 1248 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1249 s->cookie_rx[i], i);
1250 }
9174fc8f 1251
e1910fcd 1252 s->active_rx = s->cookie_rx[0];
9174fc8f 1253
e1910fcd
GU		 1254 dma_async_issue_pending(chan);
1255 return;
9174fc8f 1256
e1910fcd
GU		 1257fail:
1258 if (i)
1259 dmaengine_terminate_all(chan);
1260 for (i = 0; i < 2; i++)
1261 s->cookie_rx[i] = -EINVAL;
1262 s->active_rx = -EINVAL;
1263 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1264 sci_rx_dma_release(s, true);
1265}
9174fc8f 1266
e1910fcd 1267static void work_fn_tx(struct work_struct *work)
1da177e4 1268{
e1910fcd
GU		 1269 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1270 struct dma_async_tx_descriptor *desc;
1271 struct dma_chan *chan = s->chan_tx;
1272 struct uart_port *port = &s->port;
1273 struct circ_buf *xmit = &port->state->xmit;
1274 dma_addr_t buf;
1da177e4 1275
9174fc8f 1276 /*
e1910fcd
GU		 1277 * DMA is idle now.
1278 * Port xmit buffer is already mapped, and it is one page... Just adjust
1279 * offsets and lengths. Since it is a circular buffer, we have to
1280 * transmit till the end, and then the rest. Take the port lock to get a
1281 * consistent xmit buffer state.
9174fc8f 1282 */
e1910fcd
GU		 1283 spin_lock_irq(&port->lock);
1284 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1285 s->tx_dma_len = min_t(unsigned int,
1286 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1287 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1288 spin_unlock_irq(&port->lock);
0e8963de 1289
e1910fcd
GU		 1290 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1291 DMA_MEM_TO_DEV,
1292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1293 if (!desc) {
1294 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1295 /* switch to PIO */
1296 sci_tx_dma_release(s, true);
1297 return;
1298 }
0e8963de 1299
e1910fcd
GU		 1300 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1301 DMA_TO_DEVICE);
1da177e4 1302
e1910fcd
GU		 1303 spin_lock_irq(&port->lock);
1304 desc->callback = sci_dma_tx_complete;
1305 desc->callback_param = s;
1306 spin_unlock_irq(&port->lock);
1307 s->cookie_tx = dmaengine_submit(desc);
1308 if (dma_submit_error(s->cookie_tx)) {
1309 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1310 /* switch to PIO */
1311 sci_tx_dma_release(s, true);
1312 return;
1da177e4 1313 }
1da177e4 1314
e1910fcd
GU		 1315 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1316 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1317
e1910fcd 1318 dma_async_issue_pending(chan);
1da177e4
LT		 1319}
1320
e1910fcd 1321static void rx_timer_fn(unsigned long arg)
1da177e4 1322{
e1910fcd 1323 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1324 struct dma_chan *chan = s->chan_rx;
e1910fcd 1325 struct uart_port *port = &s->port;
67f462b0
GU		 1326 struct dma_tx_state state;
1327 enum dma_status status;
1328 unsigned long flags;
1329 unsigned int read;
1330 int active, count;
1331 u16 scr;
1332
1333 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1334
67f462b0 1335 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0
GU		 1336
1337 active = sci_dma_rx_find_active(s);
1338 if (active < 0) {
1339 spin_unlock_irqrestore(&port->lock, flags);
1340 return;
1341 }
1342
1343 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1344 if (status == DMA_COMPLETE) {
67f462b0
GU		 1345 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1346 s->active_rx, active);
3b963042
MHF		 1347 spin_unlock_irqrestore(&port->lock, flags);
1348
1349 /* Let packet complete handler take care of the packet */
1350 return;
1351 }
67f462b0 1352
e7327c09
MHF		 1353 dmaengine_pause(chan);
1354
1355 /*
1356 * sometimes DMA transfer doesn't stop even if it is stopped and
1357 * data keeps on coming until transaction is complete so check
1358 * for DMA_COMPLETE again
1359 * Let packet complete handler take care of the packet
1360 */
1361 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1362 if (status == DMA_COMPLETE) {
1363 spin_unlock_irqrestore(&port->lock, flags);
1364 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1365 return;
1366 }
1367
67f462b0
GU		 1368 /* Handle incomplete DMA receive */
1369 dmaengine_terminate_all(s->chan_rx);
1370 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1371 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1372 s->active_rx);
1373
1374 if (read) {
1375 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1376 if (count)
1377 tty_flip_buffer_push(&port->state->port);
1378 }
1379
756981be
GU		 1380 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1381 sci_submit_rx(s);
371cfed3
MHF		 1382
1383 /* Direct new serial port interrupts back to CPU */
1384 scr = serial_port_in(port, SCSCR);
1385 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1386 scr &= ~SCSCR_RDRQE;
1387 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1388 }
1389 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1390
1391 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1392}
1393
ff441129
GU		 1394static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1395 enum dma_transfer_direction dir,
1396 unsigned int id)
1397{
1398 dma_cap_mask_t mask;
1399 struct dma_chan *chan;
1400 struct dma_slave_config cfg;
1401 int ret;
1402
1403 dma_cap_zero(mask);
1404 dma_cap_set(DMA_SLAVE, mask);
1405
1406 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1407 (void *)(unsigned long)id, port->dev,
1408 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1409 if (!chan) {
1410 dev_warn(port->dev,
1411 "dma_request_slave_channel_compat failed\n");
1412 return NULL;
1413 }
1414
1415 memset(&cfg, 0, sizeof(cfg));
1416 cfg.direction = dir;
1417 if (dir == DMA_MEM_TO_DEV) {
1418 cfg.dst_addr = port->mapbase +
1419 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1420 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1421 } else {
1422 cfg.src_addr = port->mapbase +
1423 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1424 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1425 }
1426
1427 ret = dmaengine_slave_config(chan, &cfg);
1428 if (ret) {
1429 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1430 dma_release_channel(chan);
1431 return NULL;
1432 }
1433
1434 return chan;
1435}
1436
e1910fcd 1437static void sci_request_dma(struct uart_port *port)
73a19e4c 1438{
e1910fcd 1439 struct sci_port *s = to_sci_port(port);
e1910fcd 1440 struct dma_chan *chan;
73a19e4c 1441
e1910fcd 1442 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1443
ff441129
GU		 1444 if (!port->dev->of_node &&
1445 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
e1910fcd 1446 return;
73a19e4c 1447
e1910fcd 1448 s->cookie_tx = -EINVAL;
ff441129 1449 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
e1910fcd
GU		 1450 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1451 if (chan) {
1452 s->chan_tx = chan;
1453 /* UART circular tx buffer is an aligned page. */
1454 s->tx_dma_addr = dma_map_single(chan->device->dev,
1455 port->state->xmit.buf,
1456 UART_XMIT_SIZE,
1457 DMA_TO_DEVICE);
1458 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1459 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1460 dma_release_channel(chan);
1461 s->chan_tx = NULL;
1462 } else {
1463 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1464 __func__, UART_XMIT_SIZE,
1465 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1466 }
e1910fcd
GU		 1467
1468 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1469 }
1470
ff441129 1471 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
e1910fcd
GU		 1472 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1473 if (chan) {
1474 unsigned int i;
1475 dma_addr_t dma;
1476 void *buf;
73a19e4c 1477
e1910fcd 1478 s->chan_rx = chan;
73a19e4c 1479
e1910fcd
GU		 1480 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1481 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1482 &dma, GFP_KERNEL);
1483 if (!buf) {
1484 dev_warn(port->dev,
1485 "Failed to allocate Rx dma buffer, using PIO\n");
1486 dma_release_channel(chan);
1487 s->chan_rx = NULL;
e1910fcd
GU		 1488 return;
1489 }
73a19e4c 1490
e1910fcd
GU		 1491 for (i = 0; i < 2; i++) {
1492 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1493
e1910fcd
GU		 1494 sg_init_table(sg, 1);
1495 s->rx_buf[i] = buf;
1496 sg_dma_address(sg) = dma;
1497 sg->length = s->buf_len_rx;
0533502d 1498
e1910fcd
GU		 1499 buf += s->buf_len_rx;
1500 dma += s->buf_len_rx;
1501 }
1502
e1910fcd
GU		 1503 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1504
756981be
GU		 1505 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1506 sci_submit_rx(s);
e1910fcd 1507 }
0533502d
GU		 1508}
1509
e1910fcd 1510static void sci_free_dma(struct uart_port *port)
73a19e4c 1511{
e1910fcd 1512 struct sci_port *s = to_sci_port(port);
73a19e4c 1513
e1910fcd
GU		 1514 if (s->chan_tx)
1515 sci_tx_dma_release(s, false);
1516 if (s->chan_rx)
1517 sci_rx_dma_release(s, false);
1518}
1519#else
1520static inline void sci_request_dma(struct uart_port *port)
1521{
1522}
73a19e4c 1523
e1910fcd
GU		 1524static inline void sci_free_dma(struct uart_port *port)
1525{
1526}
1527#endif
73a19e4c 1528
e1910fcd
GU		 1529static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1530{
1531#ifdef CONFIG_SERIAL_SH_SCI_DMA
1532 struct uart_port *port = ptr;
1533 struct sci_port *s = to_sci_port(port);
73a19e4c 1534
e1910fcd
GU		 1535 if (s->chan_rx) {
1536 u16 scr = serial_port_in(port, SCSCR);
1537 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1538
e1910fcd
GU		 1539 /* Disable future Rx interrupts */
1540 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1541 disable_irq_nosync(irq);
1542 scr |= SCSCR_RDRQE;
1543 } else {
1544 scr &= ~SCSCR_RIE;
756981be 1545 sci_submit_rx(s);
e1910fcd
GU		 1546 }
1547 serial_port_out(port, SCSCR, scr);
1548 /* Clear current interrupt */
1549 serial_port_out(port, SCxSR,
1550 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1551 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1552 jiffies, s->rx_timeout);
1553 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1554
e1910fcd
GU		 1555 return IRQ_HANDLED;
1556 }
1557#endif
73a19e4c 1558
e1910fcd
GU		 1559 /* I think sci_receive_chars has to be called irrespective
1560 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1561 * to be disabled?
1562 */
1563 sci_receive_chars(ptr);
1564
1565 return IRQ_HANDLED;
73a19e4c
GL		 1566}
1567
e1910fcd 1568static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1569{
e1910fcd 1570 struct uart_port *port = ptr;
04928b79 1571 unsigned long flags;
73a19e4c 1572
04928b79 1573 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1574 sci_transmit_chars(port);
04928b79 1575 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1576
1577 return IRQ_HANDLED;
73a19e4c
GL		 1578}
1579
e1910fcd 1580static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1581{
e1910fcd
GU		 1582 struct uart_port *port = ptr;
1583 struct sci_port *s = to_sci_port(port);
73a19e4c 1584
e1910fcd
GU		 1585 /* Handle errors */
1586 if (port->type == PORT_SCI) {
1587 if (sci_handle_errors(port)) {
1588 /* discard character in rx buffer */
1589 serial_port_in(port, SCxSR);
1590 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1591 }
1592 } else {
1593 sci_handle_fifo_overrun(port);
1594 if (!s->chan_rx)
1595 sci_receive_chars(ptr);
1596 }
1597
1598 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1599
1600 /* Kick the transmission */
1601 if (!s->chan_tx)
1602 sci_tx_interrupt(irq, ptr);
1603
1604 return IRQ_HANDLED;
73a19e4c
GL		 1605}
1606
e1910fcd 1607static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1608{
e1910fcd 1609 struct uart_port *port = ptr;
73a19e4c 1610
e1910fcd
GU		 1611 /* Handle BREAKs */
1612 sci_handle_breaks(port);
1613 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1614
e1910fcd
GU		 1615 return IRQ_HANDLED;
1616}
73a19e4c 1617
e1910fcd
GU		 1618static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1619{
1620 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1621 struct uart_port *port = ptr;
1622 struct sci_port *s = to_sci_port(port);
1623 irqreturn_t ret = IRQ_NONE;
73a19e4c 1624
e1910fcd
GU		 1625 ssr_status = serial_port_in(port, SCxSR);
1626 scr_status = serial_port_in(port, SCSCR);
1627 if (s->overrun_reg == SCxSR)
1628 orer_status = ssr_status;
1629 else {
1630 if (sci_getreg(port, s->overrun_reg)->size)
1631 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1632 }
1633
e1910fcd 1634 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1635
e1910fcd
GU		 1636 /* Tx Interrupt */
1637 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1638 !s->chan_tx)
1639 ret = sci_tx_interrupt(irq, ptr);
658daa95 1640
e1910fcd
GU		 1641 /*
1642 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1643 * DR flags
1644 */
1645 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1646 (scr_status & SCSCR_RIE))
1647 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1648
e1910fcd
GU		 1649 /* Error Interrupt */
1650 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1651 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1652
e1910fcd
GU		 1653 /* Break Interrupt */
1654 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1655 ret = sci_br_interrupt(irq, ptr);
1656
1657 /* Overrun Interrupt */
1658 if (orer_status & s->overrun_mask) {
1659 sci_handle_fifo_overrun(port);
1660 ret = IRQ_HANDLED;
73a19e4c 1661 }
73a19e4c 1662
e1910fcd
GU		 1663 return ret;
1664}
73a19e4c 1665
e1910fcd
GU		 1666/*
1667 * Here we define a transition notifier so that we can update all of our
1668 * ports' baud rate when the peripheral clock changes.
1669 */
1670static int sci_notifier(struct notifier_block *self,
1671 unsigned long phase, void *p)
1672{
1673 struct sci_port *sci_port;
1674 unsigned long flags;
f4998e55 1675 unsigned int i;
73a19e4c 1676
e1910fcd 1677 sci_port = container_of(self, struct sci_port, freq_transition);
73a19e4c 1678
e1910fcd
GU		 1679 if (phase == CPUFREQ_POSTCHANGE) {
1680 struct uart_port *port = &sci_port->port;
73a19e4c 1681
e1910fcd 1682 spin_lock_irqsave(&port->lock, flags);
f4998e55
GU		 1683 for (i = 0; i < SCI_NUM_CLKS; i++)
1684 sci_port->clk_rates[i] =
1685 clk_get_rate(sci_port->clks[i]);
e1910fcd 1686 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1687 }
1688
e1910fcd
GU		 1689 return NOTIFY_OK;
1690}
73a19e4c 1691
e1910fcd
GU		 1692static const struct sci_irq_desc {
1693 const char *desc;
1694 irq_handler_t handler;
1695} sci_irq_desc[] = {
1696 /*
1697 * Split out handlers, the default case.
1698 */
1699 [SCIx_ERI_IRQ] = {
1700 .desc = "rx err",
1701 .handler = sci_er_interrupt,
1702 },
3089f381 1703
e1910fcd
GU		 1704 [SCIx_RXI_IRQ] = {
1705 .desc = "rx full",
1706 .handler = sci_rx_interrupt,
1707 },
47aceb92 1708
e1910fcd
GU		 1709 [SCIx_TXI_IRQ] = {
1710 .desc = "tx empty",
1711 .handler = sci_tx_interrupt,
1712 },
73a19e4c 1713
e1910fcd
GU		 1714 [SCIx_BRI_IRQ] = {
1715 .desc = "break",
1716 .handler = sci_br_interrupt,
1717 },
73a19e4c
GL		 1718
1719 /*
e1910fcd 1720 * Special muxed handler.
73a19e4c 1721 */
e1910fcd
GU		 1722 [SCIx_MUX_IRQ] = {
1723 .desc = "mux",
1724 .handler = sci_mpxed_interrupt,
1725 },
1726};
73a19e4c 1727
e1910fcd
GU		 1728static int sci_request_irq(struct sci_port *port)
1729{
1730 struct uart_port *up = &port->port;
1731 int i, j, ret = 0;
73a19e4c 1732
e1910fcd
GU		 1733 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1734 const struct sci_irq_desc *desc;
1735 int irq;
73a19e4c 1736
e1910fcd
GU		 1737 if (SCIx_IRQ_IS_MUXED(port)) {
1738 i = SCIx_MUX_IRQ;
1739 irq = up->irq;
1740 } else {
1741 irq = port->irqs[i];
1742
1743 /*
1744 * Certain port types won't support all of the
1745 * available interrupt sources.
1746 */
1747 if (unlikely(irq < 0))
1748 continue;
1749 }
1750
1751 desc = sci_irq_desc + i;
1752 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1753 dev_name(up->dev), desc->desc);
1754 if (!port->irqstr[j])
1755 goto out_nomem;
1756
1757 ret = request_irq(irq, desc->handler, up->irqflags,
1758 port->irqstr[j], port);
1759 if (unlikely(ret)) {
1760 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1761 goto out_noirq;
1762 }
73a19e4c
GL		 1763 }
1764
e1910fcd 1765 return 0;
1da177e4 1766
e1910fcd
GU		 1767out_noirq:
1768 while (--i >= 0)
1769 free_irq(port->irqs[i], port);
f43dc23d 1770
e1910fcd
GU		 1771out_nomem:
1772 while (--j >= 0)
1773 kfree(port->irqstr[j]);
f43dc23d 1774
e1910fcd 1775 return ret;
1da177e4
LT		 1776}
1777
e1910fcd 1778static void sci_free_irq(struct sci_port *port)
1da177e4 1779{
e1910fcd 1780 int i;
1da177e4 1781
e1910fcd
GU		 1782 /*
1783 * Intentionally in reverse order so we iterate over the muxed
1784 * IRQ first.
1785 */
1786 for (i = 0; i < SCIx_NR_IRQS; i++) {
1787 int irq = port->irqs[i];
f43dc23d 1788
e1910fcd
GU		 1789 /*
1790 * Certain port types won't support all of the available
1791 * interrupt sources.
1792 */
1793 if (unlikely(irq < 0))
1794 continue;
f43dc23d 1795
e1910fcd
GU		 1796 free_irq(port->irqs[i], port);
1797 kfree(port->irqstr[i]);
f43dc23d 1798
e1910fcd
GU		 1799 if (SCIx_IRQ_IS_MUXED(port)) {
1800 /* If there's only one IRQ, we're done. */
1801 return;
1802 }
1803 }
1da177e4
LT		 1804}
1805
e1910fcd 1806static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1807{
e1910fcd
GU		 1808 unsigned short status = serial_port_in(port, SCxSR);
1809 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1810
e1910fcd 1811 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1812}
1813
e1910fcd
GU		 1814/*
1815 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1816 * CTS/RTS is supported in hardware by at least one port and controlled
1817 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1818 * handled via the ->init_pins() op, which is a bit of a one-way street,
1819 * lacking any ability to defer pin control -- this will later be
1820 * converted over to the GPIO framework).
1821 *
1822 * Other modes (such as loopback) are supported generically on certain
1823 * port types, but not others. For these it's sufficient to test for the
1824 * existence of the support register and simply ignore the port type.
1825 */
1826static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1827{
e1910fcd
GU		 1828 if (mctrl & TIOCM_LOOP) {
1829 const struct plat_sci_reg *reg;
f43dc23d 1830
e1910fcd
GU		 1831 /*
1832 * Standard loopback mode for SCFCR ports.
1833 */
1834 reg = sci_getreg(port, SCFCR);
1835 if (reg->size)
1836 serial_port_out(port, SCFCR,
1837 serial_port_in(port, SCFCR) |
1838 SCFCR_LOOP);
1839 }
1840}
f43dc23d 1841
e1910fcd
GU		 1842static unsigned int sci_get_mctrl(struct uart_port *port)
1843{
1844 /*
1845 * CTS/RTS is handled in hardware when supported, while nothing
1846 * else is wired up. Keep it simple and simply assert DSR/CAR.
1847 */
1848 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1849}
1850
1da177e4
LT		 1851static void sci_break_ctl(struct uart_port *port, int break_state)
1852{
bbb4ce50 1853 struct sci_port *s = to_sci_port(port);
d3184e68 1854 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1855 unsigned short scscr, scsptr;
1856
a4e02f6d
SY		 1857 /* check wheter the port has SCSPTR */
1858 if (!reg->size) {
bbb4ce50
SY		 1859 /*
1860 * Not supported by hardware. Most parts couple break and rx
1861 * interrupts together, with break detection always enabled.
1862 */
a4e02f6d 1863 return;
bbb4ce50 1864 }
a4e02f6d
SY		 1865
1866 scsptr = serial_port_in(port, SCSPTR);
1867 scscr = serial_port_in(port, SCSCR);
1868
1869 if (break_state == -1) {
1870 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1871 scscr &= ~SCSCR_TE;
1872 } else {
1873 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1874 scscr |= SCSCR_TE;
1875 }
1876
1877 serial_port_out(port, SCSPTR, scsptr);
1878 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1879}
1880
1881static int sci_startup(struct uart_port *port)
1882{
a5660ada 1883 struct sci_port *s = to_sci_port(port);
33b48e16 1884 unsigned long flags;
073e84c9 1885 int ret;
1da177e4 1886
73a19e4c
GL		 1887 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1888
073e84c9
PM		 1889 ret = sci_request_irq(s);
1890 if (unlikely(ret < 0))
1891 return ret;
1892
73a19e4c 1893 sci_request_dma(port);
073e84c9 1894
33b48e16 1895 spin_lock_irqsave(&port->lock, flags);
d656901b 1896 sci_start_tx(port);
73a19e4c 1897 sci_start_rx(port);
33b48e16 1898 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1899
1900 return 0;
1901}
1902
1903static void sci_shutdown(struct uart_port *port)
1904{
a5660ada 1905 struct sci_port *s = to_sci_port(port);
33b48e16 1906 unsigned long flags;
1da177e4 1907
73a19e4c
GL		 1908 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1909
33b48e16 1910 spin_lock_irqsave(&port->lock, flags);
1da177e4 1911 sci_stop_rx(port);
b129a8cc 1912 sci_stop_tx(port);
33b48e16 1913 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1914
9ab76556
AM		 1915#ifdef CONFIG_SERIAL_SH_SCI_DMA
1916 if (s->chan_rx) {
1917 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1918 port->line);
1919 del_timer_sync(&s->rx_timer);
1920 }
1921#endif
1922
73a19e4c 1923 sci_free_dma(port);
1da177e4 1924 sci_free_irq(s);
1da177e4
LT		 1925}
1926
b4a5c459 1927/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 1928static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1929 unsigned int *brr, unsigned int *srr,
1930 unsigned int *cks)
26c92f37 1931{
b4a5c459 1932 unsigned int min_sr, max_sr, shift, sr, br, prediv, scrate, c;
f4998e55 1933 unsigned long freq = s->clk_rates[SCI_FCK];
6c51332d 1934 int err, min_err = INT_MAX;
f303b364 1935
b4a5c459
GU		 1936 if (s->sampling_rate) {
1937 min_sr = max_sr = s->sampling_rate;
1938 shift = 0;
1939 } else {
1940 /* HSCIF has a variable sample rate */
1941 min_sr = 8;
1942 max_sr = 32;
1943 shift = 1;
1944 }
1945
6c51332d
GU		 1946 /*
1947 * Find the combination of sample rate and clock select with the
1948 * smallest deviation from the desired baud rate.
1949 * Prefer high sample rates to maximise the receive margin.
1950 *
1951 * M: Receive margin (%)
1952 * N: Ratio of bit rate to clock (N = sampling rate)
1953 * D: Clock duty (D = 0 to 1.0)
1954 * L: Frame length (L = 9 to 12)
1955 * F: Absolute value of clock frequency deviation
1956 *
1957 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1958 * (|D - 0.5| / N * (1 + F))|
1959 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
1960 */
b4a5c459 1961 for (sr = max_sr; sr >= min_sr; sr--) {
f303b364
UH		 1962 for (c = 0; c <= 3; c++) {
1963 /* integerized formulas from HSCIF documentation */
b4a5c459 1964 prediv = sr * (1 << (2 * c + shift));
de01e6cd
GU		 1965
1966 /*
1967 * We need to calculate:
1968 *
1969 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 1970 * err = freq / (br * prediv) - bps
de01e6cd
GU		 1971 *
1972 * Watch out for overflow when calculating the desired
1973 * sampling clock rate!
1974 */
1975 if (bps > UINT_MAX / prediv)
1976 break;
1977
1978 scrate = prediv * bps;
1979 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 1980 br = clamp(br, 1U, 256U);
6c51332d 1981
881a7489 1982 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 1983 if (abs(err) >= abs(min_err))
730c4e78
NI		 1984 continue;
1985
6c51332d 1986 min_err = err;
95a2703e 1987 *brr = br - 1;
730c4e78
NI		 1988 *srr = sr - 1;
1989 *cks = c;
6c51332d
GU		 1990
1991 if (!err)
1992 goto found;
f303b364
UH		 1993 }
1994 }
1995
6c51332d 1996found:
881a7489
GU		 1997 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
1998 min_err, *brr, *srr + 1, *cks);
f4998e55 1999 return min_err;
f303b364
UH		 2000}
2001
1ba76220
MD		 2002static void sci_reset(struct uart_port *port)
2003{
d3184e68 2004 const struct plat_sci_reg *reg;
1ba76220
MD		 2005 unsigned int status;
2006
2007 do {
b12bb29f 2008 status = serial_port_in(port, SCxSR);
1ba76220
MD		 2009 } while (!(status & SCxSR_TEND(port)));
2010
b12bb29f 2011 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 2012
0979e0e6
PM		 2013 reg = sci_getreg(port, SCFCR);
2014 if (reg->size)
b12bb29f 2015 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 2016}
2017
606d099c
AC		 2018static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2019 struct ktermios *old)
1da177e4 2020{
f4998e55
GU		 2021 unsigned int baud, smr_val = 0, scr_val = 0, i;
2022 unsigned int brr = 255, cks = 0, srr = 15;
2023 unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
00b9de9c 2024 struct sci_port *s = to_sci_port(port);
d3184e68 2025 const struct plat_sci_reg *reg;
f4998e55
GU		 2026 int min_err = INT_MAX, err;
2027 unsigned long max_freq = 0;
2028 int best_clk = -1;
1da177e4 2029
730c4e78
NI		 2030 if ((termios->c_cflag & CSIZE) == CS7)
2031 smr_val |= SCSMR_CHR;
2032 if (termios->c_cflag & PARENB)
2033 smr_val |= SCSMR_PE;
2034 if (termios->c_cflag & PARODD)
2035 smr_val |= SCSMR_PE | SCSMR_ODD;
2036 if (termios->c_cflag & CSTOPB)
2037 smr_val |= SCSMR_STOP;
2038
154280fd
MD		 2039 /*
2040 * earlyprintk comes here early on with port->uartclk set to zero.
2041 * the clock framework is not up and running at this point so here
2042 * we assume that 115200 is the maximum baud rate. please note that
2043 * the baud rate is not programmed during earlyprintk - it is assumed
2044 * that the previous boot loader has enabled required clocks and
2045 * setup the baud rate generator hardware for us already.
2046 */
f4998e55
GU		 2047 if (!port->uartclk) {
2048 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2049 goto done;
2050 }
1da177e4 2051
f4998e55
GU		 2052 for (i = 0; i < SCI_NUM_CLKS; i++)
2053 max_freq = max(max_freq, s->clk_rates[i]);
2054
2055 baud = uart_get_baud_rate(port, termios, old, 0,
2056 max_freq / max(s->sampling_rate, 8U));
2057 if (!baud)
2058 goto done;
2059
2060 /*
2061 * There can be multiple sources for the sampling clock. Find the one
2062 * that gives us the smallest deviation from the desired baud rate.
2063 */
2064
2065 /* Divided Functional Clock using standard Bit Rate Register */
2066 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2067 if (abs(err) < abs(min_err)) {
2068 best_clk = SCI_FCK;
2069 min_err = err;
2070 brr = brr1;
2071 srr = srr1;
2072 cks = cks1;
2073 }
2074
2075done:
2076 if (best_clk >= 0)
2077 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2078 s->clks[best_clk], baud, min_err);
e108b2ca 2079
23241d43 2080 sci_port_enable(s);
36003386 2081
1ba76220 2082 sci_reset(port);
1da177e4 2083
1da177e4
LT		 2084 uart_update_timeout(port, termios->c_cflag, baud);
2085
f4998e55
GU		 2086 if (best_clk >= 0) {
2087 smr_val |= cks;
2088 dev_dbg(port->dev, "SMR 0x%x BRR %u SRR %u\n", smr_val, brr,
2089 srr);
2090 serial_port_out(port, SCSMR, smr_val);
2091 serial_port_out(port, SCBRR, brr);
2092 if (sci_getreg(port, HSSRR)->size)
f303b364 2093 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2094
2095 /* Wait one bit interval */
2096 udelay((1000000 + (baud - 1)) / baud);
2097 } else {
2098 /* Don't touch the bit rate configuration */
2099 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2100 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
2101 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2102 serial_port_out(port, SCSCR, scr_val);
9d482cc3 2103 serial_port_out(port, SCSMR, smr_val);
f4998e55 2104 }
1da177e4 2105
d5701647 2106 sci_init_pins(port, termios->c_cflag);
0979e0e6 2107
73c3d53f
PM		 2108 reg = sci_getreg(port, SCFCR);
2109 if (reg->size) {
b12bb29f 2110 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2111
73c3d53f 2112 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2113 if (termios->c_cflag & CRTSCTS)
2114 ctrl |= SCFCR_MCE;
2115 else
2116 ctrl &= ~SCFCR_MCE;
faf02f8f 2117 }
73c3d53f
PM		 2118
2119 /*
2120 * As we've done a sci_reset() above, ensure we don't
2121 * interfere with the FIFOs while toggling MCE. As the
2122 * reset values could still be set, simply mask them out.
2123 */
2124 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2125
b12bb29f 2126 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2127 }
b7a76e4b 2128
f4998e55
GU		 2129 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2130 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2131 serial_port_out(port, SCSCR, scr_val);
1da177e4 2132
3089f381
GL		 2133#ifdef CONFIG_SERIAL_SH_SCI_DMA
2134 /*
5f6d8515 2135 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2136 * See serial_core.c::uart_update_timeout().
2137 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2138 * function calculates 1 jiffie for the data plus 5 jiffies for the
2139 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2140 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2141 * value obtained by this formula is too small. Therefore, if the value
2142 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2143 */
2144 if (s->chan_rx) {
5f6d8515
NI		 2145 unsigned int bits;
2146
2147 /* byte size and parity */
2148 switch (termios->c_cflag & CSIZE) {
2149 case CS5:
2150 bits = 7;
2151 break;
2152 case CS6:
2153 bits = 8;
2154 break;
2155 case CS7:
2156 bits = 9;
2157 break;
2158 default:
2159 bits = 10;
2160 break;
2161 }
2162
2163 if (termios->c_cflag & CSTOPB)
2164 bits++;
2165 if (termios->c_cflag & PARENB)
2166 bits++;
2167 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2168 (baud / 10), 10);
9b971cd2 2169 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2170 s->rx_timeout * 1000 / HZ, port->timeout);
2171 if (s->rx_timeout < msecs_to_jiffies(20))
2172 s->rx_timeout = msecs_to_jiffies(20);
2173 }
2174#endif
2175
1da177e4 2176 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2177 sci_start_rx(port);
36003386 2178
23241d43 2179 sci_port_disable(s);
1da177e4
LT		 2180}
2181
0174e5ca
TK		 2182static void sci_pm(struct uart_port *port, unsigned int state,
2183 unsigned int oldstate)
2184{
2185 struct sci_port *sci_port = to_sci_port(port);
2186
2187 switch (state) {
d3dfe5d9 2188 case UART_PM_STATE_OFF:
0174e5ca
TK		 2189 sci_port_disable(sci_port);
2190 break;
2191 default:
2192 sci_port_enable(sci_port);
2193 break;
2194 }
2195}
2196
1da177e4
LT		 2197static const char *sci_type(struct uart_port *port)
2198{
2199 switch (port->type) {
e7c98dc7
MT		 2200 case PORT_IRDA:
2201 return "irda";
2202 case PORT_SCI:
2203 return "sci";
2204 case PORT_SCIF:
2205 return "scif";
2206 case PORT_SCIFA:
2207 return "scifa";
d1d4b10c
GL		 2208 case PORT_SCIFB:
2209 return "scifb";
f303b364
UH		 2210 case PORT_HSCIF:
2211 return "hscif";
1da177e4
LT		 2212 }
2213
fa43972f 2214 return NULL;
1da177e4
LT		 2215}
2216
f6e9495d
PM		 2217static int sci_remap_port(struct uart_port *port)
2218{
e4d6f911 2219 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2220
2221 /*
2222 * Nothing to do if there's already an established membase.
2223 */
2224 if (port->membase)
2225 return 0;
2226
2227 if (port->flags & UPF_IOREMAP) {
e4d6f911 2228 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2229 if (unlikely(!port->membase)) {
2230 dev_err(port->dev, "can't remap port#%d\n", port->line);
2231 return -ENXIO;
2232 }
2233 } else {
2234 /*
2235 * For the simple (and majority of) cases where we don't
2236 * need to do any remapping, just cast the cookie
2237 * directly.
2238 */
3af4e960 2239 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2240 }
2241
2242 return 0;
2243}
2244
e2651647 2245static void sci_release_port(struct uart_port *port)
1da177e4 2246{
e4d6f911
YS		 2247 struct sci_port *sport = to_sci_port(port);
2248
e2651647
PM		 2249 if (port->flags & UPF_IOREMAP) {
2250 iounmap(port->membase);
2251 port->membase = NULL;
2252 }
2253
e4d6f911 2254 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2255}
2256
e2651647 2257static int sci_request_port(struct uart_port *port)
1da177e4 2258{
e2651647 2259 struct resource *res;
e4d6f911 2260 struct sci_port *sport = to_sci_port(port);
f6e9495d 2261 int ret;
1da177e4 2262
e4d6f911
YS		 2263 res = request_mem_region(port->mapbase, sport->reg_size,
2264 dev_name(port->dev));
2265 if (unlikely(res == NULL)) {
2266 dev_err(port->dev, "request_mem_region failed.");
e2651647 2267 return -EBUSY;
e4d6f911 2268 }
1da177e4 2269
f6e9495d
PM		 2270 ret = sci_remap_port(port);
2271 if (unlikely(ret != 0)) {
2272 release_resource(res);
2273 return ret;
7ff731ae 2274 }
e2651647
PM		 2275
2276 return 0;
2277}
2278
2279static void sci_config_port(struct uart_port *port, int flags)
2280{
2281 if (flags & UART_CONFIG_TYPE) {
2282 struct sci_port *sport = to_sci_port(port);
2283
2284 port->type = sport->cfg->type;
2285 sci_request_port(port);
2286 }
1da177e4
LT		 2287}
2288
2289static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2290{
1da177e4
LT		 2291 if (ser->baud_base < 2400)
2292 /* No paper tape reader for Mitch.. */
2293 return -EINVAL;
2294
2295 return 0;
2296}
2297
2298static struct uart_ops sci_uart_ops = {
2299 .tx_empty = sci_tx_empty,
2300 .set_mctrl = sci_set_mctrl,
2301 .get_mctrl = sci_get_mctrl,
2302 .start_tx = sci_start_tx,
2303 .stop_tx = sci_stop_tx,
2304 .stop_rx = sci_stop_rx,
1da177e4
LT		 2305 .break_ctl = sci_break_ctl,
2306 .startup = sci_startup,
2307 .shutdown = sci_shutdown,
2308 .set_termios = sci_set_termios,
0174e5ca 2309 .pm = sci_pm,
1da177e4
LT		 2310 .type = sci_type,
2311 .release_port = sci_release_port,
2312 .request_port = sci_request_port,
2313 .config_port = sci_config_port,
2314 .verify_port = sci_verify_port,
07d2a1a1
PM		 2315#ifdef CONFIG_CONSOLE_POLL
2316 .poll_get_char = sci_poll_get_char,
2317 .poll_put_char = sci_poll_put_char,
2318#endif
1da177e4
LT		 2319};
2320
a9ec81f4
LP		 2321static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2322{
f4998e55
GU		 2323 const char *clk_names[] = {
2324 [SCI_FCK] = "fck",
2325 };
2326 struct clk *clk;
2327 unsigned int i;
a9ec81f4 2328
f4998e55
GU		 2329 for (i = 0; i < SCI_NUM_CLKS; i++) {
2330 clk = devm_clk_get(dev, clk_names[i]);
2331 if (PTR_ERR(clk) == -EPROBE_DEFER)
2332 return -EPROBE_DEFER;
a9ec81f4 2333
f4998e55
GU		 2334 if (IS_ERR(clk) && i == SCI_FCK) {
2335 /*
2336 * "fck" used to be called "sci_ick", and we need to
2337 * maintain DT backward compatibility.
2338 */
2339 clk = devm_clk_get(dev, "sci_ick");
2340 if (PTR_ERR(clk) == -EPROBE_DEFER)
2341 return -EPROBE_DEFER;
a9ec81f4 2342
f4998e55
GU		 2343 if (!IS_ERR(clk))
2344 goto found;
a9ec81f4 2345
f4998e55
GU		 2346 /* SH has historically named the clock "sci_fck". */
2347 clk = devm_clk_get(dev, "sci_fck");
2348 if (!IS_ERR(clk))
2349 goto found;
2350
2351 /*
2352 * Not all SH platforms declare a clock lookup entry
2353 * for SCI devices, in which case we need to get the
2354 * global "peripheral_clk" clock.
2355 */
2356 clk = devm_clk_get(dev, "peripheral_clk");
2357 if (!IS_ERR(clk))
2358 goto found;
2359
2360 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2361 PTR_ERR(clk));
2362 return PTR_ERR(clk);
2363 }
2364
2365found:
2366 if (IS_ERR(clk))
2367 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2368 PTR_ERR(clk));
2369 else
2370 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2371 clk, clk);
2372 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2373 }
2374 return 0;
a9ec81f4
LP		 2375}
2376
9671f099 2377static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2378 struct sci_port *sci_port, unsigned int index,
2379 struct plat_sci_port *p, bool early)
e108b2ca 2380{
73a19e4c 2381 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2382 const struct resource *res;
2383 unsigned int i;
3127c6b2 2384 int ret;
e108b2ca 2385
50f0959a
PM		 2386 sci_port->cfg = p;
2387
73a19e4c
GL		 2388 port->ops = &sci_uart_ops;
2389 port->iotype = UPIO_MEM;
2390 port->line = index;
75136d48 2391
89b5c1ab
LP		 2392 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2393 if (res == NULL)
2394 return -ENOMEM;
1fcc91a6 2395
89b5c1ab 2396 port->mapbase = res->start;
e4d6f911 2397 sci_port->reg_size = resource_size(res);
1fcc91a6 2398
89b5c1ab
LP		 2399 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2400 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2401
89b5c1ab
LP		 2402 /* The SCI generates several interrupts. They can be muxed together or
2403 * connected to different interrupt lines. In the muxed case only one
2404 * interrupt resource is specified. In the non-muxed case three or four
2405 * interrupt resources are specified, as the BRI interrupt is optional.
2406 */
2407 if (sci_port->irqs[0] < 0)
2408 return -ENXIO;
1fcc91a6 2409
89b5c1ab
LP		 2410 if (sci_port->irqs[1] < 0) {
2411 sci_port->irqs[1] = sci_port->irqs[0];
2412 sci_port->irqs[2] = sci_port->irqs[0];
2413 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2414 }
2415
b545e4f4
LP		 2416 if (p->regtype == SCIx_PROBE_REGTYPE) {
2417 ret = sci_probe_regmap(p);
2418 if (unlikely(ret))
2419 return ret;
2420 }
2421
75136d48 2422 switch (p->type) {
d1d4b10c
GL		 2423 case PORT_SCIFB:
2424 port->fifosize = 256;
2e0842a1 2425 sci_port->overrun_reg = SCxSR;
75c249fd 2426 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2427 sci_port->sampling_rate = 16;
d1d4b10c 2428 break;
f303b364
UH		 2429 case PORT_HSCIF:
2430 port->fifosize = 128;
2e0842a1 2431 sci_port->overrun_reg = SCLSR;
75c249fd 2432 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2433 sci_port->sampling_rate = 0;
f303b364 2434 break;
75136d48 2435 case PORT_SCIFA:
73a19e4c 2436 port->fifosize = 64;
2e0842a1 2437 sci_port->overrun_reg = SCxSR;
75c249fd 2438 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2439 sci_port->sampling_rate = 16;
75136d48
MP		 2440 break;
2441 case PORT_SCIF:
73a19e4c 2442 port->fifosize = 16;
ec09c5eb 2443 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2444 sci_port->overrun_reg = SCxSR;
75c249fd 2445 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2446 sci_port->sampling_rate = 16;
ec09c5eb 2447 } else {
2e0842a1 2448 sci_port->overrun_reg = SCLSR;
75c249fd 2449 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2450 sci_port->sampling_rate = 32;
ec09c5eb 2451 }
75136d48
MP		 2452 break;
2453 default:
73a19e4c 2454 port->fifosize = 1;
2e0842a1 2455 sci_port->overrun_reg = SCxSR;
75c249fd 2456 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2457 sci_port->sampling_rate = 32;
75136d48
MP		 2458 break;
2459 }
7b6fd3bf 2460
878fbb91
LP		 2461 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2462 * match the SoC datasheet, this should be investigated. Let platform
2463 * data override the sampling rate for now.
ec09c5eb 2464 */
f84b6bdc
GU		 2465 if (p->sampling_rate)
2466 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2467
1fcc91a6 2468 if (!early) {
a9ec81f4
LP		 2469 ret = sci_init_clocks(sci_port, &dev->dev);
2470 if (ret < 0)
2471 return ret;
c7ed1ab3 2472
73a19e4c 2473 port->dev = &dev->dev;
5e50d2d6
MD		 2474
2475 pm_runtime_enable(&dev->dev);
7b6fd3bf 2476 }
e108b2ca 2477
7ed7e071
MD		 2478 sci_port->break_timer.data = (unsigned long)sci_port;
2479 sci_port->break_timer.function = sci_break_timer;
2480 init_timer(&sci_port->break_timer);
2481
debf9507
PM		 2482 /*
2483 * Establish some sensible defaults for the error detection.
2484 */
5da0f468
GU		 2485 if (p->type == PORT_SCI) {
2486 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2487 sci_port->error_clear = SCI_ERROR_CLEAR;
2488 } else {
2489 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2490 sci_port->error_clear = SCIF_ERROR_CLEAR;
2491 }
debf9507 2492
3ae988d9
LP		 2493 /*
2494 * Make the error mask inclusive of overrun detection, if
2495 * supported.
2496 */
5da0f468 2497 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2498 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2499 sci_port->error_clear &= ~sci_port->overrun_mask;
2500 }
debf9507 2501
ce6738b6 2502 port->type = p->type;
b6e4a3f1 2503 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2504 port->regshift = p->regshift;
73a19e4c 2505
ce6738b6 2506 /*
61a6976b 2507 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2508 * for the multi-IRQ ports, which is where we are primarily
2509 * concerned with the shutdown path synchronization.
2510 *
2511 * For the muxed case there's nothing more to do.
2512 */
1fcc91a6 2513 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2514 port->irqflags = 0;
73a19e4c 2515
61a6976b
PM		 2516 port->serial_in = sci_serial_in;
2517 port->serial_out = sci_serial_out;
2518
937bb6e4
GL		 2519 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2520 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2521 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2522
c7ed1ab3 2523 return 0;
e108b2ca
PM		 2524}
2525
6dae1421
LP		 2526static void sci_cleanup_single(struct sci_port *port)
2527{
6dae1421
LP		 2528 pm_runtime_disable(port->port.dev);
2529}
2530
1da177e4 2531#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2532static void serial_console_putchar(struct uart_port *port, int ch)
2533{
2534 sci_poll_put_char(port, ch);
2535}
2536
1da177e4
LT		 2537/*
2538 * Print a string to the serial port trying not to disturb
2539 * any possible real use of the port...
2540 */
2541static void serial_console_write(struct console *co, const char *s,
2542 unsigned count)
2543{
906b17dc
PM		 2544 struct sci_port *sci_port = &sci_ports[co->index];
2545 struct uart_port *port = &sci_port->port;
a67969b5 2546 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2547 unsigned long flags;
2548 int locked = 1;
2549
2550 local_irq_save(flags);
2551 if (port->sysrq)
2552 locked = 0;
2553 else if (oops_in_progress)
2554 locked = spin_trylock(&port->lock);
2555 else
2556 spin_lock(&port->lock);
2557
a67969b5 2558 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2559 ctrl = serial_port_in(port, SCSCR);
a67969b5
GU		 2560 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2561 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2562 serial_port_out(port, SCSCR, ctrl_temp);
07d2a1a1 2563
501b825d 2564 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2565
2566 /* wait until fifo is empty and last bit has been transmitted */
2567 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2568 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2569 cpu_relax();
40f70c03
SK		 2570
2571 /* restore the SCSCR */
2572 serial_port_out(port, SCSCR, ctrl);
2573
2574 if (locked)
2575 spin_unlock(&port->lock);
2576 local_irq_restore(flags);
1da177e4
LT		 2577}
2578
9671f099 2579static int serial_console_setup(struct console *co, char *options)
1da177e4 2580{
dc8e6f5b 2581 struct sci_port *sci_port;
1da177e4
LT		 2582 struct uart_port *port;
2583 int baud = 115200;
2584 int bits = 8;
2585 int parity = 'n';
2586 int flow = 'n';
2587 int ret;
2588
e108b2ca 2589 /*
906b17dc 2590 * Refuse to handle any bogus ports.
1da177e4 2591 */
906b17dc 2592 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2593 return -ENODEV;
e108b2ca 2594
906b17dc
PM		 2595 sci_port = &sci_ports[co->index];
2596 port = &sci_port->port;
2597
b2267a6b
AC		 2598 /*
2599 * Refuse to handle uninitialized ports.
2600 */
2601 if (!port->ops)
2602 return -ENODEV;
2603
f6e9495d
PM		 2604 ret = sci_remap_port(port);
2605 if (unlikely(ret != 0))
2606 return ret;
e108b2ca 2607
1da177e4
LT		 2608 if (options)
2609 uart_parse_options(options, &baud, &parity, &bits, &flow);
2610
ab7cfb55 2611 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2612}
2613
2614static struct console serial_console = {
2615 .name = "ttySC",
906b17dc 2616 .device = uart_console_device,
1da177e4
LT		 2617 .write = serial_console_write,
2618 .setup = serial_console_setup,
fa5da2f7 2619 .flags = CON_PRINTBUFFER,
1da177e4 2620 .index = -1,
906b17dc 2621 .data = &sci_uart_driver,
1da177e4
LT		 2622};
2623
7b6fd3bf
MD		 2624static struct console early_serial_console = {
2625 .name = "early_ttySC",
2626 .write = serial_console_write,
2627 .flags = CON_PRINTBUFFER,
906b17dc 2628 .index = -1,
7b6fd3bf 2629};
ecdf8a46 2630
7b6fd3bf
MD		 2631static char early_serial_buf[32];
2632
9671f099 2633static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2634{
574de559 2635 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2636
2637 if (early_serial_console.data)
2638 return -EEXIST;
2639
2640 early_serial_console.index = pdev->id;
ecdf8a46 2641
1fcc91a6 2642 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2643
2644 serial_console_setup(&early_serial_console, early_serial_buf);
2645
2646 if (!strstr(early_serial_buf, "keep"))
2647 early_serial_console.flags |= CON_BOOT;
2648
2649 register_console(&early_serial_console);
2650 return 0;
2651}
6a8c9799
NI		 2652
2653#define SCI_CONSOLE (&serial_console)
2654
ecdf8a46 2655#else
9671f099 2656static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2657{
2658 return -EINVAL;
2659}
1da177e4 2660
6a8c9799
NI		 2661#define SCI_CONSOLE NULL
2662
2663#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2664
6c13d5d2 2665static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2666
2667static struct uart_driver sci_uart_driver = {
2668 .owner = THIS_MODULE,
2669 .driver_name = "sci",
1da177e4
LT		 2670 .dev_name = "ttySC",
2671 .major = SCI_MAJOR,
2672 .minor = SCI_MINOR_START,
e108b2ca 2673 .nr = SCI_NPORTS,
1da177e4
LT		 2674 .cons = SCI_CONSOLE,
2675};
2676
54507f6e 2677static int sci_remove(struct platform_device *dev)
e552de24 2678{
d535a230 2679 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2680
d535a230
PM		 2681 cpufreq_unregister_notifier(&port->freq_transition,
2682 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2683
d535a230
PM		 2684 uart_remove_one_port(&sci_uart_driver, &port->port);
2685
6dae1421 2686 sci_cleanup_single(port);
e552de24 2687
e552de24
MD		 2688 return 0;
2689}
2690
bd2238fb
GU		 2691
2692#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2693#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2694#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 2695
2696static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 2697 /* SoC-specific types */
2698 {
2699 .compatible = "renesas,scif-r7s72100",
2700 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2701 },
9ed44bb2
GU		 2702 /* Family-specific types */
2703 {
2704 .compatible = "renesas,rcar-gen1-scif",
2705 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2706 }, {
2707 .compatible = "renesas,rcar-gen2-scif",
2708 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2709 }, {
2710 .compatible = "renesas,rcar-gen3-scif",
2711 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2712 },
f443ff80 2713 /* Generic types */
20bdcab8
BH		 2714 {
2715 .compatible = "renesas,scif",
bd2238fb 2716 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 2717 }, {
2718 .compatible = "renesas,scifa",
bd2238fb 2719 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 2720 }, {
2721 .compatible = "renesas,scifb",
bd2238fb 2722 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 2723 }, {
2724 .compatible = "renesas,hscif",
bd2238fb 2725 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 2726 }, {
2727 .compatible = "renesas,sci",
bd2238fb 2728 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 2729 }, {
2730 /* Terminator */
2731 },
2732};
2733MODULE_DEVICE_TABLE(of, of_sci_match);
2734
2735static struct plat_sci_port *
2736sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2737{
2738 struct device_node *np = pdev->dev.of_node;
2739 const struct of_device_id *match;
20bdcab8
BH		 2740 struct plat_sci_port *p;
2741 int id;
2742
2743 if (!IS_ENABLED(CONFIG_OF) || !np)
2744 return NULL;
2745
495bb47c 2746 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 2747 if (!match)
2748 return NULL;
2749
20bdcab8 2750 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2751 if (!p)
20bdcab8 2752 return NULL;
20bdcab8 2753
2095fc76 2754 /* Get the line number from the aliases node. */
20bdcab8
BH		 2755 id = of_alias_get_id(np, "serial");
2756 if (id < 0) {
2757 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2758 return NULL;
2759 }
2760
2761 *dev_id = id;
2762
2763 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
bd2238fb
GU		 2764 p->type = SCI_OF_TYPE(match->data);
2765 p->regtype = SCI_OF_REGTYPE(match->data);
20bdcab8
BH		 2766 p->scscr = SCSCR_RE | SCSCR_TE;
2767
2768 return p;
2769}
2770
9671f099 2771static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2772 unsigned int index,
2773 struct plat_sci_port *p,
2774 struct sci_port *sciport)
2775{
0ee70712
MD		 2776 int ret;
2777
2778 /* Sanity check */
2779 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2780 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2781 index+1, SCI_NPORTS);
9b971cd2 2782 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2783 return -EINVAL;
0ee70712
MD		 2784 }
2785
1fcc91a6 2786 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2787 if (ret)
2788 return ret;
0ee70712 2789
6dae1421
LP		 2790 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2791 if (ret) {
2792 sci_cleanup_single(sciport);
2793 return ret;
2794 }
2795
2796 return 0;
0ee70712
MD		 2797}
2798
9671f099 2799static int sci_probe(struct platform_device *dev)
1da177e4 2800{
20bdcab8
BH		 2801 struct plat_sci_port *p;
2802 struct sci_port *sp;
2803 unsigned int dev_id;
ecdf8a46 2804 int ret;
d535a230 2805
ecdf8a46
PM		 2806 /*
2807 * If we've come here via earlyprintk initialization, head off to
2808 * the special early probe. We don't have sufficient device state
2809 * to make it beyond this yet.
2810 */
2811 if (is_early_platform_device(dev))
2812 return sci_probe_earlyprintk(dev);
7b6fd3bf 2813
20bdcab8
BH		 2814 if (dev->dev.of_node) {
2815 p = sci_parse_dt(dev, &dev_id);
2816 if (p == NULL)
2817 return -EINVAL;
2818 } else {
2819 p = dev->dev.platform_data;
2820 if (p == NULL) {
2821 dev_err(&dev->dev, "no platform data supplied\n");
2822 return -EINVAL;
2823 }
2824
2825 dev_id = dev->id;
2826 }
2827
2828 sp = &sci_ports[dev_id];
d535a230 2829 platform_set_drvdata(dev, sp);
e552de24 2830
20bdcab8 2831 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2832 if (ret)
6dae1421 2833 return ret;
e552de24 2834
d535a230 2835 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2836
d535a230
PM		 2837 ret = cpufreq_register_notifier(&sp->freq_transition,
2838 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2839 if (unlikely(ret < 0)) {
bf13c9a8 2840 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2841 sci_cleanup_single(sp);
2842 return ret;
2843 }
1da177e4
LT		 2844
2845#ifdef CONFIG_SH_STANDARD_BIOS
2846 sh_bios_gdb_detach();
2847#endif
2848
e108b2ca 2849 return 0;
1da177e4
LT		 2850}
2851
cb876341 2852static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2853{
d535a230 2854 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2855
d535a230
PM		 2856 if (sport)
2857 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2858
e108b2ca
PM		 2859 return 0;
2860}
1da177e4 2861
cb876341 2862static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2863{
d535a230 2864 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2865
d535a230
PM		 2866 if (sport)
2867 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2868
2869 return 0;
2870}
2871
cb876341 2872static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2873
e108b2ca
PM		 2874static struct platform_driver sci_driver = {
2875 .probe = sci_probe,
b9e39c89 2876 .remove = sci_remove,
e108b2ca
PM		 2877 .driver = {
2878 .name = "sh-sci",
6daa79b3 2879 .pm = &sci_dev_pm_ops,
20bdcab8 2880 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2881 },
2882};
2883
2884static int __init sci_init(void)
2885{
2886 int ret;
2887
6c13d5d2 2888 pr_info("%s\n", banner);
e108b2ca 2889
e108b2ca
PM		 2890 ret = uart_register_driver(&sci_uart_driver);
2891 if (likely(ret == 0)) {
2892 ret = platform_driver_register(&sci_driver);
2893 if (unlikely(ret))
2894 uart_unregister_driver(&sci_uart_driver);
2895 }
2896
2897 return ret;
2898}
2899
2900static void __exit sci_exit(void)
2901{
2902 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2903 uart_unregister_driver(&sci_uart_driver);
2904}
2905
7b6fd3bf
MD		 2906#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2907early_platform_init_buffer("earlyprintk", &sci_driver,
2908 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2909#endif
1da177e4
LT		 2910module_init(sci_init);
2911module_exit(sci_exit);
2912
e108b2ca 2913MODULE_LICENSE("GPL");
e169c139 2914MODULE_ALIAS("platform:sh-sci");
7f405f9c 2915MODULE_AUTHOR("Paul Mundt");
f303b364 2916MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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