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Merge tag 'sh-for-linus' of git://github.com/pmundt/linux-sh
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
1da177e4
LT		 28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
e108b2ca 41#include <linux/platform_device.h>
96de1a8f 42#include <linux/serial_sci.h>
1da177e4 43#include <linux/notifier.h>
5e50d2d6 44#include <linux/pm_runtime.h>
1da177e4 45#include <linux/cpufreq.h>
85f094ec 46#include <linux/clk.h>
fa5da2f7 47#include <linux/ctype.h>
7ff731ae 48#include <linux/err.h>
73a19e4c 49#include <linux/dmaengine.h>
5beabc7f 50#include <linux/dma-mapping.h>
73a19e4c 51#include <linux/scatterlist.h>
5a0e3ad6 52#include <linux/slab.h>
50f0959a 53#include <linux/gpio.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
1da177e4
LT		 59#include "sh-sci.h"
60
e108b2ca
PM		 61struct sci_port {
62 struct uart_port port;
63
ce6738b6
PM		 64 /* Platform configuration */
65 struct plat_sci_port *cfg;
e108b2ca 66
e108b2ca
PM		 67 /* Break timer */
68 struct timer_list break_timer;
69 int break_flag;
1534a3b3 70
501b825d
MD		 71 /* Interface clock */
72 struct clk *iclk;
c7ed1ab3
PM		 73 /* Function clock */
74 struct clk *fclk;
edad1f20 75
9174fc8f 76 char *irqstr[SCIx_NR_IRQS];
50f0959a 77 char *gpiostr[SCIx_NR_FNS];
9174fc8f 78
73a19e4c
GL		 79 struct dma_chan *chan_tx;
80 struct dma_chan *chan_rx;
f43dc23d 81
73a19e4c 82#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 83 struct dma_async_tx_descriptor *desc_tx;
84 struct dma_async_tx_descriptor *desc_rx[2];
85 dma_cookie_t cookie_tx;
86 dma_cookie_t cookie_rx[2];
87 dma_cookie_t active_rx;
88 struct scatterlist sg_tx;
89 unsigned int sg_len_tx;
90 struct scatterlist sg_rx[2];
91 size_t buf_len_rx;
92 struct sh_dmae_slave param_tx;
93 struct sh_dmae_slave param_rx;
94 struct work_struct work_tx;
95 struct work_struct work_rx;
96 struct timer_list rx_timer;
3089f381 97 unsigned int rx_timeout;
73a19e4c 98#endif
e552de24 99
d535a230 100 struct notifier_block freq_transition;
1ba76220
MD		 101
102#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
103 unsigned short saved_smr;
104 unsigned short saved_fcr;
105 unsigned char saved_brr;
106#endif
e108b2ca
PM		 107};
108
1da177e4 109/* Function prototypes */
d535a230 110static void sci_start_tx(struct uart_port *port);
b129a8cc 111static void sci_stop_tx(struct uart_port *port);
d535a230 112static void sci_start_rx(struct uart_port *port);
1da177e4 113
e108b2ca 114#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 115
e108b2ca
PM		 116static struct sci_port sci_ports[SCI_NPORTS];
117static struct uart_driver sci_uart_driver;
1da177e4 118
e7c98dc7
MT		 119static inline struct sci_port *
120to_sci_port(struct uart_port *uart)
121{
122 return container_of(uart, struct sci_port, port);
123}
124
61a6976b
PM		 125struct plat_sci_reg {
126 u8 offset, size;
127};
128
129/* Helper for invalidating specific entries of an inherited map. */
130#define sci_reg_invalid { .offset = 0, .size = 0 }
131
132static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
133 [SCIx_PROBE_REGTYPE] = {
134 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
135 },
136
137 /*
138 * Common SCI definitions, dependent on the port's regshift
139 * value.
140 */
141 [SCIx_SCI_REGTYPE] = {
142 [SCSMR] = { 0x00, 8 },
143 [SCBRR] = { 0x01, 8 },
144 [SCSCR] = { 0x02, 8 },
145 [SCxTDR] = { 0x03, 8 },
146 [SCxSR] = { 0x04, 8 },
147 [SCxRDR] = { 0x05, 8 },
148 [SCFCR] = sci_reg_invalid,
149 [SCFDR] = sci_reg_invalid,
150 [SCTFDR] = sci_reg_invalid,
151 [SCRFDR] = sci_reg_invalid,
152 [SCSPTR] = sci_reg_invalid,
153 [SCLSR] = sci_reg_invalid,
154 },
155
156 /*
157 * Common definitions for legacy IrDA ports, dependent on
158 * regshift value.
159 */
160 [SCIx_IRDA_REGTYPE] = {
161 [SCSMR] = { 0x00, 8 },
162 [SCBRR] = { 0x01, 8 },
163 [SCSCR] = { 0x02, 8 },
164 [SCxTDR] = { 0x03, 8 },
165 [SCxSR] = { 0x04, 8 },
166 [SCxRDR] = { 0x05, 8 },
167 [SCFCR] = { 0x06, 8 },
168 [SCFDR] = { 0x07, 16 },
169 [SCTFDR] = sci_reg_invalid,
170 [SCRFDR] = sci_reg_invalid,
171 [SCSPTR] = sci_reg_invalid,
172 [SCLSR] = sci_reg_invalid,
173 },
174
175 /*
176 * Common SCIFA definitions.
177 */
178 [SCIx_SCIFA_REGTYPE] = {
179 [SCSMR] = { 0x00, 16 },
180 [SCBRR] = { 0x04, 8 },
181 [SCSCR] = { 0x08, 16 },
182 [SCxTDR] = { 0x20, 8 },
183 [SCxSR] = { 0x14, 16 },
184 [SCxRDR] = { 0x24, 8 },
185 [SCFCR] = { 0x18, 16 },
186 [SCFDR] = { 0x1c, 16 },
187 [SCTFDR] = sci_reg_invalid,
188 [SCRFDR] = sci_reg_invalid,
189 [SCSPTR] = sci_reg_invalid,
190 [SCLSR] = sci_reg_invalid,
191 },
192
193 /*
194 * Common SCIFB definitions.
195 */
196 [SCIx_SCIFB_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x40, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x60, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
209 },
210
3af1f8a4
PE		 211 /*
212 * Common SH-2(A) SCIF definitions for ports with FIFO data
213 * count registers.
214 */
215 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x0c, 8 },
220 [SCxSR] = { 0x10, 16 },
221 [SCxRDR] = { 0x14, 8 },
222 [SCFCR] = { 0x18, 16 },
223 [SCFDR] = { 0x1c, 16 },
224 [SCTFDR] = sci_reg_invalid,
225 [SCRFDR] = sci_reg_invalid,
226 [SCSPTR] = { 0x20, 16 },
227 [SCLSR] = { 0x24, 16 },
228 },
229
61a6976b
PM		 230 /*
231 * Common SH-3 SCIF definitions.
232 */
233 [SCIx_SH3_SCIF_REGTYPE] = {
234 [SCSMR] = { 0x00, 8 },
235 [SCBRR] = { 0x02, 8 },
236 [SCSCR] = { 0x04, 8 },
237 [SCxTDR] = { 0x06, 8 },
238 [SCxSR] = { 0x08, 16 },
239 [SCxRDR] = { 0x0a, 8 },
240 [SCFCR] = { 0x0c, 8 },
241 [SCFDR] = { 0x0e, 16 },
242 [SCTFDR] = sci_reg_invalid,
243 [SCRFDR] = sci_reg_invalid,
244 [SCSPTR] = sci_reg_invalid,
245 [SCLSR] = sci_reg_invalid,
246 },
247
248 /*
249 * Common SH-4(A) SCIF(B) definitions.
250 */
251 [SCIx_SH4_SCIF_REGTYPE] = {
252 [SCSMR] = { 0x00, 16 },
253 [SCBRR] = { 0x04, 8 },
254 [SCSCR] = { 0x08, 16 },
255 [SCxTDR] = { 0x0c, 8 },
256 [SCxSR] = { 0x10, 16 },
257 [SCxRDR] = { 0x14, 8 },
258 [SCFCR] = { 0x18, 16 },
259 [SCFDR] = { 0x1c, 16 },
260 [SCTFDR] = sci_reg_invalid,
261 [SCRFDR] = sci_reg_invalid,
262 [SCSPTR] = { 0x20, 16 },
263 [SCLSR] = { 0x24, 16 },
264 },
265
266 /*
267 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
268 * register.
269 */
270 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
271 [SCSMR] = { 0x00, 16 },
272 [SCBRR] = { 0x04, 8 },
273 [SCSCR] = { 0x08, 16 },
274 [SCxTDR] = { 0x0c, 8 },
275 [SCxSR] = { 0x10, 16 },
276 [SCxRDR] = { 0x14, 8 },
277 [SCFCR] = { 0x18, 16 },
278 [SCFDR] = { 0x1c, 16 },
279 [SCTFDR] = sci_reg_invalid,
280 [SCRFDR] = sci_reg_invalid,
281 [SCSPTR] = sci_reg_invalid,
282 [SCLSR] = { 0x24, 16 },
283 },
284
285 /*
286 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
287 * count registers.
288 */
289 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
290 [SCSMR] = { 0x00, 16 },
291 [SCBRR] = { 0x04, 8 },
292 [SCSCR] = { 0x08, 16 },
293 [SCxTDR] = { 0x0c, 8 },
294 [SCxSR] = { 0x10, 16 },
295 [SCxRDR] = { 0x14, 8 },
296 [SCFCR] = { 0x18, 16 },
297 [SCFDR] = { 0x1c, 16 },
298 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
299 [SCRFDR] = { 0x20, 16 },
300 [SCSPTR] = { 0x24, 16 },
301 [SCLSR] = { 0x28, 16 },
302 },
303
304 /*
305 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
306 * registers.
307 */
308 [SCIx_SH7705_SCIF_REGTYPE] = {
309 [SCSMR] = { 0x00, 16 },
310 [SCBRR] = { 0x04, 8 },
311 [SCSCR] = { 0x08, 16 },
312 [SCxTDR] = { 0x20, 8 },
313 [SCxSR] = { 0x14, 16 },
314 [SCxRDR] = { 0x24, 8 },
315 [SCFCR] = { 0x18, 16 },
316 [SCFDR] = { 0x1c, 16 },
317 [SCTFDR] = sci_reg_invalid,
318 [SCRFDR] = sci_reg_invalid,
319 [SCSPTR] = sci_reg_invalid,
320 [SCLSR] = sci_reg_invalid,
321 },
322};
323
72b294cf
PM		 324#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
325
61a6976b
PM		 326/*
327 * The "offset" here is rather misleading, in that it refers to an enum
328 * value relative to the port mapping rather than the fixed offset
329 * itself, which needs to be manually retrieved from the platform's
330 * register map for the given port.
331 */
332static unsigned int sci_serial_in(struct uart_port *p, int offset)
333{
72b294cf 334 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 335
336 if (reg->size == 8)
337 return ioread8(p->membase + (reg->offset << p->regshift));
338 else if (reg->size == 16)
339 return ioread16(p->membase + (reg->offset << p->regshift));
340 else
341 WARN(1, "Invalid register access\n");
342
343 return 0;
344}
345
346static void sci_serial_out(struct uart_port *p, int offset, int value)
347{
72b294cf 348 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 349
350 if (reg->size == 8)
351 iowrite8(value, p->membase + (reg->offset << p->regshift));
352 else if (reg->size == 16)
353 iowrite16(value, p->membase + (reg->offset << p->regshift));
354 else
355 WARN(1, "Invalid register access\n");
356}
357
358#define sci_in(up, offset) (up->serial_in(up, offset))
359#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
360
361static int sci_probe_regmap(struct plat_sci_port *cfg)
362{
363 switch (cfg->type) {
364 case PORT_SCI:
365 cfg->regtype = SCIx_SCI_REGTYPE;
366 break;
367 case PORT_IRDA:
368 cfg->regtype = SCIx_IRDA_REGTYPE;
369 break;
370 case PORT_SCIFA:
371 cfg->regtype = SCIx_SCIFA_REGTYPE;
372 break;
373 case PORT_SCIFB:
374 cfg->regtype = SCIx_SCIFB_REGTYPE;
375 break;
376 case PORT_SCIF:
377 /*
378 * The SH-4 is a bit of a misnomer here, although that's
379 * where this particular port layout originated. This
380 * configuration (or some slight variation thereof)
381 * remains the dominant model for all SCIFs.
382 */
383 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
384 break;
385 default:
386 printk(KERN_ERR "Can't probe register map for given port\n");
387 return -EINVAL;
388 }
389
390 return 0;
391}
392
23241d43
PM		 393static void sci_port_enable(struct sci_port *sci_port)
394{
395 if (!sci_port->port.dev)
396 return;
397
398 pm_runtime_get_sync(sci_port->port.dev);
399
400 clk_enable(sci_port->iclk);
401 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
402 clk_enable(sci_port->fclk);
403}
404
405static void sci_port_disable(struct sci_port *sci_port)
406{
407 if (!sci_port->port.dev)
408 return;
409
410 clk_disable(sci_port->fclk);
411 clk_disable(sci_port->iclk);
412
413 pm_runtime_put_sync(sci_port->port.dev);
414}
415
07d2a1a1 416#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 417
418#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 419static int sci_poll_get_char(struct uart_port *port)
1da177e4 420{
1da177e4
LT		 421 unsigned short status;
422 int c;
423
e108b2ca 424 do {
1da177e4
LT		 425 status = sci_in(port, SCxSR);
426 if (status & SCxSR_ERRORS(port)) {
94c8b6db 427 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 428 continue;
429 }
3f255eb3
JW		 430 break;
431 } while (1);
432
433 if (!(status & SCxSR_RDxF(port)))
434 return NO_POLL_CHAR;
07d2a1a1 435
1da177e4 436 c = sci_in(port, SCxRDR);
07d2a1a1 437
e7c98dc7
MT		 438 /* Dummy read */
439 sci_in(port, SCxSR);
1da177e4 440 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 441
442 return c;
443}
1f6fd5c9 444#endif
1da177e4 445
07d2a1a1 446static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 447{
1da177e4
LT		 448 unsigned short status;
449
1da177e4
LT		 450 do {
451 status = sci_in(port, SCxSR);
452 } while (!(status & SCxSR_TDxE(port)));
453
272966c0 454 sci_out(port, SCxTDR, c);
dd0a3e77 455 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 456}
07d2a1a1 457#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 458
61a6976b 459static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 460{
61a6976b
PM		 461 struct sci_port *s = to_sci_port(port);
462 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 463
61a6976b
PM		 464 /*
465 * Use port-specific handler if provided.
466 */
467 if (s->cfg->ops && s->cfg->ops->init_pins) {
468 s->cfg->ops->init_pins(port, cflag);
469 return;
1da177e4 470 }
41504c39 471
61a6976b
PM		 472 /*
473 * For the generic path SCSPTR is necessary. Bail out if that's
474 * unavailable, too.
475 */
476 if (!reg->size)
477 return;
41504c39 478
faf02f8f
PM		 479 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
480 ((!(cflag & CRTSCTS)))) {
481 unsigned short status;
482
483 status = sci_in(port, SCSPTR);
484 status &= ~SCSPTR_CTSIO;
485 status |= SCSPTR_RTSIO;
486 sci_out(port, SCSPTR, status); /* Set RTS = 1 */
487 }
d5701647 488}
e108b2ca 489
72b294cf 490static int sci_txfill(struct uart_port *port)
e108b2ca 491{
72b294cf 492 struct plat_sci_reg *reg;
e108b2ca 493
72b294cf
PM		 494 reg = sci_getreg(port, SCTFDR);
495 if (reg->size)
73a19e4c 496 return sci_in(port, SCTFDR) & 0xff;
c63847a3 497
72b294cf
PM		 498 reg = sci_getreg(port, SCFDR);
499 if (reg->size)
d1d4b10c 500 return sci_in(port, SCFDR) >> 8;
d1d4b10c 501
73a19e4c 502 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 503}
504
73a19e4c
GL		 505static int sci_txroom(struct uart_port *port)
506{
72b294cf 507 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 508}
509
510static int sci_rxfill(struct uart_port *port)
e108b2ca 511{
72b294cf
PM		 512 struct plat_sci_reg *reg;
513
514 reg = sci_getreg(port, SCRFDR);
515 if (reg->size)
516 return sci_in(port, SCRFDR) & 0xff;
517
518 reg = sci_getreg(port, SCFDR);
519 if (reg->size)
520 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
521
e7c98dc7 522 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 523}
524
514820eb
PM		 525/*
526 * SCI helper for checking the state of the muxed port/RXD pins.
527 */
528static inline int sci_rxd_in(struct uart_port *port)
529{
530 struct sci_port *s = to_sci_port(port);
531
532 if (s->cfg->port_reg <= 0)
533 return 1;
534
535 return !!__raw_readb(s->cfg->port_reg);
536}
537
1da177e4
LT		 538/* ********************************************************************** *
539 * the interrupt related routines *
540 * ********************************************************************** */
541
542static void sci_transmit_chars(struct uart_port *port)
543{
ebd2c8f6 544 struct circ_buf *xmit = &port->state->xmit;
1da177e4 545 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 546 unsigned short status;
547 unsigned short ctrl;
e108b2ca 548 int count;
1da177e4
LT		 549
550 status = sci_in(port, SCxSR);
551 if (!(status & SCxSR_TDxE(port))) {
1da177e4 552 ctrl = sci_in(port, SCSCR);
e7c98dc7 553 if (uart_circ_empty(xmit))
8e698614 554 ctrl &= ~SCSCR_TIE;
e7c98dc7 555 else
8e698614 556 ctrl |= SCSCR_TIE;
1da177e4 557 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 558 return;
559 }
560
72b294cf 561 count = sci_txroom(port);
1da177e4
LT		 562
563 do {
564 unsigned char c;
565
566 if (port->x_char) {
567 c = port->x_char;
568 port->x_char = 0;
569 } else if (!uart_circ_empty(xmit) && !stopped) {
570 c = xmit->buf[xmit->tail];
571 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
572 } else {
573 break;
574 }
575
576 sci_out(port, SCxTDR, c);
577
578 port->icount.tx++;
579 } while (--count > 0);
580
581 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
582
583 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
584 uart_write_wakeup(port);
585 if (uart_circ_empty(xmit)) {
b129a8cc 586 sci_stop_tx(port);
1da177e4 587 } else {
1da177e4
LT		 588 ctrl = sci_in(port, SCSCR);
589
1a22f08d 590 if (port->type != PORT_SCI) {
1da177e4
LT		 591 sci_in(port, SCxSR); /* Dummy read */
592 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
593 }
1da177e4 594
8e698614 595 ctrl |= SCSCR_TIE;
1da177e4 596 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 597 }
598}
599
600/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 601#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 602
94c8b6db 603static void sci_receive_chars(struct uart_port *port)
1da177e4 604{
e7c98dc7 605 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 606 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 607 int i, count, copied = 0;
608 unsigned short status;
33f0f88f 609 unsigned char flag;
1da177e4
LT		 610
611 status = sci_in(port, SCxSR);
612 if (!(status & SCxSR_RDxF(port)))
613 return;
614
615 while (1) {
1da177e4 616 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 617 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 618
619 /* If for any reason we can't copy more data, we're done! */
620 if (count == 0)
621 break;
622
623 if (port->type == PORT_SCI) {
624 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 625 if (uart_handle_sysrq_char(port, c) ||
626 sci_port->break_flag)
1da177e4 627 count = 0;
e7c98dc7 628 else
e108b2ca 629 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 630 } else {
e7c98dc7 631 for (i = 0; i < count; i++) {
1da177e4 632 char c = sci_in(port, SCxRDR);
d97fbbed 633
1da177e4
LT		 634 status = sci_in(port, SCxSR);
635#if defined(CONFIG_CPU_SH3)
636 /* Skip "chars" during break */
e108b2ca 637 if (sci_port->break_flag) {
1da177e4
LT		 638 if ((c == 0) &&
639 (status & SCxSR_FER(port))) {
640 count--; i--;
641 continue;
642 }
e108b2ca 643
1da177e4 644 /* Nonzero => end-of-break */
762c69e3 645 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 646 sci_port->break_flag = 0;
647
1da177e4
LT		 648 if (STEPFN(c)) {
649 count--; i--;
650 continue;
651 }
652 }
653#endif /* CONFIG_CPU_SH3 */
7d12e780 654 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 655 count--; i--;
656 continue;
657 }
658
659 /* Store data and status */
73a19e4c 660 if (status & SCxSR_FER(port)) {
33f0f88f 661 flag = TTY_FRAME;
d97fbbed 662 port->icount.frame++;
762c69e3 663 dev_notice(port->dev, "frame error\n");
73a19e4c 664 } else if (status & SCxSR_PER(port)) {
33f0f88f 665 flag = TTY_PARITY;
d97fbbed 666 port->icount.parity++;
762c69e3 667 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 668 } else
669 flag = TTY_NORMAL;
762c69e3 670
33f0f88f 671 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 672 }
673 }
674
675 sci_in(port, SCxSR); /* dummy read */
676 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
677
1da177e4
LT		 678 copied += count;
679 port->icount.rx += count;
680 }
681
682 if (copied) {
683 /* Tell the rest of the system the news. New characters! */
684 tty_flip_buffer_push(tty);
685 } else {
686 sci_in(port, SCxSR); /* dummy read */
687 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
688 }
689}
690
691#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 692
693/*
694 * The sci generates interrupts during the break,
1da177e4
LT		 695 * 1 per millisecond or so during the break period, for 9600 baud.
696 * So dont bother disabling interrupts.
697 * But dont want more than 1 break event.
698 * Use a kernel timer to periodically poll the rx line until
699 * the break is finished.
700 */
94c8b6db 701static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 702{
bc9b3f5c 703 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 704}
94c8b6db 705
1da177e4
LT		 706/* Ensure that two consecutive samples find the break over. */
707static void sci_break_timer(unsigned long data)
708{
e108b2ca
PM		 709 struct sci_port *port = (struct sci_port *)data;
710
23241d43 711 sci_port_enable(port);
5e50d2d6 712
e108b2ca 713 if (sci_rxd_in(&port->port) == 0) {
1da177e4 714 port->break_flag = 1;
e108b2ca
PM		 715 sci_schedule_break_timer(port);
716 } else if (port->break_flag == 1) {
1da177e4
LT		 717 /* break is over. */
718 port->break_flag = 2;
e108b2ca
PM		 719 sci_schedule_break_timer(port);
720 } else
721 port->break_flag = 0;
5e50d2d6 722
23241d43 723 sci_port_disable(port);
1da177e4
LT		 724}
725
94c8b6db 726static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 727{
728 int copied = 0;
729 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 730 struct tty_struct *tty = port->state->port.tty;
debf9507 731 struct sci_port *s = to_sci_port(port);
1da177e4 732
debf9507
PM		 733 /*
734 * Handle overruns, if supported.
735 */
736 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
737 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 738 port->icount.overrun++;
739
debf9507
PM		 740 /* overrun error */
741 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
742 copied++;
762c69e3 743
debf9507
PM		 744 dev_notice(port->dev, "overrun error");
745 }
1da177e4
LT		 746 }
747
e108b2ca 748 if (status & SCxSR_FER(port)) {
1da177e4
LT		 749 if (sci_rxd_in(port) == 0) {
750 /* Notify of BREAK */
e7c98dc7 751 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 752
753 if (!sci_port->break_flag) {
d97fbbed
PM		 754 port->icount.brk++;
755
e108b2ca
PM		 756 sci_port->break_flag = 1;
757 sci_schedule_break_timer(sci_port);
758
1da177e4 759 /* Do sysrq handling. */
e108b2ca 760 if (uart_handle_break(port))
1da177e4 761 return 0;
762c69e3
PM		 762
763 dev_dbg(port->dev, "BREAK detected\n");
764
e108b2ca 765 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 766 copied++;
767 }
768
e108b2ca 769 } else {
1da177e4 770 /* frame error */
d97fbbed
PM		 771 port->icount.frame++;
772
e108b2ca 773 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 774 copied++;
762c69e3
PM		 775
776 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 777 }
778 }
779
e108b2ca 780 if (status & SCxSR_PER(port)) {
1da177e4 781 /* parity error */
d97fbbed
PM		 782 port->icount.parity++;
783
e108b2ca
PM		 784 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
785 copied++;
762c69e3
PM		 786
787 dev_notice(port->dev, "parity error");
1da177e4
LT		 788 }
789
33f0f88f 790 if (copied)
1da177e4 791 tty_flip_buffer_push(tty);
1da177e4
LT		 792
793 return copied;
794}
795
94c8b6db 796static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 797{
ebd2c8f6 798 struct tty_struct *tty = port->state->port.tty;
debf9507 799 struct sci_port *s = to_sci_port(port);
4b8c59a3 800 struct plat_sci_reg *reg;
d830fa45
PM		 801 int copied = 0;
802
4b8c59a3
PM		 803 reg = sci_getreg(port, SCLSR);
804 if (!reg->size)
d830fa45
PM		 805 return 0;
806
debf9507 807 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
d830fa45
PM		 808 sci_out(port, SCLSR, 0);
809
d97fbbed
PM		 810 port->icount.overrun++;
811
d830fa45
PM		 812 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
813 tty_flip_buffer_push(tty);
814
815 dev_notice(port->dev, "overrun error\n");
816 copied++;
817 }
818
819 return copied;
820}
821
94c8b6db 822static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 823{
824 int copied = 0;
825 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 826 struct tty_struct *tty = port->state->port.tty;
a5660ada 827 struct sci_port *s = to_sci_port(port);
1da177e4 828
0b3d4ef6
PM		 829 if (uart_handle_break(port))
830 return 0;
831
b7a76e4b 832 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 833#if defined(CONFIG_CPU_SH3)
834 /* Debounce break */
835 s->break_flag = 1;
836#endif
d97fbbed
PM		 837
838 port->icount.brk++;
839
1da177e4 840 /* Notify of BREAK */
e108b2ca 841 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 842 copied++;
762c69e3
PM		 843
844 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 845 }
846
33f0f88f 847 if (copied)
1da177e4 848 tty_flip_buffer_push(tty);
e108b2ca 849
d830fa45
PM		 850 copied += sci_handle_fifo_overrun(port);
851
1da177e4
LT		 852 return copied;
853}
854
73a19e4c 855static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 856{
73a19e4c
GL		 857#ifdef CONFIG_SERIAL_SH_SCI_DMA
858 struct uart_port *port = ptr;
859 struct sci_port *s = to_sci_port(port);
860
861 if (s->chan_rx) {
73a19e4c
GL		 862 u16 scr = sci_in(port, SCSCR);
863 u16 ssr = sci_in(port, SCxSR);
864
865 /* Disable future Rx interrupts */
d1d4b10c 866 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 867 disable_irq_nosync(irq);
868 scr |= 0x4000;
869 } else {
f43dc23d 870 scr &= ~SCSCR_RIE;
3089f381
GL		 871 }
872 sci_out(port, SCSCR, scr);
73a19e4c
GL		 873 /* Clear current interrupt */
874 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 875 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
876 jiffies, s->rx_timeout);
877 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 878
879 return IRQ_HANDLED;
880 }
881#endif
882
1da177e4
LT		 883 /* I think sci_receive_chars has to be called irrespective
884 * of whether the I_IXOFF is set, otherwise, how is the interrupt
885 * to be disabled?
886 */
73a19e4c 887 sci_receive_chars(ptr);
1da177e4
LT		 888
889 return IRQ_HANDLED;
890}
891
7d12e780 892static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 893{
894 struct uart_port *port = ptr;
fd78a76a 895 unsigned long flags;
1da177e4 896
fd78a76a 897 spin_lock_irqsave(&port->lock, flags);
1da177e4 898 sci_transmit_chars(port);
fd78a76a 899 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 900
901 return IRQ_HANDLED;
902}
903
7d12e780 904static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 905{
906 struct uart_port *port = ptr;
907
908 /* Handle errors */
909 if (port->type == PORT_SCI) {
910 if (sci_handle_errors(port)) {
911 /* discard character in rx buffer */
912 sci_in(port, SCxSR);
913 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
914 }
915 } else {
d830fa45 916 sci_handle_fifo_overrun(port);
7d12e780 917 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 918 }
919
920 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
921
922 /* Kick the transmission */
7d12e780 923 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 924
925 return IRQ_HANDLED;
926}
927
7d12e780 928static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 929{
930 struct uart_port *port = ptr;
931
932 /* Handle BREAKs */
933 sci_handle_breaks(port);
934 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
935
936 return IRQ_HANDLED;
937}
938
f43dc23d
PM		 939static inline unsigned long port_rx_irq_mask(struct uart_port *port)
940{
941 /*
942 * Not all ports (such as SCIFA) will support REIE. Rather than
943 * special-casing the port type, we check the port initialization
944 * IRQ enable mask to see whether the IRQ is desired at all. If
945 * it's unset, it's logically inferred that there's no point in
946 * testing for it.
947 */
ce6738b6 948 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 949}
950
7d12e780 951static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 952{
44e18e9e 953 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 954 struct uart_port *port = ptr;
73a19e4c 955 struct sci_port *s = to_sci_port(port);
a8884e34 956 irqreturn_t ret = IRQ_NONE;
1da177e4 957
e7c98dc7
MT		 958 ssr_status = sci_in(port, SCxSR);
959 scr_status = sci_in(port, SCSCR);
f43dc23d 960 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 961
962 /* Tx Interrupt */
f43dc23d 963 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 964 !s->chan_tx)
a8884e34 965 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 966
73a19e4c
GL		 967 /*
968 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
969 * DR flags
970 */
971 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 972 (scr_status & SCSCR_RIE))
a8884e34 973 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 974
1da177e4 975 /* Error Interrupt */
dd4da3a5 976 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 977 ret = sci_er_interrupt(irq, ptr);
f43dc23d 978
1da177e4 979 /* Break Interrupt */
dd4da3a5 980 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 981 ret = sci_br_interrupt(irq, ptr);
1da177e4 982
a8884e34 983 return ret;
1da177e4
LT		 984}
985
1da177e4 986/*
25985edc 987 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 988 * ports' baud rate when the peripheral clock changes.
989 */
e108b2ca
PM		 990static int sci_notifier(struct notifier_block *self,
991 unsigned long phase, void *p)
1da177e4 992{
e552de24
MD		 993 struct sci_port *sci_port;
994 unsigned long flags;
1da177e4 995
d535a230
PM		 996 sci_port = container_of(self, struct sci_port, freq_transition);
997
1da177e4 998 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 999 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 1000 struct uart_port *port = &sci_port->port;
073e84c9 1001
d535a230
PM		 1002 spin_lock_irqsave(&port->lock, flags);
1003 port->uartclk = clk_get_rate(sci_port->iclk);
1004 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1005 }
1da177e4 1006
1da177e4
LT		 1007 return NOTIFY_OK;
1008}
501b825d 1009
9174fc8f
PM		 1010static struct sci_irq_desc {
1011 const char *desc;
1012 irq_handler_t handler;
1013} sci_irq_desc[] = {
1014 /*
1015 * Split out handlers, the default case.
1016 */
1017 [SCIx_ERI_IRQ] = {
1018 .desc = "rx err",
1019 .handler = sci_er_interrupt,
1020 },
1021
1022 [SCIx_RXI_IRQ] = {
1023 .desc = "rx full",
1024 .handler = sci_rx_interrupt,
1025 },
1026
1027 [SCIx_TXI_IRQ] = {
1028 .desc = "tx empty",
1029 .handler = sci_tx_interrupt,
1030 },
1031
1032 [SCIx_BRI_IRQ] = {
1033 .desc = "break",
1034 .handler = sci_br_interrupt,
1035 },
1036
1037 /*
1038 * Special muxed handler.
1039 */
1040 [SCIx_MUX_IRQ] = {
1041 .desc = "mux",
1042 .handler = sci_mpxed_interrupt,
1043 },
1044};
1045
1da177e4
LT		 1046static int sci_request_irq(struct sci_port *port)
1047{
9174fc8f
PM		 1048 struct uart_port *up = &port->port;
1049 int i, j, ret = 0;
1050
1051 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1052 struct sci_irq_desc *desc;
1053 unsigned int irq;
1054
1055 if (SCIx_IRQ_IS_MUXED(port)) {
1056 i = SCIx_MUX_IRQ;
1057 irq = up->irq;
1058 } else
1059 irq = port->cfg->irqs[i];
1060
1061 desc = sci_irq_desc + i;
1062 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1063 dev_name(up->dev), desc->desc);
1064 if (!port->irqstr[j]) {
1065 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1066 desc->desc);
1067 goto out_nomem;
1da177e4 1068 }
9174fc8f
PM		 1069
1070 ret = request_irq(irq, desc->handler, up->irqflags,
1071 port->irqstr[j], port);
1072 if (unlikely(ret)) {
1073 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1074 goto out_noirq;
1da177e4
LT		 1075 }
1076 }
1077
1078 return 0;
9174fc8f
PM		 1079
1080out_noirq:
1081 while (--i >= 0)
1082 free_irq(port->cfg->irqs[i], port);
1083
1084out_nomem:
1085 while (--j >= 0)
1086 kfree(port->irqstr[j]);
1087
1088 return ret;
1da177e4
LT		 1089}
1090
1091static void sci_free_irq(struct sci_port *port)
1092{
1093 int i;
1094
9174fc8f
PM		 1095 /*
1096 * Intentionally in reverse order so we iterate over the muxed
1097 * IRQ first.
1098 */
1099 for (i = 0; i < SCIx_NR_IRQS; i++) {
1100 free_irq(port->cfg->irqs[i], port);
1101 kfree(port->irqstr[i]);
1da177e4 1102
9174fc8f
PM		 1103 if (SCIx_IRQ_IS_MUXED(port)) {
1104 /* If there's only one IRQ, we're done. */
1105 return;
1da177e4
LT		 1106 }
1107 }
1108}
1109
50f0959a
PM		 1110static const char *sci_gpio_names[SCIx_NR_FNS] = {
1111 "sck", "rxd", "txd", "cts", "rts",
1112};
1113
1114static const char *sci_gpio_str(unsigned int index)
1115{
1116 return sci_gpio_names[index];
1117}
1118
1119static void __devinit sci_init_gpios(struct sci_port *port)
1120{
1121 struct uart_port *up = &port->port;
1122 int i;
1123
1124 if (!port->cfg)
1125 return;
1126
1127 for (i = 0; i < SCIx_NR_FNS; i++) {
1128 const char *desc;
1129 int ret;
1130
1131 if (!port->cfg->gpios[i])
1132 continue;
1133
1134 desc = sci_gpio_str(i);
1135
1136 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1137 dev_name(up->dev), desc);
1138
1139 /*
1140 * If we've failed the allocation, we can still continue
1141 * on with a NULL string.
1142 */
1143 if (!port->gpiostr[i])
1144 dev_notice(up->dev, "%s string allocation failure\n",
1145 desc);
1146
1147 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1148 if (unlikely(ret != 0)) {
1149 dev_notice(up->dev, "failed %s gpio request\n", desc);
1150
1151 /*
1152 * If we can't get the GPIO for whatever reason,
1153 * no point in keeping the verbose string around.
1154 */
1155 kfree(port->gpiostr[i]);
1156 }
1157 }
1158}
1159
1160static void sci_free_gpios(struct sci_port *port)
1161{
1162 int i;
1163
1164 for (i = 0; i < SCIx_NR_FNS; i++)
1165 if (port->cfg->gpios[i]) {
1166 gpio_free(port->cfg->gpios[i]);
1167 kfree(port->gpiostr[i]);
1168 }
1169}
1170
1da177e4
LT		 1171static unsigned int sci_tx_empty(struct uart_port *port)
1172{
b1516803 1173 unsigned short status = sci_in(port, SCxSR);
72b294cf 1174 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1175
1176 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1177}
1178
cdf7c42f
PM		 1179/*
1180 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1181 * CTS/RTS is supported in hardware by at least one port and controlled
1182 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1183 * handled via the ->init_pins() op, which is a bit of a one-way street,
1184 * lacking any ability to defer pin control -- this will later be
1185 * converted over to the GPIO framework).
dc7e3ef7
PM		 1186 *
1187 * Other modes (such as loopback) are supported generically on certain
1188 * port types, but not others. For these it's sufficient to test for the
1189 * existence of the support register and simply ignore the port type.
cdf7c42f 1190 */
1da177e4
LT		 1191static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1192{
dc7e3ef7
PM		 1193 if (mctrl & TIOCM_LOOP) {
1194 struct plat_sci_reg *reg;
1195
1196 /*
1197 * Standard loopback mode for SCFCR ports.
1198 */
1199 reg = sci_getreg(port, SCFCR);
1200 if (reg->size)
1201 sci_out(port, SCFCR, sci_in(port, SCFCR) | 1);
1202 }
1da177e4
LT		 1203}
1204
1205static unsigned int sci_get_mctrl(struct uart_port *port)
1206{
cdf7c42f
PM		 1207 /*
1208 * CTS/RTS is handled in hardware when supported, while nothing
1209 * else is wired up. Keep it simple and simply assert DSR/CAR.
1210 */
1211 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1212}
1213
73a19e4c
GL		 1214#ifdef CONFIG_SERIAL_SH_SCI_DMA
1215static void sci_dma_tx_complete(void *arg)
1216{
1217 struct sci_port *s = arg;
1218 struct uart_port *port = &s->port;
1219 struct circ_buf *xmit = &port->state->xmit;
1220 unsigned long flags;
1221
1222 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1223
1224 spin_lock_irqsave(&port->lock, flags);
1225
f354a381 1226 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1227 xmit->tail &= UART_XMIT_SIZE - 1;
1228
f354a381 1229 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1230
1231 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1232 s->desc_tx = NULL;
1233
73a19e4c
GL		 1234 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1235 uart_write_wakeup(port);
1236
3089f381 1237 if (!uart_circ_empty(xmit)) {
49d4bcad 1238 s->cookie_tx = 0;
73a19e4c 1239 schedule_work(&s->work_tx);
49d4bcad
YT		 1240 } else {
1241 s->cookie_tx = -EINVAL;
1242 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1243 u16 ctrl = sci_in(port, SCSCR);
1244 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1245 }
3089f381
GL		 1246 }
1247
1248 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1249}
1250
1251/* Locking: called with port lock held */
1252static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1253 size_t count)
1254{
1255 struct uart_port *port = &s->port;
1256 int i, active, room;
1257
1258 room = tty_buffer_request_room(tty, count);
1259
1260 if (s->active_rx == s->cookie_rx[0]) {
1261 active = 0;
1262 } else if (s->active_rx == s->cookie_rx[1]) {
1263 active = 1;
1264 } else {
1265 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1266 return 0;
1267 }
1268
1269 if (room < count)
1270 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1271 count - room);
1272 if (!room)
1273 return room;
1274
1275 for (i = 0; i < room; i++)
1276 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1277 TTY_NORMAL);
1278
1279 port->icount.rx += room;
1280
1281 return room;
1282}
1283
1284static void sci_dma_rx_complete(void *arg)
1285{
1286 struct sci_port *s = arg;
1287 struct uart_port *port = &s->port;
1288 struct tty_struct *tty = port->state->port.tty;
1289 unsigned long flags;
1290 int count;
1291
3089f381 1292 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1293
1294 spin_lock_irqsave(&port->lock, flags);
1295
1296 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1297
3089f381 1298 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1299
1300 spin_unlock_irqrestore(&port->lock, flags);
1301
1302 if (count)
1303 tty_flip_buffer_push(tty);
1304
1305 schedule_work(&s->work_rx);
1306}
1307
73a19e4c
GL		 1308static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1309{
1310 struct dma_chan *chan = s->chan_rx;
1311 struct uart_port *port = &s->port;
73a19e4c
GL		 1312
1313 s->chan_rx = NULL;
1314 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1315 dma_release_channel(chan);
85b8e3ff
GL		 1316 if (sg_dma_address(&s->sg_rx[0]))
1317 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1318 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1319 if (enable_pio)
1320 sci_start_rx(port);
1321}
1322
1323static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1324{
1325 struct dma_chan *chan = s->chan_tx;
1326 struct uart_port *port = &s->port;
73a19e4c
GL		 1327
1328 s->chan_tx = NULL;
1329 s->cookie_tx = -EINVAL;
1330 dma_release_channel(chan);
1331 if (enable_pio)
1332 sci_start_tx(port);
1333}
1334
1335static void sci_submit_rx(struct sci_port *s)
1336{
1337 struct dma_chan *chan = s->chan_rx;
1338 int i;
1339
1340 for (i = 0; i < 2; i++) {
1341 struct scatterlist *sg = &s->sg_rx[i];
1342 struct dma_async_tx_descriptor *desc;
1343
16052827 1344 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1345 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1346
1347 if (desc) {
1348 s->desc_rx[i] = desc;
1349 desc->callback = sci_dma_rx_complete;
1350 desc->callback_param = s;
1351 s->cookie_rx[i] = desc->tx_submit(desc);
1352 }
1353
1354 if (!desc || s->cookie_rx[i] < 0) {
1355 if (i) {
1356 async_tx_ack(s->desc_rx[0]);
1357 s->cookie_rx[0] = -EINVAL;
1358 }
1359 if (desc) {
1360 async_tx_ack(desc);
1361 s->cookie_rx[i] = -EINVAL;
1362 }
1363 dev_warn(s->port.dev,
1364 "failed to re-start DMA, using PIO\n");
1365 sci_rx_dma_release(s, true);
1366 return;
1367 }
3089f381
GL		 1368 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1369 s->cookie_rx[i], i);
73a19e4c
GL		 1370 }
1371
1372 s->active_rx = s->cookie_rx[0];
1373
1374 dma_async_issue_pending(chan);
1375}
1376
1377static void work_fn_rx(struct work_struct *work)
1378{
1379 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1380 struct uart_port *port = &s->port;
1381 struct dma_async_tx_descriptor *desc;
1382 int new;
1383
1384 if (s->active_rx == s->cookie_rx[0]) {
1385 new = 0;
1386 } else if (s->active_rx == s->cookie_rx[1]) {
1387 new = 1;
1388 } else {
1389 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1390 return;
1391 }
1392 desc = s->desc_rx[new];
1393
1394 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1395 DMA_SUCCESS) {
1396 /* Handle incomplete DMA receive */
1397 struct tty_struct *tty = port->state->port.tty;
1398 struct dma_chan *chan = s->chan_rx;
1399 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1400 async_tx);
1401 unsigned long flags;
1402 int count;
1403
05827630 1404 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1405 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1406 sh_desc->partial, sh_desc->cookie);
1407
1408 spin_lock_irqsave(&port->lock, flags);
1409 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1410 spin_unlock_irqrestore(&port->lock, flags);
1411
1412 if (count)
1413 tty_flip_buffer_push(tty);
1414
1415 sci_submit_rx(s);
1416
1417 return;
1418 }
1419
1420 s->cookie_rx[new] = desc->tx_submit(desc);
1421 if (s->cookie_rx[new] < 0) {
1422 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1423 sci_rx_dma_release(s, true);
1424 return;
1425 }
1426
73a19e4c 1427 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1428
1429 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1430 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1431}
1432
1433static void work_fn_tx(struct work_struct *work)
1434{
1435 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1436 struct dma_async_tx_descriptor *desc;
1437 struct dma_chan *chan = s->chan_tx;
1438 struct uart_port *port = &s->port;
1439 struct circ_buf *xmit = &port->state->xmit;
1440 struct scatterlist *sg = &s->sg_tx;
1441
1442 /*
1443 * DMA is idle now.
1444 * Port xmit buffer is already mapped, and it is one page... Just adjust
1445 * offsets and lengths. Since it is a circular buffer, we have to
1446 * transmit till the end, and then the rest. Take the port lock to get a
1447 * consistent xmit buffer state.
1448 */
1449 spin_lock_irq(&port->lock);
1450 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1451 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1452 sg->offset;
f354a381 1453 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1454 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1455 spin_unlock_irq(&port->lock);
1456
f354a381 1457 BUG_ON(!sg_dma_len(sg));
73a19e4c 1458
16052827 1459 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1460 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1461 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1462 if (!desc) {
1463 /* switch to PIO */
1464 sci_tx_dma_release(s, true);
1465 return;
1466 }
1467
1468 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1469
1470 spin_lock_irq(&port->lock);
1471 s->desc_tx = desc;
1472 desc->callback = sci_dma_tx_complete;
1473 desc->callback_param = s;
1474 spin_unlock_irq(&port->lock);
1475 s->cookie_tx = desc->tx_submit(desc);
1476 if (s->cookie_tx < 0) {
1477 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1478 /* switch to PIO */
1479 sci_tx_dma_release(s, true);
1480 return;
1481 }
1482
1483 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1484 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1485
1486 dma_async_issue_pending(chan);
1487}
1488#endif
1489
b129a8cc 1490static void sci_start_tx(struct uart_port *port)
1da177e4 1491{
3089f381 1492 struct sci_port *s = to_sci_port(port);
e108b2ca 1493 unsigned short ctrl;
1da177e4 1494
73a19e4c 1495#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1496 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1497 u16 new, scr = sci_in(port, SCSCR);
1498 if (s->chan_tx)
1499 new = scr | 0x8000;
1500 else
1501 new = scr & ~0x8000;
1502 if (new != scr)
1503 sci_out(port, SCSCR, new);
73a19e4c 1504 }
f43dc23d 1505
3089f381 1506 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1507 s->cookie_tx < 0) {
1508 s->cookie_tx = 0;
3089f381 1509 schedule_work(&s->work_tx);
49d4bcad 1510 }
73a19e4c 1511#endif
f43dc23d 1512
d1d4b10c 1513 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1514 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1515 ctrl = sci_in(port, SCSCR);
f43dc23d 1516 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1517 }
1da177e4
LT		 1518}
1519
b129a8cc 1520static void sci_stop_tx(struct uart_port *port)
1da177e4 1521{
1da177e4
LT		 1522 unsigned short ctrl;
1523
1524 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1525 ctrl = sci_in(port, SCSCR);
f43dc23d 1526
d1d4b10c 1527 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1528 ctrl &= ~0x8000;
f43dc23d 1529
8e698614 1530 ctrl &= ~SCSCR_TIE;
f43dc23d 1531
1da177e4 1532 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1533}
1534
73a19e4c 1535static void sci_start_rx(struct uart_port *port)
1da177e4 1536{
1da177e4
LT		 1537 unsigned short ctrl;
1538
f43dc23d 1539 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1540
d1d4b10c 1541 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1542 ctrl &= ~0x4000;
f43dc23d 1543
1da177e4 1544 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1545}
1546
1547static void sci_stop_rx(struct uart_port *port)
1548{
1da177e4
LT		 1549 unsigned short ctrl;
1550
1da177e4 1551 ctrl = sci_in(port, SCSCR);
f43dc23d 1552
d1d4b10c 1553 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1554 ctrl &= ~0x4000;
f43dc23d
PM		 1555
1556 ctrl &= ~port_rx_irq_mask(port);
1557
1da177e4 1558 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1559}
1560
1561static void sci_enable_ms(struct uart_port *port)
1562{
d39ec6ce
PM		 1563 /*
1564 * Not supported by hardware, always a nop.
1565 */
1da177e4
LT		 1566}
1567
1568static void sci_break_ctl(struct uart_port *port, int break_state)
1569{
d39ec6ce
PM		 1570 /*
1571 * Not supported by hardware. Most parts couple break and rx
1572 * interrupts together, with break detection always enabled.
1573 */
1da177e4
LT		 1574}
1575
73a19e4c
GL		 1576#ifdef CONFIG_SERIAL_SH_SCI_DMA
1577static bool filter(struct dma_chan *chan, void *slave)
1578{
1579 struct sh_dmae_slave *param = slave;
1580
1581 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1582 param->slave_id);
1583
937bb6e4
GL		 1584 chan->private = param;
1585 return true;
73a19e4c
GL		 1586}
1587
1588static void rx_timer_fn(unsigned long arg)
1589{
1590 struct sci_port *s = (struct sci_port *)arg;
1591 struct uart_port *port = &s->port;
73a19e4c 1592 u16 scr = sci_in(port, SCSCR);
3089f381 1593
d1d4b10c 1594 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1595 scr &= ~0x4000;
ce6738b6 1596 enable_irq(s->cfg->irqs[1]);
3089f381 1597 }
f43dc23d 1598 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1599 dev_dbg(port->dev, "DMA Rx timed out\n");
1600 schedule_work(&s->work_rx);
1601}
1602
1603static void sci_request_dma(struct uart_port *port)
1604{
1605 struct sci_port *s = to_sci_port(port);
1606 struct sh_dmae_slave *param;
1607 struct dma_chan *chan;
1608 dma_cap_mask_t mask;
1609 int nent;
1610
937bb6e4
GL		 1611 dev_dbg(port->dev, "%s: port %d\n", __func__,
1612 port->line);
73a19e4c 1613
937bb6e4 1614 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1615 return;
1616
1617 dma_cap_zero(mask);
1618 dma_cap_set(DMA_SLAVE, mask);
1619
1620 param = &s->param_tx;
1621
1622 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6 1623 param->slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1624
1625 s->cookie_tx = -EINVAL;
1626 chan = dma_request_channel(mask, filter, param);
1627 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1628 if (chan) {
1629 s->chan_tx = chan;
1630 sg_init_table(&s->sg_tx, 1);
1631 /* UART circular tx buffer is an aligned page. */
1632 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1633 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1634 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1635 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1636 if (!nent)
1637 sci_tx_dma_release(s, false);
1638 else
1639 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1640 sg_dma_len(&s->sg_tx),
1641 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1642
1643 s->sg_len_tx = nent;
1644
1645 INIT_WORK(&s->work_tx, work_fn_tx);
1646 }
1647
1648 param = &s->param_rx;
1649
1650 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6 1651 param->slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1652
1653 chan = dma_request_channel(mask, filter, param);
1654 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1655 if (chan) {
1656 dma_addr_t dma[2];
1657 void *buf[2];
1658 int i;
1659
1660 s->chan_rx = chan;
1661
1662 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1663 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1664 &dma[0], GFP_KERNEL);
1665
1666 if (!buf[0]) {
1667 dev_warn(port->dev,
1668 "failed to allocate dma buffer, using PIO\n");
1669 sci_rx_dma_release(s, true);
1670 return;
1671 }
1672
1673 buf[1] = buf[0] + s->buf_len_rx;
1674 dma[1] = dma[0] + s->buf_len_rx;
1675
1676 for (i = 0; i < 2; i++) {
1677 struct scatterlist *sg = &s->sg_rx[i];
1678
1679 sg_init_table(sg, 1);
1680 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1681 (int)buf[i] & ~PAGE_MASK);
f354a381 1682 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1683 }
1684
1685 INIT_WORK(&s->work_rx, work_fn_rx);
1686 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1687
1688 sci_submit_rx(s);
1689 }
1690}
1691
1692static void sci_free_dma(struct uart_port *port)
1693{
1694 struct sci_port *s = to_sci_port(port);
1695
73a19e4c
GL		 1696 if (s->chan_tx)
1697 sci_tx_dma_release(s, false);
1698 if (s->chan_rx)
1699 sci_rx_dma_release(s, false);
1700}
27bd1075
PM		 1701#else
1702static inline void sci_request_dma(struct uart_port *port)
1703{
1704}
1705
1706static inline void sci_free_dma(struct uart_port *port)
1707{
1708}
73a19e4c
GL		 1709#endif
1710
1da177e4
LT		 1711static int sci_startup(struct uart_port *port)
1712{
a5660ada 1713 struct sci_port *s = to_sci_port(port);
073e84c9 1714 int ret;
1da177e4 1715
73a19e4c
GL		 1716 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1717
048be431
RW		 1718 pm_runtime_put_noidle(port->dev);
1719
23241d43 1720 sci_port_enable(s);
1da177e4 1721
073e84c9
PM		 1722 ret = sci_request_irq(s);
1723 if (unlikely(ret < 0))
1724 return ret;
1725
73a19e4c 1726 sci_request_dma(port);
073e84c9 1727
d656901b 1728 sci_start_tx(port);
73a19e4c 1729 sci_start_rx(port);
1da177e4
LT		 1730
1731 return 0;
1732}
1733
1734static void sci_shutdown(struct uart_port *port)
1735{
a5660ada 1736 struct sci_port *s = to_sci_port(port);
1da177e4 1737
73a19e4c
GL		 1738 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1739
1da177e4 1740 sci_stop_rx(port);
b129a8cc 1741 sci_stop_tx(port);
073e84c9 1742
73a19e4c 1743 sci_free_dma(port);
1da177e4
LT		 1744 sci_free_irq(s);
1745
23241d43 1746 sci_port_disable(s);
048be431
RW		 1747
1748 pm_runtime_get_noresume(port->dev);
1da177e4
LT		 1749}
1750
26c92f37
PM		 1751static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1752 unsigned long freq)
1753{
1754 switch (algo_id) {
1755 case SCBRR_ALGO_1:
1756 return ((freq + 16 * bps) / (16 * bps) - 1);
1757 case SCBRR_ALGO_2:
1758 return ((freq + 16 * bps) / (32 * bps) - 1);
1759 case SCBRR_ALGO_3:
1760 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1761 case SCBRR_ALGO_4:
1762 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1763 case SCBRR_ALGO_5:
1764 return (((freq * 1000 / 32) / bps) - 1);
1765 }
1766
1767 /* Warn, but use a safe default */
1768 WARN_ON(1);
e8183a6c 1769
26c92f37
PM		 1770 return ((freq + 16 * bps) / (32 * bps) - 1);
1771}
1772
1ba76220
MD		 1773static void sci_reset(struct uart_port *port)
1774{
0979e0e6 1775 struct plat_sci_reg *reg;
1ba76220
MD		 1776 unsigned int status;
1777
1778 do {
1779 status = sci_in(port, SCxSR);
1780 } while (!(status & SCxSR_TEND(port)));
1781
1782 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1783
0979e0e6
PM		 1784 reg = sci_getreg(port, SCFCR);
1785 if (reg->size)
1ba76220
MD		 1786 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1787}
1788
606d099c
AC		 1789static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1790 struct ktermios *old)
1da177e4 1791{
00b9de9c 1792 struct sci_port *s = to_sci_port(port);
0979e0e6 1793 struct plat_sci_reg *reg;
1ba76220 1794 unsigned int baud, smr_val, max_baud;
a2159b52 1795 int t = -1;
1da177e4 1796
154280fd
MD		 1797 /*
1798 * earlyprintk comes here early on with port->uartclk set to zero.
1799 * the clock framework is not up and running at this point so here
1800 * we assume that 115200 is the maximum baud rate. please note that
1801 * the baud rate is not programmed during earlyprintk - it is assumed
1802 * that the previous boot loader has enabled required clocks and
1803 * setup the baud rate generator hardware for us already.
1804 */
1805 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1806
154280fd
MD		 1807 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1808 if (likely(baud && port->uartclk))
ce6738b6 1809 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1810
23241d43 1811 sci_port_enable(s);
36003386 1812
1ba76220 1813 sci_reset(port);
1da177e4
LT		 1814
1815 smr_val = sci_in(port, SCSMR) & 3;
e8183a6c 1816
1da177e4
LT		 1817 if ((termios->c_cflag & CSIZE) == CS7)
1818 smr_val |= 0x40;
1819 if (termios->c_cflag & PARENB)
1820 smr_val |= 0x20;
1821 if (termios->c_cflag & PARODD)
1822 smr_val |= 0x30;
1823 if (termios->c_cflag & CSTOPB)
1824 smr_val |= 0x08;
1825
1826 uart_update_timeout(port, termios->c_cflag, baud);
1827
1828 sci_out(port, SCSMR, smr_val);
1829
73a19e4c 1830 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1831 s->cfg->scscr);
73a19e4c 1832
1da177e4 1833 if (t > 0) {
e7c98dc7 1834 if (t >= 256) {
1da177e4
LT		 1835 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1836 t >>= 2;
e7c98dc7 1837 } else
1da177e4 1838 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1839
1da177e4
LT		 1840 sci_out(port, SCBRR, t);
1841 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1842 }
1843
d5701647 1844 sci_init_pins(port, termios->c_cflag);
0979e0e6 1845
73c3d53f
PM		 1846 reg = sci_getreg(port, SCFCR);
1847 if (reg->size) {
1848 unsigned short ctrl = sci_in(port, SCFCR);
0979e0e6 1849
73c3d53f 1850 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1851 if (termios->c_cflag & CRTSCTS)
1852 ctrl |= SCFCR_MCE;
1853 else
1854 ctrl &= ~SCFCR_MCE;
faf02f8f 1855 }
73c3d53f
PM		 1856
1857 /*
1858 * As we've done a sci_reset() above, ensure we don't
1859 * interfere with the FIFOs while toggling MCE. As the
1860 * reset values could still be set, simply mask them out.
1861 */
1862 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1863
1864 sci_out(port, SCFCR, ctrl);
0979e0e6 1865 }
b7a76e4b 1866
ce6738b6 1867 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1868
3089f381
GL		 1869#ifdef CONFIG_SERIAL_SH_SCI_DMA
1870 /*
1871 * Calculate delay for 1.5 DMA buffers: see
1872 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1873 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1874 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1875 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1876 * sizes), but it has been found out experimentally, that this is not
1877 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1878 * as a minimum seem to work perfectly.
1879 */
1880 if (s->chan_rx) {
1881 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1882 port->fifosize / 2;
1883 dev_dbg(port->dev,
1884 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1885 s->rx_timeout * 1000 / HZ, port->timeout);
1886 if (s->rx_timeout < msecs_to_jiffies(20))
1887 s->rx_timeout = msecs_to_jiffies(20);
1888 }
1889#endif
1890
1da177e4 1891 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1892 sci_start_rx(port);
36003386 1893
23241d43 1894 sci_port_disable(s);
1da177e4
LT		 1895}
1896
1897static const char *sci_type(struct uart_port *port)
1898{
1899 switch (port->type) {
e7c98dc7
MT		 1900 case PORT_IRDA:
1901 return "irda";
1902 case PORT_SCI:
1903 return "sci";
1904 case PORT_SCIF:
1905 return "scif";
1906 case PORT_SCIFA:
1907 return "scifa";
d1d4b10c
GL		 1908 case PORT_SCIFB:
1909 return "scifb";
1da177e4
LT		 1910 }
1911
fa43972f 1912 return NULL;
1da177e4
LT		 1913}
1914
e2651647 1915static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1916{
e2651647
PM		 1917 /*
1918 * Pick an arbitrary size that encapsulates all of the base
1919 * registers by default. This can be optimized later, or derived
1920 * from platform resource data at such a time that ports begin to
1921 * behave more erratically.
1922 */
1923 return 64;
1da177e4
LT		 1924}
1925
f6e9495d
PM		 1926static int sci_remap_port(struct uart_port *port)
1927{
1928 unsigned long size = sci_port_size(port);
1929
1930 /*
1931 * Nothing to do if there's already an established membase.
1932 */
1933 if (port->membase)
1934 return 0;
1935
1936 if (port->flags & UPF_IOREMAP) {
1937 port->membase = ioremap_nocache(port->mapbase, size);
1938 if (unlikely(!port->membase)) {
1939 dev_err(port->dev, "can't remap port#%d\n", port->line);
1940 return -ENXIO;
1941 }
1942 } else {
1943 /*
1944 * For the simple (and majority of) cases where we don't
1945 * need to do any remapping, just cast the cookie
1946 * directly.
1947 */
1948 port->membase = (void __iomem *)port->mapbase;
1949 }
1950
1951 return 0;
1952}
1953
e2651647 1954static void sci_release_port(struct uart_port *port)
1da177e4 1955{
e2651647
PM		 1956 if (port->flags & UPF_IOREMAP) {
1957 iounmap(port->membase);
1958 port->membase = NULL;
1959 }
1960
1961 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1962}
1963
e2651647 1964static int sci_request_port(struct uart_port *port)
1da177e4 1965{
e2651647
PM		 1966 unsigned long size = sci_port_size(port);
1967 struct resource *res;
f6e9495d 1968 int ret;
1da177e4 1969
1020520e 1970 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 1971 if (unlikely(res == NULL))
1972 return -EBUSY;
1da177e4 1973
f6e9495d
PM		 1974 ret = sci_remap_port(port);
1975 if (unlikely(ret != 0)) {
1976 release_resource(res);
1977 return ret;
7ff731ae 1978 }
e2651647
PM		 1979
1980 return 0;
1981}
1982
1983static void sci_config_port(struct uart_port *port, int flags)
1984{
1985 if (flags & UART_CONFIG_TYPE) {
1986 struct sci_port *sport = to_sci_port(port);
1987
1988 port->type = sport->cfg->type;
1989 sci_request_port(port);
1990 }
1da177e4
LT		 1991}
1992
1993static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1994{
a5660ada 1995 struct sci_port *s = to_sci_port(port);
1da177e4 1996
ce6738b6 1997 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1998 return -EINVAL;
1999 if (ser->baud_base < 2400)
2000 /* No paper tape reader for Mitch.. */
2001 return -EINVAL;
2002
2003 return 0;
2004}
2005
2006static struct uart_ops sci_uart_ops = {
2007 .tx_empty = sci_tx_empty,
2008 .set_mctrl = sci_set_mctrl,
2009 .get_mctrl = sci_get_mctrl,
2010 .start_tx = sci_start_tx,
2011 .stop_tx = sci_stop_tx,
2012 .stop_rx = sci_stop_rx,
2013 .enable_ms = sci_enable_ms,
2014 .break_ctl = sci_break_ctl,
2015 .startup = sci_startup,
2016 .shutdown = sci_shutdown,
2017 .set_termios = sci_set_termios,
2018 .type = sci_type,
2019 .release_port = sci_release_port,
2020 .request_port = sci_request_port,
2021 .config_port = sci_config_port,
2022 .verify_port = sci_verify_port,
07d2a1a1
PM		 2023#ifdef CONFIG_CONSOLE_POLL
2024 .poll_get_char = sci_poll_get_char,
2025 .poll_put_char = sci_poll_put_char,
2026#endif
1da177e4
LT		 2027};
2028
c7ed1ab3
PM		 2029static int __devinit sci_init_single(struct platform_device *dev,
2030 struct sci_port *sci_port,
2031 unsigned int index,
2032 struct plat_sci_port *p)
e108b2ca 2033{
73a19e4c 2034 struct uart_port *port = &sci_port->port;
3127c6b2 2035 int ret;
e108b2ca 2036
50f0959a
PM		 2037 sci_port->cfg = p;
2038
73a19e4c
GL		 2039 port->ops = &sci_uart_ops;
2040 port->iotype = UPIO_MEM;
2041 port->line = index;
75136d48
MP		 2042
2043 switch (p->type) {
d1d4b10c
GL		 2044 case PORT_SCIFB:
2045 port->fifosize = 256;
2046 break;
75136d48 2047 case PORT_SCIFA:
73a19e4c 2048 port->fifosize = 64;
75136d48
MP		 2049 break;
2050 case PORT_SCIF:
73a19e4c 2051 port->fifosize = 16;
75136d48
MP		 2052 break;
2053 default:
73a19e4c 2054 port->fifosize = 1;
75136d48
MP		 2055 break;
2056 }
7b6fd3bf 2057
3127c6b2
PM		 2058 if (p->regtype == SCIx_PROBE_REGTYPE) {
2059 ret = sci_probe_regmap(p);
fc97114b 2060 if (unlikely(ret))
3127c6b2
PM		 2061 return ret;
2062 }
61a6976b 2063
7b6fd3bf 2064 if (dev) {
c7ed1ab3
PM		 2065 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2066 if (IS_ERR(sci_port->iclk)) {
2067 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2068 if (IS_ERR(sci_port->iclk)) {
2069 dev_err(&dev->dev, "can't get iclk\n");
2070 return PTR_ERR(sci_port->iclk);
2071 }
2072 }
2073
2074 /*
2075 * The function clock is optional, ignore it if we can't
2076 * find it.
2077 */
2078 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2079 if (IS_ERR(sci_port->fclk))
2080 sci_port->fclk = NULL;
2081
73a19e4c 2082 port->dev = &dev->dev;
5e50d2d6 2083
50f0959a
PM		 2084 sci_init_gpios(sci_port);
2085
5a50a01b 2086 pm_runtime_irq_safe(&dev->dev);
048be431 2087 pm_runtime_get_noresume(&dev->dev);
5e50d2d6 2088 pm_runtime_enable(&dev->dev);
7b6fd3bf 2089 }
e108b2ca 2090
7ed7e071
MD		 2091 sci_port->break_timer.data = (unsigned long)sci_port;
2092 sci_port->break_timer.function = sci_break_timer;
2093 init_timer(&sci_port->break_timer);
2094
debf9507
PM		 2095 /*
2096 * Establish some sensible defaults for the error detection.
2097 */
2098 if (!p->error_mask)
2099 p->error_mask = (p->type == PORT_SCI) ?
2100 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2101
2102 /*
2103 * Establish sensible defaults for the overrun detection, unless
2104 * the part has explicitly disabled support for it.
2105 */
2106 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2107 if (p->type == PORT_SCI)
2108 p->overrun_bit = 5;
2109 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2110 p->overrun_bit = 9;
2111 else
2112 p->overrun_bit = 0;
2113
2114 /*
2115 * Make the error mask inclusive of overrun detection, if
2116 * supported.
2117 */
2118 p->error_mask |= (1 << p->overrun_bit);
2119 }
2120
ce6738b6
PM		 2121 port->mapbase = p->mapbase;
2122 port->type = p->type;
f43dc23d 2123 port->flags = p->flags;
61a6976b 2124 port->regshift = p->regshift;
73a19e4c 2125
ce6738b6 2126 /*
61a6976b 2127 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2128 * for the multi-IRQ ports, which is where we are primarily
2129 * concerned with the shutdown path synchronization.
2130 *
2131 * For the muxed case there's nothing more to do.
2132 */
54aa89ea 2133 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2134 port->irqflags = 0;
73a19e4c 2135
61a6976b
PM		 2136 port->serial_in = sci_serial_in;
2137 port->serial_out = sci_serial_out;
2138
937bb6e4
GL		 2139 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2140 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2141 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2142
c7ed1ab3 2143 return 0;
e108b2ca
PM		 2144}
2145
1da177e4 2146#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2147static void serial_console_putchar(struct uart_port *port, int ch)
2148{
2149 sci_poll_put_char(port, ch);
2150}
2151
1da177e4
LT		 2152/*
2153 * Print a string to the serial port trying not to disturb
2154 * any possible real use of the port...
2155 */
2156static void serial_console_write(struct console *co, const char *s,
2157 unsigned count)
2158{
906b17dc
PM		 2159 struct sci_port *sci_port = &sci_ports[co->index];
2160 struct uart_port *port = &sci_port->port;
973e5d52 2161 unsigned short bits;
07d2a1a1 2162
23241d43 2163 sci_port_enable(sci_port);
501b825d
MD		 2164
2165 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2166
2167 /* wait until fifo is empty and last bit has been transmitted */
2168 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2169 while ((sci_in(port, SCxSR) & bits) != bits)
2170 cpu_relax();
501b825d 2171
23241d43 2172 sci_port_disable(sci_port);
1da177e4
LT		 2173}
2174
7b6fd3bf 2175static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 2176{
dc8e6f5b 2177 struct sci_port *sci_port;
1da177e4
LT		 2178 struct uart_port *port;
2179 int baud = 115200;
2180 int bits = 8;
2181 int parity = 'n';
2182 int flow = 'n';
2183 int ret;
2184
e108b2ca 2185 /*
906b17dc 2186 * Refuse to handle any bogus ports.
1da177e4 2187 */
906b17dc 2188 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2189 return -ENODEV;
e108b2ca 2190
906b17dc
PM		 2191 sci_port = &sci_ports[co->index];
2192 port = &sci_port->port;
2193
b2267a6b
AC		 2194 /*
2195 * Refuse to handle uninitialized ports.
2196 */
2197 if (!port->ops)
2198 return -ENODEV;
2199
f6e9495d
PM		 2200 ret = sci_remap_port(port);
2201 if (unlikely(ret != 0))
2202 return ret;
e108b2ca 2203
23241d43 2204 sci_port_enable(sci_port);
b7a76e4b 2205
1da177e4
LT		 2206 if (options)
2207 uart_parse_options(options, &baud, &parity, &bits, &flow);
2208
1ba76220
MD		 2209 sci_port_disable(sci_port);
2210
ab7cfb55 2211 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2212}
2213
2214static struct console serial_console = {
2215 .name = "ttySC",
906b17dc 2216 .device = uart_console_device,
1da177e4
LT		 2217 .write = serial_console_write,
2218 .setup = serial_console_setup,
fa5da2f7 2219 .flags = CON_PRINTBUFFER,
1da177e4 2220 .index = -1,
906b17dc 2221 .data = &sci_uart_driver,
1da177e4
LT		 2222};
2223
7b6fd3bf
MD		 2224static struct console early_serial_console = {
2225 .name = "early_ttySC",
2226 .write = serial_console_write,
2227 .flags = CON_PRINTBUFFER,
906b17dc 2228 .index = -1,
7b6fd3bf 2229};
ecdf8a46 2230
7b6fd3bf
MD		 2231static char early_serial_buf[32];
2232
ecdf8a46
PM		 2233static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2234{
2235 struct plat_sci_port *cfg = pdev->dev.platform_data;
2236
2237 if (early_serial_console.data)
2238 return -EEXIST;
2239
2240 early_serial_console.index = pdev->id;
ecdf8a46 2241
906b17dc 2242 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2243
2244 serial_console_setup(&early_serial_console, early_serial_buf);
2245
2246 if (!strstr(early_serial_buf, "keep"))
2247 early_serial_console.flags |= CON_BOOT;
2248
2249 register_console(&early_serial_console);
2250 return 0;
2251}
6a8c9799 2252
1ba76220
MD		 2253#define uart_console(port) ((port)->cons->index == (port)->line)
2254
2255static int sci_runtime_suspend(struct device *dev)
2256{
2257 struct sci_port *sci_port = dev_get_drvdata(dev);
2258 struct uart_port *port = &sci_port->port;
2259
2260 if (uart_console(port)) {
0979e0e6
PM		 2261 struct plat_sci_reg *reg;
2262
1ba76220
MD		 2263 sci_port->saved_smr = sci_in(port, SCSMR);
2264 sci_port->saved_brr = sci_in(port, SCBRR);
0979e0e6
PM		 2265
2266 reg = sci_getreg(port, SCFCR);
2267 if (reg->size)
2268 sci_port->saved_fcr = sci_in(port, SCFCR);
2269 else
2270 sci_port->saved_fcr = 0;
1ba76220
MD		 2271 }
2272 return 0;
2273}
2274
2275static int sci_runtime_resume(struct device *dev)
2276{
2277 struct sci_port *sci_port = dev_get_drvdata(dev);
2278 struct uart_port *port = &sci_port->port;
2279
2280 if (uart_console(port)) {
2281 sci_reset(port);
2282 sci_out(port, SCSMR, sci_port->saved_smr);
2283 sci_out(port, SCBRR, sci_port->saved_brr);
0979e0e6
PM		 2284
2285 if (sci_port->saved_fcr)
2286 sci_out(port, SCFCR, sci_port->saved_fcr);
2287
1ba76220
MD		 2288 sci_out(port, SCSCR, sci_port->cfg->scscr);
2289 }
2290 return 0;
2291}
2292
6a8c9799
NI		 2293#define SCI_CONSOLE (&serial_console)
2294
ecdf8a46
PM		 2295#else
2296static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2297{
2298 return -EINVAL;
2299}
1da177e4 2300
6a8c9799 2301#define SCI_CONSOLE NULL
1ba76220
MD		 2302#define sci_runtime_suspend NULL
2303#define sci_runtime_resume NULL
6a8c9799
NI		 2304
2305#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2306
2307static char banner[] __initdata =
2308 KERN_INFO "SuperH SCI(F) driver initialized\n";
2309
2310static struct uart_driver sci_uart_driver = {
2311 .owner = THIS_MODULE,
2312 .driver_name = "sci",
1da177e4
LT		 2313 .dev_name = "ttySC",
2314 .major = SCI_MAJOR,
2315 .minor = SCI_MINOR_START,
e108b2ca 2316 .nr = SCI_NPORTS,
1da177e4
LT		 2317 .cons = SCI_CONSOLE,
2318};
2319
54507f6e 2320static int sci_remove(struct platform_device *dev)
e552de24 2321{
d535a230 2322 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2323
d535a230
PM		 2324 cpufreq_unregister_notifier(&port->freq_transition,
2325 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2326
50f0959a
PM		 2327 sci_free_gpios(port);
2328
d535a230
PM		 2329 uart_remove_one_port(&sci_uart_driver, &port->port);
2330
2331 clk_put(port->iclk);
2332 clk_put(port->fclk);
e552de24 2333
5e50d2d6 2334 pm_runtime_disable(&dev->dev);
e552de24
MD		 2335 return 0;
2336}
2337
0ee70712
MD		 2338static int __devinit sci_probe_single(struct platform_device *dev,
2339 unsigned int index,
2340 struct plat_sci_port *p,
2341 struct sci_port *sciport)
2342{
0ee70712
MD		 2343 int ret;
2344
2345 /* Sanity check */
2346 if (unlikely(index >= SCI_NPORTS)) {
2347 dev_notice(&dev->dev, "Attempting to register port "
2348 "%d when only %d are available.\n",
2349 index+1, SCI_NPORTS);
2350 dev_notice(&dev->dev, "Consider bumping "
2351 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2352 return 0;
2353 }
2354
c7ed1ab3
PM		 2355 ret = sci_init_single(dev, sciport, index, p);
2356 if (ret)
2357 return ret;
0ee70712 2358
d535a230 2359 return uart_add_one_port(&sci_uart_driver, &sciport->port);
0ee70712
MD		 2360}
2361
e108b2ca 2362static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2363{
e108b2ca 2364 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2365 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2366 int ret;
d535a230 2367
ecdf8a46
PM		 2368 /*
2369 * If we've come here via earlyprintk initialization, head off to
2370 * the special early probe. We don't have sufficient device state
2371 * to make it beyond this yet.
2372 */
2373 if (is_early_platform_device(dev))
2374 return sci_probe_earlyprintk(dev);
7b6fd3bf 2375
d535a230 2376 platform_set_drvdata(dev, sp);
e552de24 2377
906b17dc 2378 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230
PM		 2379 if (ret)
2380 goto err_unreg;
e552de24 2381
d535a230 2382 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2383
d535a230
PM		 2384 ret = cpufreq_register_notifier(&sp->freq_transition,
2385 CPUFREQ_TRANSITION_NOTIFIER);
2386 if (unlikely(ret < 0))
2387 goto err_unreg;
1da177e4
LT		 2388
2389#ifdef CONFIG_SH_STANDARD_BIOS
2390 sh_bios_gdb_detach();
2391#endif
2392
e108b2ca 2393 return 0;
7ff731ae
PM		 2394
2395err_unreg:
e552de24 2396 sci_remove(dev);
7ff731ae 2397 return ret;
1da177e4
LT		 2398}
2399
6daa79b3 2400static int sci_suspend(struct device *dev)
1da177e4 2401{
d535a230 2402 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2403
d535a230
PM		 2404 if (sport)
2405 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2406
e108b2ca
PM		 2407 return 0;
2408}
1da177e4 2409
6daa79b3 2410static int sci_resume(struct device *dev)
e108b2ca 2411{
d535a230 2412 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2413
d535a230
PM		 2414 if (sport)
2415 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2416
2417 return 0;
2418}
2419
47145210 2420static const struct dev_pm_ops sci_dev_pm_ops = {
1ba76220
MD		 2421 .runtime_suspend = sci_runtime_suspend,
2422 .runtime_resume = sci_runtime_resume,
6daa79b3
PM		 2423 .suspend = sci_suspend,
2424 .resume = sci_resume,
2425};
2426
e108b2ca
PM		 2427static struct platform_driver sci_driver = {
2428 .probe = sci_probe,
b9e39c89 2429 .remove = sci_remove,
e108b2ca
PM		 2430 .driver = {
2431 .name = "sh-sci",
2432 .owner = THIS_MODULE,
6daa79b3 2433 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2434 },
2435};
2436
2437static int __init sci_init(void)
2438{
2439 int ret;
2440
2441 printk(banner);
2442
e108b2ca
PM		 2443 ret = uart_register_driver(&sci_uart_driver);
2444 if (likely(ret == 0)) {
2445 ret = platform_driver_register(&sci_driver);
2446 if (unlikely(ret))
2447 uart_unregister_driver(&sci_uart_driver);
2448 }
2449
2450 return ret;
2451}
2452
2453static void __exit sci_exit(void)
2454{
2455 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2456 uart_unregister_driver(&sci_uart_driver);
2457}
2458
7b6fd3bf
MD		 2459#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2460early_platform_init_buffer("earlyprintk", &sci_driver,
2461 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2462#endif
1da177e4
LT		 2463module_init(sci_init);
2464module_exit(sci_exit);
2465
e108b2ca 2466MODULE_LICENSE("GPL");
e169c139 2467MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2468MODULE_AUTHOR("Paul Mundt");
2469MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux kernel - Deliverables
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