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serial: sh-sci: per-port modem control.
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
1da177e4
LT		 28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
e108b2ca 41#include <linux/platform_device.h>
96de1a8f 42#include <linux/serial_sci.h>
1da177e4 43#include <linux/notifier.h>
5e50d2d6 44#include <linux/pm_runtime.h>
1da177e4 45#include <linux/cpufreq.h>
85f094ec 46#include <linux/clk.h>
fa5da2f7 47#include <linux/ctype.h>
7ff731ae 48#include <linux/err.h>
73a19e4c 49#include <linux/dmaengine.h>
5beabc7f 50#include <linux/dma-mapping.h>
73a19e4c 51#include <linux/scatterlist.h>
5a0e3ad6 52#include <linux/slab.h>
85f094ec
PM		 53
54#ifdef CONFIG_SUPERH
1da177e4
LT		 55#include <asm/sh_bios.h>
56#endif
57
1da177e4
LT		 58#include "sh-sci.h"
59
e108b2ca
PM		 60struct sci_port {
61 struct uart_port port;
62
ce6738b6
PM		 63 /* Platform configuration */
64 struct plat_sci_port *cfg;
e108b2ca 65
e108b2ca
PM		 66 /* Break timer */
67 struct timer_list break_timer;
68 int break_flag;
1534a3b3 69
501b825d
MD		 70 /* Interface clock */
71 struct clk *iclk;
c7ed1ab3
PM		 72 /* Function clock */
73 struct clk *fclk;
edad1f20 74
9174fc8f
PM		 75 char *irqstr[SCIx_NR_IRQS];
76
73a19e4c
GL		 77 struct dma_chan *chan_tx;
78 struct dma_chan *chan_rx;
f43dc23d 79
73a19e4c 80#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 81 struct dma_async_tx_descriptor *desc_tx;
82 struct dma_async_tx_descriptor *desc_rx[2];
83 dma_cookie_t cookie_tx;
84 dma_cookie_t cookie_rx[2];
85 dma_cookie_t active_rx;
86 struct scatterlist sg_tx;
87 unsigned int sg_len_tx;
88 struct scatterlist sg_rx[2];
89 size_t buf_len_rx;
90 struct sh_dmae_slave param_tx;
91 struct sh_dmae_slave param_rx;
92 struct work_struct work_tx;
93 struct work_struct work_rx;
94 struct timer_list rx_timer;
3089f381 95 unsigned int rx_timeout;
73a19e4c 96#endif
e552de24 97
d535a230 98 struct notifier_block freq_transition;
1ba76220
MD		 99
100#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
101 unsigned short saved_smr;
102 unsigned short saved_fcr;
103 unsigned char saved_brr;
104#endif
e108b2ca
PM		 105};
106
1da177e4 107/* Function prototypes */
d535a230 108static void sci_start_tx(struct uart_port *port);
b129a8cc 109static void sci_stop_tx(struct uart_port *port);
d535a230 110static void sci_start_rx(struct uart_port *port);
1da177e4 111
e108b2ca 112#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 113
e108b2ca
PM		 114static struct sci_port sci_ports[SCI_NPORTS];
115static struct uart_driver sci_uart_driver;
1da177e4 116
e7c98dc7
MT		 117static inline struct sci_port *
118to_sci_port(struct uart_port *uart)
119{
120 return container_of(uart, struct sci_port, port);
121}
122
61a6976b
PM		 123struct plat_sci_reg {
124 u8 offset, size;
125};
126
127/* Helper for invalidating specific entries of an inherited map. */
128#define sci_reg_invalid { .offset = 0, .size = 0 }
129
130static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
131 [SCIx_PROBE_REGTYPE] = {
132 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 },
134
135 /*
136 * Common SCI definitions, dependent on the port's regshift
137 * value.
138 */
139 [SCIx_SCI_REGTYPE] = {
140 [SCSMR] = { 0x00, 8 },
141 [SCBRR] = { 0x01, 8 },
142 [SCSCR] = { 0x02, 8 },
143 [SCxTDR] = { 0x03, 8 },
144 [SCxSR] = { 0x04, 8 },
145 [SCxRDR] = { 0x05, 8 },
146 [SCFCR] = sci_reg_invalid,
147 [SCFDR] = sci_reg_invalid,
148 [SCTFDR] = sci_reg_invalid,
149 [SCRFDR] = sci_reg_invalid,
150 [SCSPTR] = sci_reg_invalid,
151 [SCLSR] = sci_reg_invalid,
152 },
153
154 /*
155 * Common definitions for legacy IrDA ports, dependent on
156 * regshift value.
157 */
158 [SCIx_IRDA_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = { 0x06, 8 },
166 [SCFDR] = { 0x07, 16 },
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
171 },
172
173 /*
174 * Common SCIFA definitions.
175 */
176 [SCIx_SCIFA_REGTYPE] = {
177 [SCSMR] = { 0x00, 16 },
178 [SCBRR] = { 0x04, 8 },
179 [SCSCR] = { 0x08, 16 },
180 [SCxTDR] = { 0x20, 8 },
181 [SCxSR] = { 0x14, 16 },
182 [SCxRDR] = { 0x24, 8 },
183 [SCFCR] = { 0x18, 16 },
184 [SCFDR] = { 0x1c, 16 },
185 [SCTFDR] = sci_reg_invalid,
186 [SCRFDR] = sci_reg_invalid,
187 [SCSPTR] = sci_reg_invalid,
188 [SCLSR] = sci_reg_invalid,
189 },
190
191 /*
192 * Common SCIFB definitions.
193 */
194 [SCIx_SCIFB_REGTYPE] = {
195 [SCSMR] = { 0x00, 16 },
196 [SCBRR] = { 0x04, 8 },
197 [SCSCR] = { 0x08, 16 },
198 [SCxTDR] = { 0x40, 8 },
199 [SCxSR] = { 0x14, 16 },
200 [SCxRDR] = { 0x60, 8 },
201 [SCFCR] = { 0x18, 16 },
202 [SCFDR] = { 0x1c, 16 },
203 [SCTFDR] = sci_reg_invalid,
204 [SCRFDR] = sci_reg_invalid,
205 [SCSPTR] = sci_reg_invalid,
206 [SCLSR] = sci_reg_invalid,
207 },
208
3af1f8a4
PE		 209 /*
210 * Common SH-2(A) SCIF definitions for ports with FIFO data
211 * count registers.
212 */
213 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
214 [SCSMR] = { 0x00, 16 },
215 [SCBRR] = { 0x04, 8 },
216 [SCSCR] = { 0x08, 16 },
217 [SCxTDR] = { 0x0c, 8 },
218 [SCxSR] = { 0x10, 16 },
219 [SCxRDR] = { 0x14, 8 },
220 [SCFCR] = { 0x18, 16 },
221 [SCFDR] = { 0x1c, 16 },
222 [SCTFDR] = sci_reg_invalid,
223 [SCRFDR] = sci_reg_invalid,
224 [SCSPTR] = { 0x20, 16 },
225 [SCLSR] = { 0x24, 16 },
226 },
227
61a6976b
PM		 228 /*
229 * Common SH-3 SCIF definitions.
230 */
231 [SCIx_SH3_SCIF_REGTYPE] = {
232 [SCSMR] = { 0x00, 8 },
233 [SCBRR] = { 0x02, 8 },
234 [SCSCR] = { 0x04, 8 },
235 [SCxTDR] = { 0x06, 8 },
236 [SCxSR] = { 0x08, 16 },
237 [SCxRDR] = { 0x0a, 8 },
238 [SCFCR] = { 0x0c, 8 },
239 [SCFDR] = { 0x0e, 16 },
240 [SCTFDR] = sci_reg_invalid,
241 [SCRFDR] = sci_reg_invalid,
242 [SCSPTR] = sci_reg_invalid,
243 [SCLSR] = sci_reg_invalid,
244 },
245
246 /*
247 * Common SH-4(A) SCIF(B) definitions.
248 */
249 [SCIx_SH4_SCIF_REGTYPE] = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x0c, 8 },
254 [SCxSR] = { 0x10, 16 },
255 [SCxRDR] = { 0x14, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCFDR] = { 0x1c, 16 },
258 [SCTFDR] = sci_reg_invalid,
259 [SCRFDR] = sci_reg_invalid,
260 [SCSPTR] = { 0x20, 16 },
261 [SCLSR] = { 0x24, 16 },
262 },
263
264 /*
265 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
266 * register.
267 */
268 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
269 [SCSMR] = { 0x00, 16 },
270 [SCBRR] = { 0x04, 8 },
271 [SCSCR] = { 0x08, 16 },
272 [SCxTDR] = { 0x0c, 8 },
273 [SCxSR] = { 0x10, 16 },
274 [SCxRDR] = { 0x14, 8 },
275 [SCFCR] = { 0x18, 16 },
276 [SCFDR] = { 0x1c, 16 },
277 [SCTFDR] = sci_reg_invalid,
278 [SCRFDR] = sci_reg_invalid,
279 [SCSPTR] = sci_reg_invalid,
280 [SCLSR] = { 0x24, 16 },
281 },
282
283 /*
284 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
285 * count registers.
286 */
287 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
288 [SCSMR] = { 0x00, 16 },
289 [SCBRR] = { 0x04, 8 },
290 [SCSCR] = { 0x08, 16 },
291 [SCxTDR] = { 0x0c, 8 },
292 [SCxSR] = { 0x10, 16 },
293 [SCxRDR] = { 0x14, 8 },
294 [SCFCR] = { 0x18, 16 },
295 [SCFDR] = { 0x1c, 16 },
296 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
297 [SCRFDR] = { 0x20, 16 },
298 [SCSPTR] = { 0x24, 16 },
299 [SCLSR] = { 0x28, 16 },
300 },
301
302 /*
303 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
304 * registers.
305 */
306 [SCIx_SH7705_SCIF_REGTYPE] = {
307 [SCSMR] = { 0x00, 16 },
308 [SCBRR] = { 0x04, 8 },
309 [SCSCR] = { 0x08, 16 },
310 [SCxTDR] = { 0x20, 8 },
311 [SCxSR] = { 0x14, 16 },
312 [SCxRDR] = { 0x24, 8 },
313 [SCFCR] = { 0x18, 16 },
314 [SCFDR] = { 0x1c, 16 },
315 [SCTFDR] = sci_reg_invalid,
316 [SCRFDR] = sci_reg_invalid,
317 [SCSPTR] = sci_reg_invalid,
318 [SCLSR] = sci_reg_invalid,
319 },
320};
321
72b294cf
PM		 322#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
323
61a6976b
PM		 324/*
325 * The "offset" here is rather misleading, in that it refers to an enum
326 * value relative to the port mapping rather than the fixed offset
327 * itself, which needs to be manually retrieved from the platform's
328 * register map for the given port.
329 */
330static unsigned int sci_serial_in(struct uart_port *p, int offset)
331{
72b294cf 332 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 333
334 if (reg->size == 8)
335 return ioread8(p->membase + (reg->offset << p->regshift));
336 else if (reg->size == 16)
337 return ioread16(p->membase + (reg->offset << p->regshift));
338 else
339 WARN(1, "Invalid register access\n");
340
341 return 0;
342}
343
344static void sci_serial_out(struct uart_port *p, int offset, int value)
345{
72b294cf 346 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 347
348 if (reg->size == 8)
349 iowrite8(value, p->membase + (reg->offset << p->regshift));
350 else if (reg->size == 16)
351 iowrite16(value, p->membase + (reg->offset << p->regshift));
352 else
353 WARN(1, "Invalid register access\n");
354}
355
356#define sci_in(up, offset) (up->serial_in(up, offset))
357#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
358
359static int sci_probe_regmap(struct plat_sci_port *cfg)
360{
361 switch (cfg->type) {
362 case PORT_SCI:
363 cfg->regtype = SCIx_SCI_REGTYPE;
364 break;
365 case PORT_IRDA:
366 cfg->regtype = SCIx_IRDA_REGTYPE;
367 break;
368 case PORT_SCIFA:
369 cfg->regtype = SCIx_SCIFA_REGTYPE;
370 break;
371 case PORT_SCIFB:
372 cfg->regtype = SCIx_SCIFB_REGTYPE;
373 break;
374 case PORT_SCIF:
375 /*
376 * The SH-4 is a bit of a misnomer here, although that's
377 * where this particular port layout originated. This
378 * configuration (or some slight variation thereof)
379 * remains the dominant model for all SCIFs.
380 */
381 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
382 break;
383 default:
384 printk(KERN_ERR "Can't probe register map for given port\n");
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
23241d43
PM		 391static void sci_port_enable(struct sci_port *sci_port)
392{
393 if (!sci_port->port.dev)
394 return;
395
396 pm_runtime_get_sync(sci_port->port.dev);
397
398 clk_enable(sci_port->iclk);
399 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
400 clk_enable(sci_port->fclk);
401}
402
403static void sci_port_disable(struct sci_port *sci_port)
404{
405 if (!sci_port->port.dev)
406 return;
407
408 clk_disable(sci_port->fclk);
409 clk_disable(sci_port->iclk);
410
411 pm_runtime_put_sync(sci_port->port.dev);
412}
413
07d2a1a1 414#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 415
416#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 417static int sci_poll_get_char(struct uart_port *port)
1da177e4 418{
1da177e4
LT		 419 unsigned short status;
420 int c;
421
e108b2ca 422 do {
1da177e4
LT		 423 status = sci_in(port, SCxSR);
424 if (status & SCxSR_ERRORS(port)) {
94c8b6db 425 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 426 continue;
427 }
3f255eb3
JW		 428 break;
429 } while (1);
430
431 if (!(status & SCxSR_RDxF(port)))
432 return NO_POLL_CHAR;
07d2a1a1 433
1da177e4 434 c = sci_in(port, SCxRDR);
07d2a1a1 435
e7c98dc7
MT		 436 /* Dummy read */
437 sci_in(port, SCxSR);
1da177e4 438 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 439
440 return c;
441}
1f6fd5c9 442#endif
1da177e4 443
07d2a1a1 444static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 445{
1da177e4
LT		 446 unsigned short status;
447
1da177e4
LT		 448 do {
449 status = sci_in(port, SCxSR);
450 } while (!(status & SCxSR_TDxE(port)));
451
272966c0 452 sci_out(port, SCxTDR, c);
dd0a3e77 453 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 454}
07d2a1a1 455#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 456
61a6976b 457static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 458{
61a6976b
PM		 459 struct sci_port *s = to_sci_port(port);
460 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 461
61a6976b
PM		 462 /*
463 * Use port-specific handler if provided.
464 */
465 if (s->cfg->ops && s->cfg->ops->init_pins) {
466 s->cfg->ops->init_pins(port, cflag);
467 return;
1da177e4 468 }
41504c39 469
61a6976b
PM		 470 /*
471 * For the generic path SCSPTR is necessary. Bail out if that's
472 * unavailable, too.
473 */
474 if (!reg->size)
475 return;
41504c39 476
faf02f8f
PM		 477 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
478 ((!(cflag & CRTSCTS)))) {
479 unsigned short status;
480
481 status = sci_in(port, SCSPTR);
482 status &= ~SCSPTR_CTSIO;
483 status |= SCSPTR_RTSIO;
484 sci_out(port, SCSPTR, status); /* Set RTS = 1 */
485 }
d5701647 486}
e108b2ca 487
72b294cf 488static int sci_txfill(struct uart_port *port)
e108b2ca 489{
72b294cf 490 struct plat_sci_reg *reg;
e108b2ca 491
72b294cf
PM		 492 reg = sci_getreg(port, SCTFDR);
493 if (reg->size)
73a19e4c 494 return sci_in(port, SCTFDR) & 0xff;
c63847a3 495
72b294cf
PM		 496 reg = sci_getreg(port, SCFDR);
497 if (reg->size)
d1d4b10c 498 return sci_in(port, SCFDR) >> 8;
d1d4b10c 499
73a19e4c 500 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 501}
502
73a19e4c
GL		 503static int sci_txroom(struct uart_port *port)
504{
72b294cf 505 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 506}
507
508static int sci_rxfill(struct uart_port *port)
e108b2ca 509{
72b294cf
PM		 510 struct plat_sci_reg *reg;
511
512 reg = sci_getreg(port, SCRFDR);
513 if (reg->size)
514 return sci_in(port, SCRFDR) & 0xff;
515
516 reg = sci_getreg(port, SCFDR);
517 if (reg->size)
518 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
519
e7c98dc7 520 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 521}
522
514820eb
PM		 523/*
524 * SCI helper for checking the state of the muxed port/RXD pins.
525 */
526static inline int sci_rxd_in(struct uart_port *port)
527{
528 struct sci_port *s = to_sci_port(port);
529
530 if (s->cfg->port_reg <= 0)
531 return 1;
532
533 return !!__raw_readb(s->cfg->port_reg);
534}
535
1da177e4
LT		 536/* ********************************************************************** *
537 * the interrupt related routines *
538 * ********************************************************************** */
539
540static void sci_transmit_chars(struct uart_port *port)
541{
ebd2c8f6 542 struct circ_buf *xmit = &port->state->xmit;
1da177e4 543 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 544 unsigned short status;
545 unsigned short ctrl;
e108b2ca 546 int count;
1da177e4
LT		 547
548 status = sci_in(port, SCxSR);
549 if (!(status & SCxSR_TDxE(port))) {
1da177e4 550 ctrl = sci_in(port, SCSCR);
e7c98dc7 551 if (uart_circ_empty(xmit))
8e698614 552 ctrl &= ~SCSCR_TIE;
e7c98dc7 553 else
8e698614 554 ctrl |= SCSCR_TIE;
1da177e4 555 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 556 return;
557 }
558
72b294cf 559 count = sci_txroom(port);
1da177e4
LT		 560
561 do {
562 unsigned char c;
563
564 if (port->x_char) {
565 c = port->x_char;
566 port->x_char = 0;
567 } else if (!uart_circ_empty(xmit) && !stopped) {
568 c = xmit->buf[xmit->tail];
569 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
570 } else {
571 break;
572 }
573
574 sci_out(port, SCxTDR, c);
575
576 port->icount.tx++;
577 } while (--count > 0);
578
579 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
580
581 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
582 uart_write_wakeup(port);
583 if (uart_circ_empty(xmit)) {
b129a8cc 584 sci_stop_tx(port);
1da177e4 585 } else {
1da177e4
LT		 586 ctrl = sci_in(port, SCSCR);
587
1a22f08d 588 if (port->type != PORT_SCI) {
1da177e4
LT		 589 sci_in(port, SCxSR); /* Dummy read */
590 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
591 }
1da177e4 592
8e698614 593 ctrl |= SCSCR_TIE;
1da177e4 594 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 595 }
596}
597
598/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 599#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 600
94c8b6db 601static void sci_receive_chars(struct uart_port *port)
1da177e4 602{
e7c98dc7 603 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 604 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 605 int i, count, copied = 0;
606 unsigned short status;
33f0f88f 607 unsigned char flag;
1da177e4
LT		 608
609 status = sci_in(port, SCxSR);
610 if (!(status & SCxSR_RDxF(port)))
611 return;
612
613 while (1) {
1da177e4 614 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 615 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 616
617 /* If for any reason we can't copy more data, we're done! */
618 if (count == 0)
619 break;
620
621 if (port->type == PORT_SCI) {
622 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 623 if (uart_handle_sysrq_char(port, c) ||
624 sci_port->break_flag)
1da177e4 625 count = 0;
e7c98dc7 626 else
e108b2ca 627 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 628 } else {
e7c98dc7 629 for (i = 0; i < count; i++) {
1da177e4 630 char c = sci_in(port, SCxRDR);
d97fbbed 631
1da177e4
LT		 632 status = sci_in(port, SCxSR);
633#if defined(CONFIG_CPU_SH3)
634 /* Skip "chars" during break */
e108b2ca 635 if (sci_port->break_flag) {
1da177e4
LT		 636 if ((c == 0) &&
637 (status & SCxSR_FER(port))) {
638 count--; i--;
639 continue;
640 }
e108b2ca 641
1da177e4 642 /* Nonzero => end-of-break */
762c69e3 643 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 644 sci_port->break_flag = 0;
645
1da177e4
LT		 646 if (STEPFN(c)) {
647 count--; i--;
648 continue;
649 }
650 }
651#endif /* CONFIG_CPU_SH3 */
7d12e780 652 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 653 count--; i--;
654 continue;
655 }
656
657 /* Store data and status */
73a19e4c 658 if (status & SCxSR_FER(port)) {
33f0f88f 659 flag = TTY_FRAME;
d97fbbed 660 port->icount.frame++;
762c69e3 661 dev_notice(port->dev, "frame error\n");
73a19e4c 662 } else if (status & SCxSR_PER(port)) {
33f0f88f 663 flag = TTY_PARITY;
d97fbbed 664 port->icount.parity++;
762c69e3 665 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 666 } else
667 flag = TTY_NORMAL;
762c69e3 668
33f0f88f 669 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 670 }
671 }
672
673 sci_in(port, SCxSR); /* dummy read */
674 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
675
1da177e4
LT		 676 copied += count;
677 port->icount.rx += count;
678 }
679
680 if (copied) {
681 /* Tell the rest of the system the news. New characters! */
682 tty_flip_buffer_push(tty);
683 } else {
684 sci_in(port, SCxSR); /* dummy read */
685 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
686 }
687}
688
689#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 690
691/*
692 * The sci generates interrupts during the break,
1da177e4
LT		 693 * 1 per millisecond or so during the break period, for 9600 baud.
694 * So dont bother disabling interrupts.
695 * But dont want more than 1 break event.
696 * Use a kernel timer to periodically poll the rx line until
697 * the break is finished.
698 */
94c8b6db 699static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 700{
bc9b3f5c 701 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 702}
94c8b6db 703
1da177e4
LT		 704/* Ensure that two consecutive samples find the break over. */
705static void sci_break_timer(unsigned long data)
706{
e108b2ca
PM		 707 struct sci_port *port = (struct sci_port *)data;
708
23241d43 709 sci_port_enable(port);
5e50d2d6 710
e108b2ca 711 if (sci_rxd_in(&port->port) == 0) {
1da177e4 712 port->break_flag = 1;
e108b2ca
PM		 713 sci_schedule_break_timer(port);
714 } else if (port->break_flag == 1) {
1da177e4
LT		 715 /* break is over. */
716 port->break_flag = 2;
e108b2ca
PM		 717 sci_schedule_break_timer(port);
718 } else
719 port->break_flag = 0;
5e50d2d6 720
23241d43 721 sci_port_disable(port);
1da177e4
LT		 722}
723
94c8b6db 724static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 725{
726 int copied = 0;
727 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 728 struct tty_struct *tty = port->state->port.tty;
debf9507 729 struct sci_port *s = to_sci_port(port);
1da177e4 730
debf9507
PM		 731 /*
732 * Handle overruns, if supported.
733 */
734 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
735 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 736 port->icount.overrun++;
737
debf9507
PM		 738 /* overrun error */
739 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
740 copied++;
762c69e3 741
debf9507
PM		 742 dev_notice(port->dev, "overrun error");
743 }
1da177e4
LT		 744 }
745
e108b2ca 746 if (status & SCxSR_FER(port)) {
1da177e4
LT		 747 if (sci_rxd_in(port) == 0) {
748 /* Notify of BREAK */
e7c98dc7 749 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 750
751 if (!sci_port->break_flag) {
d97fbbed
PM		 752 port->icount.brk++;
753
e108b2ca
PM		 754 sci_port->break_flag = 1;
755 sci_schedule_break_timer(sci_port);
756
1da177e4 757 /* Do sysrq handling. */
e108b2ca 758 if (uart_handle_break(port))
1da177e4 759 return 0;
762c69e3
PM		 760
761 dev_dbg(port->dev, "BREAK detected\n");
762
e108b2ca 763 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 764 copied++;
765 }
766
e108b2ca 767 } else {
1da177e4 768 /* frame error */
d97fbbed
PM		 769 port->icount.frame++;
770
e108b2ca 771 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 772 copied++;
762c69e3
PM		 773
774 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 775 }
776 }
777
e108b2ca 778 if (status & SCxSR_PER(port)) {
1da177e4 779 /* parity error */
d97fbbed
PM		 780 port->icount.parity++;
781
e108b2ca
PM		 782 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
783 copied++;
762c69e3
PM		 784
785 dev_notice(port->dev, "parity error");
1da177e4
LT		 786 }
787
33f0f88f 788 if (copied)
1da177e4 789 tty_flip_buffer_push(tty);
1da177e4
LT		 790
791 return copied;
792}
793
94c8b6db 794static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 795{
ebd2c8f6 796 struct tty_struct *tty = port->state->port.tty;
debf9507 797 struct sci_port *s = to_sci_port(port);
4b8c59a3 798 struct plat_sci_reg *reg;
d830fa45
PM		 799 int copied = 0;
800
4b8c59a3
PM		 801 reg = sci_getreg(port, SCLSR);
802 if (!reg->size)
d830fa45
PM		 803 return 0;
804
debf9507 805 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
d830fa45
PM		 806 sci_out(port, SCLSR, 0);
807
d97fbbed
PM		 808 port->icount.overrun++;
809
d830fa45
PM		 810 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
811 tty_flip_buffer_push(tty);
812
813 dev_notice(port->dev, "overrun error\n");
814 copied++;
815 }
816
817 return copied;
818}
819
94c8b6db 820static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 821{
822 int copied = 0;
823 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 824 struct tty_struct *tty = port->state->port.tty;
a5660ada 825 struct sci_port *s = to_sci_port(port);
1da177e4 826
0b3d4ef6
PM		 827 if (uart_handle_break(port))
828 return 0;
829
b7a76e4b 830 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 831#if defined(CONFIG_CPU_SH3)
832 /* Debounce break */
833 s->break_flag = 1;
834#endif
d97fbbed
PM		 835
836 port->icount.brk++;
837
1da177e4 838 /* Notify of BREAK */
e108b2ca 839 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 840 copied++;
762c69e3
PM		 841
842 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 843 }
844
33f0f88f 845 if (copied)
1da177e4 846 tty_flip_buffer_push(tty);
e108b2ca 847
d830fa45
PM		 848 copied += sci_handle_fifo_overrun(port);
849
1da177e4
LT		 850 return copied;
851}
852
73a19e4c 853static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 854{
73a19e4c
GL		 855#ifdef CONFIG_SERIAL_SH_SCI_DMA
856 struct uart_port *port = ptr;
857 struct sci_port *s = to_sci_port(port);
858
859 if (s->chan_rx) {
73a19e4c
GL		 860 u16 scr = sci_in(port, SCSCR);
861 u16 ssr = sci_in(port, SCxSR);
862
863 /* Disable future Rx interrupts */
d1d4b10c 864 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 865 disable_irq_nosync(irq);
866 scr |= 0x4000;
867 } else {
f43dc23d 868 scr &= ~SCSCR_RIE;
3089f381
GL		 869 }
870 sci_out(port, SCSCR, scr);
73a19e4c
GL		 871 /* Clear current interrupt */
872 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 873 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
874 jiffies, s->rx_timeout);
875 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 876
877 return IRQ_HANDLED;
878 }
879#endif
880
1da177e4
LT		 881 /* I think sci_receive_chars has to be called irrespective
882 * of whether the I_IXOFF is set, otherwise, how is the interrupt
883 * to be disabled?
884 */
73a19e4c 885 sci_receive_chars(ptr);
1da177e4
LT		 886
887 return IRQ_HANDLED;
888}
889
7d12e780 890static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 891{
892 struct uart_port *port = ptr;
fd78a76a 893 unsigned long flags;
1da177e4 894
fd78a76a 895 spin_lock_irqsave(&port->lock, flags);
1da177e4 896 sci_transmit_chars(port);
fd78a76a 897 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 898
899 return IRQ_HANDLED;
900}
901
7d12e780 902static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 903{
904 struct uart_port *port = ptr;
905
906 /* Handle errors */
907 if (port->type == PORT_SCI) {
908 if (sci_handle_errors(port)) {
909 /* discard character in rx buffer */
910 sci_in(port, SCxSR);
911 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
912 }
913 } else {
d830fa45 914 sci_handle_fifo_overrun(port);
7d12e780 915 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 916 }
917
918 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
919
920 /* Kick the transmission */
7d12e780 921 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 922
923 return IRQ_HANDLED;
924}
925
7d12e780 926static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 927{
928 struct uart_port *port = ptr;
929
930 /* Handle BREAKs */
931 sci_handle_breaks(port);
932 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
933
934 return IRQ_HANDLED;
935}
936
f43dc23d
PM		 937static inline unsigned long port_rx_irq_mask(struct uart_port *port)
938{
939 /*
940 * Not all ports (such as SCIFA) will support REIE. Rather than
941 * special-casing the port type, we check the port initialization
942 * IRQ enable mask to see whether the IRQ is desired at all. If
943 * it's unset, it's logically inferred that there's no point in
944 * testing for it.
945 */
ce6738b6 946 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 947}
948
7d12e780 949static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 950{
44e18e9e 951 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 952 struct uart_port *port = ptr;
73a19e4c 953 struct sci_port *s = to_sci_port(port);
a8884e34 954 irqreturn_t ret = IRQ_NONE;
1da177e4 955
e7c98dc7
MT		 956 ssr_status = sci_in(port, SCxSR);
957 scr_status = sci_in(port, SCSCR);
f43dc23d 958 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 959
960 /* Tx Interrupt */
f43dc23d 961 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 962 !s->chan_tx)
a8884e34 963 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 964
73a19e4c
GL		 965 /*
966 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
967 * DR flags
968 */
969 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 970 (scr_status & SCSCR_RIE))
a8884e34 971 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 972
1da177e4 973 /* Error Interrupt */
dd4da3a5 974 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 975 ret = sci_er_interrupt(irq, ptr);
f43dc23d 976
1da177e4 977 /* Break Interrupt */
dd4da3a5 978 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 979 ret = sci_br_interrupt(irq, ptr);
1da177e4 980
a8884e34 981 return ret;
1da177e4
LT		 982}
983
1da177e4 984/*
25985edc 985 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 986 * ports' baud rate when the peripheral clock changes.
987 */
e108b2ca
PM		 988static int sci_notifier(struct notifier_block *self,
989 unsigned long phase, void *p)
1da177e4 990{
e552de24
MD		 991 struct sci_port *sci_port;
992 unsigned long flags;
1da177e4 993
d535a230
PM		 994 sci_port = container_of(self, struct sci_port, freq_transition);
995
1da177e4 996 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 997 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 998 struct uart_port *port = &sci_port->port;
073e84c9 999
d535a230
PM		 1000 spin_lock_irqsave(&port->lock, flags);
1001 port->uartclk = clk_get_rate(sci_port->iclk);
1002 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1003 }
1da177e4 1004
1da177e4
LT		 1005 return NOTIFY_OK;
1006}
501b825d 1007
9174fc8f
PM		 1008static struct sci_irq_desc {
1009 const char *desc;
1010 irq_handler_t handler;
1011} sci_irq_desc[] = {
1012 /*
1013 * Split out handlers, the default case.
1014 */
1015 [SCIx_ERI_IRQ] = {
1016 .desc = "rx err",
1017 .handler = sci_er_interrupt,
1018 },
1019
1020 [SCIx_RXI_IRQ] = {
1021 .desc = "rx full",
1022 .handler = sci_rx_interrupt,
1023 },
1024
1025 [SCIx_TXI_IRQ] = {
1026 .desc = "tx empty",
1027 .handler = sci_tx_interrupt,
1028 },
1029
1030 [SCIx_BRI_IRQ] = {
1031 .desc = "break",
1032 .handler = sci_br_interrupt,
1033 },
1034
1035 /*
1036 * Special muxed handler.
1037 */
1038 [SCIx_MUX_IRQ] = {
1039 .desc = "mux",
1040 .handler = sci_mpxed_interrupt,
1041 },
1042};
1043
1da177e4
LT		 1044static int sci_request_irq(struct sci_port *port)
1045{
9174fc8f
PM		 1046 struct uart_port *up = &port->port;
1047 int i, j, ret = 0;
1048
1049 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1050 struct sci_irq_desc *desc;
1051 unsigned int irq;
1052
1053 if (SCIx_IRQ_IS_MUXED(port)) {
1054 i = SCIx_MUX_IRQ;
1055 irq = up->irq;
1056 } else
1057 irq = port->cfg->irqs[i];
1058
1059 desc = sci_irq_desc + i;
1060 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1061 dev_name(up->dev), desc->desc);
1062 if (!port->irqstr[j]) {
1063 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1064 desc->desc);
1065 goto out_nomem;
1da177e4 1066 }
9174fc8f
PM		 1067
1068 ret = request_irq(irq, desc->handler, up->irqflags,
1069 port->irqstr[j], port);
1070 if (unlikely(ret)) {
1071 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1072 goto out_noirq;
1da177e4
LT		 1073 }
1074 }
1075
1076 return 0;
9174fc8f
PM		 1077
1078out_noirq:
1079 while (--i >= 0)
1080 free_irq(port->cfg->irqs[i], port);
1081
1082out_nomem:
1083 while (--j >= 0)
1084 kfree(port->irqstr[j]);
1085
1086 return ret;
1da177e4
LT		 1087}
1088
1089static void sci_free_irq(struct sci_port *port)
1090{
1091 int i;
1092
9174fc8f
PM		 1093 /*
1094 * Intentionally in reverse order so we iterate over the muxed
1095 * IRQ first.
1096 */
1097 for (i = 0; i < SCIx_NR_IRQS; i++) {
1098 free_irq(port->cfg->irqs[i], port);
1099 kfree(port->irqstr[i]);
1da177e4 1100
9174fc8f
PM		 1101 if (SCIx_IRQ_IS_MUXED(port)) {
1102 /* If there's only one IRQ, we're done. */
1103 return;
1da177e4
LT		 1104 }
1105 }
1106}
1107
1108static unsigned int sci_tx_empty(struct uart_port *port)
1109{
b1516803 1110 unsigned short status = sci_in(port, SCxSR);
72b294cf 1111 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1112
1113 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1114}
1115
cdf7c42f
PM		 1116/*
1117 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1118 * CTS/RTS is supported in hardware by at least one port and controlled
1119 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1120 * handled via the ->init_pins() op, which is a bit of a one-way street,
1121 * lacking any ability to defer pin control -- this will later be
1122 * converted over to the GPIO framework).
dc7e3ef7
PM		 1123 *
1124 * Other modes (such as loopback) are supported generically on certain
1125 * port types, but not others. For these it's sufficient to test for the
1126 * existence of the support register and simply ignore the port type.
cdf7c42f 1127 */
1da177e4
LT		 1128static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1129{
dc7e3ef7
PM		 1130 if (mctrl & TIOCM_LOOP) {
1131 struct plat_sci_reg *reg;
1132
1133 /*
1134 * Standard loopback mode for SCFCR ports.
1135 */
1136 reg = sci_getreg(port, SCFCR);
1137 if (reg->size)
1138 sci_out(port, SCFCR, sci_in(port, SCFCR) | 1);
1139 }
1da177e4
LT		 1140}
1141
1142static unsigned int sci_get_mctrl(struct uart_port *port)
1143{
cdf7c42f
PM		 1144 /*
1145 * CTS/RTS is handled in hardware when supported, while nothing
1146 * else is wired up. Keep it simple and simply assert DSR/CAR.
1147 */
1148 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1149}
1150
73a19e4c
GL		 1151#ifdef CONFIG_SERIAL_SH_SCI_DMA
1152static void sci_dma_tx_complete(void *arg)
1153{
1154 struct sci_port *s = arg;
1155 struct uart_port *port = &s->port;
1156 struct circ_buf *xmit = &port->state->xmit;
1157 unsigned long flags;
1158
1159 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1160
1161 spin_lock_irqsave(&port->lock, flags);
1162
f354a381 1163 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1164 xmit->tail &= UART_XMIT_SIZE - 1;
1165
f354a381 1166 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1167
1168 async_tx_ack(s->desc_tx);
1169 s->cookie_tx = -EINVAL;
1170 s->desc_tx = NULL;
1171
73a19e4c
GL		 1172 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1173 uart_write_wakeup(port);
1174
3089f381 1175 if (!uart_circ_empty(xmit)) {
73a19e4c 1176 schedule_work(&s->work_tx);
d1d4b10c 1177 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1178 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 1179 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 1180 }
1181
1182 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1183}
1184
1185/* Locking: called with port lock held */
1186static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1187 size_t count)
1188{
1189 struct uart_port *port = &s->port;
1190 int i, active, room;
1191
1192 room = tty_buffer_request_room(tty, count);
1193
1194 if (s->active_rx == s->cookie_rx[0]) {
1195 active = 0;
1196 } else if (s->active_rx == s->cookie_rx[1]) {
1197 active = 1;
1198 } else {
1199 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1200 return 0;
1201 }
1202
1203 if (room < count)
1204 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1205 count - room);
1206 if (!room)
1207 return room;
1208
1209 for (i = 0; i < room; i++)
1210 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1211 TTY_NORMAL);
1212
1213 port->icount.rx += room;
1214
1215 return room;
1216}
1217
1218static void sci_dma_rx_complete(void *arg)
1219{
1220 struct sci_port *s = arg;
1221 struct uart_port *port = &s->port;
1222 struct tty_struct *tty = port->state->port.tty;
1223 unsigned long flags;
1224 int count;
1225
3089f381 1226 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1227
1228 spin_lock_irqsave(&port->lock, flags);
1229
1230 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1231
3089f381 1232 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1233
1234 spin_unlock_irqrestore(&port->lock, flags);
1235
1236 if (count)
1237 tty_flip_buffer_push(tty);
1238
1239 schedule_work(&s->work_rx);
1240}
1241
73a19e4c
GL		 1242static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1243{
1244 struct dma_chan *chan = s->chan_rx;
1245 struct uart_port *port = &s->port;
73a19e4c
GL		 1246
1247 s->chan_rx = NULL;
1248 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1249 dma_release_channel(chan);
85b8e3ff
GL		 1250 if (sg_dma_address(&s->sg_rx[0]))
1251 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1252 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1253 if (enable_pio)
1254 sci_start_rx(port);
1255}
1256
1257static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1258{
1259 struct dma_chan *chan = s->chan_tx;
1260 struct uart_port *port = &s->port;
73a19e4c
GL		 1261
1262 s->chan_tx = NULL;
1263 s->cookie_tx = -EINVAL;
1264 dma_release_channel(chan);
1265 if (enable_pio)
1266 sci_start_tx(port);
1267}
1268
1269static void sci_submit_rx(struct sci_port *s)
1270{
1271 struct dma_chan *chan = s->chan_rx;
1272 int i;
1273
1274 for (i = 0; i < 2; i++) {
1275 struct scatterlist *sg = &s->sg_rx[i];
1276 struct dma_async_tx_descriptor *desc;
1277
1278 desc = chan->device->device_prep_slave_sg(chan,
1279 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1280
1281 if (desc) {
1282 s->desc_rx[i] = desc;
1283 desc->callback = sci_dma_rx_complete;
1284 desc->callback_param = s;
1285 s->cookie_rx[i] = desc->tx_submit(desc);
1286 }
1287
1288 if (!desc || s->cookie_rx[i] < 0) {
1289 if (i) {
1290 async_tx_ack(s->desc_rx[0]);
1291 s->cookie_rx[0] = -EINVAL;
1292 }
1293 if (desc) {
1294 async_tx_ack(desc);
1295 s->cookie_rx[i] = -EINVAL;
1296 }
1297 dev_warn(s->port.dev,
1298 "failed to re-start DMA, using PIO\n");
1299 sci_rx_dma_release(s, true);
1300 return;
1301 }
3089f381
GL		 1302 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1303 s->cookie_rx[i], i);
73a19e4c
GL		 1304 }
1305
1306 s->active_rx = s->cookie_rx[0];
1307
1308 dma_async_issue_pending(chan);
1309}
1310
1311static void work_fn_rx(struct work_struct *work)
1312{
1313 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1314 struct uart_port *port = &s->port;
1315 struct dma_async_tx_descriptor *desc;
1316 int new;
1317
1318 if (s->active_rx == s->cookie_rx[0]) {
1319 new = 0;
1320 } else if (s->active_rx == s->cookie_rx[1]) {
1321 new = 1;
1322 } else {
1323 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1324 return;
1325 }
1326 desc = s->desc_rx[new];
1327
1328 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1329 DMA_SUCCESS) {
1330 /* Handle incomplete DMA receive */
1331 struct tty_struct *tty = port->state->port.tty;
1332 struct dma_chan *chan = s->chan_rx;
1333 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1334 async_tx);
1335 unsigned long flags;
1336 int count;
1337
05827630 1338 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1339 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1340 sh_desc->partial, sh_desc->cookie);
1341
1342 spin_lock_irqsave(&port->lock, flags);
1343 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1344 spin_unlock_irqrestore(&port->lock, flags);
1345
1346 if (count)
1347 tty_flip_buffer_push(tty);
1348
1349 sci_submit_rx(s);
1350
1351 return;
1352 }
1353
1354 s->cookie_rx[new] = desc->tx_submit(desc);
1355 if (s->cookie_rx[new] < 0) {
1356 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1357 sci_rx_dma_release(s, true);
1358 return;
1359 }
1360
73a19e4c 1361 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1362
1363 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1364 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1365}
1366
1367static void work_fn_tx(struct work_struct *work)
1368{
1369 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1370 struct dma_async_tx_descriptor *desc;
1371 struct dma_chan *chan = s->chan_tx;
1372 struct uart_port *port = &s->port;
1373 struct circ_buf *xmit = &port->state->xmit;
1374 struct scatterlist *sg = &s->sg_tx;
1375
1376 /*
1377 * DMA is idle now.
1378 * Port xmit buffer is already mapped, and it is one page... Just adjust
1379 * offsets and lengths. Since it is a circular buffer, we have to
1380 * transmit till the end, and then the rest. Take the port lock to get a
1381 * consistent xmit buffer state.
1382 */
1383 spin_lock_irq(&port->lock);
1384 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1385 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1386 sg->offset;
f354a381 1387 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1388 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1389 spin_unlock_irq(&port->lock);
1390
f354a381 1391 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1392
1393 desc = chan->device->device_prep_slave_sg(chan,
1394 sg, s->sg_len_tx, DMA_TO_DEVICE,
1395 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1396 if (!desc) {
1397 /* switch to PIO */
1398 sci_tx_dma_release(s, true);
1399 return;
1400 }
1401
1402 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1403
1404 spin_lock_irq(&port->lock);
1405 s->desc_tx = desc;
1406 desc->callback = sci_dma_tx_complete;
1407 desc->callback_param = s;
1408 spin_unlock_irq(&port->lock);
1409 s->cookie_tx = desc->tx_submit(desc);
1410 if (s->cookie_tx < 0) {
1411 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1412 /* switch to PIO */
1413 sci_tx_dma_release(s, true);
1414 return;
1415 }
1416
1417 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1418 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1419
1420 dma_async_issue_pending(chan);
1421}
1422#endif
1423
b129a8cc 1424static void sci_start_tx(struct uart_port *port)
1da177e4 1425{
3089f381 1426 struct sci_port *s = to_sci_port(port);
e108b2ca 1427 unsigned short ctrl;
1da177e4 1428
73a19e4c 1429#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1430 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1431 u16 new, scr = sci_in(port, SCSCR);
1432 if (s->chan_tx)
1433 new = scr | 0x8000;
1434 else
1435 new = scr & ~0x8000;
1436 if (new != scr)
1437 sci_out(port, SCSCR, new);
73a19e4c 1438 }
f43dc23d 1439
3089f381
GL		 1440 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1441 s->cookie_tx < 0)
1442 schedule_work(&s->work_tx);
73a19e4c 1443#endif
f43dc23d 1444
d1d4b10c 1445 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1446 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1447 ctrl = sci_in(port, SCSCR);
f43dc23d 1448 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1449 }
1da177e4
LT		 1450}
1451
b129a8cc 1452static void sci_stop_tx(struct uart_port *port)
1da177e4 1453{
1da177e4
LT		 1454 unsigned short ctrl;
1455
1456 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1457 ctrl = sci_in(port, SCSCR);
f43dc23d 1458
d1d4b10c 1459 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1460 ctrl &= ~0x8000;
f43dc23d 1461
8e698614 1462 ctrl &= ~SCSCR_TIE;
f43dc23d 1463
1da177e4 1464 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1465}
1466
73a19e4c 1467static void sci_start_rx(struct uart_port *port)
1da177e4 1468{
1da177e4
LT		 1469 unsigned short ctrl;
1470
f43dc23d 1471 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1472
d1d4b10c 1473 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1474 ctrl &= ~0x4000;
f43dc23d 1475
1da177e4 1476 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1477}
1478
1479static void sci_stop_rx(struct uart_port *port)
1480{
1da177e4
LT		 1481 unsigned short ctrl;
1482
1da177e4 1483 ctrl = sci_in(port, SCSCR);
f43dc23d 1484
d1d4b10c 1485 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1486 ctrl &= ~0x4000;
f43dc23d
PM		 1487
1488 ctrl &= ~port_rx_irq_mask(port);
1489
1da177e4 1490 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1491}
1492
1493static void sci_enable_ms(struct uart_port *port)
1494{
d39ec6ce
PM		 1495 /*
1496 * Not supported by hardware, always a nop.
1497 */
1da177e4
LT		 1498}
1499
1500static void sci_break_ctl(struct uart_port *port, int break_state)
1501{
d39ec6ce
PM		 1502 /*
1503 * Not supported by hardware. Most parts couple break and rx
1504 * interrupts together, with break detection always enabled.
1505 */
1da177e4
LT		 1506}
1507
73a19e4c
GL		 1508#ifdef CONFIG_SERIAL_SH_SCI_DMA
1509static bool filter(struct dma_chan *chan, void *slave)
1510{
1511 struct sh_dmae_slave *param = slave;
1512
1513 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1514 param->slave_id);
1515
937bb6e4
GL		 1516 chan->private = param;
1517 return true;
73a19e4c
GL		 1518}
1519
1520static void rx_timer_fn(unsigned long arg)
1521{
1522 struct sci_port *s = (struct sci_port *)arg;
1523 struct uart_port *port = &s->port;
73a19e4c 1524 u16 scr = sci_in(port, SCSCR);
3089f381 1525
d1d4b10c 1526 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1527 scr &= ~0x4000;
ce6738b6 1528 enable_irq(s->cfg->irqs[1]);
3089f381 1529 }
f43dc23d 1530 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1531 dev_dbg(port->dev, "DMA Rx timed out\n");
1532 schedule_work(&s->work_rx);
1533}
1534
1535static void sci_request_dma(struct uart_port *port)
1536{
1537 struct sci_port *s = to_sci_port(port);
1538 struct sh_dmae_slave *param;
1539 struct dma_chan *chan;
1540 dma_cap_mask_t mask;
1541 int nent;
1542
937bb6e4
GL		 1543 dev_dbg(port->dev, "%s: port %d\n", __func__,
1544 port->line);
73a19e4c 1545
937bb6e4 1546 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1547 return;
1548
1549 dma_cap_zero(mask);
1550 dma_cap_set(DMA_SLAVE, mask);
1551
1552 param = &s->param_tx;
1553
1554 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6 1555 param->slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1556
1557 s->cookie_tx = -EINVAL;
1558 chan = dma_request_channel(mask, filter, param);
1559 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1560 if (chan) {
1561 s->chan_tx = chan;
1562 sg_init_table(&s->sg_tx, 1);
1563 /* UART circular tx buffer is an aligned page. */
1564 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1565 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1566 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1567 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1568 if (!nent)
1569 sci_tx_dma_release(s, false);
1570 else
1571 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1572 sg_dma_len(&s->sg_tx),
1573 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1574
1575 s->sg_len_tx = nent;
1576
1577 INIT_WORK(&s->work_tx, work_fn_tx);
1578 }
1579
1580 param = &s->param_rx;
1581
1582 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6 1583 param->slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1584
1585 chan = dma_request_channel(mask, filter, param);
1586 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1587 if (chan) {
1588 dma_addr_t dma[2];
1589 void *buf[2];
1590 int i;
1591
1592 s->chan_rx = chan;
1593
1594 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1595 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1596 &dma[0], GFP_KERNEL);
1597
1598 if (!buf[0]) {
1599 dev_warn(port->dev,
1600 "failed to allocate dma buffer, using PIO\n");
1601 sci_rx_dma_release(s, true);
1602 return;
1603 }
1604
1605 buf[1] = buf[0] + s->buf_len_rx;
1606 dma[1] = dma[0] + s->buf_len_rx;
1607
1608 for (i = 0; i < 2; i++) {
1609 struct scatterlist *sg = &s->sg_rx[i];
1610
1611 sg_init_table(sg, 1);
1612 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1613 (int)buf[i] & ~PAGE_MASK);
f354a381 1614 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1615 }
1616
1617 INIT_WORK(&s->work_rx, work_fn_rx);
1618 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1619
1620 sci_submit_rx(s);
1621 }
1622}
1623
1624static void sci_free_dma(struct uart_port *port)
1625{
1626 struct sci_port *s = to_sci_port(port);
1627
73a19e4c
GL		 1628 if (s->chan_tx)
1629 sci_tx_dma_release(s, false);
1630 if (s->chan_rx)
1631 sci_rx_dma_release(s, false);
1632}
27bd1075
PM		 1633#else
1634static inline void sci_request_dma(struct uart_port *port)
1635{
1636}
1637
1638static inline void sci_free_dma(struct uart_port *port)
1639{
1640}
73a19e4c
GL		 1641#endif
1642
1da177e4
LT		 1643static int sci_startup(struct uart_port *port)
1644{
a5660ada 1645 struct sci_port *s = to_sci_port(port);
073e84c9 1646 int ret;
1da177e4 1647
73a19e4c
GL		 1648 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1649
23241d43 1650 sci_port_enable(s);
1da177e4 1651
073e84c9
PM		 1652 ret = sci_request_irq(s);
1653 if (unlikely(ret < 0))
1654 return ret;
1655
73a19e4c 1656 sci_request_dma(port);
073e84c9 1657
d656901b 1658 sci_start_tx(port);
73a19e4c 1659 sci_start_rx(port);
1da177e4
LT		 1660
1661 return 0;
1662}
1663
1664static void sci_shutdown(struct uart_port *port)
1665{
a5660ada 1666 struct sci_port *s = to_sci_port(port);
1da177e4 1667
73a19e4c
GL		 1668 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1669
1da177e4 1670 sci_stop_rx(port);
b129a8cc 1671 sci_stop_tx(port);
073e84c9 1672
73a19e4c 1673 sci_free_dma(port);
1da177e4
LT		 1674 sci_free_irq(s);
1675
23241d43 1676 sci_port_disable(s);
1da177e4
LT		 1677}
1678
26c92f37
PM		 1679static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1680 unsigned long freq)
1681{
1682 switch (algo_id) {
1683 case SCBRR_ALGO_1:
1684 return ((freq + 16 * bps) / (16 * bps) - 1);
1685 case SCBRR_ALGO_2:
1686 return ((freq + 16 * bps) / (32 * bps) - 1);
1687 case SCBRR_ALGO_3:
1688 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1689 case SCBRR_ALGO_4:
1690 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1691 case SCBRR_ALGO_5:
1692 return (((freq * 1000 / 32) / bps) - 1);
1693 }
1694
1695 /* Warn, but use a safe default */
1696 WARN_ON(1);
e8183a6c 1697
26c92f37
PM		 1698 return ((freq + 16 * bps) / (32 * bps) - 1);
1699}
1700
1ba76220
MD		 1701static void sci_reset(struct uart_port *port)
1702{
0979e0e6 1703 struct plat_sci_reg *reg;
1ba76220
MD		 1704 unsigned int status;
1705
1706 do {
1707 status = sci_in(port, SCxSR);
1708 } while (!(status & SCxSR_TEND(port)));
1709
1710 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1711
0979e0e6
PM		 1712 reg = sci_getreg(port, SCFCR);
1713 if (reg->size)
1ba76220
MD		 1714 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1715}
1716
606d099c
AC		 1717static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1718 struct ktermios *old)
1da177e4 1719{
00b9de9c 1720 struct sci_port *s = to_sci_port(port);
0979e0e6 1721 struct plat_sci_reg *reg;
1ba76220 1722 unsigned int baud, smr_val, max_baud;
a2159b52 1723 int t = -1;
1da177e4 1724
154280fd
MD		 1725 /*
1726 * earlyprintk comes here early on with port->uartclk set to zero.
1727 * the clock framework is not up and running at this point so here
1728 * we assume that 115200 is the maximum baud rate. please note that
1729 * the baud rate is not programmed during earlyprintk - it is assumed
1730 * that the previous boot loader has enabled required clocks and
1731 * setup the baud rate generator hardware for us already.
1732 */
1733 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1734
154280fd
MD		 1735 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1736 if (likely(baud && port->uartclk))
ce6738b6 1737 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1738
23241d43 1739 sci_port_enable(s);
36003386 1740
1ba76220 1741 sci_reset(port);
1da177e4
LT		 1742
1743 smr_val = sci_in(port, SCSMR) & 3;
e8183a6c 1744
1da177e4
LT		 1745 if ((termios->c_cflag & CSIZE) == CS7)
1746 smr_val |= 0x40;
1747 if (termios->c_cflag & PARENB)
1748 smr_val |= 0x20;
1749 if (termios->c_cflag & PARODD)
1750 smr_val |= 0x30;
1751 if (termios->c_cflag & CSTOPB)
1752 smr_val |= 0x08;
1753
1754 uart_update_timeout(port, termios->c_cflag, baud);
1755
1756 sci_out(port, SCSMR, smr_val);
1757
73a19e4c 1758 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1759 s->cfg->scscr);
73a19e4c 1760
1da177e4 1761 if (t > 0) {
e7c98dc7 1762 if (t >= 256) {
1da177e4
LT		 1763 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1764 t >>= 2;
e7c98dc7 1765 } else
1da177e4 1766 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1767
1da177e4
LT		 1768 sci_out(port, SCBRR, t);
1769 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1770 }
1771
d5701647 1772 sci_init_pins(port, termios->c_cflag);
0979e0e6 1773
faf02f8f
PM		 1774 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1775 reg = sci_getreg(port, SCFCR);
1776 if (reg->size) {
1777 unsigned short ctrl;
0979e0e6 1778
faf02f8f
PM		 1779 ctrl = sci_in(port, SCFCR);
1780 if (termios->c_cflag & CRTSCTS)
1781 ctrl |= SCFCR_MCE;
1782 else
1783 ctrl &= ~SCFCR_MCE;
1784 sci_out(port, SCFCR, ctrl);
1785 }
0979e0e6 1786 }
b7a76e4b 1787
ce6738b6 1788 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1789
3089f381
GL		 1790#ifdef CONFIG_SERIAL_SH_SCI_DMA
1791 /*
1792 * Calculate delay for 1.5 DMA buffers: see
1793 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1794 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1795 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1796 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1797 * sizes), but it has been found out experimentally, that this is not
1798 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1799 * as a minimum seem to work perfectly.
1800 */
1801 if (s->chan_rx) {
1802 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1803 port->fifosize / 2;
1804 dev_dbg(port->dev,
1805 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1806 s->rx_timeout * 1000 / HZ, port->timeout);
1807 if (s->rx_timeout < msecs_to_jiffies(20))
1808 s->rx_timeout = msecs_to_jiffies(20);
1809 }
1810#endif
1811
1da177e4 1812 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1813 sci_start_rx(port);
36003386 1814
23241d43 1815 sci_port_disable(s);
1da177e4
LT		 1816}
1817
1818static const char *sci_type(struct uart_port *port)
1819{
1820 switch (port->type) {
e7c98dc7
MT		 1821 case PORT_IRDA:
1822 return "irda";
1823 case PORT_SCI:
1824 return "sci";
1825 case PORT_SCIF:
1826 return "scif";
1827 case PORT_SCIFA:
1828 return "scifa";
d1d4b10c
GL		 1829 case PORT_SCIFB:
1830 return "scifb";
1da177e4
LT		 1831 }
1832
fa43972f 1833 return NULL;
1da177e4
LT		 1834}
1835
e2651647 1836static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1837{
e2651647
PM		 1838 /*
1839 * Pick an arbitrary size that encapsulates all of the base
1840 * registers by default. This can be optimized later, or derived
1841 * from platform resource data at such a time that ports begin to
1842 * behave more erratically.
1843 */
1844 return 64;
1da177e4
LT		 1845}
1846
f6e9495d
PM		 1847static int sci_remap_port(struct uart_port *port)
1848{
1849 unsigned long size = sci_port_size(port);
1850
1851 /*
1852 * Nothing to do if there's already an established membase.
1853 */
1854 if (port->membase)
1855 return 0;
1856
1857 if (port->flags & UPF_IOREMAP) {
1858 port->membase = ioremap_nocache(port->mapbase, size);
1859 if (unlikely(!port->membase)) {
1860 dev_err(port->dev, "can't remap port#%d\n", port->line);
1861 return -ENXIO;
1862 }
1863 } else {
1864 /*
1865 * For the simple (and majority of) cases where we don't
1866 * need to do any remapping, just cast the cookie
1867 * directly.
1868 */
1869 port->membase = (void __iomem *)port->mapbase;
1870 }
1871
1872 return 0;
1873}
1874
e2651647 1875static void sci_release_port(struct uart_port *port)
1da177e4 1876{
e2651647
PM		 1877 if (port->flags & UPF_IOREMAP) {
1878 iounmap(port->membase);
1879 port->membase = NULL;
1880 }
1881
1882 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1883}
1884
e2651647 1885static int sci_request_port(struct uart_port *port)
1da177e4 1886{
e2651647
PM		 1887 unsigned long size = sci_port_size(port);
1888 struct resource *res;
f6e9495d 1889 int ret;
1da177e4 1890
1020520e 1891 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 1892 if (unlikely(res == NULL))
1893 return -EBUSY;
1da177e4 1894
f6e9495d
PM		 1895 ret = sci_remap_port(port);
1896 if (unlikely(ret != 0)) {
1897 release_resource(res);
1898 return ret;
7ff731ae 1899 }
e2651647
PM		 1900
1901 return 0;
1902}
1903
1904static void sci_config_port(struct uart_port *port, int flags)
1905{
1906 if (flags & UART_CONFIG_TYPE) {
1907 struct sci_port *sport = to_sci_port(port);
1908
1909 port->type = sport->cfg->type;
1910 sci_request_port(port);
1911 }
1da177e4
LT		 1912}
1913
1914static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1915{
a5660ada 1916 struct sci_port *s = to_sci_port(port);
1da177e4 1917
ce6738b6 1918 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1919 return -EINVAL;
1920 if (ser->baud_base < 2400)
1921 /* No paper tape reader for Mitch.. */
1922 return -EINVAL;
1923
1924 return 0;
1925}
1926
1927static struct uart_ops sci_uart_ops = {
1928 .tx_empty = sci_tx_empty,
1929 .set_mctrl = sci_set_mctrl,
1930 .get_mctrl = sci_get_mctrl,
1931 .start_tx = sci_start_tx,
1932 .stop_tx = sci_stop_tx,
1933 .stop_rx = sci_stop_rx,
1934 .enable_ms = sci_enable_ms,
1935 .break_ctl = sci_break_ctl,
1936 .startup = sci_startup,
1937 .shutdown = sci_shutdown,
1938 .set_termios = sci_set_termios,
1939 .type = sci_type,
1940 .release_port = sci_release_port,
1941 .request_port = sci_request_port,
1942 .config_port = sci_config_port,
1943 .verify_port = sci_verify_port,
07d2a1a1
PM		 1944#ifdef CONFIG_CONSOLE_POLL
1945 .poll_get_char = sci_poll_get_char,
1946 .poll_put_char = sci_poll_put_char,
1947#endif
1da177e4
LT		 1948};
1949
c7ed1ab3
PM		 1950static int __devinit sci_init_single(struct platform_device *dev,
1951 struct sci_port *sci_port,
1952 unsigned int index,
1953 struct plat_sci_port *p)
e108b2ca 1954{
73a19e4c 1955 struct uart_port *port = &sci_port->port;
3127c6b2 1956 int ret;
e108b2ca 1957
73a19e4c
GL		 1958 port->ops = &sci_uart_ops;
1959 port->iotype = UPIO_MEM;
1960 port->line = index;
75136d48
MP		 1961
1962 switch (p->type) {
d1d4b10c
GL		 1963 case PORT_SCIFB:
1964 port->fifosize = 256;
1965 break;
75136d48 1966 case PORT_SCIFA:
73a19e4c 1967 port->fifosize = 64;
75136d48
MP		 1968 break;
1969 case PORT_SCIF:
73a19e4c 1970 port->fifosize = 16;
75136d48
MP		 1971 break;
1972 default:
73a19e4c 1973 port->fifosize = 1;
75136d48
MP		 1974 break;
1975 }
7b6fd3bf 1976
3127c6b2
PM		 1977 if (p->regtype == SCIx_PROBE_REGTYPE) {
1978 ret = sci_probe_regmap(p);
fc97114b 1979 if (unlikely(ret))
3127c6b2
PM		 1980 return ret;
1981 }
61a6976b 1982
7b6fd3bf 1983 if (dev) {
c7ed1ab3
PM		 1984 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1985 if (IS_ERR(sci_port->iclk)) {
1986 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1987 if (IS_ERR(sci_port->iclk)) {
1988 dev_err(&dev->dev, "can't get iclk\n");
1989 return PTR_ERR(sci_port->iclk);
1990 }
1991 }
1992
1993 /*
1994 * The function clock is optional, ignore it if we can't
1995 * find it.
1996 */
1997 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1998 if (IS_ERR(sci_port->fclk))
1999 sci_port->fclk = NULL;
2000
73a19e4c 2001 port->dev = &dev->dev;
5e50d2d6 2002
5a50a01b 2003 pm_runtime_irq_safe(&dev->dev);
5e50d2d6 2004 pm_runtime_enable(&dev->dev);
7b6fd3bf 2005 }
e108b2ca 2006
7ed7e071
MD		 2007 sci_port->break_timer.data = (unsigned long)sci_port;
2008 sci_port->break_timer.function = sci_break_timer;
2009 init_timer(&sci_port->break_timer);
2010
debf9507
PM		 2011 /*
2012 * Establish some sensible defaults for the error detection.
2013 */
2014 if (!p->error_mask)
2015 p->error_mask = (p->type == PORT_SCI) ?
2016 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2017
2018 /*
2019 * Establish sensible defaults for the overrun detection, unless
2020 * the part has explicitly disabled support for it.
2021 */
2022 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2023 if (p->type == PORT_SCI)
2024 p->overrun_bit = 5;
2025 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2026 p->overrun_bit = 9;
2027 else
2028 p->overrun_bit = 0;
2029
2030 /*
2031 * Make the error mask inclusive of overrun detection, if
2032 * supported.
2033 */
2034 p->error_mask |= (1 << p->overrun_bit);
2035 }
2036
ce6738b6 2037 sci_port->cfg = p;
7ed7e071 2038
ce6738b6
PM		 2039 port->mapbase = p->mapbase;
2040 port->type = p->type;
f43dc23d 2041 port->flags = p->flags;
61a6976b 2042 port->regshift = p->regshift;
73a19e4c 2043
ce6738b6 2044 /*
61a6976b 2045 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2046 * for the multi-IRQ ports, which is where we are primarily
2047 * concerned with the shutdown path synchronization.
2048 *
2049 * For the muxed case there's nothing more to do.
2050 */
54aa89ea 2051 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2052 port->irqflags = 0;
73a19e4c 2053
61a6976b
PM		 2054 port->serial_in = sci_serial_in;
2055 port->serial_out = sci_serial_out;
2056
937bb6e4
GL		 2057 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2058 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2059 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2060
c7ed1ab3 2061 return 0;
e108b2ca
PM		 2062}
2063
1da177e4 2064#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2065static void serial_console_putchar(struct uart_port *port, int ch)
2066{
2067 sci_poll_put_char(port, ch);
2068}
2069
1da177e4
LT		 2070/*
2071 * Print a string to the serial port trying not to disturb
2072 * any possible real use of the port...
2073 */
2074static void serial_console_write(struct console *co, const char *s,
2075 unsigned count)
2076{
906b17dc
PM		 2077 struct sci_port *sci_port = &sci_ports[co->index];
2078 struct uart_port *port = &sci_port->port;
973e5d52 2079 unsigned short bits;
07d2a1a1 2080
23241d43 2081 sci_port_enable(sci_port);
501b825d
MD		 2082
2083 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2084
2085 /* wait until fifo is empty and last bit has been transmitted */
2086 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2087 while ((sci_in(port, SCxSR) & bits) != bits)
2088 cpu_relax();
501b825d 2089
23241d43 2090 sci_port_disable(sci_port);
1da177e4
LT		 2091}
2092
7b6fd3bf 2093static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 2094{
dc8e6f5b 2095 struct sci_port *sci_port;
1da177e4
LT		 2096 struct uart_port *port;
2097 int baud = 115200;
2098 int bits = 8;
2099 int parity = 'n';
2100 int flow = 'n';
2101 int ret;
2102
e108b2ca 2103 /*
906b17dc 2104 * Refuse to handle any bogus ports.
1da177e4 2105 */
906b17dc 2106 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2107 return -ENODEV;
e108b2ca 2108
906b17dc
PM		 2109 sci_port = &sci_ports[co->index];
2110 port = &sci_port->port;
2111
b2267a6b
AC		 2112 /*
2113 * Refuse to handle uninitialized ports.
2114 */
2115 if (!port->ops)
2116 return -ENODEV;
2117
f6e9495d
PM		 2118 ret = sci_remap_port(port);
2119 if (unlikely(ret != 0))
2120 return ret;
e108b2ca 2121
23241d43 2122 sci_port_enable(sci_port);
b7a76e4b 2123
1da177e4
LT		 2124 if (options)
2125 uart_parse_options(options, &baud, &parity, &bits, &flow);
2126
1ba76220
MD		 2127 sci_port_disable(sci_port);
2128
ab7cfb55 2129 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2130}
2131
2132static struct console serial_console = {
2133 .name = "ttySC",
906b17dc 2134 .device = uart_console_device,
1da177e4
LT		 2135 .write = serial_console_write,
2136 .setup = serial_console_setup,
fa5da2f7 2137 .flags = CON_PRINTBUFFER,
1da177e4 2138 .index = -1,
906b17dc 2139 .data = &sci_uart_driver,
1da177e4
LT		 2140};
2141
7b6fd3bf
MD		 2142static struct console early_serial_console = {
2143 .name = "early_ttySC",
2144 .write = serial_console_write,
2145 .flags = CON_PRINTBUFFER,
906b17dc 2146 .index = -1,
7b6fd3bf 2147};
ecdf8a46 2148
7b6fd3bf
MD		 2149static char early_serial_buf[32];
2150
ecdf8a46
PM		 2151static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2152{
2153 struct plat_sci_port *cfg = pdev->dev.platform_data;
2154
2155 if (early_serial_console.data)
2156 return -EEXIST;
2157
2158 early_serial_console.index = pdev->id;
ecdf8a46 2159
906b17dc 2160 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2161
2162 serial_console_setup(&early_serial_console, early_serial_buf);
2163
2164 if (!strstr(early_serial_buf, "keep"))
2165 early_serial_console.flags |= CON_BOOT;
2166
2167 register_console(&early_serial_console);
2168 return 0;
2169}
6a8c9799 2170
1ba76220
MD		 2171#define uart_console(port) ((port)->cons->index == (port)->line)
2172
2173static int sci_runtime_suspend(struct device *dev)
2174{
2175 struct sci_port *sci_port = dev_get_drvdata(dev);
2176 struct uart_port *port = &sci_port->port;
2177
2178 if (uart_console(port)) {
0979e0e6
PM		 2179 struct plat_sci_reg *reg;
2180
1ba76220
MD		 2181 sci_port->saved_smr = sci_in(port, SCSMR);
2182 sci_port->saved_brr = sci_in(port, SCBRR);
0979e0e6
PM		 2183
2184 reg = sci_getreg(port, SCFCR);
2185 if (reg->size)
2186 sci_port->saved_fcr = sci_in(port, SCFCR);
2187 else
2188 sci_port->saved_fcr = 0;
1ba76220
MD		 2189 }
2190 return 0;
2191}
2192
2193static int sci_runtime_resume(struct device *dev)
2194{
2195 struct sci_port *sci_port = dev_get_drvdata(dev);
2196 struct uart_port *port = &sci_port->port;
2197
2198 if (uart_console(port)) {
2199 sci_reset(port);
2200 sci_out(port, SCSMR, sci_port->saved_smr);
2201 sci_out(port, SCBRR, sci_port->saved_brr);
0979e0e6
PM		 2202
2203 if (sci_port->saved_fcr)
2204 sci_out(port, SCFCR, sci_port->saved_fcr);
2205
1ba76220
MD		 2206 sci_out(port, SCSCR, sci_port->cfg->scscr);
2207 }
2208 return 0;
2209}
2210
6a8c9799
NI		 2211#define SCI_CONSOLE (&serial_console)
2212
ecdf8a46
PM		 2213#else
2214static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2215{
2216 return -EINVAL;
2217}
1da177e4 2218
6a8c9799 2219#define SCI_CONSOLE NULL
1ba76220
MD		 2220#define sci_runtime_suspend NULL
2221#define sci_runtime_resume NULL
6a8c9799
NI		 2222
2223#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2224
2225static char banner[] __initdata =
2226 KERN_INFO "SuperH SCI(F) driver initialized\n";
2227
2228static struct uart_driver sci_uart_driver = {
2229 .owner = THIS_MODULE,
2230 .driver_name = "sci",
1da177e4
LT		 2231 .dev_name = "ttySC",
2232 .major = SCI_MAJOR,
2233 .minor = SCI_MINOR_START,
e108b2ca 2234 .nr = SCI_NPORTS,
1da177e4
LT		 2235 .cons = SCI_CONSOLE,
2236};
2237
54507f6e 2238static int sci_remove(struct platform_device *dev)
e552de24 2239{
d535a230 2240 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2241
d535a230
PM		 2242 cpufreq_unregister_notifier(&port->freq_transition,
2243 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2244
d535a230
PM		 2245 uart_remove_one_port(&sci_uart_driver, &port->port);
2246
2247 clk_put(port->iclk);
2248 clk_put(port->fclk);
e552de24 2249
5e50d2d6 2250 pm_runtime_disable(&dev->dev);
e552de24
MD		 2251 return 0;
2252}
2253
0ee70712
MD		 2254static int __devinit sci_probe_single(struct platform_device *dev,
2255 unsigned int index,
2256 struct plat_sci_port *p,
2257 struct sci_port *sciport)
2258{
0ee70712
MD		 2259 int ret;
2260
2261 /* Sanity check */
2262 if (unlikely(index >= SCI_NPORTS)) {
2263 dev_notice(&dev->dev, "Attempting to register port "
2264 "%d when only %d are available.\n",
2265 index+1, SCI_NPORTS);
2266 dev_notice(&dev->dev, "Consider bumping "
2267 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2268 return 0;
2269 }
2270
c7ed1ab3
PM		 2271 ret = sci_init_single(dev, sciport, index, p);
2272 if (ret)
2273 return ret;
0ee70712 2274
d535a230 2275 return uart_add_one_port(&sci_uart_driver, &sciport->port);
0ee70712
MD		 2276}
2277
e108b2ca 2278static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2279{
e108b2ca 2280 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2281 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2282 int ret;
d535a230 2283
ecdf8a46
PM		 2284 /*
2285 * If we've come here via earlyprintk initialization, head off to
2286 * the special early probe. We don't have sufficient device state
2287 * to make it beyond this yet.
2288 */
2289 if (is_early_platform_device(dev))
2290 return sci_probe_earlyprintk(dev);
7b6fd3bf 2291
d535a230 2292 platform_set_drvdata(dev, sp);
e552de24 2293
906b17dc 2294 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230
PM		 2295 if (ret)
2296 goto err_unreg;
e552de24 2297
d535a230 2298 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2299
d535a230
PM		 2300 ret = cpufreq_register_notifier(&sp->freq_transition,
2301 CPUFREQ_TRANSITION_NOTIFIER);
2302 if (unlikely(ret < 0))
2303 goto err_unreg;
1da177e4
LT		 2304
2305#ifdef CONFIG_SH_STANDARD_BIOS
2306 sh_bios_gdb_detach();
2307#endif
2308
e108b2ca 2309 return 0;
7ff731ae
PM		 2310
2311err_unreg:
e552de24 2312 sci_remove(dev);
7ff731ae 2313 return ret;
1da177e4
LT		 2314}
2315
6daa79b3 2316static int sci_suspend(struct device *dev)
1da177e4 2317{
d535a230 2318 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2319
d535a230
PM		 2320 if (sport)
2321 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2322
e108b2ca
PM		 2323 return 0;
2324}
1da177e4 2325
6daa79b3 2326static int sci_resume(struct device *dev)
e108b2ca 2327{
d535a230 2328 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2329
d535a230
PM		 2330 if (sport)
2331 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2332
2333 return 0;
2334}
2335
47145210 2336static const struct dev_pm_ops sci_dev_pm_ops = {
1ba76220
MD		 2337 .runtime_suspend = sci_runtime_suspend,
2338 .runtime_resume = sci_runtime_resume,
6daa79b3
PM		 2339 .suspend = sci_suspend,
2340 .resume = sci_resume,
2341};
2342
e108b2ca
PM		 2343static struct platform_driver sci_driver = {
2344 .probe = sci_probe,
b9e39c89 2345 .remove = sci_remove,
e108b2ca
PM		 2346 .driver = {
2347 .name = "sh-sci",
2348 .owner = THIS_MODULE,
6daa79b3 2349 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2350 },
2351};
2352
2353static int __init sci_init(void)
2354{
2355 int ret;
2356
2357 printk(banner);
2358
e108b2ca
PM		 2359 ret = uart_register_driver(&sci_uart_driver);
2360 if (likely(ret == 0)) {
2361 ret = platform_driver_register(&sci_driver);
2362 if (unlikely(ret))
2363 uart_unregister_driver(&sci_uart_driver);
2364 }
2365
2366 return ret;
2367}
2368
2369static void __exit sci_exit(void)
2370{
2371 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2372 uart_unregister_driver(&sci_uart_driver);
2373}
2374
7b6fd3bf
MD		 2375#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2376early_platform_init_buffer("earlyprintk", &sci_driver,
2377 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2378#endif
1da177e4
LT		 2379module_init(sci_init);
2380module_exit(sci_exit);
2381
e108b2ca 2382MODULE_LICENSE("GPL");
e169c139 2383MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2384MODULE_AUTHOR("Paul Mundt");
2385MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux kernel - Deliverables
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