[deliverable/linux.git] / drivers / tty / serial / sh-sci.h

#include <linux/bitops.h>
#include <linux/serial_core.h>
#include <linux/io.h>
#include <linux/gpio.h>

#define SCI_MAJOR		204
#define SCI_MINOR_START		8


/*
 * SCI register subset common for all port types.
 * Not all registers will exist on all parts.
 */
enum {
	SCSMR,				/* Serial Mode Register */
	SCBRR,				/* Bit Rate Register */
	SCSCR,				/* Serial Control Register */
	SCxSR,				/* Serial Status Register */
	SCFCR,				/* FIFO Control Register */
	SCFDR,				/* FIFO Data Count Register */
	SCxTDR,				/* Transmit (FIFO) Data Register */
	SCxRDR,				/* Receive (FIFO) Data Register */
	SCLSR,				/* Line Status Register */
	SCTFDR,				/* Transmit FIFO Data Count Register */
	SCRFDR,				/* Receive FIFO Data Count Register */
	SCSPTR,				/* Serial Port Register */
	HSSRR,				/* Sampling Rate Register */
	SCPCR,				/* Serial Port Control Register */
	SCPDR,				/* Serial Port Data Register */
	SCDL,				/* BRG Frequency Division Register */
	SCCKS,				/* BRG Clock Select Register */

	SCIx_NR_REGS,
};


/* SCSMR (Serial Mode Register) */
#define SCSMR_CHR	BIT(6)	/* 7-bit Character Length */
#define SCSMR_PE	BIT(5)	/* Parity Enable */
#define SCSMR_ODD	BIT(4)	/* Odd Parity */
#define SCSMR_STOP	BIT(3)	/* Stop Bit Length */
#define SCSMR_CKS	0x0003	/* Clock Select */

/* Serial Control Register, SCIFA/SCIFB only bits */
#define SCSCR_TDRQE	BIT(15)	/* Tx Data Transfer Request Enable */
#define SCSCR_RDRQE	BIT(14)	/* Rx Data Transfer Request Enable */

/* SCxSR (Serial Status Register) on SCI */
#define SCI_TDRE	BIT(7)	/* Transmit Data Register Empty */
#define SCI_RDRF	BIT(6)	/* Receive Data Register Full */
#define SCI_ORER	BIT(5)	/* Overrun Error */
#define SCI_FER		BIT(4)	/* Framing Error */
#define SCI_PER		BIT(3)	/* Parity Error */
#define SCI_TEND	BIT(2)	/* Transmit End */
#define SCI_RESERVED	0x03	/* All reserved bits */

#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)

#define SCI_RDxF_CLEAR	(u32)(~(SCI_RESERVED | SCI_RDRF))
#define SCI_ERROR_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))
#define SCI_TDxE_CLEAR	(u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE))
#define SCI_BREAK_CLEAR	(u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER))

/* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
#define SCIF_ER		BIT(7)	/* Receive Error */
#define SCIF_TEND	BIT(6)	/* Transmission End */
#define SCIF_TDFE	BIT(5)	/* Transmit FIFO Data Empty */
#define SCIF_BRK	BIT(4)	/* Break Detect */
#define SCIF_FER	BIT(3)	/* Framing Error */
#define SCIF_PER	BIT(2)	/* Parity Error */
#define SCIF_RDF	BIT(1)	/* Receive FIFO Data Full */
#define SCIF_DR		BIT(0)	/* Receive Data Ready */
/* SCIF only (optional) */
#define SCIF_PERC	0xf000	/* Number of Parity Errors */
#define SCIF_FERC	0x0f00	/* Number of Framing Errors */
/*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */
#define SCIFA_ORER	BIT(9)	/* Overrun Error */

#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER)

#define SCIF_RDxF_CLEAR		(u32)(~(SCIF_DR | SCIF_RDF))
#define SCIF_ERROR_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_ER))
#define SCIF_TDxE_CLEAR		(u32)(~(SCIF_TDFE))
#define SCIF_BREAK_CLEAR	(u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK))

/* SCFCR (FIFO Control Register) */
#define SCFCR_MCE	BIT(3)	/* Modem Control Enable */
#define SCFCR_TFRST	BIT(2)	/* Transmit FIFO Data Register Reset */
#define SCFCR_RFRST	BIT(1)	/* Receive FIFO Data Register Reset */
#define SCFCR_LOOP	BIT(0)	/* Loopback Test */

/* SCLSR (Line Status Register) on (H)SCIF */
#define SCLSR_ORER	BIT(0)	/* Overrun Error */

/* SCSPTR (Serial Port Register), optional */
#define SCSPTR_RTSIO	BIT(7)	/* Serial Port RTS Pin Input/Output */
#define SCSPTR_RTSDT	BIT(6)	/* Serial Port RTS Pin Data */
#define SCSPTR_CTSIO	BIT(5)	/* Serial Port CTS Pin Input/Output */
#define SCSPTR_CTSDT	BIT(4)	/* Serial Port CTS Pin Data */
#define SCSPTR_SPB2IO	BIT(1)	/* Serial Port Break Input/Output */
#define SCSPTR_SPB2DT	BIT(0)	/* Serial Port Break Data */

/* HSSRR HSCIF */
#define HSCIF_SRE	BIT(15)	/* Sampling Rate Register Enable */

/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
#define SCPCR_RTSC	BIT(4)	/* Serial Port RTS Pin / Output Pin */
#define SCPCR_CTSC	BIT(3)	/* Serial Port CTS Pin / Input Pin */

/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
#define SCPDR_RTSD	BIT(4)	/* Serial Port RTS Output Pin Data */
#define SCPDR_CTSD	BIT(3)	/* Serial Port CTS Input Pin Data */

/*
 * BRG Clock Select Register (Some SCIF and HSCIF)
 * The Baud Rate Generator for external clock can provide a clock source for
 * the sampling clock. It outputs either its frequency divided clock, or the
 * (undivided) (H)SCK external clock.
 */
#define SCCKS_CKS	BIT(15)	/* Select (H)SCK (1) or divided SC_CLK (0) */
#define SCCKS_XIN	BIT(14)	/* SC_CLK uses bus clock (1) or SCIF_CLK (0) */

#define SCxSR_TEND(port)	(((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
#define SCxSR_RDxF(port)	(((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
#define SCxSR_TDxE(port)	(((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
#define SCxSR_FER(port)		(((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
#define SCxSR_PER(port)		(((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
#define SCxSR_BRK(port)		(((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)

#define SCxSR_ERRORS(port)	(to_sci_port(port)->error_mask)

#define SCxSR_RDxF_CLEAR(port) \
	(((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
#define SCxSR_ERROR_CLEAR(port) \
	(to_sci_port(port)->error_clear)
#define SCxSR_TDxE_CLEAR(port) \
	(((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
#define SCxSR_BREAK_CLEAR(port) \
	(((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
Commit	Line	Data
d94a0a38	1	#include <linux/bitops.h>
1da177e4	2	#include <linux/serial_core.h>
edad1f20	3	#include <linux/io.h>
69edbba0	4	#include <linux/gpio.h>
3ea6bc3d	5
c27ffc10 GU	6	#define SCI_MAJOR 204
	7	#define SCI_MINOR_START 8
	8
	9
	10	/*
	11	* SCI register subset common for all port types.
	12	* Not all registers will exist on all parts.
	13	*/
	14	enum {
	15	SCSMR, /* Serial Mode Register */
	16	SCBRR, /* Bit Rate Register */
	17	SCSCR, /* Serial Control Register */
	18	SCxSR, /* Serial Status Register */
	19	SCFCR, /* FIFO Control Register */
	20	SCFDR, /* FIFO Data Count Register */
	21	SCxTDR, /* Transmit (FIFO) Data Register */
	22	SCxRDR, /* Receive (FIFO) Data Register */
	23	SCLSR, /* Line Status Register */
	24	SCTFDR, /* Transmit FIFO Data Count Register */
	25	SCRFDR, /* Receive FIFO Data Count Register */
	26	SCSPTR, /* Serial Port Register */
	27	HSSRR, /* Sampling Rate Register */
c097abc3 GU	28	SCPCR, /* Serial Port Control Register */
c097abc3 GU	29	SCPDR, /* Serial Port Data Register */
b8bbd6b2 GU	30	SCDL, /* BRG Frequency Division Register */
b8bbd6b2 GU	31	SCCKS, /* BRG Clock Select Register */
c27ffc10 GU	32
	33	SCIx_NR_REGS,
	34	};
	35
	36
	37	/* SCSMR (Serial Mode Register) */
d94a0a38 GU	38	#define SCSMR_CHR BIT(6) /* 7-bit Character Length */
	39	#define SCSMR_PE BIT(5) /* Parity Enable */
	40	#define SCSMR_ODD BIT(4) /* Odd Parity */
	41	#define SCSMR_STOP BIT(3) /* Stop Bit Length */
	42	#define SCSMR_CKS 0x0003 /* Clock Select */
c27ffc10 GU	43
c27ffc10 GU	44	/* Serial Control Register, SCIFA/SCIFB only bits */
d94a0a38 GU	45	#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */
d94a0a38 GU	46	#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */
c27ffc10 GU	47
c27ffc10 GU	48	/* SCxSR (Serial Status Register) on SCI */
d94a0a38 GU	49	#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */
	50	#define SCI_RDRF BIT(6) /* Receive Data Register Full */
	51	#define SCI_ORER BIT(5) /* Overrun Error */
	52	#define SCI_FER BIT(4) /* Framing Error */
	53	#define SCI_PER BIT(3) /* Parity Error */
	54	#define SCI_TEND BIT(2) /* Transmit End */
2922598c	55	#define SCI_RESERVED 0x03 /* All reserved bits */
c27ffc10 GU	56
	57	#define SCI_DEFAULT_ERROR_MASK (SCI_PER \| SCI_FER)
	58
a9efeca6 GU	59	#define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED \| SCI_RDRF))
	60	#define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED \| SCI_PER \| SCI_FER \| SCI_ORER))
	61	#define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED \| SCI_TEND \| SCI_TDRE))
	62	#define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED \| SCI_PER \| SCI_FER \| SCI_ORER))
2922598c GU	63
2922598c GU	64	/* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */
d94a0a38 GU	65	#define SCIF_ER BIT(7) /* Receive Error */
	66	#define SCIF_TEND BIT(6) /* Transmission End */
	67	#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */
	68	#define SCIF_BRK BIT(4) /* Break Detect */
	69	#define SCIF_FER BIT(3) /* Framing Error */
	70	#define SCIF_PER BIT(2) /* Parity Error */
	71	#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */
	72	#define SCIF_DR BIT(0) /* Receive Data Ready */
2922598c GU	73	/* SCIF only (optional) */
	74	#define SCIF_PERC 0xf000 /* Number of Parity Errors */
	75	#define SCIF_FERC 0x0f00 /* Number of Framing Errors */
	76	/SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only /
	77	#define SCIFA_ORER BIT(9) /* Overrun Error */
	78
	79	#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER \| SCIF_FER \| SCIF_BRK \| SCIF_ER)
c27ffc10	80
a9efeca6	81	#define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR \| SCIF_RDF))
5da0f468	82	#define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER \| SCIF_FER \| SCIF_ER))
a9efeca6 GU	83	#define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE))
a9efeca6 GU	84	#define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER \| SCIF_FER \| SCIF_BRK))
c27ffc10 GU	85
c27ffc10 GU	86	/* SCFCR (FIFO Control Register) */
d94a0a38 GU	87	#define SCFCR_MCE BIT(3) /* Modem Control Enable */
	88	#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
	89	#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
	90	#define SCFCR_LOOP BIT(0) /* Loopback Test */
c27ffc10	91
75c249fd GU	92	/* SCLSR (Line Status Register) on (H)SCIF */
	93	#define SCLSR_ORER BIT(0) /* Overrun Error */
	94
c27ffc10	95	/* SCSPTR (Serial Port Register), optional */
d94a0a38 GU	96	#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS Pin Input/Output */
	97	#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS Pin Data */
	98	#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS Pin Input/Output */
	99	#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS Pin Data */
	100	#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
	101	#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */
c27ffc10 GU	102
c27ffc10 GU	103	/* HSSRR HSCIF */
d94a0a38	104	#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */
c27ffc10	105
c097abc3	106	/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */
d94a0a38 GU	107	#define SCPCR_RTSC BIT(4) /* Serial Port RTS Pin / Output Pin */
d94a0a38 GU	108	#define SCPCR_CTSC BIT(3) /* Serial Port CTS Pin / Input Pin */
c097abc3 GU	109
c097abc3 GU	110	/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */
d94a0a38 GU	111	#define SCPDR_RTSD BIT(4) /* Serial Port RTS Output Pin Data */
d94a0a38 GU	112	#define SCPDR_CTSD BIT(3) /* Serial Port CTS Input Pin Data */
c097abc3	113
b8bbd6b2 GU	114	/*
	115	* BRG Clock Select Register (Some SCIF and HSCIF)
	116	* The Baud Rate Generator for external clock can provide a clock source for
	117	* the sampling clock. It outputs either its frequency divided clock, or the
	118	* (undivided) (H)SCK external clock.
	119	*/
	120	#define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */
	121	#define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */
c27ffc10	122
15c73aaa	123	#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
15c73aaa PM	124	#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
	125	#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
	126	#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
	127	#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
	128	#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
debf9507	129
3ae988d9	130	#define SCxSR_ERRORS(port) (to_sci_port(port)->error_mask)
15c73aaa	131
a1b5b43f GU	132	#define SCxSR_RDxF_CLEAR(port) \
	133	(((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR)
	134	#define SCxSR_ERROR_CLEAR(port) \
5da0f468	135	(to_sci_port(port)->error_clear)
a1b5b43f GU	136	#define SCxSR_TDxE_CLEAR(port) \
	137	(((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR)
	138	#define SCxSR_BREAK_CLEAR(port) \
	139	(((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)