Commit | Line | Data |
---|---|---|
61ec9016 | 1 | /* |
d9bb3fb1 | 2 | * Cadence UART driver (found in Xilinx Zynq) |
61ec9016 | 3 | * |
e555a211 | 4 | * 2011 - 2014 (C) Xilinx Inc. |
61ec9016 JL |
5 | * |
6 | * This program is free software; you can redistribute it | |
7 | * and/or modify it under the terms of the GNU General Public | |
8 | * License as published by the Free Software Foundation; | |
9 | * either version 2 of the License, or (at your option) any | |
10 | * later version. | |
d9bb3fb1 SB |
11 | * |
12 | * This driver has originally been pushed by Xilinx using a Zynq-branding. This | |
13 | * still shows in the naming of this file, the kconfig symbols and some symbols | |
14 | * in the code. | |
61ec9016 JL |
15 | */ |
16 | ||
0c0c47bc VL |
17 | #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
18 | #define SUPPORT_SYSRQ | |
19 | #endif | |
20 | ||
61ec9016 | 21 | #include <linux/platform_device.h> |
ee160a38 | 22 | #include <linux/serial.h> |
0c0c47bc | 23 | #include <linux/console.h> |
61ec9016 | 24 | #include <linux/serial_core.h> |
30e1e285 | 25 | #include <linux/slab.h> |
ee160a38 JS |
26 | #include <linux/tty.h> |
27 | #include <linux/tty_flip.h> | |
2326669c | 28 | #include <linux/clk.h> |
61ec9016 JL |
29 | #include <linux/irq.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/of.h> | |
578b9ce0 | 32 | #include <linux/module.h> |
61ec9016 | 33 | |
d9bb3fb1 SB |
34 | #define CDNS_UART_TTY_NAME "ttyPS" |
35 | #define CDNS_UART_NAME "xuartps" | |
36 | #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ | |
37 | #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ | |
38 | #define CDNS_UART_NR_PORTS 2 | |
39 | #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ | |
9646e4fe | 40 | #define CDNS_UART_REGISTER_SPACE 0x1000 |
61ec9016 | 41 | |
85baf542 S |
42 | /* Rx Trigger level */ |
43 | static int rx_trigger_level = 56; | |
44 | module_param(rx_trigger_level, uint, S_IRUGO); | |
45 | MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); | |
46 | ||
47 | /* Rx Timeout */ | |
48 | static int rx_timeout = 10; | |
49 | module_param(rx_timeout, uint, S_IRUGO); | |
50 | MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); | |
51 | ||
e555a211 | 52 | /* Register offsets for the UART. */ |
d9bb3fb1 SB |
53 | #define CDNS_UART_CR_OFFSET 0x00 /* Control Register */ |
54 | #define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */ | |
55 | #define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */ | |
56 | #define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */ | |
57 | #define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */ | |
58 | #define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */ | |
59 | #define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */ | |
60 | #define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */ | |
61 | #define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */ | |
62 | #define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */ | |
63 | #define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */ | |
64 | #define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */ | |
65 | #define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */ | |
66 | #define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */ | |
67 | #define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */ | |
68 | #define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */ | |
69 | #define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */ | |
70 | #define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */ | |
e555a211 SB |
71 | |
72 | /* Control Register Bit Definitions */ | |
d9bb3fb1 SB |
73 | #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ |
74 | #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ | |
75 | #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ | |
76 | #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ | |
77 | #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ | |
78 | #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ | |
79 | #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ | |
80 | #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ | |
81 | #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ | |
61ec9016 | 82 | |
e555a211 SB |
83 | /* |
84 | * Mode Register: | |
61ec9016 JL |
85 | * The mode register (MR) defines the mode of transfer as well as the data |
86 | * format. If this register is modified during transmission or reception, | |
87 | * data validity cannot be guaranteed. | |
61ec9016 | 88 | */ |
d9bb3fb1 SB |
89 | #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ |
90 | #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ | |
91 | #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ | |
61ec9016 | 92 | |
d9bb3fb1 SB |
93 | #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ |
94 | #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ | |
61ec9016 | 95 | |
d9bb3fb1 SB |
96 | #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ |
97 | #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ | |
98 | #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ | |
99 | #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ | |
100 | #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ | |
61ec9016 | 101 | |
d9bb3fb1 SB |
102 | #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ |
103 | #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ | |
104 | #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ | |
61ec9016 | 105 | |
e555a211 SB |
106 | /* |
107 | * Interrupt Registers: | |
61ec9016 JL |
108 | * Interrupt control logic uses the interrupt enable register (IER) and the |
109 | * interrupt disable register (IDR) to set the value of the bits in the | |
110 | * interrupt mask register (IMR). The IMR determines whether to pass an | |
111 | * interrupt to the interrupt status register (ISR). | |
112 | * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an | |
113 | * interrupt. IMR and ISR are read only, and IER and IDR are write only. | |
114 | * Reading either IER or IDR returns 0x00. | |
61ec9016 JL |
115 | * All four registers have the same bit definitions. |
116 | */ | |
d9bb3fb1 SB |
117 | #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ |
118 | #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ | |
119 | #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ | |
120 | #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ | |
121 | #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ | |
122 | #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ | |
123 | #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ | |
124 | #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ | |
125 | #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ | |
126 | #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ | |
127 | #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ | |
61ec9016 | 128 | |
0c0c47bc | 129 | /* Goes in read_status_mask for break detection as the HW doesn't do it*/ |
d9bb3fb1 | 130 | #define CDNS_UART_IXR_BRK 0x80000000 |
0c0c47bc | 131 | |
19038ad9 LPC |
132 | /* |
133 | * Modem Control register: | |
134 | * The read/write Modem Control register controls the interface with the modem | |
135 | * or data set, or a peripheral device emulating a modem. | |
136 | */ | |
137 | #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ | |
138 | #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ | |
139 | #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ | |
140 | ||
e555a211 SB |
141 | /* |
142 | * Channel Status Register: | |
61ec9016 JL |
143 | * The channel status register (CSR) is provided to enable the control logic |
144 | * to monitor the status of bits in the channel interrupt status register, | |
145 | * even if these are masked out by the interrupt mask register. | |
146 | */ | |
d9bb3fb1 SB |
147 | #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ |
148 | #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ | |
149 | #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ | |
150 | #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ | |
61ec9016 | 151 | |
e6b39bfd | 152 | /* baud dividers min/max values */ |
d9bb3fb1 SB |
153 | #define CDNS_UART_BDIV_MIN 4 |
154 | #define CDNS_UART_BDIV_MAX 255 | |
155 | #define CDNS_UART_CD_MAX 65535 | |
e6b39bfd | 156 | |
30e1e285 | 157 | /** |
d9bb3fb1 | 158 | * struct cdns_uart - device data |
489810a1 | 159 | * @port: Pointer to the UART port |
d9bb3fb1 SB |
160 | * @uartclk: Reference clock |
161 | * @pclk: APB clock | |
489810a1 MS |
162 | * @baud: Current baud rate |
163 | * @clk_rate_change_nb: Notifier block for clock changes | |
30e1e285 | 164 | */ |
d9bb3fb1 | 165 | struct cdns_uart { |
c4b0510c | 166 | struct uart_port *port; |
d9bb3fb1 SB |
167 | struct clk *uartclk; |
168 | struct clk *pclk; | |
c4b0510c SB |
169 | unsigned int baud; |
170 | struct notifier_block clk_rate_change_nb; | |
30e1e285 | 171 | }; |
d9bb3fb1 SB |
172 | #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ |
173 | clk_rate_change_nb); | |
30e1e285 | 174 | |
61ec9016 | 175 | /** |
d9bb3fb1 | 176 | * cdns_uart_isr - Interrupt handler |
61ec9016 JL |
177 | * @irq: Irq number |
178 | * @dev_id: Id of the port | |
179 | * | |
489810a1 MS |
180 | * Return: IRQHANDLED |
181 | */ | |
d9bb3fb1 | 182 | static irqreturn_t cdns_uart_isr(int irq, void *dev_id) |
61ec9016 JL |
183 | { |
184 | struct uart_port *port = (struct uart_port *)dev_id; | |
61ec9016 JL |
185 | unsigned long flags; |
186 | unsigned int isrstatus, numbytes; | |
187 | unsigned int data; | |
188 | char status = TTY_NORMAL; | |
189 | ||
61ec9016 JL |
190 | spin_lock_irqsave(&port->lock, flags); |
191 | ||
192 | /* Read the interrupt status register to determine which | |
193 | * interrupt(s) is/are active. | |
194 | */ | |
19f22efd | 195 | isrstatus = readl(port->membase + CDNS_UART_ISR_OFFSET); |
61ec9016 | 196 | |
0c0c47bc VL |
197 | /* |
198 | * There is no hardware break detection, so we interpret framing | |
199 | * error with all-zeros data as a break sequence. Most of the time, | |
200 | * there's another non-zero byte at the end of the sequence. | |
201 | */ | |
d9bb3fb1 | 202 | if (isrstatus & CDNS_UART_IXR_FRAMING) { |
19f22efd | 203 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
d9bb3fb1 | 204 | CDNS_UART_SR_RXEMPTY)) { |
19f22efd | 205 | if (!readl(port->membase + CDNS_UART_FIFO_OFFSET)) { |
d9bb3fb1 SB |
206 | port->read_status_mask |= CDNS_UART_IXR_BRK; |
207 | isrstatus &= ~CDNS_UART_IXR_FRAMING; | |
0c0c47bc VL |
208 | } |
209 | } | |
19f22efd TB |
210 | writel(CDNS_UART_IXR_FRAMING, |
211 | port->membase + CDNS_UART_ISR_OFFSET); | |
0c0c47bc VL |
212 | } |
213 | ||
61ec9016 | 214 | /* drop byte with parity error if IGNPAR specified */ |
d9bb3fb1 SB |
215 | if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY) |
216 | isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT); | |
61ec9016 JL |
217 | |
218 | isrstatus &= port->read_status_mask; | |
219 | isrstatus &= ~port->ignore_status_mask; | |
220 | ||
d9bb3fb1 SB |
221 | if ((isrstatus & CDNS_UART_IXR_TOUT) || |
222 | (isrstatus & CDNS_UART_IXR_RXTRIG)) { | |
61ec9016 | 223 | /* Receive Timeout Interrupt */ |
19f22efd TB |
224 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
225 | CDNS_UART_SR_RXEMPTY)) { | |
226 | data = readl(port->membase + CDNS_UART_FIFO_OFFSET); | |
0c0c47bc VL |
227 | |
228 | /* Non-NULL byte after BREAK is garbage (99%) */ | |
229 | if (data && (port->read_status_mask & | |
d9bb3fb1 SB |
230 | CDNS_UART_IXR_BRK)) { |
231 | port->read_status_mask &= ~CDNS_UART_IXR_BRK; | |
0c0c47bc VL |
232 | port->icount.brk++; |
233 | if (uart_handle_break(port)) | |
234 | continue; | |
235 | } | |
236 | ||
c2db11ec | 237 | #ifdef SUPPORT_SYSRQ |
0c0c47bc VL |
238 | /* |
239 | * uart_handle_sysrq_char() doesn't work if | |
240 | * spinlocked, for some reason | |
241 | */ | |
242 | if (port->sysrq) { | |
243 | spin_unlock(&port->lock); | |
244 | if (uart_handle_sysrq_char(port, | |
245 | (unsigned char)data)) { | |
246 | spin_lock(&port->lock); | |
247 | continue; | |
248 | } | |
249 | spin_lock(&port->lock); | |
250 | } | |
c2db11ec | 251 | #endif |
0c0c47bc | 252 | |
61ec9016 JL |
253 | port->icount.rx++; |
254 | ||
d9bb3fb1 | 255 | if (isrstatus & CDNS_UART_IXR_PARITY) { |
61ec9016 JL |
256 | port->icount.parity++; |
257 | status = TTY_PARITY; | |
d9bb3fb1 | 258 | } else if (isrstatus & CDNS_UART_IXR_FRAMING) { |
61ec9016 JL |
259 | port->icount.frame++; |
260 | status = TTY_FRAME; | |
d9bb3fb1 | 261 | } else if (isrstatus & CDNS_UART_IXR_OVERRUN) { |
61ec9016 | 262 | port->icount.overrun++; |
e555a211 | 263 | } |
61ec9016 | 264 | |
d9bb3fb1 | 265 | uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN, |
2e124b4a | 266 | data, status); |
61ec9016 JL |
267 | } |
268 | spin_unlock(&port->lock); | |
2e124b4a | 269 | tty_flip_buffer_push(&port->state->port); |
61ec9016 JL |
270 | spin_lock(&port->lock); |
271 | } | |
272 | ||
273 | /* Dispatch an appropriate handler */ | |
d9bb3fb1 | 274 | if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) { |
61ec9016 | 275 | if (uart_circ_empty(&port->state->xmit)) { |
19f22efd TB |
276 | writel(CDNS_UART_IXR_TXEMPTY, |
277 | port->membase + CDNS_UART_IDR_OFFSET); | |
61ec9016 JL |
278 | } else { |
279 | numbytes = port->fifosize; | |
280 | /* Break if no more data available in the UART buffer */ | |
281 | while (numbytes--) { | |
282 | if (uart_circ_empty(&port->state->xmit)) | |
283 | break; | |
284 | /* Get the data from the UART circular buffer | |
d9bb3fb1 | 285 | * and write it to the cdns_uart's TX_FIFO |
61ec9016 JL |
286 | * register. |
287 | */ | |
19f22efd TB |
288 | writel(port->state->xmit.buf[ |
289 | port->state->xmit.tail], | |
290 | port->membase + CDNS_UART_FIFO_OFFSET); | |
61ec9016 JL |
291 | |
292 | port->icount.tx++; | |
293 | ||
294 | /* Adjust the tail of the UART buffer and wrap | |
295 | * the buffer if it reaches limit. | |
296 | */ | |
297 | port->state->xmit.tail = | |
e555a211 | 298 | (port->state->xmit.tail + 1) & |
61ec9016 JL |
299 | (UART_XMIT_SIZE - 1); |
300 | } | |
301 | ||
302 | if (uart_circ_chars_pending( | |
303 | &port->state->xmit) < WAKEUP_CHARS) | |
304 | uart_write_wakeup(port); | |
305 | } | |
306 | } | |
307 | ||
19f22efd | 308 | writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); |
61ec9016 JL |
309 | |
310 | /* be sure to release the lock and tty before leaving */ | |
311 | spin_unlock_irqrestore(&port->lock, flags); | |
61ec9016 JL |
312 | |
313 | return IRQ_HANDLED; | |
314 | } | |
315 | ||
316 | /** | |
d9bb3fb1 | 317 | * cdns_uart_calc_baud_divs - Calculate baud rate divisors |
e6b39bfd SB |
318 | * @clk: UART module input clock |
319 | * @baud: Desired baud rate | |
320 | * @rbdiv: BDIV value (return value) | |
321 | * @rcd: CD value (return value) | |
322 | * @div8: Value for clk_sel bit in mod (return value) | |
489810a1 | 323 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
324 | * was too much error, zero if no valid divisors are found. |
325 | * | |
326 | * Formula to obtain baud rate is | |
327 | * baud_tx/rx rate = clk/CD * (BDIV + 1) | |
328 | * input_clk = (Uart User Defined Clock or Apb Clock) | |
329 | * depends on UCLKEN in MR Reg | |
330 | * clk = input_clk or input_clk/8; | |
331 | * depends on CLKS in MR reg | |
332 | * CD and BDIV depends on values in | |
333 | * baud rate generate register | |
334 | * baud rate clock divisor register | |
335 | */ | |
d9bb3fb1 SB |
336 | static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, |
337 | unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) | |
61ec9016 | 338 | { |
e6b39bfd SB |
339 | u32 cd, bdiv; |
340 | unsigned int calc_baud; | |
341 | unsigned int bestbaud = 0; | |
61ec9016 | 342 | unsigned int bauderror; |
e6b39bfd | 343 | unsigned int besterror = ~0; |
61ec9016 | 344 | |
d9bb3fb1 | 345 | if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { |
e6b39bfd SB |
346 | *div8 = 1; |
347 | clk /= 8; | |
348 | } else { | |
349 | *div8 = 0; | |
350 | } | |
61ec9016 | 351 | |
d9bb3fb1 | 352 | for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { |
e6b39bfd | 353 | cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); |
d9bb3fb1 | 354 | if (cd < 1 || cd > CDNS_UART_CD_MAX) |
61ec9016 JL |
355 | continue; |
356 | ||
e6b39bfd | 357 | calc_baud = clk / (cd * (bdiv + 1)); |
61ec9016 JL |
358 | |
359 | if (baud > calc_baud) | |
360 | bauderror = baud - calc_baud; | |
361 | else | |
362 | bauderror = calc_baud - baud; | |
363 | ||
e6b39bfd SB |
364 | if (besterror > bauderror) { |
365 | *rbdiv = bdiv; | |
366 | *rcd = cd; | |
367 | bestbaud = calc_baud; | |
368 | besterror = bauderror; | |
61ec9016 JL |
369 | } |
370 | } | |
e6b39bfd SB |
371 | /* use the values when percent error is acceptable */ |
372 | if (((besterror * 100) / baud) < 3) | |
373 | bestbaud = baud; | |
374 | ||
375 | return bestbaud; | |
376 | } | |
61ec9016 | 377 | |
e6b39bfd | 378 | /** |
d9bb3fb1 | 379 | * cdns_uart_set_baud_rate - Calculate and set the baud rate |
e6b39bfd SB |
380 | * @port: Handle to the uart port structure |
381 | * @baud: Baud rate to set | |
489810a1 | 382 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
383 | * was too much error, zero if no valid divisors are found. |
384 | */ | |
d9bb3fb1 | 385 | static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, |
e6b39bfd SB |
386 | unsigned int baud) |
387 | { | |
388 | unsigned int calc_baud; | |
d54b181e | 389 | u32 cd = 0, bdiv = 0; |
e6b39bfd SB |
390 | u32 mreg; |
391 | int div8; | |
d9bb3fb1 | 392 | struct cdns_uart *cdns_uart = port->private_data; |
e6b39bfd | 393 | |
d9bb3fb1 | 394 | calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, |
e6b39bfd SB |
395 | &div8); |
396 | ||
397 | /* Write new divisors to hardware */ | |
19f22efd | 398 | mreg = readl(port->membase + CDNS_UART_MR_OFFSET); |
e6b39bfd | 399 | if (div8) |
d9bb3fb1 | 400 | mreg |= CDNS_UART_MR_CLKSEL; |
e6b39bfd | 401 | else |
d9bb3fb1 | 402 | mreg &= ~CDNS_UART_MR_CLKSEL; |
19f22efd TB |
403 | writel(mreg, port->membase + CDNS_UART_MR_OFFSET); |
404 | writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET); | |
405 | writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET); | |
d9bb3fb1 | 406 | cdns_uart->baud = baud; |
61ec9016 JL |
407 | |
408 | return calc_baud; | |
409 | } | |
410 | ||
7ac57347 | 411 | #ifdef CONFIG_COMMON_CLK |
c4b0510c | 412 | /** |
d9bb3fb1 | 413 | * cdns_uart_clk_notitifer_cb - Clock notifier callback |
c4b0510c SB |
414 | * @nb: Notifier block |
415 | * @event: Notify event | |
416 | * @data: Notifier data | |
e555a211 | 417 | * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. |
c4b0510c | 418 | */ |
d9bb3fb1 | 419 | static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, |
c4b0510c SB |
420 | unsigned long event, void *data) |
421 | { | |
422 | u32 ctrl_reg; | |
423 | struct uart_port *port; | |
424 | int locked = 0; | |
425 | struct clk_notifier_data *ndata = data; | |
426 | unsigned long flags = 0; | |
d9bb3fb1 | 427 | struct cdns_uart *cdns_uart = to_cdns_uart(nb); |
c4b0510c | 428 | |
d9bb3fb1 | 429 | port = cdns_uart->port; |
c4b0510c SB |
430 | if (port->suspended) |
431 | return NOTIFY_OK; | |
432 | ||
433 | switch (event) { | |
434 | case PRE_RATE_CHANGE: | |
435 | { | |
e555a211 | 436 | u32 bdiv, cd; |
c4b0510c SB |
437 | int div8; |
438 | ||
439 | /* | |
440 | * Find out if current baud-rate can be achieved with new clock | |
441 | * frequency. | |
442 | */ | |
d9bb3fb1 | 443 | if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, |
5ce15d2d SB |
444 | &bdiv, &cd, &div8)) { |
445 | dev_warn(port->dev, "clock rate change rejected\n"); | |
c4b0510c | 446 | return NOTIFY_BAD; |
5ce15d2d | 447 | } |
c4b0510c | 448 | |
d9bb3fb1 | 449 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
450 | |
451 | /* Disable the TX and RX to set baud rate */ | |
19f22efd | 452 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 | 453 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
19f22efd | 454 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
c4b0510c | 455 | |
d9bb3fb1 | 456 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
457 | |
458 | return NOTIFY_OK; | |
459 | } | |
460 | case POST_RATE_CHANGE: | |
461 | /* | |
462 | * Set clk dividers to generate correct baud with new clock | |
463 | * frequency. | |
464 | */ | |
465 | ||
d9bb3fb1 | 466 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
467 | |
468 | locked = 1; | |
469 | port->uartclk = ndata->new_rate; | |
470 | ||
d9bb3fb1 SB |
471 | cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, |
472 | cdns_uart->baud); | |
c4b0510c SB |
473 | /* fall through */ |
474 | case ABORT_RATE_CHANGE: | |
475 | if (!locked) | |
d9bb3fb1 | 476 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
477 | |
478 | /* Set TX/RX Reset */ | |
19f22efd | 479 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 | 480 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
19f22efd | 481 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
c4b0510c | 482 | |
19f22efd | 483 | while (readl(port->membase + CDNS_UART_CR_OFFSET) & |
d9bb3fb1 | 484 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
c4b0510c SB |
485 | cpu_relax(); |
486 | ||
487 | /* | |
488 | * Clear the RX disable and TX disable bits and then set the TX | |
489 | * enable bit and RX enable bit to enable the transmitter and | |
490 | * receiver. | |
491 | */ | |
19f22efd TB |
492 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
493 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); | |
d9bb3fb1 SB |
494 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
495 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
19f22efd | 496 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
c4b0510c | 497 | |
d9bb3fb1 | 498 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
499 | |
500 | return NOTIFY_OK; | |
501 | default: | |
502 | return NOTIFY_DONE; | |
503 | } | |
504 | } | |
7ac57347 | 505 | #endif |
c4b0510c | 506 | |
61ec9016 | 507 | /** |
d9bb3fb1 | 508 | * cdns_uart_start_tx - Start transmitting bytes |
61ec9016 | 509 | * @port: Handle to the uart port structure |
489810a1 | 510 | */ |
d9bb3fb1 | 511 | static void cdns_uart_start_tx(struct uart_port *port) |
61ec9016 JL |
512 | { |
513 | unsigned int status, numbytes = port->fifosize; | |
514 | ||
515 | if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port)) | |
516 | return; | |
517 | ||
19f22efd | 518 | status = readl(port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 JL |
519 | /* Set the TX enable bit and clear the TX disable bit to enable the |
520 | * transmitter. | |
521 | */ | |
19f22efd TB |
522 | writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, |
523 | port->membase + CDNS_UART_CR_OFFSET); | |
61ec9016 | 524 | |
19f22efd | 525 | while (numbytes-- && ((readl(port->membase + CDNS_UART_SR_OFFSET) & |
d9bb3fb1 | 526 | CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) { |
61ec9016 JL |
527 | /* Break if no more data available in the UART buffer */ |
528 | if (uart_circ_empty(&port->state->xmit)) | |
529 | break; | |
530 | ||
531 | /* Get the data from the UART circular buffer and | |
d9bb3fb1 | 532 | * write it to the cdns_uart's TX_FIFO register. |
61ec9016 | 533 | */ |
19f22efd TB |
534 | writel(port->state->xmit.buf[port->state->xmit.tail], |
535 | port->membase + CDNS_UART_FIFO_OFFSET); | |
61ec9016 JL |
536 | port->icount.tx++; |
537 | ||
538 | /* Adjust the tail of the UART buffer and wrap | |
539 | * the buffer if it reaches limit. | |
540 | */ | |
541 | port->state->xmit.tail = (port->state->xmit.tail + 1) & | |
542 | (UART_XMIT_SIZE - 1); | |
543 | } | |
19f22efd | 544 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET); |
61ec9016 | 545 | /* Enable the TX Empty interrupt */ |
19f22efd | 546 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET); |
61ec9016 JL |
547 | |
548 | if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) | |
549 | uart_write_wakeup(port); | |
550 | } | |
551 | ||
552 | /** | |
d9bb3fb1 | 553 | * cdns_uart_stop_tx - Stop TX |
61ec9016 | 554 | * @port: Handle to the uart port structure |
489810a1 | 555 | */ |
d9bb3fb1 | 556 | static void cdns_uart_stop_tx(struct uart_port *port) |
61ec9016 JL |
557 | { |
558 | unsigned int regval; | |
559 | ||
19f22efd | 560 | regval = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 | 561 | regval |= CDNS_UART_CR_TX_DIS; |
61ec9016 | 562 | /* Disable the transmitter */ |
19f22efd | 563 | writel(regval, port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 JL |
564 | } |
565 | ||
566 | /** | |
d9bb3fb1 | 567 | * cdns_uart_stop_rx - Stop RX |
61ec9016 | 568 | * @port: Handle to the uart port structure |
489810a1 | 569 | */ |
d9bb3fb1 | 570 | static void cdns_uart_stop_rx(struct uart_port *port) |
61ec9016 JL |
571 | { |
572 | unsigned int regval; | |
573 | ||
19f22efd | 574 | regval = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 | 575 | regval |= CDNS_UART_CR_RX_DIS; |
61ec9016 | 576 | /* Disable the receiver */ |
19f22efd | 577 | writel(regval, port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 JL |
578 | } |
579 | ||
580 | /** | |
d9bb3fb1 | 581 | * cdns_uart_tx_empty - Check whether TX is empty |
61ec9016 JL |
582 | * @port: Handle to the uart port structure |
583 | * | |
489810a1 MS |
584 | * Return: TIOCSER_TEMT on success, 0 otherwise |
585 | */ | |
d9bb3fb1 | 586 | static unsigned int cdns_uart_tx_empty(struct uart_port *port) |
61ec9016 JL |
587 | { |
588 | unsigned int status; | |
589 | ||
19f22efd TB |
590 | status = readl(port->membase + CDNS_UART_SR_OFFSET) & |
591 | CDNS_UART_SR_TXEMPTY; | |
61ec9016 JL |
592 | return status ? TIOCSER_TEMT : 0; |
593 | } | |
594 | ||
595 | /** | |
d9bb3fb1 | 596 | * cdns_uart_break_ctl - Based on the input ctl we have to start or stop |
61ec9016 JL |
597 | * transmitting char breaks |
598 | * @port: Handle to the uart port structure | |
599 | * @ctl: Value based on which start or stop decision is taken | |
489810a1 | 600 | */ |
d9bb3fb1 | 601 | static void cdns_uart_break_ctl(struct uart_port *port, int ctl) |
61ec9016 JL |
602 | { |
603 | unsigned int status; | |
604 | unsigned long flags; | |
605 | ||
606 | spin_lock_irqsave(&port->lock, flags); | |
607 | ||
19f22efd | 608 | status = readl(port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 JL |
609 | |
610 | if (ctl == -1) | |
19f22efd TB |
611 | writel(CDNS_UART_CR_STARTBRK | status, |
612 | port->membase + CDNS_UART_CR_OFFSET); | |
61ec9016 | 613 | else { |
d9bb3fb1 | 614 | if ((status & CDNS_UART_CR_STOPBRK) == 0) |
19f22efd TB |
615 | writel(CDNS_UART_CR_STOPBRK | status, |
616 | port->membase + CDNS_UART_CR_OFFSET); | |
61ec9016 JL |
617 | } |
618 | spin_unlock_irqrestore(&port->lock, flags); | |
619 | } | |
620 | ||
621 | /** | |
d9bb3fb1 | 622 | * cdns_uart_set_termios - termios operations, handling data length, parity, |
61ec9016 JL |
623 | * stop bits, flow control, baud rate |
624 | * @port: Handle to the uart port structure | |
625 | * @termios: Handle to the input termios structure | |
626 | * @old: Values of the previously saved termios structure | |
489810a1 | 627 | */ |
d9bb3fb1 | 628 | static void cdns_uart_set_termios(struct uart_port *port, |
61ec9016 JL |
629 | struct ktermios *termios, struct ktermios *old) |
630 | { | |
631 | unsigned int cval = 0; | |
e6b39bfd | 632 | unsigned int baud, minbaud, maxbaud; |
61ec9016 JL |
633 | unsigned long flags; |
634 | unsigned int ctrl_reg, mode_reg; | |
635 | ||
636 | spin_lock_irqsave(&port->lock, flags); | |
637 | ||
6ecde472 | 638 | /* Wait for the transmit FIFO to empty before making changes */ |
19f22efd TB |
639 | if (!(readl(port->membase + CDNS_UART_CR_OFFSET) & |
640 | CDNS_UART_CR_TX_DIS)) { | |
641 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & | |
6ecde472 NR |
642 | CDNS_UART_SR_TXEMPTY)) { |
643 | cpu_relax(); | |
644 | } | |
61ec9016 JL |
645 | } |
646 | ||
647 | /* Disable the TX and RX to set baud rate */ | |
19f22efd | 648 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 | 649 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
19f22efd | 650 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 | 651 | |
e6b39bfd SB |
652 | /* |
653 | * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk | |
654 | * min and max baud should be calculated here based on port->uartclk. | |
655 | * this way we get a valid baud and can safely call set_baud() | |
656 | */ | |
d9bb3fb1 SB |
657 | minbaud = port->uartclk / |
658 | ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); | |
659 | maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); | |
e6b39bfd | 660 | baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); |
d9bb3fb1 | 661 | baud = cdns_uart_set_baud_rate(port, baud); |
61ec9016 JL |
662 | if (tty_termios_baud_rate(termios)) |
663 | tty_termios_encode_baud_rate(termios, baud, baud); | |
664 | ||
e555a211 | 665 | /* Update the per-port timeout. */ |
61ec9016 JL |
666 | uart_update_timeout(port, termios->c_cflag, baud); |
667 | ||
668 | /* Set TX/RX Reset */ | |
19f22efd | 669 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 | 670 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
19f22efd | 671 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 | 672 | |
e555a211 SB |
673 | /* |
674 | * Clear the RX disable and TX disable bits and then set the TX enable | |
61ec9016 JL |
675 | * bit and RX enable bit to enable the transmitter and receiver. |
676 | */ | |
19f22efd | 677 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 SB |
678 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
679 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
19f22efd | 680 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 | 681 | |
19f22efd | 682 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
61ec9016 | 683 | |
d9bb3fb1 SB |
684 | port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | |
685 | CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; | |
61ec9016 JL |
686 | port->ignore_status_mask = 0; |
687 | ||
688 | if (termios->c_iflag & INPCK) | |
d9bb3fb1 SB |
689 | port->read_status_mask |= CDNS_UART_IXR_PARITY | |
690 | CDNS_UART_IXR_FRAMING; | |
61ec9016 JL |
691 | |
692 | if (termios->c_iflag & IGNPAR) | |
d9bb3fb1 SB |
693 | port->ignore_status_mask |= CDNS_UART_IXR_PARITY | |
694 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 JL |
695 | |
696 | /* ignore all characters if CREAD is not set */ | |
697 | if ((termios->c_cflag & CREAD) == 0) | |
d9bb3fb1 SB |
698 | port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | |
699 | CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | | |
700 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 | 701 | |
19f22efd | 702 | mode_reg = readl(port->membase + CDNS_UART_MR_OFFSET); |
61ec9016 JL |
703 | |
704 | /* Handling Data Size */ | |
705 | switch (termios->c_cflag & CSIZE) { | |
706 | case CS6: | |
d9bb3fb1 | 707 | cval |= CDNS_UART_MR_CHARLEN_6_BIT; |
61ec9016 JL |
708 | break; |
709 | case CS7: | |
d9bb3fb1 | 710 | cval |= CDNS_UART_MR_CHARLEN_7_BIT; |
61ec9016 JL |
711 | break; |
712 | default: | |
713 | case CS8: | |
d9bb3fb1 | 714 | cval |= CDNS_UART_MR_CHARLEN_8_BIT; |
61ec9016 JL |
715 | termios->c_cflag &= ~CSIZE; |
716 | termios->c_cflag |= CS8; | |
717 | break; | |
718 | } | |
719 | ||
720 | /* Handling Parity and Stop Bits length */ | |
721 | if (termios->c_cflag & CSTOPB) | |
d9bb3fb1 | 722 | cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ |
61ec9016 | 723 | else |
d9bb3fb1 | 724 | cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ |
61ec9016 JL |
725 | |
726 | if (termios->c_cflag & PARENB) { | |
727 | /* Mark or Space parity */ | |
728 | if (termios->c_cflag & CMSPAR) { | |
729 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 730 | cval |= CDNS_UART_MR_PARITY_MARK; |
61ec9016 | 731 | else |
d9bb3fb1 | 732 | cval |= CDNS_UART_MR_PARITY_SPACE; |
e6b39bfd SB |
733 | } else { |
734 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 735 | cval |= CDNS_UART_MR_PARITY_ODD; |
61ec9016 | 736 | else |
d9bb3fb1 | 737 | cval |= CDNS_UART_MR_PARITY_EVEN; |
e6b39bfd SB |
738 | } |
739 | } else { | |
d9bb3fb1 | 740 | cval |= CDNS_UART_MR_PARITY_NONE; |
e6b39bfd SB |
741 | } |
742 | cval |= mode_reg & 1; | |
19f22efd | 743 | writel(cval, port->membase + CDNS_UART_MR_OFFSET); |
61ec9016 JL |
744 | |
745 | spin_unlock_irqrestore(&port->lock, flags); | |
746 | } | |
747 | ||
748 | /** | |
d9bb3fb1 | 749 | * cdns_uart_startup - Called when an application opens a cdns_uart port |
61ec9016 JL |
750 | * @port: Handle to the uart port structure |
751 | * | |
e555a211 | 752 | * Return: 0 on success, negative errno otherwise |
489810a1 | 753 | */ |
d9bb3fb1 | 754 | static int cdns_uart_startup(struct uart_port *port) |
61ec9016 JL |
755 | { |
756 | unsigned int retval = 0, status = 0; | |
757 | ||
d9bb3fb1 | 758 | retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, |
61ec9016 JL |
759 | (void *)port); |
760 | if (retval) | |
761 | return retval; | |
762 | ||
763 | /* Disable the TX and RX */ | |
19f22efd TB |
764 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
765 | port->membase + CDNS_UART_CR_OFFSET); | |
61ec9016 JL |
766 | |
767 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, | |
768 | * no break chars. | |
769 | */ | |
19f22efd TB |
770 | writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, |
771 | port->membase + CDNS_UART_CR_OFFSET); | |
61ec9016 | 772 | |
19f22efd | 773 | status = readl(port->membase + CDNS_UART_CR_OFFSET); |
61ec9016 JL |
774 | |
775 | /* Clear the RX disable and TX disable bits and then set the TX enable | |
776 | * bit and RX enable bit to enable the transmitter and receiver. | |
777 | */ | |
19f22efd | 778 | writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS)) |
d9bb3fb1 | 779 | | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN | |
19f22efd TB |
780 | CDNS_UART_CR_STOPBRK), |
781 | port->membase + CDNS_UART_CR_OFFSET); | |
61ec9016 JL |
782 | |
783 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, | |
784 | * no parity. | |
785 | */ | |
19f22efd | 786 | writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT |
d9bb3fb1 | 787 | | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, |
19f22efd | 788 | port->membase + CDNS_UART_MR_OFFSET); |
61ec9016 | 789 | |
85baf542 S |
790 | /* |
791 | * Set the RX FIFO Trigger level to use most of the FIFO, but it | |
792 | * can be tuned with a module parameter | |
793 | */ | |
19f22efd | 794 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET); |
61ec9016 | 795 | |
85baf542 S |
796 | /* |
797 | * Receive Timeout register is enabled but it | |
798 | * can be tuned with a module parameter | |
799 | */ | |
19f22efd | 800 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
61ec9016 | 801 | |
855f6fd9 | 802 | /* Clear out any pending interrupts before enabling them */ |
19f22efd TB |
803 | writel(readl(port->membase + CDNS_UART_ISR_OFFSET), |
804 | port->membase + CDNS_UART_ISR_OFFSET); | |
61ec9016 JL |
805 | |
806 | /* Set the Interrupt Registers with desired interrupts */ | |
19f22efd | 807 | writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY | |
d9bb3fb1 SB |
808 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN | |
809 | CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT, | |
19f22efd | 810 | port->membase + CDNS_UART_IER_OFFSET); |
61ec9016 JL |
811 | |
812 | return retval; | |
813 | } | |
814 | ||
815 | /** | |
d9bb3fb1 | 816 | * cdns_uart_shutdown - Called when an application closes a cdns_uart port |
61ec9016 | 817 | * @port: Handle to the uart port structure |
489810a1 | 818 | */ |
d9bb3fb1 | 819 | static void cdns_uart_shutdown(struct uart_port *port) |
61ec9016 JL |
820 | { |
821 | int status; | |
822 | ||
823 | /* Disable interrupts */ | |
19f22efd TB |
824 | status = readl(port->membase + CDNS_UART_IMR_OFFSET); |
825 | writel(status, port->membase + CDNS_UART_IDR_OFFSET); | |
61ec9016 JL |
826 | |
827 | /* Disable the TX and RX */ | |
19f22efd TB |
828 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
829 | port->membase + CDNS_UART_CR_OFFSET); | |
61ec9016 JL |
830 | free_irq(port->irq, port); |
831 | } | |
832 | ||
833 | /** | |
d9bb3fb1 | 834 | * cdns_uart_type - Set UART type to cdns_uart port |
61ec9016 JL |
835 | * @port: Handle to the uart port structure |
836 | * | |
489810a1 MS |
837 | * Return: string on success, NULL otherwise |
838 | */ | |
d9bb3fb1 | 839 | static const char *cdns_uart_type(struct uart_port *port) |
61ec9016 | 840 | { |
d9bb3fb1 | 841 | return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; |
61ec9016 JL |
842 | } |
843 | ||
844 | /** | |
d9bb3fb1 | 845 | * cdns_uart_verify_port - Verify the port params |
61ec9016 JL |
846 | * @port: Handle to the uart port structure |
847 | * @ser: Handle to the structure whose members are compared | |
848 | * | |
e555a211 | 849 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 850 | */ |
d9bb3fb1 | 851 | static int cdns_uart_verify_port(struct uart_port *port, |
61ec9016 JL |
852 | struct serial_struct *ser) |
853 | { | |
854 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) | |
855 | return -EINVAL; | |
856 | if (port->irq != ser->irq) | |
857 | return -EINVAL; | |
858 | if (ser->io_type != UPIO_MEM) | |
859 | return -EINVAL; | |
860 | if (port->iobase != ser->port) | |
861 | return -EINVAL; | |
862 | if (ser->hub6 != 0) | |
863 | return -EINVAL; | |
864 | return 0; | |
865 | } | |
866 | ||
867 | /** | |
d9bb3fb1 SB |
868 | * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, |
869 | * called when the driver adds a cdns_uart port via | |
61ec9016 JL |
870 | * uart_add_one_port() |
871 | * @port: Handle to the uart port structure | |
872 | * | |
e555a211 | 873 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 874 | */ |
d9bb3fb1 | 875 | static int cdns_uart_request_port(struct uart_port *port) |
61ec9016 | 876 | { |
d9bb3fb1 SB |
877 | if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, |
878 | CDNS_UART_NAME)) { | |
61ec9016 JL |
879 | return -ENOMEM; |
880 | } | |
881 | ||
d9bb3fb1 | 882 | port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
883 | if (!port->membase) { |
884 | dev_err(port->dev, "Unable to map registers\n"); | |
d9bb3fb1 | 885 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
886 | return -ENOMEM; |
887 | } | |
888 | return 0; | |
889 | } | |
890 | ||
891 | /** | |
d9bb3fb1 | 892 | * cdns_uart_release_port - Release UART port |
61ec9016 | 893 | * @port: Handle to the uart port structure |
e555a211 | 894 | * |
d9bb3fb1 SB |
895 | * Release the memory region attached to a cdns_uart port. Called when the |
896 | * driver removes a cdns_uart port via uart_remove_one_port(). | |
489810a1 | 897 | */ |
d9bb3fb1 | 898 | static void cdns_uart_release_port(struct uart_port *port) |
61ec9016 | 899 | { |
d9bb3fb1 | 900 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
901 | iounmap(port->membase); |
902 | port->membase = NULL; | |
903 | } | |
904 | ||
905 | /** | |
d9bb3fb1 | 906 | * cdns_uart_config_port - Configure UART port |
61ec9016 JL |
907 | * @port: Handle to the uart port structure |
908 | * @flags: If any | |
489810a1 | 909 | */ |
d9bb3fb1 | 910 | static void cdns_uart_config_port(struct uart_port *port, int flags) |
61ec9016 | 911 | { |
d9bb3fb1 | 912 | if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) |
61ec9016 JL |
913 | port->type = PORT_XUARTPS; |
914 | } | |
915 | ||
916 | /** | |
d9bb3fb1 | 917 | * cdns_uart_get_mctrl - Get the modem control state |
61ec9016 JL |
918 | * @port: Handle to the uart port structure |
919 | * | |
489810a1 MS |
920 | * Return: the modem control state |
921 | */ | |
d9bb3fb1 | 922 | static unsigned int cdns_uart_get_mctrl(struct uart_port *port) |
61ec9016 JL |
923 | { |
924 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
925 | } | |
926 | ||
d9bb3fb1 | 927 | static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
61ec9016 | 928 | { |
19038ad9 LPC |
929 | u32 val; |
930 | ||
19f22efd | 931 | val = readl(port->membase + CDNS_UART_MODEMCR_OFFSET); |
19038ad9 LPC |
932 | |
933 | val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); | |
934 | ||
935 | if (mctrl & TIOCM_RTS) | |
936 | val |= CDNS_UART_MODEMCR_RTS; | |
937 | if (mctrl & TIOCM_DTR) | |
938 | val |= CDNS_UART_MODEMCR_DTR; | |
939 | ||
19f22efd | 940 | writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET); |
61ec9016 JL |
941 | } |
942 | ||
6ee04c6c | 943 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 | 944 | static int cdns_uart_poll_get_char(struct uart_port *port) |
6ee04c6c VL |
945 | { |
946 | u32 imr; | |
947 | int c; | |
948 | ||
949 | /* Disable all interrupts */ | |
19f22efd TB |
950 | imr = readl(port->membase + CDNS_UART_IMR_OFFSET); |
951 | writel(imr, port->membase + CDNS_UART_IDR_OFFSET); | |
6ee04c6c VL |
952 | |
953 | /* Check if FIFO is empty */ | |
19f22efd | 954 | if (readl(port->membase + CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY) |
6ee04c6c VL |
955 | c = NO_POLL_CHAR; |
956 | else /* Read a character */ | |
19f22efd TB |
957 | c = (unsigned char) readl( |
958 | port->membase + CDNS_UART_FIFO_OFFSET); | |
6ee04c6c VL |
959 | |
960 | /* Enable interrupts */ | |
19f22efd | 961 | writel(imr, port->membase + CDNS_UART_IER_OFFSET); |
6ee04c6c VL |
962 | |
963 | return c; | |
964 | } | |
965 | ||
d9bb3fb1 | 966 | static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) |
6ee04c6c VL |
967 | { |
968 | u32 imr; | |
969 | ||
970 | /* Disable all interrupts */ | |
19f22efd TB |
971 | imr = readl(port->membase + CDNS_UART_IMR_OFFSET); |
972 | writel(imr, port->membase + CDNS_UART_IDR_OFFSET); | |
6ee04c6c VL |
973 | |
974 | /* Wait until FIFO is empty */ | |
19f22efd TB |
975 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
976 | CDNS_UART_SR_TXEMPTY)) | |
6ee04c6c VL |
977 | cpu_relax(); |
978 | ||
979 | /* Write a character */ | |
19f22efd | 980 | writel(c, port->membase + CDNS_UART_FIFO_OFFSET); |
6ee04c6c VL |
981 | |
982 | /* Wait until FIFO is empty */ | |
19f22efd TB |
983 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
984 | CDNS_UART_SR_TXEMPTY)) | |
6ee04c6c VL |
985 | cpu_relax(); |
986 | ||
987 | /* Enable interrupts */ | |
19f22efd | 988 | writel(imr, port->membase + CDNS_UART_IER_OFFSET); |
6ee04c6c VL |
989 | |
990 | return; | |
991 | } | |
992 | #endif | |
993 | ||
d9bb3fb1 SB |
994 | static struct uart_ops cdns_uart_ops = { |
995 | .set_mctrl = cdns_uart_set_mctrl, | |
996 | .get_mctrl = cdns_uart_get_mctrl, | |
d9bb3fb1 SB |
997 | .start_tx = cdns_uart_start_tx, |
998 | .stop_tx = cdns_uart_stop_tx, | |
999 | .stop_rx = cdns_uart_stop_rx, | |
1000 | .tx_empty = cdns_uart_tx_empty, | |
1001 | .break_ctl = cdns_uart_break_ctl, | |
1002 | .set_termios = cdns_uart_set_termios, | |
1003 | .startup = cdns_uart_startup, | |
1004 | .shutdown = cdns_uart_shutdown, | |
1005 | .type = cdns_uart_type, | |
1006 | .verify_port = cdns_uart_verify_port, | |
1007 | .request_port = cdns_uart_request_port, | |
1008 | .release_port = cdns_uart_release_port, | |
1009 | .config_port = cdns_uart_config_port, | |
6ee04c6c | 1010 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 SB |
1011 | .poll_get_char = cdns_uart_poll_get_char, |
1012 | .poll_put_char = cdns_uart_poll_put_char, | |
6ee04c6c | 1013 | #endif |
61ec9016 JL |
1014 | }; |
1015 | ||
6db6df0e | 1016 | static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; |
61ec9016 JL |
1017 | |
1018 | /** | |
d9bb3fb1 | 1019 | * cdns_uart_get_port - Configure the port from platform device resource info |
928e9263 MS |
1020 | * @id: Port id |
1021 | * | |
489810a1 MS |
1022 | * Return: a pointer to a uart_port or NULL for failure |
1023 | */ | |
d9bb3fb1 | 1024 | static struct uart_port *cdns_uart_get_port(int id) |
61ec9016 JL |
1025 | { |
1026 | struct uart_port *port; | |
61ec9016 | 1027 | |
928e9263 | 1028 | /* Try the given port id if failed use default method */ |
d9bb3fb1 | 1029 | if (cdns_uart_port[id].mapbase != 0) { |
928e9263 | 1030 | /* Find the next unused port */ |
d9bb3fb1 SB |
1031 | for (id = 0; id < CDNS_UART_NR_PORTS; id++) |
1032 | if (cdns_uart_port[id].mapbase == 0) | |
928e9263 MS |
1033 | break; |
1034 | } | |
61ec9016 | 1035 | |
d9bb3fb1 | 1036 | if (id >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1037 | return NULL; |
1038 | ||
d9bb3fb1 | 1039 | port = &cdns_uart_port[id]; |
61ec9016 JL |
1040 | |
1041 | /* At this point, we've got an empty uart_port struct, initialize it */ | |
1042 | spin_lock_init(&port->lock); | |
1043 | port->membase = NULL; | |
61ec9016 JL |
1044 | port->irq = 0; |
1045 | port->type = PORT_UNKNOWN; | |
1046 | port->iotype = UPIO_MEM32; | |
1047 | port->flags = UPF_BOOT_AUTOCONF; | |
d9bb3fb1 SB |
1048 | port->ops = &cdns_uart_ops; |
1049 | port->fifosize = CDNS_UART_FIFO_SIZE; | |
61ec9016 JL |
1050 | port->line = id; |
1051 | port->dev = NULL; | |
1052 | return port; | |
1053 | } | |
1054 | ||
61ec9016 JL |
1055 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
1056 | /** | |
d9bb3fb1 | 1057 | * cdns_uart_console_wait_tx - Wait for the TX to be full |
61ec9016 | 1058 | * @port: Handle to the uart port structure |
489810a1 | 1059 | */ |
d9bb3fb1 | 1060 | static void cdns_uart_console_wait_tx(struct uart_port *port) |
61ec9016 | 1061 | { |
19f22efd TB |
1062 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
1063 | CDNS_UART_SR_TXEMPTY)) | |
61ec9016 JL |
1064 | barrier(); |
1065 | } | |
1066 | ||
1067 | /** | |
d9bb3fb1 | 1068 | * cdns_uart_console_putchar - write the character to the FIFO buffer |
61ec9016 JL |
1069 | * @port: Handle to the uart port structure |
1070 | * @ch: Character to be written | |
489810a1 | 1071 | */ |
d9bb3fb1 | 1072 | static void cdns_uart_console_putchar(struct uart_port *port, int ch) |
61ec9016 | 1073 | { |
d9bb3fb1 | 1074 | cdns_uart_console_wait_tx(port); |
19f22efd | 1075 | writel(ch, port->membase + CDNS_UART_FIFO_OFFSET); |
61ec9016 JL |
1076 | } |
1077 | ||
54585ba0 MY |
1078 | static void __init cdns_early_write(struct console *con, const char *s, |
1079 | unsigned n) | |
6fa62fc4 MS |
1080 | { |
1081 | struct earlycon_device *dev = con->data; | |
1082 | ||
1083 | uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); | |
1084 | } | |
1085 | ||
1086 | static int __init cdns_early_console_setup(struct earlycon_device *device, | |
1087 | const char *opt) | |
1088 | { | |
1089 | if (!device->port.membase) | |
1090 | return -ENODEV; | |
1091 | ||
1092 | device->con->write = cdns_early_write; | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | EARLYCON_DECLARE(cdns, cdns_early_console_setup); | |
1097 | ||
61ec9016 | 1098 | /** |
d9bb3fb1 | 1099 | * cdns_uart_console_write - perform write operation |
489810a1 | 1100 | * @co: Console handle |
61ec9016 JL |
1101 | * @s: Pointer to character array |
1102 | * @count: No of characters | |
489810a1 | 1103 | */ |
d9bb3fb1 | 1104 | static void cdns_uart_console_write(struct console *co, const char *s, |
61ec9016 JL |
1105 | unsigned int count) |
1106 | { | |
d9bb3fb1 | 1107 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 | 1108 | unsigned long flags; |
d3755f5e | 1109 | unsigned int imr, ctrl; |
61ec9016 JL |
1110 | int locked = 1; |
1111 | ||
1112 | if (oops_in_progress) | |
1113 | locked = spin_trylock_irqsave(&port->lock, flags); | |
1114 | else | |
1115 | spin_lock_irqsave(&port->lock, flags); | |
1116 | ||
1117 | /* save and disable interrupt */ | |
19f22efd TB |
1118 | imr = readl(port->membase + CDNS_UART_IMR_OFFSET); |
1119 | writel(imr, port->membase + CDNS_UART_IDR_OFFSET); | |
61ec9016 | 1120 | |
d3755f5e LPC |
1121 | /* |
1122 | * Make sure that the tx part is enabled. Set the TX enable bit and | |
1123 | * clear the TX disable bit to enable the transmitter. | |
1124 | */ | |
19f22efd TB |
1125 | ctrl = readl(port->membase + CDNS_UART_CR_OFFSET); |
1126 | writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, | |
1127 | port->membase + CDNS_UART_CR_OFFSET); | |
d3755f5e | 1128 | |
d9bb3fb1 SB |
1129 | uart_console_write(port, s, count, cdns_uart_console_putchar); |
1130 | cdns_uart_console_wait_tx(port); | |
61ec9016 | 1131 | |
19f22efd | 1132 | writel(ctrl, port->membase + CDNS_UART_CR_OFFSET); |
d3755f5e | 1133 | |
b494a5fa | 1134 | /* restore interrupt state */ |
19f22efd | 1135 | writel(imr, port->membase + CDNS_UART_IER_OFFSET); |
61ec9016 JL |
1136 | |
1137 | if (locked) | |
1138 | spin_unlock_irqrestore(&port->lock, flags); | |
1139 | } | |
1140 | ||
1141 | /** | |
d9bb3fb1 | 1142 | * cdns_uart_console_setup - Initialize the uart to default config |
61ec9016 JL |
1143 | * @co: Console handle |
1144 | * @options: Initial settings of uart | |
1145 | * | |
e555a211 | 1146 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 1147 | */ |
d9bb3fb1 | 1148 | static int __init cdns_uart_console_setup(struct console *co, char *options) |
61ec9016 | 1149 | { |
d9bb3fb1 | 1150 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 JL |
1151 | int baud = 9600; |
1152 | int bits = 8; | |
1153 | int parity = 'n'; | |
1154 | int flow = 'n'; | |
1155 | ||
d9bb3fb1 | 1156 | if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1157 | return -EINVAL; |
1158 | ||
136debf7 | 1159 | if (!port->membase) { |
f6415491 PC |
1160 | pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", |
1161 | co->index); | |
61ec9016 JL |
1162 | return -ENODEV; |
1163 | } | |
1164 | ||
1165 | if (options) | |
1166 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1167 | ||
1168 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1169 | } | |
1170 | ||
d9bb3fb1 | 1171 | static struct uart_driver cdns_uart_uart_driver; |
61ec9016 | 1172 | |
d9bb3fb1 SB |
1173 | static struct console cdns_uart_console = { |
1174 | .name = CDNS_UART_TTY_NAME, | |
1175 | .write = cdns_uart_console_write, | |
61ec9016 | 1176 | .device = uart_console_device, |
d9bb3fb1 | 1177 | .setup = cdns_uart_console_setup, |
61ec9016 JL |
1178 | .flags = CON_PRINTBUFFER, |
1179 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ | |
d9bb3fb1 | 1180 | .data = &cdns_uart_uart_driver, |
61ec9016 JL |
1181 | }; |
1182 | ||
1183 | /** | |
d9bb3fb1 | 1184 | * cdns_uart_console_init - Initialization call |
61ec9016 | 1185 | * |
e555a211 | 1186 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1187 | */ |
d9bb3fb1 | 1188 | static int __init cdns_uart_console_init(void) |
61ec9016 | 1189 | { |
d9bb3fb1 | 1190 | register_console(&cdns_uart_console); |
61ec9016 JL |
1191 | return 0; |
1192 | } | |
1193 | ||
d9bb3fb1 | 1194 | console_initcall(cdns_uart_console_init); |
61ec9016 JL |
1195 | |
1196 | #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ | |
1197 | ||
d9bb3fb1 | 1198 | static struct uart_driver cdns_uart_uart_driver = { |
e555a211 | 1199 | .owner = THIS_MODULE, |
d9bb3fb1 SB |
1200 | .driver_name = CDNS_UART_NAME, |
1201 | .dev_name = CDNS_UART_TTY_NAME, | |
1202 | .major = CDNS_UART_MAJOR, | |
1203 | .minor = CDNS_UART_MINOR, | |
1204 | .nr = CDNS_UART_NR_PORTS, | |
d3641f64 | 1205 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
d9bb3fb1 | 1206 | .cons = &cdns_uart_console, |
d3641f64 SB |
1207 | #endif |
1208 | }; | |
1209 | ||
4b47d9aa SB |
1210 | #ifdef CONFIG_PM_SLEEP |
1211 | /** | |
d9bb3fb1 | 1212 | * cdns_uart_suspend - suspend event |
4b47d9aa SB |
1213 | * @device: Pointer to the device structure |
1214 | * | |
489810a1 | 1215 | * Return: 0 |
4b47d9aa | 1216 | */ |
d9bb3fb1 | 1217 | static int cdns_uart_suspend(struct device *device) |
4b47d9aa SB |
1218 | { |
1219 | struct uart_port *port = dev_get_drvdata(device); | |
1220 | struct tty_struct *tty; | |
1221 | struct device *tty_dev; | |
1222 | int may_wake = 0; | |
1223 | ||
1224 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1225 | tty = tty_port_tty_get(&port->state->port); | |
1226 | if (tty) { | |
1227 | tty_dev = tty->dev; | |
1228 | may_wake = device_may_wakeup(tty_dev); | |
1229 | tty_kref_put(tty); | |
1230 | } | |
1231 | ||
1232 | /* | |
1233 | * Call the API provided in serial_core.c file which handles | |
1234 | * the suspend. | |
1235 | */ | |
d9bb3fb1 | 1236 | uart_suspend_port(&cdns_uart_uart_driver, port); |
4b47d9aa | 1237 | if (console_suspend_enabled && !may_wake) { |
d9bb3fb1 | 1238 | struct cdns_uart *cdns_uart = port->private_data; |
4b47d9aa | 1239 | |
d9bb3fb1 SB |
1240 | clk_disable(cdns_uart->uartclk); |
1241 | clk_disable(cdns_uart->pclk); | |
4b47d9aa SB |
1242 | } else { |
1243 | unsigned long flags = 0; | |
1244 | ||
1245 | spin_lock_irqsave(&port->lock, flags); | |
1246 | /* Empty the receive FIFO 1st before making changes */ | |
19f22efd | 1247 | while (!(readl(port->membase + CDNS_UART_SR_OFFSET) & |
d9bb3fb1 | 1248 | CDNS_UART_SR_RXEMPTY)) |
19f22efd | 1249 | readl(port->membase + CDNS_UART_FIFO_OFFSET); |
4b47d9aa | 1250 | /* set RX trigger level to 1 */ |
19f22efd | 1251 | writel(1, port->membase + CDNS_UART_RXWM_OFFSET); |
4b47d9aa | 1252 | /* disable RX timeout interrups */ |
19f22efd TB |
1253 | writel(CDNS_UART_IXR_TOUT, |
1254 | port->membase + CDNS_UART_IDR_OFFSET); | |
4b47d9aa SB |
1255 | spin_unlock_irqrestore(&port->lock, flags); |
1256 | } | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
1261 | /** | |
d9bb3fb1 | 1262 | * cdns_uart_resume - Resume after a previous suspend |
4b47d9aa SB |
1263 | * @device: Pointer to the device structure |
1264 | * | |
489810a1 | 1265 | * Return: 0 |
4b47d9aa | 1266 | */ |
d9bb3fb1 | 1267 | static int cdns_uart_resume(struct device *device) |
4b47d9aa SB |
1268 | { |
1269 | struct uart_port *port = dev_get_drvdata(device); | |
1270 | unsigned long flags = 0; | |
1271 | u32 ctrl_reg; | |
1272 | struct tty_struct *tty; | |
1273 | struct device *tty_dev; | |
1274 | int may_wake = 0; | |
1275 | ||
1276 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1277 | tty = tty_port_tty_get(&port->state->port); | |
1278 | if (tty) { | |
1279 | tty_dev = tty->dev; | |
1280 | may_wake = device_may_wakeup(tty_dev); | |
1281 | tty_kref_put(tty); | |
1282 | } | |
1283 | ||
1284 | if (console_suspend_enabled && !may_wake) { | |
d9bb3fb1 | 1285 | struct cdns_uart *cdns_uart = port->private_data; |
4b47d9aa | 1286 | |
d9bb3fb1 SB |
1287 | clk_enable(cdns_uart->pclk); |
1288 | clk_enable(cdns_uart->uartclk); | |
4b47d9aa SB |
1289 | |
1290 | spin_lock_irqsave(&port->lock, flags); | |
1291 | ||
1292 | /* Set TX/RX Reset */ | |
19f22efd | 1293 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 | 1294 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
19f22efd TB |
1295 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
1296 | while (readl(port->membase + CDNS_UART_CR_OFFSET) & | |
d9bb3fb1 | 1297 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
4b47d9aa SB |
1298 | cpu_relax(); |
1299 | ||
1300 | /* restore rx timeout value */ | |
19f22efd | 1301 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); |
4b47d9aa | 1302 | /* Enable Tx/Rx */ |
19f22efd | 1303 | ctrl_reg = readl(port->membase + CDNS_UART_CR_OFFSET); |
d9bb3fb1 SB |
1304 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
1305 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
19f22efd | 1306 | writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); |
4b47d9aa SB |
1307 | |
1308 | spin_unlock_irqrestore(&port->lock, flags); | |
1309 | } else { | |
1310 | spin_lock_irqsave(&port->lock, flags); | |
1311 | /* restore original rx trigger level */ | |
19f22efd TB |
1312 | writel(rx_trigger_level, |
1313 | port->membase + CDNS_UART_RXWM_OFFSET); | |
4b47d9aa | 1314 | /* enable RX timeout interrupt */ |
19f22efd TB |
1315 | writel(CDNS_UART_IXR_TOUT, |
1316 | port->membase + CDNS_UART_IER_OFFSET); | |
4b47d9aa SB |
1317 | spin_unlock_irqrestore(&port->lock, flags); |
1318 | } | |
1319 | ||
d9bb3fb1 | 1320 | return uart_resume_port(&cdns_uart_uart_driver, port); |
4b47d9aa SB |
1321 | } |
1322 | #endif /* ! CONFIG_PM_SLEEP */ | |
1323 | ||
d9bb3fb1 SB |
1324 | static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend, |
1325 | cdns_uart_resume); | |
4b47d9aa | 1326 | |
61ec9016 | 1327 | /** |
d9bb3fb1 | 1328 | * cdns_uart_probe - Platform driver probe |
61ec9016 JL |
1329 | * @pdev: Pointer to the platform device structure |
1330 | * | |
e555a211 | 1331 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1332 | */ |
d9bb3fb1 | 1333 | static int cdns_uart_probe(struct platform_device *pdev) |
61ec9016 | 1334 | { |
5c90c07b | 1335 | int rc, id, irq; |
61ec9016 | 1336 | struct uart_port *port; |
5c90c07b | 1337 | struct resource *res; |
d9bb3fb1 | 1338 | struct cdns_uart *cdns_uart_data; |
61ec9016 | 1339 | |
d9bb3fb1 | 1340 | cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), |
c03cae17 | 1341 | GFP_KERNEL); |
d9bb3fb1 | 1342 | if (!cdns_uart_data) |
30e1e285 SB |
1343 | return -ENOMEM; |
1344 | ||
d9bb3fb1 SB |
1345 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); |
1346 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1347 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); | |
1348 | if (!IS_ERR(cdns_uart_data->pclk)) | |
1349 | dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); | |
1350 | } | |
1351 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1352 | dev_err(&pdev->dev, "pclk clock not found.\n"); | |
1353 | return PTR_ERR(cdns_uart_data->pclk); | |
1354 | } | |
1355 | ||
1356 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); | |
1357 | if (IS_ERR(cdns_uart_data->uartclk)) { | |
1358 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); | |
1359 | if (!IS_ERR(cdns_uart_data->uartclk)) | |
1360 | dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); | |
30e1e285 | 1361 | } |
d9bb3fb1 SB |
1362 | if (IS_ERR(cdns_uart_data->uartclk)) { |
1363 | dev_err(&pdev->dev, "uart_clk clock not found.\n"); | |
1364 | return PTR_ERR(cdns_uart_data->uartclk); | |
2326669c JC |
1365 | } |
1366 | ||
d9bb3fb1 | 1367 | rc = clk_prepare_enable(cdns_uart_data->pclk); |
30e1e285 | 1368 | if (rc) { |
d9bb3fb1 | 1369 | dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); |
c03cae17 | 1370 | return rc; |
30e1e285 | 1371 | } |
d9bb3fb1 | 1372 | rc = clk_prepare_enable(cdns_uart_data->uartclk); |
2326669c | 1373 | if (rc) { |
30e1e285 | 1374 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
d9bb3fb1 | 1375 | goto err_out_clk_dis_pclk; |
61ec9016 JL |
1376 | } |
1377 | ||
1378 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
30e1e285 SB |
1379 | if (!res) { |
1380 | rc = -ENODEV; | |
1381 | goto err_out_clk_disable; | |
1382 | } | |
61ec9016 | 1383 | |
5c90c07b MS |
1384 | irq = platform_get_irq(pdev, 0); |
1385 | if (irq <= 0) { | |
1386 | rc = -ENXIO; | |
30e1e285 SB |
1387 | goto err_out_clk_disable; |
1388 | } | |
61ec9016 | 1389 | |
7ac57347 | 1390 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1391 | cdns_uart_data->clk_rate_change_nb.notifier_call = |
1392 | cdns_uart_clk_notifier_cb; | |
1393 | if (clk_notifier_register(cdns_uart_data->uartclk, | |
1394 | &cdns_uart_data->clk_rate_change_nb)) | |
c4b0510c | 1395 | dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); |
7ac57347 | 1396 | #endif |
928e9263 MS |
1397 | /* Look for a serialN alias */ |
1398 | id = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1399 | if (id < 0) | |
1400 | id = 0; | |
c4b0510c | 1401 | |
61ec9016 | 1402 | /* Initialize the port structure */ |
d9bb3fb1 | 1403 | port = cdns_uart_get_port(id); |
61ec9016 JL |
1404 | |
1405 | if (!port) { | |
1406 | dev_err(&pdev->dev, "Cannot get uart_port structure\n"); | |
30e1e285 | 1407 | rc = -ENODEV; |
c4b0510c | 1408 | goto err_out_notif_unreg; |
61ec9016 JL |
1409 | } else { |
1410 | /* Register the port. | |
1411 | * This function also registers this device with the tty layer | |
1412 | * and triggers invocation of the config_port() entry point. | |
1413 | */ | |
1414 | port->mapbase = res->start; | |
5c90c07b | 1415 | port->irq = irq; |
61ec9016 | 1416 | port->dev = &pdev->dev; |
d9bb3fb1 SB |
1417 | port->uartclk = clk_get_rate(cdns_uart_data->uartclk); |
1418 | port->private_data = cdns_uart_data; | |
1419 | cdns_uart_data->port = port; | |
696faedd | 1420 | platform_set_drvdata(pdev, port); |
d9bb3fb1 | 1421 | rc = uart_add_one_port(&cdns_uart_uart_driver, port); |
61ec9016 JL |
1422 | if (rc) { |
1423 | dev_err(&pdev->dev, | |
1424 | "uart_add_one_port() failed; err=%i\n", rc); | |
c4b0510c | 1425 | goto err_out_notif_unreg; |
61ec9016 JL |
1426 | } |
1427 | return 0; | |
1428 | } | |
30e1e285 | 1429 | |
c4b0510c | 1430 | err_out_notif_unreg: |
7ac57347 | 1431 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1432 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1433 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1434 | #endif |
30e1e285 | 1435 | err_out_clk_disable: |
d9bb3fb1 SB |
1436 | clk_disable_unprepare(cdns_uart_data->uartclk); |
1437 | err_out_clk_dis_pclk: | |
1438 | clk_disable_unprepare(cdns_uart_data->pclk); | |
30e1e285 SB |
1439 | |
1440 | return rc; | |
61ec9016 JL |
1441 | } |
1442 | ||
1443 | /** | |
d9bb3fb1 | 1444 | * cdns_uart_remove - called when the platform driver is unregistered |
61ec9016 JL |
1445 | * @pdev: Pointer to the platform device structure |
1446 | * | |
e555a211 | 1447 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1448 | */ |
d9bb3fb1 | 1449 | static int cdns_uart_remove(struct platform_device *pdev) |
61ec9016 | 1450 | { |
696faedd | 1451 | struct uart_port *port = platform_get_drvdata(pdev); |
d9bb3fb1 | 1452 | struct cdns_uart *cdns_uart_data = port->private_data; |
2326669c | 1453 | int rc; |
61ec9016 | 1454 | |
d9bb3fb1 | 1455 | /* Remove the cdns_uart port from the serial core */ |
7ac57347 | 1456 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1457 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1458 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1459 | #endif |
d9bb3fb1 | 1460 | rc = uart_remove_one_port(&cdns_uart_uart_driver, port); |
2326669c | 1461 | port->mapbase = 0; |
d9bb3fb1 SB |
1462 | clk_disable_unprepare(cdns_uart_data->uartclk); |
1463 | clk_disable_unprepare(cdns_uart_data->pclk); | |
61ec9016 JL |
1464 | return rc; |
1465 | } | |
1466 | ||
61ec9016 | 1467 | /* Match table for of_platform binding */ |
ed0bb232 | 1468 | static const struct of_device_id cdns_uart_of_match[] = { |
61ec9016 | 1469 | { .compatible = "xlnx,xuartps", }, |
d9bb3fb1 | 1470 | { .compatible = "cdns,uart-r1p8", }, |
61ec9016 JL |
1471 | {} |
1472 | }; | |
d9bb3fb1 | 1473 | MODULE_DEVICE_TABLE(of, cdns_uart_of_match); |
61ec9016 | 1474 | |
d9bb3fb1 SB |
1475 | static struct platform_driver cdns_uart_platform_driver = { |
1476 | .probe = cdns_uart_probe, | |
1477 | .remove = cdns_uart_remove, | |
61ec9016 | 1478 | .driver = { |
d9bb3fb1 SB |
1479 | .name = CDNS_UART_NAME, |
1480 | .of_match_table = cdns_uart_of_match, | |
1481 | .pm = &cdns_uart_dev_pm_ops, | |
61ec9016 JL |
1482 | }, |
1483 | }; | |
1484 | ||
d9bb3fb1 | 1485 | static int __init cdns_uart_init(void) |
61ec9016 JL |
1486 | { |
1487 | int retval = 0; | |
1488 | ||
d9bb3fb1 SB |
1489 | /* Register the cdns_uart driver with the serial core */ |
1490 | retval = uart_register_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1491 | if (retval) |
1492 | return retval; | |
1493 | ||
1494 | /* Register the platform driver */ | |
d9bb3fb1 | 1495 | retval = platform_driver_register(&cdns_uart_platform_driver); |
61ec9016 | 1496 | if (retval) |
d9bb3fb1 | 1497 | uart_unregister_driver(&cdns_uart_uart_driver); |
61ec9016 JL |
1498 | |
1499 | return retval; | |
1500 | } | |
1501 | ||
d9bb3fb1 | 1502 | static void __exit cdns_uart_exit(void) |
61ec9016 | 1503 | { |
61ec9016 | 1504 | /* Unregister the platform driver */ |
d9bb3fb1 | 1505 | platform_driver_unregister(&cdns_uart_platform_driver); |
61ec9016 | 1506 | |
d9bb3fb1 SB |
1507 | /* Unregister the cdns_uart driver */ |
1508 | uart_unregister_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1509 | } |
1510 | ||
d9bb3fb1 SB |
1511 | module_init(cdns_uart_init); |
1512 | module_exit(cdns_uart_exit); | |
61ec9016 | 1513 | |
d9bb3fb1 | 1514 | MODULE_DESCRIPTION("Driver for Cadence UART"); |
61ec9016 JL |
1515 | MODULE_AUTHOR("Xilinx Inc."); |
1516 | MODULE_LICENSE("GPL"); |