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1da177e4 | 1 | /* |
0ff1b2c8 | 2 | * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $ |
1da177e4 LT |
3 | * |
4 | * Device driver for Microgate SyncLink ISA and PCI | |
5 | * high speed multiprotocol serial adapters. | |
6 | * | |
7 | * written by Paul Fulghum for Microgate Corporation | |
8 | * paulkf@microgate.com | |
9 | * | |
10 | * Microgate and SyncLink are trademarks of Microgate Corporation | |
11 | * | |
12 | * Derived from serial.c written by Theodore Ts'o and Linus Torvalds | |
13 | * | |
14 | * Original release 01/11/99 | |
15 | * | |
16 | * This code is released under the GNU General Public License (GPL) | |
17 | * | |
18 | * This driver is primarily intended for use in synchronous | |
19 | * HDLC mode. Asynchronous mode is also provided. | |
20 | * | |
21 | * When operating in synchronous mode, each call to mgsl_write() | |
22 | * contains exactly one complete HDLC frame. Calling mgsl_put_char | |
23 | * will start assembling an HDLC frame that will not be sent until | |
24 | * mgsl_flush_chars or mgsl_write is called. | |
25 | * | |
26 | * Synchronous receive data is reported as complete frames. To accomplish | |
27 | * this, the TTY flip buffer is bypassed (too small to hold largest | |
28 | * frame and may fragment frames) and the line discipline | |
29 | * receive entry point is called directly. | |
30 | * | |
31 | * This driver has been tested with a slightly modified ppp.c driver | |
32 | * for synchronous PPP. | |
33 | * | |
34 | * 2000/02/16 | |
35 | * Added interface for syncppp.c driver (an alternate synchronous PPP | |
36 | * implementation that also supports Cisco HDLC). Each device instance | |
37 | * registers as a tty device AND a network device (if dosyncppp option | |
38 | * is set for the device). The functionality is determined by which | |
39 | * device interface is opened. | |
40 | * | |
41 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
42 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | |
43 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
44 | * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, | |
45 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
46 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
47 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
48 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
49 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
50 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED | |
51 | * OF THE POSSIBILITY OF SUCH DAMAGE. | |
52 | */ | |
53 | ||
54 | #if defined(__i386__) | |
55 | # define BREAKPOINT() asm(" int $3"); | |
56 | #else | |
57 | # define BREAKPOINT() { } | |
58 | #endif | |
59 | ||
60 | #define MAX_ISA_DEVICES 10 | |
61 | #define MAX_PCI_DEVICES 10 | |
62 | #define MAX_TOTAL_DEVICES 20 | |
63 | ||
1da177e4 LT |
64 | #include <linux/module.h> |
65 | #include <linux/errno.h> | |
66 | #include <linux/signal.h> | |
67 | #include <linux/sched.h> | |
68 | #include <linux/timer.h> | |
69 | #include <linux/interrupt.h> | |
70 | #include <linux/pci.h> | |
71 | #include <linux/tty.h> | |
72 | #include <linux/tty_flip.h> | |
73 | #include <linux/serial.h> | |
74 | #include <linux/major.h> | |
75 | #include <linux/string.h> | |
76 | #include <linux/fcntl.h> | |
77 | #include <linux/ptrace.h> | |
78 | #include <linux/ioport.h> | |
79 | #include <linux/mm.h> | |
d337829b | 80 | #include <linux/seq_file.h> |
1da177e4 LT |
81 | #include <linux/slab.h> |
82 | #include <linux/delay.h> | |
1da177e4 | 83 | #include <linux/netdevice.h> |
1da177e4 LT |
84 | #include <linux/vmalloc.h> |
85 | #include <linux/init.h> | |
1da177e4 | 86 | #include <linux/ioctl.h> |
3dd1247f | 87 | #include <linux/synclink.h> |
1da177e4 | 88 | |
1da177e4 LT |
89 | #include <asm/io.h> |
90 | #include <asm/irq.h> | |
91 | #include <asm/dma.h> | |
92 | #include <linux/bitops.h> | |
93 | #include <asm/types.h> | |
94 | #include <linux/termios.h> | |
95 | #include <linux/workqueue.h> | |
96 | #include <linux/hdlc.h> | |
0ff1b2c8 | 97 | #include <linux/dma-mapping.h> |
1da177e4 | 98 | |
af69c7f9 PF |
99 | #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE)) |
100 | #define SYNCLINK_GENERIC_HDLC 1 | |
101 | #else | |
102 | #define SYNCLINK_GENERIC_HDLC 0 | |
1da177e4 LT |
103 | #endif |
104 | ||
105 | #define GET_USER(error,value,addr) error = get_user(value,addr) | |
106 | #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0 | |
107 | #define PUT_USER(error,value,addr) error = put_user(value,addr) | |
108 | #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0 | |
109 | ||
110 | #include <asm/uaccess.h> | |
111 | ||
1da177e4 LT |
112 | #define RCLRVALUE 0xffff |
113 | ||
114 | static MGSL_PARAMS default_params = { | |
115 | MGSL_MODE_HDLC, /* unsigned long mode */ | |
116 | 0, /* unsigned char loopback; */ | |
117 | HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */ | |
118 | HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */ | |
119 | 0, /* unsigned long clock_speed; */ | |
120 | 0xff, /* unsigned char addr_filter; */ | |
121 | HDLC_CRC_16_CCITT, /* unsigned short crc_type; */ | |
122 | HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */ | |
123 | HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */ | |
124 | 9600, /* unsigned long data_rate; */ | |
125 | 8, /* unsigned char data_bits; */ | |
126 | 1, /* unsigned char stop_bits; */ | |
127 | ASYNC_PARITY_NONE /* unsigned char parity; */ | |
128 | }; | |
129 | ||
130 | #define SHARED_MEM_ADDRESS_SIZE 0x40000 | |
623a4395 PF |
131 | #define BUFFERLISTSIZE 4096 |
132 | #define DMABUFFERSIZE 4096 | |
1da177e4 LT |
133 | #define MAXRXFRAMES 7 |
134 | ||
135 | typedef struct _DMABUFFERENTRY | |
136 | { | |
137 | u32 phys_addr; /* 32-bit flat physical address of data buffer */ | |
4a918bc2 PF |
138 | volatile u16 count; /* buffer size/data count */ |
139 | volatile u16 status; /* Control/status field */ | |
140 | volatile u16 rcc; /* character count field */ | |
1da177e4 LT |
141 | u16 reserved; /* padding required by 16C32 */ |
142 | u32 link; /* 32-bit flat link to next buffer entry */ | |
143 | char *virt_addr; /* virtual address of data buffer */ | |
144 | u32 phys_entry; /* physical address of this buffer entry */ | |
0ff1b2c8 | 145 | dma_addr_t dma_addr; |
1da177e4 LT |
146 | } DMABUFFERENTRY, *DMAPBUFFERENTRY; |
147 | ||
148 | /* The queue of BH actions to be performed */ | |
149 | ||
150 | #define BH_RECEIVE 1 | |
151 | #define BH_TRANSMIT 2 | |
152 | #define BH_STATUS 4 | |
153 | ||
154 | #define IO_PIN_SHUTDOWN_LIMIT 100 | |
155 | ||
1da177e4 LT |
156 | struct _input_signal_events { |
157 | int ri_up; | |
158 | int ri_down; | |
159 | int dsr_up; | |
160 | int dsr_down; | |
161 | int dcd_up; | |
162 | int dcd_down; | |
163 | int cts_up; | |
164 | int cts_down; | |
165 | }; | |
166 | ||
167 | /* transmit holding buffer definitions*/ | |
168 | #define MAX_TX_HOLDING_BUFFERS 5 | |
169 | struct tx_holding_buffer { | |
170 | int buffer_size; | |
171 | unsigned char * buffer; | |
172 | }; | |
173 | ||
174 | ||
175 | /* | |
176 | * Device instance data structure | |
177 | */ | |
178 | ||
179 | struct mgsl_struct { | |
180 | int magic; | |
8fb06c77 | 181 | struct tty_port port; |
1da177e4 LT |
182 | int line; |
183 | int hw_version; | |
1da177e4 LT |
184 | |
185 | struct mgsl_icount icount; | |
186 | ||
1da177e4 LT |
187 | int timeout; |
188 | int x_char; /* xon/xoff character */ | |
1da177e4 LT |
189 | u16 read_status_mask; |
190 | u16 ignore_status_mask; | |
191 | unsigned char *xmit_buf; | |
192 | int xmit_head; | |
193 | int xmit_tail; | |
194 | int xmit_cnt; | |
195 | ||
1da177e4 LT |
196 | wait_queue_head_t status_event_wait_q; |
197 | wait_queue_head_t event_wait_q; | |
198 | struct timer_list tx_timer; /* HDLC transmit timeout timer */ | |
199 | struct mgsl_struct *next_device; /* device list link */ | |
200 | ||
201 | spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */ | |
202 | struct work_struct task; /* task structure for scheduling bh */ | |
203 | ||
204 | u32 EventMask; /* event trigger mask */ | |
205 | u32 RecordedEvents; /* pending events */ | |
206 | ||
207 | u32 max_frame_size; /* as set by device config */ | |
208 | ||
209 | u32 pending_bh; | |
210 | ||
0fab6de0 | 211 | bool bh_running; /* Protection from multiple */ |
1da177e4 | 212 | int isr_overflow; |
0fab6de0 | 213 | bool bh_requested; |
1da177e4 LT |
214 | |
215 | int dcd_chkcount; /* check counts to prevent */ | |
216 | int cts_chkcount; /* too many IRQs if a signal */ | |
217 | int dsr_chkcount; /* is floating */ | |
218 | int ri_chkcount; | |
219 | ||
220 | char *buffer_list; /* virtual address of Rx & Tx buffer lists */ | |
0ff1b2c8 PF |
221 | u32 buffer_list_phys; |
222 | dma_addr_t buffer_list_dma_addr; | |
1da177e4 LT |
223 | |
224 | unsigned int rx_buffer_count; /* count of total allocated Rx buffers */ | |
225 | DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */ | |
226 | unsigned int current_rx_buffer; | |
227 | ||
228 | int num_tx_dma_buffers; /* number of tx dma frames required */ | |
229 | int tx_dma_buffers_used; | |
230 | unsigned int tx_buffer_count; /* count of total allocated Tx buffers */ | |
231 | DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */ | |
232 | int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */ | |
233 | int current_tx_buffer; /* next tx dma buffer to be loaded */ | |
234 | ||
235 | unsigned char *intermediate_rxbuffer; | |
236 | ||
237 | int num_tx_holding_buffers; /* number of tx holding buffer allocated */ | |
238 | int get_tx_holding_index; /* next tx holding buffer for adapter to load */ | |
239 | int put_tx_holding_index; /* next tx holding buffer to store user request */ | |
240 | int tx_holding_count; /* number of tx holding buffers waiting */ | |
241 | struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS]; | |
242 | ||
0fab6de0 JP |
243 | bool rx_enabled; |
244 | bool rx_overflow; | |
245 | bool rx_rcc_underrun; | |
1da177e4 | 246 | |
0fab6de0 JP |
247 | bool tx_enabled; |
248 | bool tx_active; | |
1da177e4 LT |
249 | u32 idle_mode; |
250 | ||
251 | u16 cmr_value; | |
252 | u16 tcsr_value; | |
253 | ||
254 | char device_name[25]; /* device instance name */ | |
255 | ||
256 | unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */ | |
257 | unsigned char bus; /* expansion bus number (zero based) */ | |
258 | unsigned char function; /* PCI device number */ | |
259 | ||
260 | unsigned int io_base; /* base I/O address of adapter */ | |
261 | unsigned int io_addr_size; /* size of the I/O address range */ | |
0fab6de0 | 262 | bool io_addr_requested; /* true if I/O address requested */ |
1da177e4 LT |
263 | |
264 | unsigned int irq_level; /* interrupt level */ | |
265 | unsigned long irq_flags; | |
0fab6de0 | 266 | bool irq_requested; /* true if IRQ requested */ |
1da177e4 LT |
267 | |
268 | unsigned int dma_level; /* DMA channel */ | |
0fab6de0 | 269 | bool dma_requested; /* true if dma channel requested */ |
1da177e4 LT |
270 | |
271 | u16 mbre_bit; | |
272 | u16 loopback_bits; | |
273 | u16 usc_idle_mode; | |
274 | ||
275 | MGSL_PARAMS params; /* communications parameters */ | |
276 | ||
277 | unsigned char serial_signals; /* current serial signal states */ | |
278 | ||
0fab6de0 | 279 | bool irq_occurred; /* for diagnostics use */ |
1da177e4 LT |
280 | unsigned int init_error; /* Initialization startup error (DIAGS) */ |
281 | int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */ | |
282 | ||
283 | u32 last_mem_alloc; | |
284 | unsigned char* memory_base; /* shared memory address (PCI only) */ | |
285 | u32 phys_memory_base; | |
0fab6de0 | 286 | bool shared_mem_requested; |
1da177e4 LT |
287 | |
288 | unsigned char* lcr_base; /* local config registers (PCI only) */ | |
289 | u32 phys_lcr_base; | |
290 | u32 lcr_offset; | |
0fab6de0 | 291 | bool lcr_mem_requested; |
1da177e4 LT |
292 | |
293 | u32 misc_ctrl_value; | |
a6b68a69 | 294 | char *flag_buf; |
0fab6de0 | 295 | bool drop_rts_on_tx_done; |
1da177e4 | 296 | |
0fab6de0 JP |
297 | bool loopmode_insert_requested; |
298 | bool loopmode_send_done_requested; | |
1da177e4 LT |
299 | |
300 | struct _input_signal_events input_signal_events; | |
301 | ||
302 | /* generic HDLC device parts */ | |
303 | int netcount; | |
1da177e4 LT |
304 | spinlock_t netlock; |
305 | ||
af69c7f9 | 306 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
307 | struct net_device *netdev; |
308 | #endif | |
309 | }; | |
310 | ||
311 | #define MGSL_MAGIC 0x5401 | |
312 | ||
313 | /* | |
314 | * The size of the serial xmit buffer is 1 page, or 4096 bytes | |
315 | */ | |
316 | #ifndef SERIAL_XMIT_SIZE | |
317 | #define SERIAL_XMIT_SIZE 4096 | |
318 | #endif | |
319 | ||
320 | /* | |
321 | * These macros define the offsets used in calculating the | |
322 | * I/O address of the specified USC registers. | |
323 | */ | |
324 | ||
325 | ||
326 | #define DCPIN 2 /* Bit 1 of I/O address */ | |
327 | #define SDPIN 4 /* Bit 2 of I/O address */ | |
328 | ||
329 | #define DCAR 0 /* DMA command/address register */ | |
330 | #define CCAR SDPIN /* channel command/address register */ | |
331 | #define DATAREG DCPIN + SDPIN /* serial data register */ | |
332 | #define MSBONLY 0x41 | |
333 | #define LSBONLY 0x40 | |
334 | ||
335 | /* | |
336 | * These macros define the register address (ordinal number) | |
337 | * used for writing address/value pairs to the USC. | |
338 | */ | |
339 | ||
340 | #define CMR 0x02 /* Channel mode Register */ | |
341 | #define CCSR 0x04 /* Channel Command/status Register */ | |
342 | #define CCR 0x06 /* Channel Control Register */ | |
343 | #define PSR 0x08 /* Port status Register */ | |
344 | #define PCR 0x0a /* Port Control Register */ | |
345 | #define TMDR 0x0c /* Test mode Data Register */ | |
346 | #define TMCR 0x0e /* Test mode Control Register */ | |
347 | #define CMCR 0x10 /* Clock mode Control Register */ | |
348 | #define HCR 0x12 /* Hardware Configuration Register */ | |
349 | #define IVR 0x14 /* Interrupt Vector Register */ | |
350 | #define IOCR 0x16 /* Input/Output Control Register */ | |
351 | #define ICR 0x18 /* Interrupt Control Register */ | |
352 | #define DCCR 0x1a /* Daisy Chain Control Register */ | |
353 | #define MISR 0x1c /* Misc Interrupt status Register */ | |
354 | #define SICR 0x1e /* status Interrupt Control Register */ | |
355 | #define RDR 0x20 /* Receive Data Register */ | |
356 | #define RMR 0x22 /* Receive mode Register */ | |
357 | #define RCSR 0x24 /* Receive Command/status Register */ | |
358 | #define RICR 0x26 /* Receive Interrupt Control Register */ | |
359 | #define RSR 0x28 /* Receive Sync Register */ | |
360 | #define RCLR 0x2a /* Receive count Limit Register */ | |
361 | #define RCCR 0x2c /* Receive Character count Register */ | |
362 | #define TC0R 0x2e /* Time Constant 0 Register */ | |
363 | #define TDR 0x30 /* Transmit Data Register */ | |
364 | #define TMR 0x32 /* Transmit mode Register */ | |
365 | #define TCSR 0x34 /* Transmit Command/status Register */ | |
366 | #define TICR 0x36 /* Transmit Interrupt Control Register */ | |
367 | #define TSR 0x38 /* Transmit Sync Register */ | |
368 | #define TCLR 0x3a /* Transmit count Limit Register */ | |
369 | #define TCCR 0x3c /* Transmit Character count Register */ | |
370 | #define TC1R 0x3e /* Time Constant 1 Register */ | |
371 | ||
372 | ||
373 | /* | |
374 | * MACRO DEFINITIONS FOR DMA REGISTERS | |
375 | */ | |
376 | ||
377 | #define DCR 0x06 /* DMA Control Register (shared) */ | |
378 | #define DACR 0x08 /* DMA Array count Register (shared) */ | |
379 | #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */ | |
380 | #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */ | |
381 | #define DICR 0x18 /* DMA Interrupt Control Register (shared) */ | |
382 | #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */ | |
383 | #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */ | |
384 | ||
385 | #define TDMR 0x02 /* Transmit DMA mode Register */ | |
386 | #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */ | |
387 | #define TBCR 0x2a /* Transmit Byte count Register */ | |
388 | #define TARL 0x2c /* Transmit Address Register (low) */ | |
389 | #define TARU 0x2e /* Transmit Address Register (high) */ | |
390 | #define NTBCR 0x3a /* Next Transmit Byte count Register */ | |
391 | #define NTARL 0x3c /* Next Transmit Address Register (low) */ | |
392 | #define NTARU 0x3e /* Next Transmit Address Register (high) */ | |
393 | ||
394 | #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */ | |
395 | #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */ | |
396 | #define RBCR 0xaa /* Receive Byte count Register */ | |
397 | #define RARL 0xac /* Receive Address Register (low) */ | |
398 | #define RARU 0xae /* Receive Address Register (high) */ | |
399 | #define NRBCR 0xba /* Next Receive Byte count Register */ | |
400 | #define NRARL 0xbc /* Next Receive Address Register (low) */ | |
401 | #define NRARU 0xbe /* Next Receive Address Register (high) */ | |
402 | ||
403 | ||
404 | /* | |
405 | * MACRO DEFINITIONS FOR MODEM STATUS BITS | |
406 | */ | |
407 | ||
408 | #define MODEMSTATUS_DTR 0x80 | |
409 | #define MODEMSTATUS_DSR 0x40 | |
410 | #define MODEMSTATUS_RTS 0x20 | |
411 | #define MODEMSTATUS_CTS 0x10 | |
412 | #define MODEMSTATUS_RI 0x04 | |
413 | #define MODEMSTATUS_DCD 0x01 | |
414 | ||
415 | ||
416 | /* | |
417 | * Channel Command/Address Register (CCAR) Command Codes | |
418 | */ | |
419 | ||
420 | #define RTCmd_Null 0x0000 | |
421 | #define RTCmd_ResetHighestIus 0x1000 | |
422 | #define RTCmd_TriggerChannelLoadDma 0x2000 | |
423 | #define RTCmd_TriggerRxDma 0x2800 | |
424 | #define RTCmd_TriggerTxDma 0x3000 | |
425 | #define RTCmd_TriggerRxAndTxDma 0x3800 | |
426 | #define RTCmd_PurgeRxFifo 0x4800 | |
427 | #define RTCmd_PurgeTxFifo 0x5000 | |
428 | #define RTCmd_PurgeRxAndTxFifo 0x5800 | |
429 | #define RTCmd_LoadRcc 0x6800 | |
430 | #define RTCmd_LoadTcc 0x7000 | |
431 | #define RTCmd_LoadRccAndTcc 0x7800 | |
432 | #define RTCmd_LoadTC0 0x8800 | |
433 | #define RTCmd_LoadTC1 0x9000 | |
434 | #define RTCmd_LoadTC0AndTC1 0x9800 | |
435 | #define RTCmd_SerialDataLSBFirst 0xa000 | |
436 | #define RTCmd_SerialDataMSBFirst 0xa800 | |
437 | #define RTCmd_SelectBigEndian 0xb000 | |
438 | #define RTCmd_SelectLittleEndian 0xb800 | |
439 | ||
440 | ||
441 | /* | |
442 | * DMA Command/Address Register (DCAR) Command Codes | |
443 | */ | |
444 | ||
445 | #define DmaCmd_Null 0x0000 | |
446 | #define DmaCmd_ResetTxChannel 0x1000 | |
447 | #define DmaCmd_ResetRxChannel 0x1200 | |
448 | #define DmaCmd_StartTxChannel 0x2000 | |
449 | #define DmaCmd_StartRxChannel 0x2200 | |
450 | #define DmaCmd_ContinueTxChannel 0x3000 | |
451 | #define DmaCmd_ContinueRxChannel 0x3200 | |
452 | #define DmaCmd_PauseTxChannel 0x4000 | |
453 | #define DmaCmd_PauseRxChannel 0x4200 | |
454 | #define DmaCmd_AbortTxChannel 0x5000 | |
455 | #define DmaCmd_AbortRxChannel 0x5200 | |
456 | #define DmaCmd_InitTxChannel 0x7000 | |
457 | #define DmaCmd_InitRxChannel 0x7200 | |
458 | #define DmaCmd_ResetHighestDmaIus 0x8000 | |
459 | #define DmaCmd_ResetAllChannels 0x9000 | |
460 | #define DmaCmd_StartAllChannels 0xa000 | |
461 | #define DmaCmd_ContinueAllChannels 0xb000 | |
462 | #define DmaCmd_PauseAllChannels 0xc000 | |
463 | #define DmaCmd_AbortAllChannels 0xd000 | |
464 | #define DmaCmd_InitAllChannels 0xf000 | |
465 | ||
466 | #define TCmd_Null 0x0000 | |
467 | #define TCmd_ClearTxCRC 0x2000 | |
468 | #define TCmd_SelectTicrTtsaData 0x4000 | |
469 | #define TCmd_SelectTicrTxFifostatus 0x5000 | |
470 | #define TCmd_SelectTicrIntLevel 0x6000 | |
471 | #define TCmd_SelectTicrdma_level 0x7000 | |
472 | #define TCmd_SendFrame 0x8000 | |
473 | #define TCmd_SendAbort 0x9000 | |
474 | #define TCmd_EnableDleInsertion 0xc000 | |
475 | #define TCmd_DisableDleInsertion 0xd000 | |
476 | #define TCmd_ClearEofEom 0xe000 | |
477 | #define TCmd_SetEofEom 0xf000 | |
478 | ||
479 | #define RCmd_Null 0x0000 | |
480 | #define RCmd_ClearRxCRC 0x2000 | |
481 | #define RCmd_EnterHuntmode 0x3000 | |
482 | #define RCmd_SelectRicrRtsaData 0x4000 | |
483 | #define RCmd_SelectRicrRxFifostatus 0x5000 | |
484 | #define RCmd_SelectRicrIntLevel 0x6000 | |
485 | #define RCmd_SelectRicrdma_level 0x7000 | |
486 | ||
487 | /* | |
488 | * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR) | |
489 | */ | |
490 | ||
491 | #define RECEIVE_STATUS BIT5 | |
492 | #define RECEIVE_DATA BIT4 | |
493 | #define TRANSMIT_STATUS BIT3 | |
494 | #define TRANSMIT_DATA BIT2 | |
495 | #define IO_PIN BIT1 | |
496 | #define MISC BIT0 | |
497 | ||
498 | ||
499 | /* | |
500 | * Receive status Bits in Receive Command/status Register RCSR | |
501 | */ | |
502 | ||
503 | #define RXSTATUS_SHORT_FRAME BIT8 | |
504 | #define RXSTATUS_CODE_VIOLATION BIT8 | |
505 | #define RXSTATUS_EXITED_HUNT BIT7 | |
506 | #define RXSTATUS_IDLE_RECEIVED BIT6 | |
507 | #define RXSTATUS_BREAK_RECEIVED BIT5 | |
508 | #define RXSTATUS_ABORT_RECEIVED BIT5 | |
509 | #define RXSTATUS_RXBOUND BIT4 | |
510 | #define RXSTATUS_CRC_ERROR BIT3 | |
511 | #define RXSTATUS_FRAMING_ERROR BIT3 | |
512 | #define RXSTATUS_ABORT BIT2 | |
513 | #define RXSTATUS_PARITY_ERROR BIT2 | |
514 | #define RXSTATUS_OVERRUN BIT1 | |
515 | #define RXSTATUS_DATA_AVAILABLE BIT0 | |
516 | #define RXSTATUS_ALL 0x01f6 | |
517 | #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) ) | |
518 | ||
519 | /* | |
520 | * Values for setting transmit idle mode in | |
521 | * Transmit Control/status Register (TCSR) | |
522 | */ | |
523 | #define IDLEMODE_FLAGS 0x0000 | |
524 | #define IDLEMODE_ALT_ONE_ZERO 0x0100 | |
525 | #define IDLEMODE_ZERO 0x0200 | |
526 | #define IDLEMODE_ONE 0x0300 | |
527 | #define IDLEMODE_ALT_MARK_SPACE 0x0500 | |
528 | #define IDLEMODE_SPACE 0x0600 | |
529 | #define IDLEMODE_MARK 0x0700 | |
530 | #define IDLEMODE_MASK 0x0700 | |
531 | ||
532 | /* | |
533 | * IUSC revision identifiers | |
534 | */ | |
535 | #define IUSC_SL1660 0x4d44 | |
536 | #define IUSC_PRE_SL1660 0x4553 | |
537 | ||
538 | /* | |
539 | * Transmit status Bits in Transmit Command/status Register (TCSR) | |
540 | */ | |
541 | ||
542 | #define TCSR_PRESERVE 0x0F00 | |
543 | ||
544 | #define TCSR_UNDERWAIT BIT11 | |
545 | #define TXSTATUS_PREAMBLE_SENT BIT7 | |
546 | #define TXSTATUS_IDLE_SENT BIT6 | |
547 | #define TXSTATUS_ABORT_SENT BIT5 | |
548 | #define TXSTATUS_EOF_SENT BIT4 | |
549 | #define TXSTATUS_EOM_SENT BIT4 | |
550 | #define TXSTATUS_CRC_SENT BIT3 | |
551 | #define TXSTATUS_ALL_SENT BIT2 | |
552 | #define TXSTATUS_UNDERRUN BIT1 | |
553 | #define TXSTATUS_FIFO_EMPTY BIT0 | |
554 | #define TXSTATUS_ALL 0x00fa | |
555 | #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) ) | |
556 | ||
557 | ||
558 | #define MISCSTATUS_RXC_LATCHED BIT15 | |
559 | #define MISCSTATUS_RXC BIT14 | |
560 | #define MISCSTATUS_TXC_LATCHED BIT13 | |
561 | #define MISCSTATUS_TXC BIT12 | |
562 | #define MISCSTATUS_RI_LATCHED BIT11 | |
563 | #define MISCSTATUS_RI BIT10 | |
564 | #define MISCSTATUS_DSR_LATCHED BIT9 | |
565 | #define MISCSTATUS_DSR BIT8 | |
566 | #define MISCSTATUS_DCD_LATCHED BIT7 | |
567 | #define MISCSTATUS_DCD BIT6 | |
568 | #define MISCSTATUS_CTS_LATCHED BIT5 | |
569 | #define MISCSTATUS_CTS BIT4 | |
570 | #define MISCSTATUS_RCC_UNDERRUN BIT3 | |
571 | #define MISCSTATUS_DPLL_NO_SYNC BIT2 | |
572 | #define MISCSTATUS_BRG1_ZERO BIT1 | |
573 | #define MISCSTATUS_BRG0_ZERO BIT0 | |
574 | ||
575 | #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0)) | |
576 | #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f)) | |
577 | ||
578 | #define SICR_RXC_ACTIVE BIT15 | |
579 | #define SICR_RXC_INACTIVE BIT14 | |
e06922aa | 580 | #define SICR_RXC (BIT15|BIT14) |
1da177e4 LT |
581 | #define SICR_TXC_ACTIVE BIT13 |
582 | #define SICR_TXC_INACTIVE BIT12 | |
e06922aa | 583 | #define SICR_TXC (BIT13|BIT12) |
1da177e4 LT |
584 | #define SICR_RI_ACTIVE BIT11 |
585 | #define SICR_RI_INACTIVE BIT10 | |
e06922aa | 586 | #define SICR_RI (BIT11|BIT10) |
1da177e4 LT |
587 | #define SICR_DSR_ACTIVE BIT9 |
588 | #define SICR_DSR_INACTIVE BIT8 | |
e06922aa | 589 | #define SICR_DSR (BIT9|BIT8) |
1da177e4 LT |
590 | #define SICR_DCD_ACTIVE BIT7 |
591 | #define SICR_DCD_INACTIVE BIT6 | |
e06922aa | 592 | #define SICR_DCD (BIT7|BIT6) |
1da177e4 LT |
593 | #define SICR_CTS_ACTIVE BIT5 |
594 | #define SICR_CTS_INACTIVE BIT4 | |
e06922aa | 595 | #define SICR_CTS (BIT5|BIT4) |
1da177e4 LT |
596 | #define SICR_RCC_UNDERFLOW BIT3 |
597 | #define SICR_DPLL_NO_SYNC BIT2 | |
598 | #define SICR_BRG1_ZERO BIT1 | |
599 | #define SICR_BRG0_ZERO BIT0 | |
600 | ||
601 | void usc_DisableMasterIrqBit( struct mgsl_struct *info ); | |
602 | void usc_EnableMasterIrqBit( struct mgsl_struct *info ); | |
603 | void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask ); | |
604 | void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask ); | |
605 | void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask ); | |
606 | ||
607 | #define usc_EnableInterrupts( a, b ) \ | |
608 | usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) ) | |
609 | ||
610 | #define usc_DisableInterrupts( a, b ) \ | |
611 | usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) ) | |
612 | ||
613 | #define usc_EnableMasterIrqBit(a) \ | |
614 | usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) ) | |
615 | ||
616 | #define usc_DisableMasterIrqBit(a) \ | |
617 | usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) ) | |
618 | ||
619 | #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) ) | |
620 | ||
621 | /* | |
622 | * Transmit status Bits in Transmit Control status Register (TCSR) | |
623 | * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) | |
624 | */ | |
625 | ||
626 | #define TXSTATUS_PREAMBLE_SENT BIT7 | |
627 | #define TXSTATUS_IDLE_SENT BIT6 | |
628 | #define TXSTATUS_ABORT_SENT BIT5 | |
629 | #define TXSTATUS_EOF BIT4 | |
630 | #define TXSTATUS_CRC_SENT BIT3 | |
631 | #define TXSTATUS_ALL_SENT BIT2 | |
632 | #define TXSTATUS_UNDERRUN BIT1 | |
633 | #define TXSTATUS_FIFO_EMPTY BIT0 | |
634 | ||
635 | #define DICR_MASTER BIT15 | |
636 | #define DICR_TRANSMIT BIT0 | |
637 | #define DICR_RECEIVE BIT1 | |
638 | ||
639 | #define usc_EnableDmaInterrupts(a,b) \ | |
640 | usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) ) | |
641 | ||
642 | #define usc_DisableDmaInterrupts(a,b) \ | |
643 | usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) ) | |
644 | ||
645 | #define usc_EnableStatusIrqs(a,b) \ | |
646 | usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) ) | |
647 | ||
648 | #define usc_DisablestatusIrqs(a,b) \ | |
649 | usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) ) | |
650 | ||
651 | /* Transmit status Bits in Transmit Control status Register (TCSR) */ | |
652 | /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */ | |
653 | ||
654 | ||
655 | #define DISABLE_UNCONDITIONAL 0 | |
656 | #define DISABLE_END_OF_FRAME 1 | |
657 | #define ENABLE_UNCONDITIONAL 2 | |
658 | #define ENABLE_AUTO_CTS 3 | |
659 | #define ENABLE_AUTO_DCD 3 | |
660 | #define usc_EnableTransmitter(a,b) \ | |
661 | usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) ) | |
662 | #define usc_EnableReceiver(a,b) \ | |
663 | usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) ) | |
664 | ||
665 | static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port ); | |
666 | static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value ); | |
667 | static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd ); | |
668 | ||
669 | static u16 usc_InReg( struct mgsl_struct *info, u16 Port ); | |
670 | static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value ); | |
671 | static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd ); | |
672 | void usc_RCmd( struct mgsl_struct *info, u16 Cmd ); | |
673 | void usc_TCmd( struct mgsl_struct *info, u16 Cmd ); | |
674 | ||
675 | #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b))) | |
676 | #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b)) | |
677 | ||
678 | #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1)) | |
679 | ||
680 | static void usc_process_rxoverrun_sync( struct mgsl_struct *info ); | |
681 | static void usc_start_receiver( struct mgsl_struct *info ); | |
682 | static void usc_stop_receiver( struct mgsl_struct *info ); | |
683 | ||
684 | static void usc_start_transmitter( struct mgsl_struct *info ); | |
685 | static void usc_stop_transmitter( struct mgsl_struct *info ); | |
686 | static void usc_set_txidle( struct mgsl_struct *info ); | |
687 | static void usc_load_txfifo( struct mgsl_struct *info ); | |
688 | ||
689 | static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate ); | |
690 | static void usc_enable_loopback( struct mgsl_struct *info, int enable ); | |
691 | ||
692 | static void usc_get_serial_signals( struct mgsl_struct *info ); | |
693 | static void usc_set_serial_signals( struct mgsl_struct *info ); | |
694 | ||
695 | static void usc_reset( struct mgsl_struct *info ); | |
696 | ||
697 | static void usc_set_sync_mode( struct mgsl_struct *info ); | |
698 | static void usc_set_sdlc_mode( struct mgsl_struct *info ); | |
699 | static void usc_set_async_mode( struct mgsl_struct *info ); | |
700 | static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate ); | |
701 | ||
702 | static void usc_loopback_frame( struct mgsl_struct *info ); | |
703 | ||
704 | static void mgsl_tx_timeout(unsigned long context); | |
705 | ||
706 | ||
707 | static void usc_loopmode_cancel_transmit( struct mgsl_struct * info ); | |
708 | static void usc_loopmode_insert_request( struct mgsl_struct * info ); | |
709 | static int usc_loopmode_active( struct mgsl_struct * info); | |
710 | static void usc_loopmode_send_done( struct mgsl_struct * info ); | |
711 | ||
712 | static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg); | |
713 | ||
af69c7f9 | 714 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
715 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) |
716 | static void hdlcdev_tx_done(struct mgsl_struct *info); | |
717 | static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size); | |
718 | static int hdlcdev_init(struct mgsl_struct *info); | |
719 | static void hdlcdev_exit(struct mgsl_struct *info); | |
720 | #endif | |
721 | ||
722 | /* | |
723 | * Defines a BUS descriptor value for the PCI adapter | |
724 | * local bus address ranges. | |
725 | */ | |
726 | ||
727 | #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \ | |
728 | (0x00400020 + \ | |
729 | ((WrHold) << 30) + \ | |
730 | ((WrDly) << 28) + \ | |
731 | ((RdDly) << 26) + \ | |
732 | ((Nwdd) << 20) + \ | |
733 | ((Nwad) << 15) + \ | |
734 | ((Nxda) << 13) + \ | |
735 | ((Nrdd) << 11) + \ | |
736 | ((Nrad) << 6) ) | |
737 | ||
738 | static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit); | |
739 | ||
740 | /* | |
741 | * Adapter diagnostic routines | |
742 | */ | |
0fab6de0 JP |
743 | static bool mgsl_register_test( struct mgsl_struct *info ); |
744 | static bool mgsl_irq_test( struct mgsl_struct *info ); | |
745 | static bool mgsl_dma_test( struct mgsl_struct *info ); | |
746 | static bool mgsl_memory_test( struct mgsl_struct *info ); | |
1da177e4 LT |
747 | static int mgsl_adapter_test( struct mgsl_struct *info ); |
748 | ||
749 | /* | |
750 | * device and resource management routines | |
751 | */ | |
752 | static int mgsl_claim_resources(struct mgsl_struct *info); | |
753 | static void mgsl_release_resources(struct mgsl_struct *info); | |
754 | static void mgsl_add_device(struct mgsl_struct *info); | |
755 | static struct mgsl_struct* mgsl_allocate_device(void); | |
756 | ||
757 | /* | |
758 | * DMA buffer manupulation functions. | |
759 | */ | |
760 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ); | |
0fab6de0 JP |
761 | static bool mgsl_get_rx_frame( struct mgsl_struct *info ); |
762 | static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info ); | |
1da177e4 LT |
763 | static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info ); |
764 | static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info ); | |
765 | static int num_free_tx_dma_buffers(struct mgsl_struct *info); | |
766 | static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize); | |
767 | static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count); | |
768 | ||
769 | /* | |
770 | * DMA and Shared Memory buffer allocation and formatting | |
771 | */ | |
772 | static int mgsl_allocate_dma_buffers(struct mgsl_struct *info); | |
773 | static void mgsl_free_dma_buffers(struct mgsl_struct *info); | |
774 | static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount); | |
775 | static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount); | |
776 | static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info); | |
777 | static void mgsl_free_buffer_list_memory(struct mgsl_struct *info); | |
778 | static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info); | |
779 | static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info); | |
780 | static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info); | |
781 | static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info); | |
0fab6de0 | 782 | static bool load_next_tx_holding_buffer(struct mgsl_struct *info); |
1da177e4 LT |
783 | static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize); |
784 | ||
785 | /* | |
786 | * Bottom half interrupt handlers | |
787 | */ | |
c4028958 | 788 | static void mgsl_bh_handler(struct work_struct *work); |
1da177e4 LT |
789 | static void mgsl_bh_receive(struct mgsl_struct *info); |
790 | static void mgsl_bh_transmit(struct mgsl_struct *info); | |
791 | static void mgsl_bh_status(struct mgsl_struct *info); | |
792 | ||
793 | /* | |
794 | * Interrupt handler routines and dispatch table. | |
795 | */ | |
796 | static void mgsl_isr_null( struct mgsl_struct *info ); | |
797 | static void mgsl_isr_transmit_data( struct mgsl_struct *info ); | |
798 | static void mgsl_isr_receive_data( struct mgsl_struct *info ); | |
799 | static void mgsl_isr_receive_status( struct mgsl_struct *info ); | |
800 | static void mgsl_isr_transmit_status( struct mgsl_struct *info ); | |
801 | static void mgsl_isr_io_pin( struct mgsl_struct *info ); | |
802 | static void mgsl_isr_misc( struct mgsl_struct *info ); | |
803 | static void mgsl_isr_receive_dma( struct mgsl_struct *info ); | |
804 | static void mgsl_isr_transmit_dma( struct mgsl_struct *info ); | |
805 | ||
806 | typedef void (*isr_dispatch_func)(struct mgsl_struct *); | |
807 | ||
808 | static isr_dispatch_func UscIsrTable[7] = | |
809 | { | |
810 | mgsl_isr_null, | |
811 | mgsl_isr_misc, | |
812 | mgsl_isr_io_pin, | |
813 | mgsl_isr_transmit_data, | |
814 | mgsl_isr_transmit_status, | |
815 | mgsl_isr_receive_data, | |
816 | mgsl_isr_receive_status | |
817 | }; | |
818 | ||
819 | /* | |
820 | * ioctl call handlers | |
821 | */ | |
60b33c13 | 822 | static int tiocmget(struct tty_struct *tty); |
20b9d177 | 823 | static int tiocmset(struct tty_struct *tty, |
1da177e4 LT |
824 | unsigned int set, unsigned int clear); |
825 | static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount | |
826 | __user *user_icount); | |
827 | static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params); | |
828 | static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params); | |
829 | static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode); | |
830 | static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode); | |
831 | static int mgsl_txenable(struct mgsl_struct * info, int enable); | |
832 | static int mgsl_txabort(struct mgsl_struct * info); | |
833 | static int mgsl_rxenable(struct mgsl_struct * info, int enable); | |
834 | static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask); | |
835 | static int mgsl_loopmode_send_done( struct mgsl_struct * info ); | |
836 | ||
837 | /* set non-zero on successful registration with PCI subsystem */ | |
0fab6de0 | 838 | static bool pci_registered; |
1da177e4 LT |
839 | |
840 | /* | |
841 | * Global linked list of SyncLink devices | |
842 | */ | |
843 | static struct mgsl_struct *mgsl_device_list; | |
844 | static int mgsl_device_count; | |
845 | ||
846 | /* | |
847 | * Set this param to non-zero to load eax with the | |
848 | * .text section address and breakpoint on module load. | |
849 | * This is useful for use with gdb and add-symbol-file command. | |
850 | */ | |
90ab5ee9 | 851 | static bool break_on_load; |
1da177e4 LT |
852 | |
853 | /* | |
854 | * Driver major number, defaults to zero to get auto | |
855 | * assigned major number. May be forced as module parameter. | |
856 | */ | |
857 | static int ttymajor; | |
858 | ||
859 | /* | |
860 | * Array of user specified options for ISA adapters. | |
861 | */ | |
862 | static int io[MAX_ISA_DEVICES]; | |
863 | static int irq[MAX_ISA_DEVICES]; | |
864 | static int dma[MAX_ISA_DEVICES]; | |
865 | static int debug_level; | |
866 | static int maxframe[MAX_TOTAL_DEVICES]; | |
1da177e4 LT |
867 | static int txdmabufs[MAX_TOTAL_DEVICES]; |
868 | static int txholdbufs[MAX_TOTAL_DEVICES]; | |
869 | ||
870 | module_param(break_on_load, bool, 0); | |
871 | module_param(ttymajor, int, 0); | |
872 | module_param_array(io, int, NULL, 0); | |
873 | module_param_array(irq, int, NULL, 0); | |
874 | module_param_array(dma, int, NULL, 0); | |
875 | module_param(debug_level, int, 0); | |
876 | module_param_array(maxframe, int, NULL, 0); | |
1da177e4 LT |
877 | module_param_array(txdmabufs, int, NULL, 0); |
878 | module_param_array(txholdbufs, int, NULL, 0); | |
879 | ||
880 | static char *driver_name = "SyncLink serial driver"; | |
0ff1b2c8 | 881 | static char *driver_version = "$Revision: 4.38 $"; |
1da177e4 LT |
882 | |
883 | static int synclink_init_one (struct pci_dev *dev, | |
884 | const struct pci_device_id *ent); | |
885 | static void synclink_remove_one (struct pci_dev *dev); | |
886 | ||
887 | static struct pci_device_id synclink_pci_tbl[] = { | |
888 | { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, }, | |
889 | { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, }, | |
890 | { 0, }, /* terminate list */ | |
891 | }; | |
892 | MODULE_DEVICE_TABLE(pci, synclink_pci_tbl); | |
893 | ||
894 | MODULE_LICENSE("GPL"); | |
895 | ||
896 | static struct pci_driver synclink_pci_driver = { | |
897 | .name = "synclink", | |
898 | .id_table = synclink_pci_tbl, | |
899 | .probe = synclink_init_one, | |
91116cba | 900 | .remove = synclink_remove_one, |
1da177e4 LT |
901 | }; |
902 | ||
903 | static struct tty_driver *serial_driver; | |
904 | ||
905 | /* number of characters left in xmit buffer before we ask for more */ | |
906 | #define WAKEUP_CHARS 256 | |
907 | ||
908 | ||
909 | static void mgsl_change_params(struct mgsl_struct *info); | |
910 | static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout); | |
911 | ||
912 | /* | |
913 | * 1st function defined in .text section. Calling this function in | |
914 | * init_module() followed by a breakpoint allows a remote debugger | |
915 | * (gdb) to get the .text address for the add-symbol-file command. | |
916 | * This allows remote debugging of dynamically loadable modules. | |
917 | */ | |
918 | static void* mgsl_get_text_ptr(void) | |
919 | { | |
920 | return mgsl_get_text_ptr; | |
921 | } | |
922 | ||
1da177e4 LT |
923 | static inline int mgsl_paranoia_check(struct mgsl_struct *info, |
924 | char *name, const char *routine) | |
925 | { | |
926 | #ifdef MGSL_PARANOIA_CHECK | |
927 | static const char *badmagic = | |
928 | "Warning: bad magic number for mgsl struct (%s) in %s\n"; | |
929 | static const char *badinfo = | |
930 | "Warning: null mgsl_struct for (%s) in %s\n"; | |
931 | ||
932 | if (!info) { | |
933 | printk(badinfo, name, routine); | |
934 | return 1; | |
935 | } | |
936 | if (info->magic != MGSL_MAGIC) { | |
937 | printk(badmagic, name, routine); | |
938 | return 1; | |
939 | } | |
940 | #else | |
941 | if (!info) | |
942 | return 1; | |
943 | #endif | |
944 | return 0; | |
945 | } | |
946 | ||
947 | /** | |
948 | * line discipline callback wrappers | |
949 | * | |
950 | * The wrappers maintain line discipline references | |
951 | * while calling into the line discipline. | |
952 | * | |
953 | * ldisc_receive_buf - pass receive data to line discipline | |
954 | */ | |
955 | ||
956 | static void ldisc_receive_buf(struct tty_struct *tty, | |
957 | const __u8 *data, char *flags, int count) | |
958 | { | |
959 | struct tty_ldisc *ld; | |
960 | if (!tty) | |
961 | return; | |
962 | ld = tty_ldisc_ref(tty); | |
963 | if (ld) { | |
a352def2 AC |
964 | if (ld->ops->receive_buf) |
965 | ld->ops->receive_buf(tty, data, flags, count); | |
1da177e4 LT |
966 | tty_ldisc_deref(ld); |
967 | } | |
968 | } | |
969 | ||
970 | /* mgsl_stop() throttle (stop) transmitter | |
971 | * | |
972 | * Arguments: tty pointer to tty info structure | |
973 | * Return Value: None | |
974 | */ | |
975 | static void mgsl_stop(struct tty_struct *tty) | |
976 | { | |
c9f19e96 | 977 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
978 | unsigned long flags; |
979 | ||
980 | if (mgsl_paranoia_check(info, tty->name, "mgsl_stop")) | |
981 | return; | |
982 | ||
983 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
984 | printk("mgsl_stop(%s)\n",info->device_name); | |
985 | ||
986 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
987 | if (info->tx_enabled) | |
988 | usc_stop_transmitter(info); | |
989 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
990 | ||
991 | } /* end of mgsl_stop() */ | |
992 | ||
993 | /* mgsl_start() release (start) transmitter | |
994 | * | |
995 | * Arguments: tty pointer to tty info structure | |
996 | * Return Value: None | |
997 | */ | |
998 | static void mgsl_start(struct tty_struct *tty) | |
999 | { | |
c9f19e96 | 1000 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
1001 | unsigned long flags; |
1002 | ||
1003 | if (mgsl_paranoia_check(info, tty->name, "mgsl_start")) | |
1004 | return; | |
1005 | ||
1006 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1007 | printk("mgsl_start(%s)\n",info->device_name); | |
1008 | ||
1009 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
1010 | if (!info->tx_enabled) | |
1011 | usc_start_transmitter(info); | |
1012 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
1013 | ||
1014 | } /* end of mgsl_start() */ | |
1015 | ||
1016 | /* | |
1017 | * Bottom half work queue access functions | |
1018 | */ | |
1019 | ||
1020 | /* mgsl_bh_action() Return next bottom half action to perform. | |
1021 | * Return Value: BH action code or 0 if nothing to do. | |
1022 | */ | |
1023 | static int mgsl_bh_action(struct mgsl_struct *info) | |
1024 | { | |
1025 | unsigned long flags; | |
1026 | int rc = 0; | |
1027 | ||
1028 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
1029 | ||
1030 | if (info->pending_bh & BH_RECEIVE) { | |
1031 | info->pending_bh &= ~BH_RECEIVE; | |
1032 | rc = BH_RECEIVE; | |
1033 | } else if (info->pending_bh & BH_TRANSMIT) { | |
1034 | info->pending_bh &= ~BH_TRANSMIT; | |
1035 | rc = BH_TRANSMIT; | |
1036 | } else if (info->pending_bh & BH_STATUS) { | |
1037 | info->pending_bh &= ~BH_STATUS; | |
1038 | rc = BH_STATUS; | |
1039 | } | |
1040 | ||
1041 | if (!rc) { | |
1042 | /* Mark BH routine as complete */ | |
0fab6de0 JP |
1043 | info->bh_running = false; |
1044 | info->bh_requested = false; | |
1da177e4 LT |
1045 | } |
1046 | ||
1047 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
1048 | ||
1049 | return rc; | |
1050 | } | |
1051 | ||
1052 | /* | |
1053 | * Perform bottom half processing of work items queued by ISR. | |
1054 | */ | |
c4028958 | 1055 | static void mgsl_bh_handler(struct work_struct *work) |
1da177e4 | 1056 | { |
c4028958 DH |
1057 | struct mgsl_struct *info = |
1058 | container_of(work, struct mgsl_struct, task); | |
1da177e4 LT |
1059 | int action; |
1060 | ||
1da177e4 LT |
1061 | if ( debug_level >= DEBUG_LEVEL_BH ) |
1062 | printk( "%s(%d):mgsl_bh_handler(%s) entry\n", | |
1063 | __FILE__,__LINE__,info->device_name); | |
1064 | ||
0fab6de0 | 1065 | info->bh_running = true; |
1da177e4 LT |
1066 | |
1067 | while((action = mgsl_bh_action(info)) != 0) { | |
1068 | ||
1069 | /* Process work item */ | |
1070 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
1071 | printk( "%s(%d):mgsl_bh_handler() work item action=%d\n", | |
1072 | __FILE__,__LINE__,action); | |
1073 | ||
1074 | switch (action) { | |
1075 | ||
1076 | case BH_RECEIVE: | |
1077 | mgsl_bh_receive(info); | |
1078 | break; | |
1079 | case BH_TRANSMIT: | |
1080 | mgsl_bh_transmit(info); | |
1081 | break; | |
1082 | case BH_STATUS: | |
1083 | mgsl_bh_status(info); | |
1084 | break; | |
1085 | default: | |
1086 | /* unknown work item ID */ | |
1087 | printk("Unknown work item ID=%08X!\n", action); | |
1088 | break; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
1093 | printk( "%s(%d):mgsl_bh_handler(%s) exit\n", | |
1094 | __FILE__,__LINE__,info->device_name); | |
1095 | } | |
1096 | ||
1097 | static void mgsl_bh_receive(struct mgsl_struct *info) | |
1098 | { | |
0fab6de0 | 1099 | bool (*get_rx_frame)(struct mgsl_struct *info) = |
1da177e4 LT |
1100 | (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame); |
1101 | ||
1102 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
1103 | printk( "%s(%d):mgsl_bh_receive(%s)\n", | |
1104 | __FILE__,__LINE__,info->device_name); | |
1105 | ||
1106 | do | |
1107 | { | |
1108 | if (info->rx_rcc_underrun) { | |
1109 | unsigned long flags; | |
1110 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
1111 | usc_start_receiver(info); | |
1112 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
1113 | return; | |
1114 | } | |
1115 | } while(get_rx_frame(info)); | |
1116 | } | |
1117 | ||
1118 | static void mgsl_bh_transmit(struct mgsl_struct *info) | |
1119 | { | |
8fb06c77 | 1120 | struct tty_struct *tty = info->port.tty; |
1da177e4 LT |
1121 | unsigned long flags; |
1122 | ||
1123 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
1124 | printk( "%s(%d):mgsl_bh_transmit() entry on %s\n", | |
1125 | __FILE__,__LINE__,info->device_name); | |
1126 | ||
b963a844 | 1127 | if (tty) |
1da177e4 | 1128 | tty_wakeup(tty); |
1da177e4 LT |
1129 | |
1130 | /* if transmitter idle and loopmode_send_done_requested | |
1131 | * then start echoing RxD to TxD | |
1132 | */ | |
1133 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
1134 | if ( !info->tx_active && info->loopmode_send_done_requested ) | |
1135 | usc_loopmode_send_done( info ); | |
1136 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
1137 | } | |
1138 | ||
1139 | static void mgsl_bh_status(struct mgsl_struct *info) | |
1140 | { | |
1141 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
1142 | printk( "%s(%d):mgsl_bh_status() entry on %s\n", | |
1143 | __FILE__,__LINE__,info->device_name); | |
1144 | ||
1145 | info->ri_chkcount = 0; | |
1146 | info->dsr_chkcount = 0; | |
1147 | info->dcd_chkcount = 0; | |
1148 | info->cts_chkcount = 0; | |
1149 | } | |
1150 | ||
1151 | /* mgsl_isr_receive_status() | |
1152 | * | |
1153 | * Service a receive status interrupt. The type of status | |
1154 | * interrupt is indicated by the state of the RCSR. | |
1155 | * This is only used for HDLC mode. | |
1156 | * | |
1157 | * Arguments: info pointer to device instance data | |
1158 | * Return Value: None | |
1159 | */ | |
1160 | static void mgsl_isr_receive_status( struct mgsl_struct *info ) | |
1161 | { | |
1162 | u16 status = usc_InReg( info, RCSR ); | |
1163 | ||
e06922aa | 1164 | if ( debug_level >= DEBUG_LEVEL_ISR ) |
1da177e4 LT |
1165 | printk("%s(%d):mgsl_isr_receive_status status=%04X\n", |
1166 | __FILE__,__LINE__,status); | |
1167 | ||
1168 | if ( (status & RXSTATUS_ABORT_RECEIVED) && | |
1169 | info->loopmode_insert_requested && | |
1170 | usc_loopmode_active(info) ) | |
1171 | { | |
1172 | ++info->icount.rxabort; | |
0fab6de0 | 1173 | info->loopmode_insert_requested = false; |
1da177e4 LT |
1174 | |
1175 | /* clear CMR:13 to start echoing RxD to TxD */ | |
1176 | info->cmr_value &= ~BIT13; | |
1177 | usc_OutReg(info, CMR, info->cmr_value); | |
1178 | ||
1179 | /* disable received abort irq (no longer required) */ | |
1180 | usc_OutReg(info, RICR, | |
1181 | (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED)); | |
1182 | } | |
1183 | ||
e06922aa | 1184 | if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) { |
1da177e4 LT |
1185 | if (status & RXSTATUS_EXITED_HUNT) |
1186 | info->icount.exithunt++; | |
1187 | if (status & RXSTATUS_IDLE_RECEIVED) | |
1188 | info->icount.rxidle++; | |
1189 | wake_up_interruptible(&info->event_wait_q); | |
1190 | } | |
1191 | ||
1192 | if (status & RXSTATUS_OVERRUN){ | |
1193 | info->icount.rxover++; | |
1194 | usc_process_rxoverrun_sync( info ); | |
1195 | } | |
1196 | ||
1197 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); | |
1198 | usc_UnlatchRxstatusBits( info, status ); | |
1199 | ||
1200 | } /* end of mgsl_isr_receive_status() */ | |
1201 | ||
1202 | /* mgsl_isr_transmit_status() | |
1203 | * | |
1204 | * Service a transmit status interrupt | |
1205 | * HDLC mode :end of transmit frame | |
1206 | * Async mode:all data is sent | |
1207 | * transmit status is indicated by bits in the TCSR. | |
1208 | * | |
1209 | * Arguments: info pointer to device instance data | |
1210 | * Return Value: None | |
1211 | */ | |
1212 | static void mgsl_isr_transmit_status( struct mgsl_struct *info ) | |
1213 | { | |
1214 | u16 status = usc_InReg( info, TCSR ); | |
1215 | ||
1216 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1217 | printk("%s(%d):mgsl_isr_transmit_status status=%04X\n", | |
1218 | __FILE__,__LINE__,status); | |
1219 | ||
1220 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); | |
1221 | usc_UnlatchTxstatusBits( info, status ); | |
1222 | ||
1223 | if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) ) | |
1224 | { | |
1225 | /* finished sending HDLC abort. This may leave */ | |
1226 | /* the TxFifo with data from the aborted frame */ | |
1227 | /* so purge the TxFifo. Also shutdown the DMA */ | |
1228 | /* channel in case there is data remaining in */ | |
1229 | /* the DMA buffer */ | |
1230 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); | |
1231 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); | |
1232 | } | |
1233 | ||
1234 | if ( status & TXSTATUS_EOF_SENT ) | |
1235 | info->icount.txok++; | |
1236 | else if ( status & TXSTATUS_UNDERRUN ) | |
1237 | info->icount.txunder++; | |
1238 | else if ( status & TXSTATUS_ABORT_SENT ) | |
1239 | info->icount.txabort++; | |
1240 | else | |
1241 | info->icount.txunder++; | |
1242 | ||
0fab6de0 | 1243 | info->tx_active = false; |
1da177e4 LT |
1244 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
1245 | del_timer(&info->tx_timer); | |
1246 | ||
1247 | if ( info->drop_rts_on_tx_done ) { | |
1248 | usc_get_serial_signals( info ); | |
1249 | if ( info->serial_signals & SerialSignal_RTS ) { | |
1250 | info->serial_signals &= ~SerialSignal_RTS; | |
1251 | usc_set_serial_signals( info ); | |
1252 | } | |
0fab6de0 | 1253 | info->drop_rts_on_tx_done = false; |
1da177e4 LT |
1254 | } |
1255 | ||
af69c7f9 | 1256 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
1257 | if (info->netcount) |
1258 | hdlcdev_tx_done(info); | |
1259 | else | |
1260 | #endif | |
1261 | { | |
8fb06c77 | 1262 | if (info->port.tty->stopped || info->port.tty->hw_stopped) { |
1da177e4 LT |
1263 | usc_stop_transmitter(info); |
1264 | return; | |
1265 | } | |
1266 | info->pending_bh |= BH_TRANSMIT; | |
1267 | } | |
1268 | ||
1269 | } /* end of mgsl_isr_transmit_status() */ | |
1270 | ||
1271 | /* mgsl_isr_io_pin() | |
1272 | * | |
1273 | * Service an Input/Output pin interrupt. The type of | |
1274 | * interrupt is indicated by bits in the MISR | |
1275 | * | |
1276 | * Arguments: info pointer to device instance data | |
1277 | * Return Value: None | |
1278 | */ | |
1279 | static void mgsl_isr_io_pin( struct mgsl_struct *info ) | |
1280 | { | |
1281 | struct mgsl_icount *icount; | |
1282 | u16 status = usc_InReg( info, MISR ); | |
1283 | ||
1284 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1285 | printk("%s(%d):mgsl_isr_io_pin status=%04X\n", | |
1286 | __FILE__,__LINE__,status); | |
1287 | ||
1288 | usc_ClearIrqPendingBits( info, IO_PIN ); | |
1289 | usc_UnlatchIostatusBits( info, status ); | |
1290 | ||
1291 | if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED | | |
1292 | MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) { | |
1293 | icount = &info->icount; | |
1294 | /* update input line counters */ | |
1295 | if (status & MISCSTATUS_RI_LATCHED) { | |
1296 | if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1297 | usc_DisablestatusIrqs(info,SICR_RI); | |
1298 | icount->rng++; | |
1299 | if ( status & MISCSTATUS_RI ) | |
1300 | info->input_signal_events.ri_up++; | |
1301 | else | |
1302 | info->input_signal_events.ri_down++; | |
1303 | } | |
1304 | if (status & MISCSTATUS_DSR_LATCHED) { | |
1305 | if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1306 | usc_DisablestatusIrqs(info,SICR_DSR); | |
1307 | icount->dsr++; | |
1308 | if ( status & MISCSTATUS_DSR ) | |
1309 | info->input_signal_events.dsr_up++; | |
1310 | else | |
1311 | info->input_signal_events.dsr_down++; | |
1312 | } | |
1313 | if (status & MISCSTATUS_DCD_LATCHED) { | |
1314 | if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1315 | usc_DisablestatusIrqs(info,SICR_DCD); | |
1316 | icount->dcd++; | |
1317 | if (status & MISCSTATUS_DCD) { | |
1318 | info->input_signal_events.dcd_up++; | |
1319 | } else | |
1320 | info->input_signal_events.dcd_down++; | |
af69c7f9 | 1321 | #if SYNCLINK_GENERIC_HDLC |
fbeff3c1 KH |
1322 | if (info->netcount) { |
1323 | if (status & MISCSTATUS_DCD) | |
1324 | netif_carrier_on(info->netdev); | |
1325 | else | |
1326 | netif_carrier_off(info->netdev); | |
1327 | } | |
1da177e4 LT |
1328 | #endif |
1329 | } | |
1330 | if (status & MISCSTATUS_CTS_LATCHED) | |
1331 | { | |
1332 | if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) | |
1333 | usc_DisablestatusIrqs(info,SICR_CTS); | |
1334 | icount->cts++; | |
1335 | if ( status & MISCSTATUS_CTS ) | |
1336 | info->input_signal_events.cts_up++; | |
1337 | else | |
1338 | info->input_signal_events.cts_down++; | |
1339 | } | |
1340 | wake_up_interruptible(&info->status_event_wait_q); | |
1341 | wake_up_interruptible(&info->event_wait_q); | |
1342 | ||
8fb06c77 | 1343 | if ( (info->port.flags & ASYNC_CHECK_CD) && |
1da177e4 LT |
1344 | (status & MISCSTATUS_DCD_LATCHED) ) { |
1345 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1346 | printk("%s CD now %s...", info->device_name, | |
1347 | (status & MISCSTATUS_DCD) ? "on" : "off"); | |
1348 | if (status & MISCSTATUS_DCD) | |
8fb06c77 | 1349 | wake_up_interruptible(&info->port.open_wait); |
1da177e4 LT |
1350 | else { |
1351 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1352 | printk("doing serial hangup..."); | |
8fb06c77 AC |
1353 | if (info->port.tty) |
1354 | tty_hangup(info->port.tty); | |
1da177e4 LT |
1355 | } |
1356 | } | |
1357 | ||
f21ec3d2 | 1358 | if (tty_port_cts_enabled(&info->port) && |
1da177e4 | 1359 | (status & MISCSTATUS_CTS_LATCHED) ) { |
8fb06c77 | 1360 | if (info->port.tty->hw_stopped) { |
1da177e4 LT |
1361 | if (status & MISCSTATUS_CTS) { |
1362 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1363 | printk("CTS tx start..."); | |
8fb06c77 AC |
1364 | if (info->port.tty) |
1365 | info->port.tty->hw_stopped = 0; | |
1da177e4 LT |
1366 | usc_start_transmitter(info); |
1367 | info->pending_bh |= BH_TRANSMIT; | |
1368 | return; | |
1369 | } | |
1370 | } else { | |
1371 | if (!(status & MISCSTATUS_CTS)) { | |
1372 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1373 | printk("CTS tx stop..."); | |
8fb06c77 AC |
1374 | if (info->port.tty) |
1375 | info->port.tty->hw_stopped = 1; | |
1da177e4 LT |
1376 | usc_stop_transmitter(info); |
1377 | } | |
1378 | } | |
1379 | } | |
1380 | } | |
1381 | ||
1382 | info->pending_bh |= BH_STATUS; | |
1383 | ||
1384 | /* for diagnostics set IRQ flag */ | |
1385 | if ( status & MISCSTATUS_TXC_LATCHED ){ | |
1386 | usc_OutReg( info, SICR, | |
1387 | (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) ); | |
1388 | usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED ); | |
0fab6de0 | 1389 | info->irq_occurred = true; |
1da177e4 LT |
1390 | } |
1391 | ||
1392 | } /* end of mgsl_isr_io_pin() */ | |
1393 | ||
1394 | /* mgsl_isr_transmit_data() | |
1395 | * | |
1396 | * Service a transmit data interrupt (async mode only). | |
1397 | * | |
1398 | * Arguments: info pointer to device instance data | |
1399 | * Return Value: None | |
1400 | */ | |
1401 | static void mgsl_isr_transmit_data( struct mgsl_struct *info ) | |
1402 | { | |
1403 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1404 | printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n", | |
1405 | __FILE__,__LINE__,info->xmit_cnt); | |
1406 | ||
1407 | usc_ClearIrqPendingBits( info, TRANSMIT_DATA ); | |
1408 | ||
8fb06c77 | 1409 | if (info->port.tty->stopped || info->port.tty->hw_stopped) { |
1da177e4 LT |
1410 | usc_stop_transmitter(info); |
1411 | return; | |
1412 | } | |
1413 | ||
1414 | if ( info->xmit_cnt ) | |
1415 | usc_load_txfifo( info ); | |
1416 | else | |
0fab6de0 | 1417 | info->tx_active = false; |
1da177e4 LT |
1418 | |
1419 | if (info->xmit_cnt < WAKEUP_CHARS) | |
1420 | info->pending_bh |= BH_TRANSMIT; | |
1421 | ||
1422 | } /* end of mgsl_isr_transmit_data() */ | |
1423 | ||
1424 | /* mgsl_isr_receive_data() | |
1425 | * | |
1426 | * Service a receive data interrupt. This occurs | |
1427 | * when operating in asynchronous interrupt transfer mode. | |
1428 | * The receive data FIFO is flushed to the receive data buffers. | |
1429 | * | |
1430 | * Arguments: info pointer to device instance data | |
1431 | * Return Value: None | |
1432 | */ | |
1433 | static void mgsl_isr_receive_data( struct mgsl_struct *info ) | |
1434 | { | |
1435 | int Fifocount; | |
1436 | u16 status; | |
33f0f88f | 1437 | int work = 0; |
1da177e4 | 1438 | unsigned char DataByte; |
1da177e4 LT |
1439 | struct mgsl_icount *icount = &info->icount; |
1440 | ||
1441 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1442 | printk("%s(%d):mgsl_isr_receive_data\n", | |
1443 | __FILE__,__LINE__); | |
1444 | ||
1445 | usc_ClearIrqPendingBits( info, RECEIVE_DATA ); | |
1446 | ||
1447 | /* select FIFO status for RICR readback */ | |
1448 | usc_RCmd( info, RCmd_SelectRicrRxFifostatus ); | |
1449 | ||
1450 | /* clear the Wordstatus bit so that status readback */ | |
1451 | /* only reflects the status of this byte */ | |
1452 | usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); | |
1453 | ||
1454 | /* flush the receive FIFO */ | |
1455 | ||
1456 | while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) { | |
33f0f88f AC |
1457 | int flag; |
1458 | ||
1da177e4 LT |
1459 | /* read one byte from RxFIFO */ |
1460 | outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY), | |
1461 | info->io_base + CCAR ); | |
1462 | DataByte = inb( info->io_base + CCAR ); | |
1463 | ||
1464 | /* get the status of the received byte */ | |
1465 | status = usc_InReg(info, RCSR); | |
e06922aa AJ |
1466 | if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR | |
1467 | RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) | |
1da177e4 LT |
1468 | usc_UnlatchRxstatusBits(info,RXSTATUS_ALL); |
1469 | ||
1da177e4 LT |
1470 | icount->rx++; |
1471 | ||
33f0f88f | 1472 | flag = 0; |
e06922aa AJ |
1473 | if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR | |
1474 | RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) { | |
1475 | printk("rxerr=%04X\n",status); | |
1da177e4 LT |
1476 | /* update error statistics */ |
1477 | if ( status & RXSTATUS_BREAK_RECEIVED ) { | |
e06922aa | 1478 | status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR); |
1da177e4 | 1479 | icount->brk++; |
e06922aa | 1480 | } else if (status & RXSTATUS_PARITY_ERROR) |
1da177e4 LT |
1481 | icount->parity++; |
1482 | else if (status & RXSTATUS_FRAMING_ERROR) | |
1483 | icount->frame++; | |
1484 | else if (status & RXSTATUS_OVERRUN) { | |
1485 | /* must issue purge fifo cmd before */ | |
1486 | /* 16C32 accepts more receive chars */ | |
1487 | usc_RTCmd(info,RTCmd_PurgeRxFifo); | |
1488 | icount->overrun++; | |
1489 | } | |
1490 | ||
e06922aa | 1491 | /* discard char if tty control flags say so */ |
1da177e4 LT |
1492 | if (status & info->ignore_status_mask) |
1493 | continue; | |
1494 | ||
1495 | status &= info->read_status_mask; | |
1496 | ||
1497 | if (status & RXSTATUS_BREAK_RECEIVED) { | |
33f0f88f | 1498 | flag = TTY_BREAK; |
8fb06c77 | 1499 | if (info->port.flags & ASYNC_SAK) |
2e124b4a | 1500 | do_SAK(info->port.tty); |
1da177e4 | 1501 | } else if (status & RXSTATUS_PARITY_ERROR) |
33f0f88f | 1502 | flag = TTY_PARITY; |
1da177e4 | 1503 | else if (status & RXSTATUS_FRAMING_ERROR) |
33f0f88f | 1504 | flag = TTY_FRAME; |
1da177e4 | 1505 | } /* end of if (error) */ |
92a19f9c | 1506 | tty_insert_flip_char(&info->port, DataByte, flag); |
33f0f88f AC |
1507 | if (status & RXSTATUS_OVERRUN) { |
1508 | /* Overrun is special, since it's | |
1509 | * reported immediately, and doesn't | |
1510 | * affect the current character | |
1511 | */ | |
92a19f9c | 1512 | work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN); |
33f0f88f | 1513 | } |
1da177e4 LT |
1514 | } |
1515 | ||
1516 | if ( debug_level >= DEBUG_LEVEL_ISR ) { | |
1da177e4 LT |
1517 | printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n", |
1518 | __FILE__,__LINE__,icount->rx,icount->brk, | |
1519 | icount->parity,icount->frame,icount->overrun); | |
1520 | } | |
1521 | ||
33f0f88f | 1522 | if(work) |
2e124b4a | 1523 | tty_flip_buffer_push(&info->port); |
1da177e4 LT |
1524 | } |
1525 | ||
1526 | /* mgsl_isr_misc() | |
1527 | * | |
8dfba4d7 | 1528 | * Service a miscellaneous interrupt source. |
1da177e4 LT |
1529 | * |
1530 | * Arguments: info pointer to device extension (instance data) | |
1531 | * Return Value: None | |
1532 | */ | |
1533 | static void mgsl_isr_misc( struct mgsl_struct *info ) | |
1534 | { | |
1535 | u16 status = usc_InReg( info, MISR ); | |
1536 | ||
1537 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1538 | printk("%s(%d):mgsl_isr_misc status=%04X\n", | |
1539 | __FILE__,__LINE__,status); | |
1540 | ||
1541 | if ((status & MISCSTATUS_RCC_UNDERRUN) && | |
1542 | (info->params.mode == MGSL_MODE_HDLC)) { | |
1543 | ||
1544 | /* turn off receiver and rx DMA */ | |
1545 | usc_EnableReceiver(info,DISABLE_UNCONDITIONAL); | |
1546 | usc_DmaCmd(info, DmaCmd_ResetRxChannel); | |
1547 | usc_UnlatchRxstatusBits(info, RXSTATUS_ALL); | |
e06922aa AJ |
1548 | usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS); |
1549 | usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS); | |
1da177e4 LT |
1550 | |
1551 | /* schedule BH handler to restart receiver */ | |
1552 | info->pending_bh |= BH_RECEIVE; | |
0fab6de0 | 1553 | info->rx_rcc_underrun = true; |
1da177e4 LT |
1554 | } |
1555 | ||
1556 | usc_ClearIrqPendingBits( info, MISC ); | |
1557 | usc_UnlatchMiscstatusBits( info, status ); | |
1558 | ||
1559 | } /* end of mgsl_isr_misc() */ | |
1560 | ||
1561 | /* mgsl_isr_null() | |
1562 | * | |
1563 | * Services undefined interrupt vectors from the | |
1564 | * USC. (hence this function SHOULD never be called) | |
1565 | * | |
1566 | * Arguments: info pointer to device extension (instance data) | |
1567 | * Return Value: None | |
1568 | */ | |
1569 | static void mgsl_isr_null( struct mgsl_struct *info ) | |
1570 | { | |
1571 | ||
1572 | } /* end of mgsl_isr_null() */ | |
1573 | ||
1574 | /* mgsl_isr_receive_dma() | |
1575 | * | |
1576 | * Service a receive DMA channel interrupt. | |
1577 | * For this driver there are two sources of receive DMA interrupts | |
1578 | * as identified in the Receive DMA mode Register (RDMR): | |
1579 | * | |
1580 | * BIT3 EOA/EOL End of List, all receive buffers in receive | |
1581 | * buffer list have been filled (no more free buffers | |
1582 | * available). The DMA controller has shut down. | |
1583 | * | |
1584 | * BIT2 EOB End of Buffer. This interrupt occurs when a receive | |
1585 | * DMA buffer is terminated in response to completion | |
1586 | * of a good frame or a frame with errors. The status | |
1587 | * of the frame is stored in the buffer entry in the | |
1588 | * list of receive buffer entries. | |
1589 | * | |
1590 | * Arguments: info pointer to device instance data | |
1591 | * Return Value: None | |
1592 | */ | |
1593 | static void mgsl_isr_receive_dma( struct mgsl_struct *info ) | |
1594 | { | |
1595 | u16 status; | |
1596 | ||
1597 | /* clear interrupt pending and IUS bit for Rx DMA IRQ */ | |
e06922aa | 1598 | usc_OutDmaReg( info, CDIR, BIT9 | BIT1 ); |
1da177e4 LT |
1599 | |
1600 | /* Read the receive DMA status to identify interrupt type. */ | |
1601 | /* This also clears the status bits. */ | |
1602 | status = usc_InDmaReg( info, RDMR ); | |
1603 | ||
1604 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1605 | printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n", | |
1606 | __FILE__,__LINE__,info->device_name,status); | |
1607 | ||
1608 | info->pending_bh |= BH_RECEIVE; | |
1609 | ||
1610 | if ( status & BIT3 ) { | |
0fab6de0 | 1611 | info->rx_overflow = true; |
1da177e4 LT |
1612 | info->icount.buf_overrun++; |
1613 | } | |
1614 | ||
1615 | } /* end of mgsl_isr_receive_dma() */ | |
1616 | ||
1617 | /* mgsl_isr_transmit_dma() | |
1618 | * | |
1619 | * This function services a transmit DMA channel interrupt. | |
1620 | * | |
1621 | * For this driver there is one source of transmit DMA interrupts | |
1622 | * as identified in the Transmit DMA Mode Register (TDMR): | |
1623 | * | |
1624 | * BIT2 EOB End of Buffer. This interrupt occurs when a | |
1625 | * transmit DMA buffer has been emptied. | |
1626 | * | |
1627 | * The driver maintains enough transmit DMA buffers to hold at least | |
1628 | * one max frame size transmit frame. When operating in a buffered | |
1629 | * transmit mode, there may be enough transmit DMA buffers to hold at | |
1630 | * least two or more max frame size frames. On an EOB condition, | |
1631 | * determine if there are any queued transmit buffers and copy into | |
1632 | * transmit DMA buffers if we have room. | |
1633 | * | |
1634 | * Arguments: info pointer to device instance data | |
1635 | * Return Value: None | |
1636 | */ | |
1637 | static void mgsl_isr_transmit_dma( struct mgsl_struct *info ) | |
1638 | { | |
1639 | u16 status; | |
1640 | ||
1641 | /* clear interrupt pending and IUS bit for Tx DMA IRQ */ | |
e06922aa | 1642 | usc_OutDmaReg(info, CDIR, BIT8 | BIT0 ); |
1da177e4 LT |
1643 | |
1644 | /* Read the transmit DMA status to identify interrupt type. */ | |
1645 | /* This also clears the status bits. */ | |
1646 | ||
1647 | status = usc_InDmaReg( info, TDMR ); | |
1648 | ||
1649 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1650 | printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n", | |
1651 | __FILE__,__LINE__,info->device_name,status); | |
1652 | ||
1653 | if ( status & BIT2 ) { | |
1654 | --info->tx_dma_buffers_used; | |
1655 | ||
1656 | /* if there are transmit frames queued, | |
1657 | * try to load the next one | |
1658 | */ | |
1659 | if ( load_next_tx_holding_buffer(info) ) { | |
1660 | /* if call returns non-zero value, we have | |
1661 | * at least one free tx holding buffer | |
1662 | */ | |
1663 | info->pending_bh |= BH_TRANSMIT; | |
1664 | } | |
1665 | } | |
1666 | ||
1667 | } /* end of mgsl_isr_transmit_dma() */ | |
1668 | ||
1669 | /* mgsl_interrupt() | |
1670 | * | |
1671 | * Interrupt service routine entry point. | |
1672 | * | |
1673 | * Arguments: | |
1674 | * | |
1675 | * irq interrupt number that caused interrupt | |
1676 | * dev_id device ID supplied during interrupt registration | |
1da177e4 LT |
1677 | * |
1678 | * Return Value: None | |
1679 | */ | |
a6f97b29 | 1680 | static irqreturn_t mgsl_interrupt(int dummy, void *dev_id) |
1da177e4 | 1681 | { |
a6f97b29 | 1682 | struct mgsl_struct *info = dev_id; |
1da177e4 LT |
1683 | u16 UscVector; |
1684 | u16 DmaVector; | |
1685 | ||
1686 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
a6f97b29 JG |
1687 | printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n", |
1688 | __FILE__, __LINE__, info->irq_level); | |
1da177e4 | 1689 | |
1da177e4 LT |
1690 | spin_lock(&info->irq_spinlock); |
1691 | ||
1692 | for(;;) { | |
1693 | /* Read the interrupt vectors from hardware. */ | |
1694 | UscVector = usc_InReg(info, IVR) >> 9; | |
1695 | DmaVector = usc_InDmaReg(info, DIVR); | |
1696 | ||
1697 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1698 | printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n", | |
1699 | __FILE__,__LINE__,info->device_name,UscVector,DmaVector); | |
1700 | ||
1701 | if ( !UscVector && !DmaVector ) | |
1702 | break; | |
1703 | ||
1704 | /* Dispatch interrupt vector */ | |
1705 | if ( UscVector ) | |
1706 | (*UscIsrTable[UscVector])(info); | |
1707 | else if ( (DmaVector&(BIT10|BIT9)) == BIT10) | |
1708 | mgsl_isr_transmit_dma(info); | |
1709 | else | |
1710 | mgsl_isr_receive_dma(info); | |
1711 | ||
1712 | if ( info->isr_overflow ) { | |
a6f97b29 JG |
1713 | printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n", |
1714 | __FILE__, __LINE__, info->device_name, info->irq_level); | |
1da177e4 LT |
1715 | usc_DisableMasterIrqBit(info); |
1716 | usc_DisableDmaInterrupts(info,DICR_MASTER); | |
1717 | break; | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | /* Request bottom half processing if there's something | |
1722 | * for it to do and the bh is not already running | |
1723 | */ | |
1724 | ||
1725 | if ( info->pending_bh && !info->bh_running && !info->bh_requested ) { | |
1726 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
1727 | printk("%s(%d):%s queueing bh task.\n", | |
1728 | __FILE__,__LINE__,info->device_name); | |
1729 | schedule_work(&info->task); | |
0fab6de0 | 1730 | info->bh_requested = true; |
1da177e4 LT |
1731 | } |
1732 | ||
1733 | spin_unlock(&info->irq_spinlock); | |
1734 | ||
1735 | if ( debug_level >= DEBUG_LEVEL_ISR ) | |
a6f97b29 JG |
1736 | printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n", |
1737 | __FILE__, __LINE__, info->irq_level); | |
1738 | ||
1da177e4 LT |
1739 | return IRQ_HANDLED; |
1740 | } /* end of mgsl_interrupt() */ | |
1741 | ||
1742 | /* startup() | |
1743 | * | |
1744 | * Initialize and start device. | |
1745 | * | |
1746 | * Arguments: info pointer to device instance data | |
1747 | * Return Value: 0 if success, otherwise error code | |
1748 | */ | |
1749 | static int startup(struct mgsl_struct * info) | |
1750 | { | |
1751 | int retval = 0; | |
1752 | ||
1753 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
1754 | printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name); | |
1755 | ||
8fb06c77 | 1756 | if (info->port.flags & ASYNC_INITIALIZED) |
1da177e4 LT |
1757 | return 0; |
1758 | ||
1759 | if (!info->xmit_buf) { | |
1760 | /* allocate a page of memory for a transmit buffer */ | |
1761 | info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL); | |
1762 | if (!info->xmit_buf) { | |
1763 | printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n", | |
1764 | __FILE__,__LINE__,info->device_name); | |
1765 | return -ENOMEM; | |
1766 | } | |
1767 | } | |
1768 | ||
1769 | info->pending_bh = 0; | |
1770 | ||
9661239f PF |
1771 | memset(&info->icount, 0, sizeof(info->icount)); |
1772 | ||
40565f19 | 1773 | setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info); |
1da177e4 LT |
1774 | |
1775 | /* Allocate and claim adapter resources */ | |
1776 | retval = mgsl_claim_resources(info); | |
1777 | ||
1778 | /* perform existence check and diagnostics */ | |
1779 | if ( !retval ) | |
1780 | retval = mgsl_adapter_test(info); | |
1781 | ||
1782 | if ( retval ) { | |
8fb06c77 AC |
1783 | if (capable(CAP_SYS_ADMIN) && info->port.tty) |
1784 | set_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
1da177e4 LT |
1785 | mgsl_release_resources(info); |
1786 | return retval; | |
1787 | } | |
1788 | ||
1789 | /* program hardware for current parameters */ | |
1790 | mgsl_change_params(info); | |
1791 | ||
8fb06c77 AC |
1792 | if (info->port.tty) |
1793 | clear_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
1da177e4 | 1794 | |
8fb06c77 | 1795 | info->port.flags |= ASYNC_INITIALIZED; |
1da177e4 LT |
1796 | |
1797 | return 0; | |
1798 | ||
1799 | } /* end of startup() */ | |
1800 | ||
1801 | /* shutdown() | |
1802 | * | |
1803 | * Called by mgsl_close() and mgsl_hangup() to shutdown hardware | |
1804 | * | |
1805 | * Arguments: info pointer to device instance data | |
1806 | * Return Value: None | |
1807 | */ | |
1808 | static void shutdown(struct mgsl_struct * info) | |
1809 | { | |
1810 | unsigned long flags; | |
1811 | ||
8fb06c77 | 1812 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
1da177e4 LT |
1813 | return; |
1814 | ||
1815 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1816 | printk("%s(%d):mgsl_shutdown(%s)\n", | |
1817 | __FILE__,__LINE__, info->device_name ); | |
1818 | ||
1819 | /* clear status wait queue because status changes */ | |
1820 | /* can't happen after shutting down the hardware */ | |
1821 | wake_up_interruptible(&info->status_event_wait_q); | |
1822 | wake_up_interruptible(&info->event_wait_q); | |
1823 | ||
40565f19 | 1824 | del_timer_sync(&info->tx_timer); |
1da177e4 LT |
1825 | |
1826 | if (info->xmit_buf) { | |
1827 | free_page((unsigned long) info->xmit_buf); | |
1828 | info->xmit_buf = NULL; | |
1829 | } | |
1830 | ||
1831 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
1832 | usc_DisableMasterIrqBit(info); | |
1833 | usc_stop_receiver(info); | |
1834 | usc_stop_transmitter(info); | |
e06922aa AJ |
1835 | usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS | |
1836 | TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC ); | |
1da177e4 | 1837 | usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE); |
adc8d746 | 1838 | |
1da177e4 LT |
1839 | /* Disable DMAEN (Port 7, Bit 14) */ |
1840 | /* This disconnects the DMA request signal from the ISA bus */ | |
1841 | /* on the ISA adapter. This has no effect for the PCI adapter */ | |
1842 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14)); | |
adc8d746 | 1843 | |
1da177e4 LT |
1844 | /* Disable INTEN (Port 6, Bit12) */ |
1845 | /* This disconnects the IRQ request signal to the ISA bus */ | |
1846 | /* on the ISA adapter. This has no effect for the PCI adapter */ | |
1847 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); | |
adc8d746 AC |
1848 | |
1849 | if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) { | |
9fe8074b | 1850 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
1da177e4 LT |
1851 | usc_set_serial_signals(info); |
1852 | } | |
adc8d746 | 1853 | |
1da177e4 LT |
1854 | spin_unlock_irqrestore(&info->irq_spinlock,flags); |
1855 | ||
1856 | mgsl_release_resources(info); | |
1857 | ||
8fb06c77 AC |
1858 | if (info->port.tty) |
1859 | set_bit(TTY_IO_ERROR, &info->port.tty->flags); | |
1da177e4 | 1860 | |
8fb06c77 | 1861 | info->port.flags &= ~ASYNC_INITIALIZED; |
1da177e4 LT |
1862 | |
1863 | } /* end of shutdown() */ | |
1864 | ||
1865 | static void mgsl_program_hw(struct mgsl_struct *info) | |
1866 | { | |
1867 | unsigned long flags; | |
1868 | ||
1869 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
1870 | ||
1871 | usc_stop_receiver(info); | |
1872 | usc_stop_transmitter(info); | |
1873 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
1874 | ||
1875 | if (info->params.mode == MGSL_MODE_HDLC || | |
1876 | info->params.mode == MGSL_MODE_RAW || | |
1877 | info->netcount) | |
1878 | usc_set_sync_mode(info); | |
1879 | else | |
1880 | usc_set_async_mode(info); | |
1881 | ||
1882 | usc_set_serial_signals(info); | |
1883 | ||
1884 | info->dcd_chkcount = 0; | |
1885 | info->cts_chkcount = 0; | |
1886 | info->ri_chkcount = 0; | |
1887 | info->dsr_chkcount = 0; | |
1888 | ||
e06922aa | 1889 | usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI); |
1da177e4 LT |
1890 | usc_EnableInterrupts(info, IO_PIN); |
1891 | usc_get_serial_signals(info); | |
1892 | ||
adc8d746 | 1893 | if (info->netcount || info->port.tty->termios.c_cflag & CREAD) |
1da177e4 LT |
1894 | usc_start_receiver(info); |
1895 | ||
1896 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
1897 | } | |
1898 | ||
1899 | /* Reconfigure adapter based on new parameters | |
1900 | */ | |
1901 | static void mgsl_change_params(struct mgsl_struct *info) | |
1902 | { | |
1903 | unsigned cflag; | |
1904 | int bits_per_char; | |
1905 | ||
adc8d746 | 1906 | if (!info->port.tty) |
1da177e4 LT |
1907 | return; |
1908 | ||
1909 | if (debug_level >= DEBUG_LEVEL_INFO) | |
1910 | printk("%s(%d):mgsl_change_params(%s)\n", | |
1911 | __FILE__,__LINE__, info->device_name ); | |
1912 | ||
adc8d746 | 1913 | cflag = info->port.tty->termios.c_cflag; |
1da177e4 | 1914 | |
9fe8074b JP |
1915 | /* if B0 rate (hangup) specified then negate RTS and DTR */ |
1916 | /* otherwise assert RTS and DTR */ | |
1da177e4 | 1917 | if (cflag & CBAUD) |
9fe8074b | 1918 | info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; |
1da177e4 | 1919 | else |
9fe8074b | 1920 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
1da177e4 LT |
1921 | |
1922 | /* byte size and parity */ | |
1923 | ||
1924 | switch (cflag & CSIZE) { | |
1925 | case CS5: info->params.data_bits = 5; break; | |
1926 | case CS6: info->params.data_bits = 6; break; | |
1927 | case CS7: info->params.data_bits = 7; break; | |
1928 | case CS8: info->params.data_bits = 8; break; | |
1929 | /* Never happens, but GCC is too dumb to figure it out */ | |
1930 | default: info->params.data_bits = 7; break; | |
1931 | } | |
1932 | ||
1933 | if (cflag & CSTOPB) | |
1934 | info->params.stop_bits = 2; | |
1935 | else | |
1936 | info->params.stop_bits = 1; | |
1937 | ||
1938 | info->params.parity = ASYNC_PARITY_NONE; | |
1939 | if (cflag & PARENB) { | |
1940 | if (cflag & PARODD) | |
1941 | info->params.parity = ASYNC_PARITY_ODD; | |
1942 | else | |
1943 | info->params.parity = ASYNC_PARITY_EVEN; | |
1944 | #ifdef CMSPAR | |
1945 | if (cflag & CMSPAR) | |
1946 | info->params.parity = ASYNC_PARITY_SPACE; | |
1947 | #endif | |
1948 | } | |
1949 | ||
1950 | /* calculate number of jiffies to transmit a full | |
1951 | * FIFO (32 bytes) at specified data rate | |
1952 | */ | |
1953 | bits_per_char = info->params.data_bits + | |
1954 | info->params.stop_bits + 1; | |
1955 | ||
1956 | /* if port data rate is set to 460800 or less then | |
1957 | * allow tty settings to override, otherwise keep the | |
1958 | * current data rate. | |
1959 | */ | |
1960 | if (info->params.data_rate <= 460800) | |
8fb06c77 | 1961 | info->params.data_rate = tty_get_baud_rate(info->port.tty); |
1da177e4 LT |
1962 | |
1963 | if ( info->params.data_rate ) { | |
1964 | info->timeout = (32*HZ*bits_per_char) / | |
1965 | info->params.data_rate; | |
1966 | } | |
1967 | info->timeout += HZ/50; /* Add .02 seconds of slop */ | |
1968 | ||
1969 | if (cflag & CRTSCTS) | |
8fb06c77 | 1970 | info->port.flags |= ASYNC_CTS_FLOW; |
1da177e4 | 1971 | else |
8fb06c77 | 1972 | info->port.flags &= ~ASYNC_CTS_FLOW; |
1da177e4 LT |
1973 | |
1974 | if (cflag & CLOCAL) | |
8fb06c77 | 1975 | info->port.flags &= ~ASYNC_CHECK_CD; |
1da177e4 | 1976 | else |
8fb06c77 | 1977 | info->port.flags |= ASYNC_CHECK_CD; |
1da177e4 LT |
1978 | |
1979 | /* process tty input control flags */ | |
1980 | ||
1981 | info->read_status_mask = RXSTATUS_OVERRUN; | |
8fb06c77 | 1982 | if (I_INPCK(info->port.tty)) |
1da177e4 | 1983 | info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR; |
8fb06c77 | 1984 | if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty)) |
1da177e4 LT |
1985 | info->read_status_mask |= RXSTATUS_BREAK_RECEIVED; |
1986 | ||
8fb06c77 | 1987 | if (I_IGNPAR(info->port.tty)) |
1da177e4 | 1988 | info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR; |
8fb06c77 | 1989 | if (I_IGNBRK(info->port.tty)) { |
1da177e4 LT |
1990 | info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED; |
1991 | /* If ignoring parity and break indicators, ignore | |
1992 | * overruns too. (For real raw support). | |
1993 | */ | |
8fb06c77 | 1994 | if (I_IGNPAR(info->port.tty)) |
1da177e4 LT |
1995 | info->ignore_status_mask |= RXSTATUS_OVERRUN; |
1996 | } | |
1997 | ||
1998 | mgsl_program_hw(info); | |
1999 | ||
2000 | } /* end of mgsl_change_params() */ | |
2001 | ||
2002 | /* mgsl_put_char() | |
2003 | * | |
2004 | * Add a character to the transmit buffer. | |
2005 | * | |
2006 | * Arguments: tty pointer to tty information structure | |
2007 | * ch character to add to transmit buffer | |
2008 | * | |
2009 | * Return Value: None | |
2010 | */ | |
55da7789 | 2011 | static int mgsl_put_char(struct tty_struct *tty, unsigned char ch) |
1da177e4 | 2012 | { |
07648230 | 2013 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 | 2014 | unsigned long flags; |
07648230 | 2015 | int ret = 0; |
1da177e4 | 2016 | |
07648230 | 2017 | if (debug_level >= DEBUG_LEVEL_INFO) { |
5098021e | 2018 | printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n", |
07648230 | 2019 | __FILE__, __LINE__, ch, info->device_name); |
1da177e4 LT |
2020 | } |
2021 | ||
2022 | if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char")) | |
55da7789 | 2023 | return 0; |
1da177e4 | 2024 | |
ca1cce49 | 2025 | if (!info->xmit_buf) |
55da7789 | 2026 | return 0; |
1da177e4 | 2027 | |
07648230 | 2028 | spin_lock_irqsave(&info->irq_spinlock, flags); |
1da177e4 | 2029 | |
07648230 | 2030 | if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) { |
1da177e4 LT |
2031 | if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) { |
2032 | info->xmit_buf[info->xmit_head++] = ch; | |
2033 | info->xmit_head &= SERIAL_XMIT_SIZE-1; | |
2034 | info->xmit_cnt++; | |
55da7789 | 2035 | ret = 1; |
1da177e4 LT |
2036 | } |
2037 | } | |
07648230 | 2038 | spin_unlock_irqrestore(&info->irq_spinlock, flags); |
55da7789 | 2039 | return ret; |
1da177e4 LT |
2040 | |
2041 | } /* end of mgsl_put_char() */ | |
2042 | ||
2043 | /* mgsl_flush_chars() | |
2044 | * | |
2045 | * Enable transmitter so remaining characters in the | |
2046 | * transmit buffer are sent. | |
2047 | * | |
2048 | * Arguments: tty pointer to tty information structure | |
2049 | * Return Value: None | |
2050 | */ | |
2051 | static void mgsl_flush_chars(struct tty_struct *tty) | |
2052 | { | |
c9f19e96 | 2053 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2054 | unsigned long flags; |
2055 | ||
2056 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2057 | printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n", | |
2058 | __FILE__,__LINE__,info->device_name,info->xmit_cnt); | |
2059 | ||
2060 | if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars")) | |
2061 | return; | |
2062 | ||
2063 | if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped || | |
2064 | !info->xmit_buf) | |
2065 | return; | |
2066 | ||
2067 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2068 | printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n", | |
2069 | __FILE__,__LINE__,info->device_name ); | |
2070 | ||
2071 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2072 | ||
2073 | if (!info->tx_active) { | |
2074 | if ( (info->params.mode == MGSL_MODE_HDLC || | |
2075 | info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) { | |
2076 | /* operating in synchronous (frame oriented) mode */ | |
2077 | /* copy data from circular xmit_buf to */ | |
2078 | /* transmit DMA buffer. */ | |
2079 | mgsl_load_tx_dma_buffer(info, | |
2080 | info->xmit_buf,info->xmit_cnt); | |
2081 | } | |
2082 | usc_start_transmitter(info); | |
2083 | } | |
2084 | ||
2085 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2086 | ||
2087 | } /* end of mgsl_flush_chars() */ | |
2088 | ||
2089 | /* mgsl_write() | |
2090 | * | |
2091 | * Send a block of data | |
2092 | * | |
2093 | * Arguments: | |
2094 | * | |
2095 | * tty pointer to tty information structure | |
2096 | * buf pointer to buffer containing send data | |
2097 | * count size of send data in bytes | |
2098 | * | |
2099 | * Return Value: number of characters written | |
2100 | */ | |
2101 | static int mgsl_write(struct tty_struct * tty, | |
2102 | const unsigned char *buf, int count) | |
2103 | { | |
2104 | int c, ret = 0; | |
c9f19e96 | 2105 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2106 | unsigned long flags; |
2107 | ||
2108 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2109 | printk( "%s(%d):mgsl_write(%s) count=%d\n", | |
2110 | __FILE__,__LINE__,info->device_name,count); | |
2111 | ||
2112 | if (mgsl_paranoia_check(info, tty->name, "mgsl_write")) | |
2113 | goto cleanup; | |
2114 | ||
ca1cce49 | 2115 | if (!info->xmit_buf) |
1da177e4 LT |
2116 | goto cleanup; |
2117 | ||
2118 | if ( info->params.mode == MGSL_MODE_HDLC || | |
2119 | info->params.mode == MGSL_MODE_RAW ) { | |
2120 | /* operating in synchronous (frame oriented) mode */ | |
1da177e4 LT |
2121 | if (info->tx_active) { |
2122 | ||
2123 | if ( info->params.mode == MGSL_MODE_HDLC ) { | |
2124 | ret = 0; | |
2125 | goto cleanup; | |
2126 | } | |
2127 | /* transmitter is actively sending data - | |
2128 | * if we have multiple transmit dma and | |
2129 | * holding buffers, attempt to queue this | |
2130 | * frame for transmission at a later time. | |
2131 | */ | |
2132 | if (info->tx_holding_count >= info->num_tx_holding_buffers ) { | |
2133 | /* no tx holding buffers available */ | |
2134 | ret = 0; | |
2135 | goto cleanup; | |
2136 | } | |
2137 | ||
2138 | /* queue transmit frame request */ | |
2139 | ret = count; | |
2140 | save_tx_buffer_request(info,buf,count); | |
2141 | ||
2142 | /* if we have sufficient tx dma buffers, | |
2143 | * load the next buffered tx request | |
2144 | */ | |
2145 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2146 | load_next_tx_holding_buffer(info); | |
2147 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2148 | goto cleanup; | |
2149 | } | |
2150 | ||
2151 | /* if operating in HDLC LoopMode and the adapter */ | |
2152 | /* has yet to be inserted into the loop, we can't */ | |
2153 | /* transmit */ | |
2154 | ||
2155 | if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) && | |
2156 | !usc_loopmode_active(info) ) | |
2157 | { | |
2158 | ret = 0; | |
2159 | goto cleanup; | |
2160 | } | |
2161 | ||
2162 | if ( info->xmit_cnt ) { | |
2163 | /* Send accumulated from send_char() calls */ | |
2164 | /* as frame and wait before accepting more data. */ | |
2165 | ret = 0; | |
2166 | ||
2167 | /* copy data from circular xmit_buf to */ | |
2168 | /* transmit DMA buffer. */ | |
2169 | mgsl_load_tx_dma_buffer(info, | |
2170 | info->xmit_buf,info->xmit_cnt); | |
2171 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2172 | printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n", | |
2173 | __FILE__,__LINE__,info->device_name); | |
2174 | } else { | |
2175 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2176 | printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n", | |
2177 | __FILE__,__LINE__,info->device_name); | |
2178 | ret = count; | |
2179 | info->xmit_cnt = count; | |
2180 | mgsl_load_tx_dma_buffer(info,buf,count); | |
2181 | } | |
2182 | } else { | |
2183 | while (1) { | |
2184 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2185 | c = min_t(int, count, | |
2186 | min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, | |
2187 | SERIAL_XMIT_SIZE - info->xmit_head)); | |
2188 | if (c <= 0) { | |
2189 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2190 | break; | |
2191 | } | |
2192 | memcpy(info->xmit_buf + info->xmit_head, buf, c); | |
2193 | info->xmit_head = ((info->xmit_head + c) & | |
2194 | (SERIAL_XMIT_SIZE-1)); | |
2195 | info->xmit_cnt += c; | |
2196 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2197 | buf += c; | |
2198 | count -= c; | |
2199 | ret += c; | |
2200 | } | |
2201 | } | |
2202 | ||
2203 | if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) { | |
2204 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2205 | if (!info->tx_active) | |
2206 | usc_start_transmitter(info); | |
2207 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2208 | } | |
2209 | cleanup: | |
2210 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2211 | printk( "%s(%d):mgsl_write(%s) returning=%d\n", | |
2212 | __FILE__,__LINE__,info->device_name,ret); | |
2213 | ||
2214 | return ret; | |
2215 | ||
2216 | } /* end of mgsl_write() */ | |
2217 | ||
2218 | /* mgsl_write_room() | |
2219 | * | |
2220 | * Return the count of free bytes in transmit buffer | |
2221 | * | |
2222 | * Arguments: tty pointer to tty info structure | |
2223 | * Return Value: None | |
2224 | */ | |
2225 | static int mgsl_write_room(struct tty_struct *tty) | |
2226 | { | |
c9f19e96 | 2227 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2228 | int ret; |
2229 | ||
2230 | if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room")) | |
2231 | return 0; | |
2232 | ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; | |
2233 | if (ret < 0) | |
2234 | ret = 0; | |
2235 | ||
2236 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2237 | printk("%s(%d):mgsl_write_room(%s)=%d\n", | |
2238 | __FILE__,__LINE__, info->device_name,ret ); | |
2239 | ||
2240 | if ( info->params.mode == MGSL_MODE_HDLC || | |
2241 | info->params.mode == MGSL_MODE_RAW ) { | |
2242 | /* operating in synchronous (frame oriented) mode */ | |
2243 | if ( info->tx_active ) | |
2244 | return 0; | |
2245 | else | |
2246 | return HDLC_MAX_FRAME_SIZE; | |
2247 | } | |
2248 | ||
2249 | return ret; | |
2250 | ||
2251 | } /* end of mgsl_write_room() */ | |
2252 | ||
2253 | /* mgsl_chars_in_buffer() | |
2254 | * | |
2255 | * Return the count of bytes in transmit buffer | |
2256 | * | |
2257 | * Arguments: tty pointer to tty info structure | |
2258 | * Return Value: None | |
2259 | */ | |
2260 | static int mgsl_chars_in_buffer(struct tty_struct *tty) | |
2261 | { | |
c9f19e96 | 2262 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2263 | |
2264 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2265 | printk("%s(%d):mgsl_chars_in_buffer(%s)\n", | |
2266 | __FILE__,__LINE__, info->device_name ); | |
2267 | ||
2268 | if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer")) | |
2269 | return 0; | |
2270 | ||
2271 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2272 | printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n", | |
2273 | __FILE__,__LINE__, info->device_name,info->xmit_cnt ); | |
2274 | ||
2275 | if ( info->params.mode == MGSL_MODE_HDLC || | |
2276 | info->params.mode == MGSL_MODE_RAW ) { | |
2277 | /* operating in synchronous (frame oriented) mode */ | |
2278 | if ( info->tx_active ) | |
2279 | return info->max_frame_size; | |
2280 | else | |
2281 | return 0; | |
2282 | } | |
2283 | ||
2284 | return info->xmit_cnt; | |
2285 | } /* end of mgsl_chars_in_buffer() */ | |
2286 | ||
2287 | /* mgsl_flush_buffer() | |
2288 | * | |
2289 | * Discard all data in the send buffer | |
2290 | * | |
2291 | * Arguments: tty pointer to tty info structure | |
2292 | * Return Value: None | |
2293 | */ | |
2294 | static void mgsl_flush_buffer(struct tty_struct *tty) | |
2295 | { | |
c9f19e96 | 2296 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2297 | unsigned long flags; |
2298 | ||
2299 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2300 | printk("%s(%d):mgsl_flush_buffer(%s) entry\n", | |
2301 | __FILE__,__LINE__, info->device_name ); | |
2302 | ||
2303 | if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer")) | |
2304 | return; | |
2305 | ||
2306 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2307 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; | |
2308 | del_timer(&info->tx_timer); | |
2309 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2310 | ||
1da177e4 LT |
2311 | tty_wakeup(tty); |
2312 | } | |
2313 | ||
2314 | /* mgsl_send_xchar() | |
2315 | * | |
2316 | * Send a high-priority XON/XOFF character | |
2317 | * | |
2318 | * Arguments: tty pointer to tty info structure | |
2319 | * ch character to send | |
2320 | * Return Value: None | |
2321 | */ | |
2322 | static void mgsl_send_xchar(struct tty_struct *tty, char ch) | |
2323 | { | |
c9f19e96 | 2324 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2325 | unsigned long flags; |
2326 | ||
2327 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2328 | printk("%s(%d):mgsl_send_xchar(%s,%d)\n", | |
2329 | __FILE__,__LINE__, info->device_name, ch ); | |
2330 | ||
2331 | if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar")) | |
2332 | return; | |
2333 | ||
2334 | info->x_char = ch; | |
2335 | if (ch) { | |
2336 | /* Make sure transmit interrupts are on */ | |
2337 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2338 | if (!info->tx_enabled) | |
2339 | usc_start_transmitter(info); | |
2340 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2341 | } | |
2342 | } /* end of mgsl_send_xchar() */ | |
2343 | ||
2344 | /* mgsl_throttle() | |
2345 | * | |
2346 | * Signal remote device to throttle send data (our receive data) | |
2347 | * | |
2348 | * Arguments: tty pointer to tty info structure | |
2349 | * Return Value: None | |
2350 | */ | |
2351 | static void mgsl_throttle(struct tty_struct * tty) | |
2352 | { | |
c9f19e96 | 2353 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2354 | unsigned long flags; |
2355 | ||
2356 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2357 | printk("%s(%d):mgsl_throttle(%s) entry\n", | |
2358 | __FILE__,__LINE__, info->device_name ); | |
2359 | ||
2360 | if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle")) | |
2361 | return; | |
2362 | ||
2363 | if (I_IXOFF(tty)) | |
2364 | mgsl_send_xchar(tty, STOP_CHAR(tty)); | |
adc8d746 AC |
2365 | |
2366 | if (tty->termios.c_cflag & CRTSCTS) { | |
1da177e4 LT |
2367 | spin_lock_irqsave(&info->irq_spinlock,flags); |
2368 | info->serial_signals &= ~SerialSignal_RTS; | |
2369 | usc_set_serial_signals(info); | |
2370 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2371 | } | |
2372 | } /* end of mgsl_throttle() */ | |
2373 | ||
2374 | /* mgsl_unthrottle() | |
2375 | * | |
2376 | * Signal remote device to stop throttling send data (our receive data) | |
2377 | * | |
2378 | * Arguments: tty pointer to tty info structure | |
2379 | * Return Value: None | |
2380 | */ | |
2381 | static void mgsl_unthrottle(struct tty_struct * tty) | |
2382 | { | |
c9f19e96 | 2383 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2384 | unsigned long flags; |
2385 | ||
2386 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2387 | printk("%s(%d):mgsl_unthrottle(%s) entry\n", | |
2388 | __FILE__,__LINE__, info->device_name ); | |
2389 | ||
2390 | if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle")) | |
2391 | return; | |
2392 | ||
2393 | if (I_IXOFF(tty)) { | |
2394 | if (info->x_char) | |
2395 | info->x_char = 0; | |
2396 | else | |
2397 | mgsl_send_xchar(tty, START_CHAR(tty)); | |
2398 | } | |
adc8d746 AC |
2399 | |
2400 | if (tty->termios.c_cflag & CRTSCTS) { | |
1da177e4 LT |
2401 | spin_lock_irqsave(&info->irq_spinlock,flags); |
2402 | info->serial_signals |= SerialSignal_RTS; | |
2403 | usc_set_serial_signals(info); | |
2404 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2405 | } | |
2406 | ||
2407 | } /* end of mgsl_unthrottle() */ | |
2408 | ||
2409 | /* mgsl_get_stats() | |
2410 | * | |
2411 | * get the current serial parameters information | |
2412 | * | |
2413 | * Arguments: info pointer to device instance data | |
2414 | * user_icount pointer to buffer to hold returned stats | |
2415 | * | |
2416 | * Return Value: 0 if success, otherwise error code | |
2417 | */ | |
2418 | static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount) | |
2419 | { | |
2420 | int err; | |
2421 | ||
2422 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2423 | printk("%s(%d):mgsl_get_params(%s)\n", | |
2424 | __FILE__,__LINE__, info->device_name); | |
2425 | ||
9661239f PF |
2426 | if (!user_icount) { |
2427 | memset(&info->icount, 0, sizeof(info->icount)); | |
2428 | } else { | |
f602501d | 2429 | mutex_lock(&info->port.mutex); |
9661239f | 2430 | COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount)); |
f602501d | 2431 | mutex_unlock(&info->port.mutex); |
9661239f PF |
2432 | if (err) |
2433 | return -EFAULT; | |
1da177e4 LT |
2434 | } |
2435 | ||
2436 | return 0; | |
2437 | ||
2438 | } /* end of mgsl_get_stats() */ | |
2439 | ||
2440 | /* mgsl_get_params() | |
2441 | * | |
2442 | * get the current serial parameters information | |
2443 | * | |
2444 | * Arguments: info pointer to device instance data | |
2445 | * user_params pointer to buffer to hold returned params | |
2446 | * | |
2447 | * Return Value: 0 if success, otherwise error code | |
2448 | */ | |
2449 | static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params) | |
2450 | { | |
2451 | int err; | |
2452 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2453 | printk("%s(%d):mgsl_get_params(%s)\n", | |
2454 | __FILE__,__LINE__, info->device_name); | |
2455 | ||
f602501d | 2456 | mutex_lock(&info->port.mutex); |
1da177e4 | 2457 | COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS)); |
f602501d | 2458 | mutex_unlock(&info->port.mutex); |
1da177e4 LT |
2459 | if (err) { |
2460 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2461 | printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n", | |
2462 | __FILE__,__LINE__,info->device_name); | |
2463 | return -EFAULT; | |
2464 | } | |
2465 | ||
2466 | return 0; | |
2467 | ||
2468 | } /* end of mgsl_get_params() */ | |
2469 | ||
2470 | /* mgsl_set_params() | |
2471 | * | |
2472 | * set the serial parameters | |
2473 | * | |
2474 | * Arguments: | |
2475 | * | |
2476 | * info pointer to device instance data | |
2477 | * new_params user buffer containing new serial params | |
2478 | * | |
2479 | * Return Value: 0 if success, otherwise error code | |
2480 | */ | |
2481 | static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params) | |
2482 | { | |
2483 | unsigned long flags; | |
2484 | MGSL_PARAMS tmp_params; | |
2485 | int err; | |
2486 | ||
2487 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2488 | printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__, | |
2489 | info->device_name ); | |
2490 | COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS)); | |
2491 | if (err) { | |
2492 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2493 | printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n", | |
2494 | __FILE__,__LINE__,info->device_name); | |
2495 | return -EFAULT; | |
2496 | } | |
2497 | ||
f602501d | 2498 | mutex_lock(&info->port.mutex); |
1da177e4 LT |
2499 | spin_lock_irqsave(&info->irq_spinlock,flags); |
2500 | memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); | |
2501 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2502 | ||
2503 | mgsl_change_params(info); | |
f602501d | 2504 | mutex_unlock(&info->port.mutex); |
1da177e4 LT |
2505 | |
2506 | return 0; | |
2507 | ||
2508 | } /* end of mgsl_set_params() */ | |
2509 | ||
2510 | /* mgsl_get_txidle() | |
2511 | * | |
2512 | * get the current transmit idle mode | |
2513 | * | |
2514 | * Arguments: info pointer to device instance data | |
2515 | * idle_mode pointer to buffer to hold returned idle mode | |
2516 | * | |
2517 | * Return Value: 0 if success, otherwise error code | |
2518 | */ | |
2519 | static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode) | |
2520 | { | |
2521 | int err; | |
2522 | ||
2523 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2524 | printk("%s(%d):mgsl_get_txidle(%s)=%d\n", | |
2525 | __FILE__,__LINE__, info->device_name, info->idle_mode); | |
2526 | ||
2527 | COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int)); | |
2528 | if (err) { | |
2529 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
2530 | printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n", | |
2531 | __FILE__,__LINE__,info->device_name); | |
2532 | return -EFAULT; | |
2533 | } | |
2534 | ||
2535 | return 0; | |
2536 | ||
2537 | } /* end of mgsl_get_txidle() */ | |
2538 | ||
2539 | /* mgsl_set_txidle() service ioctl to set transmit idle mode | |
2540 | * | |
2541 | * Arguments: info pointer to device instance data | |
2542 | * idle_mode new idle mode | |
2543 | * | |
2544 | * Return Value: 0 if success, otherwise error code | |
2545 | */ | |
2546 | static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode) | |
2547 | { | |
2548 | unsigned long flags; | |
2549 | ||
2550 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2551 | printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__, | |
2552 | info->device_name, idle_mode ); | |
2553 | ||
2554 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2555 | info->idle_mode = idle_mode; | |
2556 | usc_set_txidle( info ); | |
2557 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2558 | return 0; | |
2559 | ||
2560 | } /* end of mgsl_set_txidle() */ | |
2561 | ||
2562 | /* mgsl_txenable() | |
2563 | * | |
2564 | * enable or disable the transmitter | |
2565 | * | |
2566 | * Arguments: | |
2567 | * | |
2568 | * info pointer to device instance data | |
2569 | * enable 1 = enable, 0 = disable | |
2570 | * | |
2571 | * Return Value: 0 if success, otherwise error code | |
2572 | */ | |
2573 | static int mgsl_txenable(struct mgsl_struct * info, int enable) | |
2574 | { | |
2575 | unsigned long flags; | |
2576 | ||
2577 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2578 | printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__, | |
2579 | info->device_name, enable); | |
2580 | ||
2581 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2582 | if ( enable ) { | |
2583 | if ( !info->tx_enabled ) { | |
2584 | ||
2585 | usc_start_transmitter(info); | |
2586 | /*-------------------------------------------------- | |
2587 | * if HDLC/SDLC Loop mode, attempt to insert the | |
2588 | * station in the 'loop' by setting CMR:13. Upon | |
2589 | * receipt of the next GoAhead (RxAbort) sequence, | |
2590 | * the OnLoop indicator (CCSR:7) should go active | |
2591 | * to indicate that we are on the loop | |
2592 | *--------------------------------------------------*/ | |
2593 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) | |
2594 | usc_loopmode_insert_request( info ); | |
2595 | } | |
2596 | } else { | |
2597 | if ( info->tx_enabled ) | |
2598 | usc_stop_transmitter(info); | |
2599 | } | |
2600 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2601 | return 0; | |
2602 | ||
2603 | } /* end of mgsl_txenable() */ | |
2604 | ||
2605 | /* mgsl_txabort() abort send HDLC frame | |
2606 | * | |
2607 | * Arguments: info pointer to device instance data | |
2608 | * Return Value: 0 if success, otherwise error code | |
2609 | */ | |
2610 | static int mgsl_txabort(struct mgsl_struct * info) | |
2611 | { | |
2612 | unsigned long flags; | |
2613 | ||
2614 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2615 | printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__, | |
2616 | info->device_name); | |
2617 | ||
2618 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2619 | if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) | |
2620 | { | |
2621 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) | |
2622 | usc_loopmode_cancel_transmit( info ); | |
2623 | else | |
2624 | usc_TCmd(info,TCmd_SendAbort); | |
2625 | } | |
2626 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2627 | return 0; | |
2628 | ||
2629 | } /* end of mgsl_txabort() */ | |
2630 | ||
2631 | /* mgsl_rxenable() enable or disable the receiver | |
2632 | * | |
2633 | * Arguments: info pointer to device instance data | |
2634 | * enable 1 = enable, 0 = disable | |
2635 | * Return Value: 0 if success, otherwise error code | |
2636 | */ | |
2637 | static int mgsl_rxenable(struct mgsl_struct * info, int enable) | |
2638 | { | |
2639 | unsigned long flags; | |
2640 | ||
2641 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2642 | printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__, | |
2643 | info->device_name, enable); | |
2644 | ||
2645 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2646 | if ( enable ) { | |
2647 | if ( !info->rx_enabled ) | |
2648 | usc_start_receiver(info); | |
2649 | } else { | |
2650 | if ( info->rx_enabled ) | |
2651 | usc_stop_receiver(info); | |
2652 | } | |
2653 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2654 | return 0; | |
2655 | ||
2656 | } /* end of mgsl_rxenable() */ | |
2657 | ||
2658 | /* mgsl_wait_event() wait for specified event to occur | |
2659 | * | |
2660 | * Arguments: info pointer to device instance data | |
2661 | * mask pointer to bitmask of events to wait for | |
2662 | * Return Value: 0 if successful and bit mask updated with | |
2663 | * of events triggerred, | |
2664 | * otherwise error code | |
2665 | */ | |
2666 | static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr) | |
2667 | { | |
2668 | unsigned long flags; | |
2669 | int s; | |
2670 | int rc=0; | |
2671 | struct mgsl_icount cprev, cnow; | |
2672 | int events; | |
2673 | int mask; | |
2674 | struct _input_signal_events oldsigs, newsigs; | |
2675 | DECLARE_WAITQUEUE(wait, current); | |
2676 | ||
2677 | COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int)); | |
2678 | if (rc) { | |
2679 | return -EFAULT; | |
2680 | } | |
2681 | ||
2682 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2683 | printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__, | |
2684 | info->device_name, mask); | |
2685 | ||
2686 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2687 | ||
2688 | /* return immediately if state matches requested events */ | |
2689 | usc_get_serial_signals(info); | |
2690 | s = info->serial_signals; | |
2691 | events = mask & | |
2692 | ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) + | |
2693 | ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) + | |
2694 | ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) + | |
2695 | ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) ); | |
2696 | if (events) { | |
2697 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2698 | goto exit; | |
2699 | } | |
2700 | ||
2701 | /* save current irq counts */ | |
2702 | cprev = info->icount; | |
2703 | oldsigs = info->input_signal_events; | |
2704 | ||
2705 | /* enable hunt and idle irqs if needed */ | |
2706 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
2707 | u16 oldreg = usc_InReg(info,RICR); | |
2708 | u16 newreg = oldreg + | |
2709 | (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) + | |
2710 | (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0); | |
2711 | if (oldreg != newreg) | |
2712 | usc_OutReg(info, RICR, newreg); | |
2713 | } | |
2714 | ||
2715 | set_current_state(TASK_INTERRUPTIBLE); | |
2716 | add_wait_queue(&info->event_wait_q, &wait); | |
2717 | ||
2718 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2719 | ||
2720 | ||
2721 | for(;;) { | |
2722 | schedule(); | |
2723 | if (signal_pending(current)) { | |
2724 | rc = -ERESTARTSYS; | |
2725 | break; | |
2726 | } | |
2727 | ||
2728 | /* get current irq counts */ | |
2729 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2730 | cnow = info->icount; | |
2731 | newsigs = info->input_signal_events; | |
2732 | set_current_state(TASK_INTERRUPTIBLE); | |
2733 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2734 | ||
2735 | /* if no change, wait aborted for some reason */ | |
2736 | if (newsigs.dsr_up == oldsigs.dsr_up && | |
2737 | newsigs.dsr_down == oldsigs.dsr_down && | |
2738 | newsigs.dcd_up == oldsigs.dcd_up && | |
2739 | newsigs.dcd_down == oldsigs.dcd_down && | |
2740 | newsigs.cts_up == oldsigs.cts_up && | |
2741 | newsigs.cts_down == oldsigs.cts_down && | |
2742 | newsigs.ri_up == oldsigs.ri_up && | |
2743 | newsigs.ri_down == oldsigs.ri_down && | |
2744 | cnow.exithunt == cprev.exithunt && | |
2745 | cnow.rxidle == cprev.rxidle) { | |
2746 | rc = -EIO; | |
2747 | break; | |
2748 | } | |
2749 | ||
2750 | events = mask & | |
2751 | ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) + | |
2752 | (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) + | |
2753 | (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) + | |
2754 | (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) + | |
2755 | (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) + | |
2756 | (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) + | |
2757 | (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) + | |
2758 | (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) + | |
2759 | (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) + | |
2760 | (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) ); | |
2761 | if (events) | |
2762 | break; | |
2763 | ||
2764 | cprev = cnow; | |
2765 | oldsigs = newsigs; | |
2766 | } | |
2767 | ||
2768 | remove_wait_queue(&info->event_wait_q, &wait); | |
2769 | set_current_state(TASK_RUNNING); | |
2770 | ||
2771 | if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) { | |
2772 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2773 | if (!waitqueue_active(&info->event_wait_q)) { | |
2774 | /* disable enable exit hunt mode/idle rcvd IRQs */ | |
2775 | usc_OutReg(info, RICR, usc_InReg(info,RICR) & | |
e06922aa | 2776 | ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)); |
1da177e4 LT |
2777 | } |
2778 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2779 | } | |
2780 | exit: | |
2781 | if ( rc == 0 ) | |
2782 | PUT_USER(rc, events, mask_ptr); | |
2783 | ||
2784 | return rc; | |
2785 | ||
2786 | } /* end of mgsl_wait_event() */ | |
2787 | ||
2788 | static int modem_input_wait(struct mgsl_struct *info,int arg) | |
2789 | { | |
2790 | unsigned long flags; | |
2791 | int rc; | |
2792 | struct mgsl_icount cprev, cnow; | |
2793 | DECLARE_WAITQUEUE(wait, current); | |
2794 | ||
2795 | /* save current irq counts */ | |
2796 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2797 | cprev = info->icount; | |
2798 | add_wait_queue(&info->status_event_wait_q, &wait); | |
2799 | set_current_state(TASK_INTERRUPTIBLE); | |
2800 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2801 | ||
2802 | for(;;) { | |
2803 | schedule(); | |
2804 | if (signal_pending(current)) { | |
2805 | rc = -ERESTARTSYS; | |
2806 | break; | |
2807 | } | |
2808 | ||
2809 | /* get new irq counts */ | |
2810 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2811 | cnow = info->icount; | |
2812 | set_current_state(TASK_INTERRUPTIBLE); | |
2813 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2814 | ||
2815 | /* if no change, wait aborted for some reason */ | |
2816 | if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && | |
2817 | cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) { | |
2818 | rc = -EIO; | |
2819 | break; | |
2820 | } | |
2821 | ||
2822 | /* check for change in caller specified modem input */ | |
2823 | if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) || | |
2824 | (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) || | |
2825 | (arg & TIOCM_CD && cnow.dcd != cprev.dcd) || | |
2826 | (arg & TIOCM_CTS && cnow.cts != cprev.cts)) { | |
2827 | rc = 0; | |
2828 | break; | |
2829 | } | |
2830 | ||
2831 | cprev = cnow; | |
2832 | } | |
2833 | remove_wait_queue(&info->status_event_wait_q, &wait); | |
2834 | set_current_state(TASK_RUNNING); | |
2835 | return rc; | |
2836 | } | |
2837 | ||
2838 | /* return the state of the serial control and status signals | |
2839 | */ | |
60b33c13 | 2840 | static int tiocmget(struct tty_struct *tty) |
1da177e4 | 2841 | { |
c9f19e96 | 2842 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2843 | unsigned int result; |
2844 | unsigned long flags; | |
2845 | ||
2846 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2847 | usc_get_serial_signals(info); | |
2848 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2849 | ||
2850 | result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) + | |
2851 | ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) + | |
2852 | ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) + | |
2853 | ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) + | |
2854 | ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) + | |
2855 | ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0); | |
2856 | ||
2857 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2858 | printk("%s(%d):%s tiocmget() value=%08X\n", | |
2859 | __FILE__,__LINE__, info->device_name, result ); | |
2860 | return result; | |
2861 | } | |
2862 | ||
2863 | /* set modem control signals (DTR/RTS) | |
2864 | */ | |
20b9d177 AC |
2865 | static int tiocmset(struct tty_struct *tty, |
2866 | unsigned int set, unsigned int clear) | |
1da177e4 | 2867 | { |
c9f19e96 | 2868 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
2869 | unsigned long flags; |
2870 | ||
2871 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2872 | printk("%s(%d):%s tiocmset(%x,%x)\n", | |
2873 | __FILE__,__LINE__,info->device_name, set, clear); | |
2874 | ||
2875 | if (set & TIOCM_RTS) | |
2876 | info->serial_signals |= SerialSignal_RTS; | |
2877 | if (set & TIOCM_DTR) | |
2878 | info->serial_signals |= SerialSignal_DTR; | |
2879 | if (clear & TIOCM_RTS) | |
2880 | info->serial_signals &= ~SerialSignal_RTS; | |
2881 | if (clear & TIOCM_DTR) | |
2882 | info->serial_signals &= ~SerialSignal_DTR; | |
2883 | ||
2884 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2885 | usc_set_serial_signals(info); | |
2886 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2887 | ||
2888 | return 0; | |
2889 | } | |
2890 | ||
2891 | /* mgsl_break() Set or clear transmit break condition | |
2892 | * | |
2893 | * Arguments: tty pointer to tty instance data | |
2894 | * break_state -1=set break condition, 0=clear | |
9e98966c | 2895 | * Return Value: error code |
1da177e4 | 2896 | */ |
9e98966c | 2897 | static int mgsl_break(struct tty_struct *tty, int break_state) |
1da177e4 | 2898 | { |
c9f19e96 | 2899 | struct mgsl_struct * info = tty->driver_data; |
1da177e4 LT |
2900 | unsigned long flags; |
2901 | ||
2902 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2903 | printk("%s(%d):mgsl_break(%s,%d)\n", | |
2904 | __FILE__,__LINE__, info->device_name, break_state); | |
2905 | ||
2906 | if (mgsl_paranoia_check(info, tty->name, "mgsl_break")) | |
9e98966c | 2907 | return -EINVAL; |
1da177e4 LT |
2908 | |
2909 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2910 | if (break_state == -1) | |
2911 | usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); | |
2912 | else | |
2913 | usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); | |
2914 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
9e98966c | 2915 | return 0; |
1da177e4 LT |
2916 | |
2917 | } /* end of mgsl_break() */ | |
2918 | ||
0587102c AC |
2919 | /* |
2920 | * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) | |
2921 | * Return: write counters to the user passed counter struct | |
2922 | * NB: both 1->0 and 0->1 transitions are counted except for | |
2923 | * RI where only 0->1 is counted. | |
2924 | */ | |
2925 | static int msgl_get_icount(struct tty_struct *tty, | |
2926 | struct serial_icounter_struct *icount) | |
2927 | ||
2928 | { | |
2929 | struct mgsl_struct * info = tty->driver_data; | |
2930 | struct mgsl_icount cnow; /* kernel counter temps */ | |
2931 | unsigned long flags; | |
2932 | ||
2933 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
2934 | cnow = info->icount; | |
2935 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
2936 | ||
2937 | icount->cts = cnow.cts; | |
2938 | icount->dsr = cnow.dsr; | |
2939 | icount->rng = cnow.rng; | |
2940 | icount->dcd = cnow.dcd; | |
2941 | icount->rx = cnow.rx; | |
2942 | icount->tx = cnow.tx; | |
2943 | icount->frame = cnow.frame; | |
2944 | icount->overrun = cnow.overrun; | |
2945 | icount->parity = cnow.parity; | |
2946 | icount->brk = cnow.brk; | |
2947 | icount->buf_overrun = cnow.buf_overrun; | |
2948 | return 0; | |
2949 | } | |
2950 | ||
1da177e4 LT |
2951 | /* mgsl_ioctl() Service an IOCTL request |
2952 | * | |
2953 | * Arguments: | |
2954 | * | |
2955 | * tty pointer to tty instance data | |
1da177e4 LT |
2956 | * cmd IOCTL command code |
2957 | * arg command argument/context | |
2958 | * | |
2959 | * Return Value: 0 if success, otherwise error code | |
2960 | */ | |
6caa76b7 | 2961 | static int mgsl_ioctl(struct tty_struct *tty, |
1da177e4 LT |
2962 | unsigned int cmd, unsigned long arg) |
2963 | { | |
c9f19e96 | 2964 | struct mgsl_struct * info = tty->driver_data; |
1da177e4 LT |
2965 | |
2966 | if (debug_level >= DEBUG_LEVEL_INFO) | |
2967 | printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__, | |
2968 | info->device_name, cmd ); | |
2969 | ||
2970 | if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl")) | |
2971 | return -ENODEV; | |
2972 | ||
2973 | if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) && | |
0587102c | 2974 | (cmd != TIOCMIWAIT)) { |
1da177e4 LT |
2975 | if (tty->flags & (1 << TTY_IO_ERROR)) |
2976 | return -EIO; | |
2977 | } | |
2978 | ||
f602501d | 2979 | return mgsl_ioctl_common(info, cmd, arg); |
1da177e4 LT |
2980 | } |
2981 | ||
2982 | static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg) | |
2983 | { | |
1da177e4 | 2984 | void __user *argp = (void __user *)arg; |
1da177e4 LT |
2985 | |
2986 | switch (cmd) { | |
2987 | case MGSL_IOCGPARAMS: | |
2988 | return mgsl_get_params(info, argp); | |
2989 | case MGSL_IOCSPARAMS: | |
2990 | return mgsl_set_params(info, argp); | |
2991 | case MGSL_IOCGTXIDLE: | |
2992 | return mgsl_get_txidle(info, argp); | |
2993 | case MGSL_IOCSTXIDLE: | |
2994 | return mgsl_set_txidle(info,(int)arg); | |
2995 | case MGSL_IOCTXENABLE: | |
2996 | return mgsl_txenable(info,(int)arg); | |
2997 | case MGSL_IOCRXENABLE: | |
2998 | return mgsl_rxenable(info,(int)arg); | |
2999 | case MGSL_IOCTXABORT: | |
3000 | return mgsl_txabort(info); | |
3001 | case MGSL_IOCGSTATS: | |
3002 | return mgsl_get_stats(info, argp); | |
3003 | case MGSL_IOCWAITEVENT: | |
3004 | return mgsl_wait_event(info, argp); | |
3005 | case MGSL_IOCLOOPTXDONE: | |
3006 | return mgsl_loopmode_send_done(info); | |
3007 | /* Wait for modem input (DCD,RI,DSR,CTS) change | |
3008 | * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS) | |
3009 | */ | |
3010 | case TIOCMIWAIT: | |
3011 | return modem_input_wait(info,(int)arg); | |
3012 | ||
1da177e4 LT |
3013 | default: |
3014 | return -ENOIOCTLCMD; | |
3015 | } | |
3016 | return 0; | |
3017 | } | |
3018 | ||
3019 | /* mgsl_set_termios() | |
3020 | * | |
3021 | * Set new termios settings | |
3022 | * | |
3023 | * Arguments: | |
3024 | * | |
3025 | * tty pointer to tty structure | |
3026 | * termios pointer to buffer to hold returned old termios | |
3027 | * | |
3028 | * Return Value: None | |
3029 | */ | |
606d099c | 3030 | static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios) |
1da177e4 | 3031 | { |
c9f19e96 | 3032 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 LT |
3033 | unsigned long flags; |
3034 | ||
3035 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3036 | printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__, | |
3037 | tty->driver->name ); | |
3038 | ||
1da177e4 LT |
3039 | mgsl_change_params(info); |
3040 | ||
3041 | /* Handle transition to B0 status */ | |
3042 | if (old_termios->c_cflag & CBAUD && | |
adc8d746 | 3043 | !(tty->termios.c_cflag & CBAUD)) { |
9fe8074b | 3044 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
1da177e4 LT |
3045 | spin_lock_irqsave(&info->irq_spinlock,flags); |
3046 | usc_set_serial_signals(info); | |
3047 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
3048 | } | |
3049 | ||
3050 | /* Handle transition away from B0 status */ | |
3051 | if (!(old_termios->c_cflag & CBAUD) && | |
adc8d746 | 3052 | tty->termios.c_cflag & CBAUD) { |
1da177e4 | 3053 | info->serial_signals |= SerialSignal_DTR; |
adc8d746 | 3054 | if (!(tty->termios.c_cflag & CRTSCTS) || |
1da177e4 LT |
3055 | !test_bit(TTY_THROTTLED, &tty->flags)) { |
3056 | info->serial_signals |= SerialSignal_RTS; | |
3057 | } | |
3058 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
3059 | usc_set_serial_signals(info); | |
3060 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
3061 | } | |
3062 | ||
3063 | /* Handle turning off CRTSCTS */ | |
3064 | if (old_termios->c_cflag & CRTSCTS && | |
adc8d746 | 3065 | !(tty->termios.c_cflag & CRTSCTS)) { |
1da177e4 LT |
3066 | tty->hw_stopped = 0; |
3067 | mgsl_start(tty); | |
3068 | } | |
3069 | ||
3070 | } /* end of mgsl_set_termios() */ | |
3071 | ||
3072 | /* mgsl_close() | |
3073 | * | |
3074 | * Called when port is closed. Wait for remaining data to be | |
3075 | * sent. Disable port and free resources. | |
3076 | * | |
3077 | * Arguments: | |
3078 | * | |
3079 | * tty pointer to open tty structure | |
3080 | * filp pointer to open file object | |
3081 | * | |
3082 | * Return Value: None | |
3083 | */ | |
3084 | static void mgsl_close(struct tty_struct *tty, struct file * filp) | |
3085 | { | |
c9f19e96 | 3086 | struct mgsl_struct * info = tty->driver_data; |
1da177e4 LT |
3087 | |
3088 | if (mgsl_paranoia_check(info, tty->name, "mgsl_close")) | |
3089 | return; | |
3090 | ||
3091 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3092 | printk("%s(%d):mgsl_close(%s) entry, count=%d\n", | |
8fb06c77 | 3093 | __FILE__,__LINE__, info->device_name, info->port.count); |
1da177e4 | 3094 | |
e06922aa | 3095 | if (tty_port_close_start(&info->port, tty, filp) == 0) |
1da177e4 | 3096 | goto cleanup; |
f602501d AC |
3097 | |
3098 | mutex_lock(&info->port.mutex); | |
8fb06c77 | 3099 | if (info->port.flags & ASYNC_INITIALIZED) |
1da177e4 | 3100 | mgsl_wait_until_sent(tty, info->timeout); |
978e595f | 3101 | mgsl_flush_buffer(tty); |
1da177e4 | 3102 | tty_ldisc_flush(tty); |
1da177e4 | 3103 | shutdown(info); |
f602501d | 3104 | mutex_unlock(&info->port.mutex); |
a6614999 AC |
3105 | |
3106 | tty_port_close_end(&info->port, tty); | |
8fb06c77 | 3107 | info->port.tty = NULL; |
1da177e4 LT |
3108 | cleanup: |
3109 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3110 | printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__, | |
8fb06c77 | 3111 | tty->driver->name, info->port.count); |
1da177e4 LT |
3112 | |
3113 | } /* end of mgsl_close() */ | |
3114 | ||
3115 | /* mgsl_wait_until_sent() | |
3116 | * | |
3117 | * Wait until the transmitter is empty. | |
3118 | * | |
3119 | * Arguments: | |
3120 | * | |
3121 | * tty pointer to tty info structure | |
3122 | * timeout time to wait for send completion | |
3123 | * | |
3124 | * Return Value: None | |
3125 | */ | |
3126 | static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout) | |
3127 | { | |
c9f19e96 | 3128 | struct mgsl_struct * info = tty->driver_data; |
1da177e4 LT |
3129 | unsigned long orig_jiffies, char_time; |
3130 | ||
3131 | if (!info ) | |
3132 | return; | |
3133 | ||
3134 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3135 | printk("%s(%d):mgsl_wait_until_sent(%s) entry\n", | |
3136 | __FILE__,__LINE__, info->device_name ); | |
3137 | ||
3138 | if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent")) | |
3139 | return; | |
3140 | ||
8fb06c77 | 3141 | if (!(info->port.flags & ASYNC_INITIALIZED)) |
1da177e4 LT |
3142 | goto exit; |
3143 | ||
3144 | orig_jiffies = jiffies; | |
3145 | ||
3146 | /* Set check interval to 1/5 of estimated time to | |
3147 | * send a character, and make it at least 1. The check | |
3148 | * interval should also be less than the timeout. | |
3149 | * Note: use tight timings here to satisfy the NIST-PCTS. | |
3150 | */ | |
978e595f | 3151 | |
1da177e4 LT |
3152 | if ( info->params.data_rate ) { |
3153 | char_time = info->timeout/(32 * 5); | |
3154 | if (!char_time) | |
3155 | char_time++; | |
3156 | } else | |
3157 | char_time = 1; | |
3158 | ||
3159 | if (timeout) | |
3160 | char_time = min_t(unsigned long, char_time, timeout); | |
3161 | ||
3162 | if ( info->params.mode == MGSL_MODE_HDLC || | |
3163 | info->params.mode == MGSL_MODE_RAW ) { | |
3164 | while (info->tx_active) { | |
3165 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
3166 | if (signal_pending(current)) | |
3167 | break; | |
3168 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
3169 | break; | |
3170 | } | |
3171 | } else { | |
3172 | while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) && | |
3173 | info->tx_enabled) { | |
3174 | msleep_interruptible(jiffies_to_msecs(char_time)); | |
3175 | if (signal_pending(current)) | |
3176 | break; | |
3177 | if (timeout && time_after(jiffies, orig_jiffies + timeout)) | |
3178 | break; | |
3179 | } | |
3180 | } | |
3181 | ||
3182 | exit: | |
3183 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3184 | printk("%s(%d):mgsl_wait_until_sent(%s) exit\n", | |
3185 | __FILE__,__LINE__, info->device_name ); | |
3186 | ||
3187 | } /* end of mgsl_wait_until_sent() */ | |
3188 | ||
3189 | /* mgsl_hangup() | |
3190 | * | |
3191 | * Called by tty_hangup() when a hangup is signaled. | |
3192 | * This is the same as to closing all open files for the port. | |
3193 | * | |
3194 | * Arguments: tty pointer to associated tty object | |
3195 | * Return Value: None | |
3196 | */ | |
3197 | static void mgsl_hangup(struct tty_struct *tty) | |
3198 | { | |
c9f19e96 | 3199 | struct mgsl_struct * info = tty->driver_data; |
1da177e4 LT |
3200 | |
3201 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3202 | printk("%s(%d):mgsl_hangup(%s)\n", | |
3203 | __FILE__,__LINE__, info->device_name ); | |
3204 | ||
3205 | if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup")) | |
3206 | return; | |
3207 | ||
3208 | mgsl_flush_buffer(tty); | |
3209 | shutdown(info); | |
3210 | ||
8fb06c77 AC |
3211 | info->port.count = 0; |
3212 | info->port.flags &= ~ASYNC_NORMAL_ACTIVE; | |
3213 | info->port.tty = NULL; | |
1da177e4 | 3214 | |
8fb06c77 | 3215 | wake_up_interruptible(&info->port.open_wait); |
1da177e4 LT |
3216 | |
3217 | } /* end of mgsl_hangup() */ | |
3218 | ||
31f35939 AC |
3219 | /* |
3220 | * carrier_raised() | |
3221 | * | |
3222 | * Return true if carrier is raised | |
3223 | */ | |
3224 | ||
3225 | static int carrier_raised(struct tty_port *port) | |
3226 | { | |
3227 | unsigned long flags; | |
3228 | struct mgsl_struct *info = container_of(port, struct mgsl_struct, port); | |
3229 | ||
3230 | spin_lock_irqsave(&info->irq_spinlock, flags); | |
3231 | usc_get_serial_signals(info); | |
3232 | spin_unlock_irqrestore(&info->irq_spinlock, flags); | |
3233 | return (info->serial_signals & SerialSignal_DCD) ? 1 : 0; | |
3234 | } | |
3235 | ||
fcc8ac18 | 3236 | static void dtr_rts(struct tty_port *port, int on) |
5d951fb4 AC |
3237 | { |
3238 | struct mgsl_struct *info = container_of(port, struct mgsl_struct, port); | |
3239 | unsigned long flags; | |
3240 | ||
3241 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
fcc8ac18 | 3242 | if (on) |
9fe8074b | 3243 | info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; |
fcc8ac18 | 3244 | else |
9fe8074b | 3245 | info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR); |
5d951fb4 AC |
3246 | usc_set_serial_signals(info); |
3247 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
3248 | } | |
3249 | ||
3250 | ||
1da177e4 LT |
3251 | /* block_til_ready() |
3252 | * | |
3253 | * Block the current process until the specified port | |
3254 | * is ready to be opened. | |
3255 | * | |
3256 | * Arguments: | |
3257 | * | |
3258 | * tty pointer to tty info structure | |
3259 | * filp pointer to open file object | |
3260 | * info pointer to device instance data | |
3261 | * | |
3262 | * Return Value: 0 if success, otherwise error code | |
3263 | */ | |
3264 | static int block_til_ready(struct tty_struct *tty, struct file * filp, | |
3265 | struct mgsl_struct *info) | |
3266 | { | |
3267 | DECLARE_WAITQUEUE(wait, current); | |
3268 | int retval; | |
0fab6de0 | 3269 | bool do_clocal = false; |
1da177e4 | 3270 | unsigned long flags; |
31f35939 AC |
3271 | int dcd; |
3272 | struct tty_port *port = &info->port; | |
1da177e4 LT |
3273 | |
3274 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3275 | printk("%s(%d):block_til_ready on %s\n", | |
3276 | __FILE__,__LINE__, tty->driver->name ); | |
3277 | ||
3278 | if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){ | |
3279 | /* nonblock mode is set or port is not enabled */ | |
31f35939 | 3280 | port->flags |= ASYNC_NORMAL_ACTIVE; |
1da177e4 LT |
3281 | return 0; |
3282 | } | |
3283 | ||
adc8d746 | 3284 | if (tty->termios.c_cflag & CLOCAL) |
0fab6de0 | 3285 | do_clocal = true; |
1da177e4 LT |
3286 | |
3287 | /* Wait for carrier detect and the line to become | |
3288 | * free (i.e., not in use by the callout). While we are in | |
31f35939 | 3289 | * this loop, port->count is dropped by one, so that |
1da177e4 LT |
3290 | * mgsl_close() knows when to free things. We restore it upon |
3291 | * exit, either normal or abnormal. | |
3292 | */ | |
3293 | ||
3294 | retval = 0; | |
31f35939 | 3295 | add_wait_queue(&port->open_wait, &wait); |
1da177e4 LT |
3296 | |
3297 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3298 | printk("%s(%d):block_til_ready before block on %s count=%d\n", | |
31f35939 | 3299 | __FILE__,__LINE__, tty->driver->name, port->count ); |
1da177e4 LT |
3300 | |
3301 | spin_lock_irqsave(&info->irq_spinlock, flags); | |
e359a4e3 | 3302 | port->count--; |
1da177e4 | 3303 | spin_unlock_irqrestore(&info->irq_spinlock, flags); |
31f35939 | 3304 | port->blocked_open++; |
1da177e4 LT |
3305 | |
3306 | while (1) { | |
78c6ccca | 3307 | if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags)) |
5d951fb4 | 3308 | tty_port_raise_dtr_rts(port); |
1da177e4 LT |
3309 | |
3310 | set_current_state(TASK_INTERRUPTIBLE); | |
3311 | ||
31f35939 AC |
3312 | if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){ |
3313 | retval = (port->flags & ASYNC_HUP_NOTIFY) ? | |
1da177e4 LT |
3314 | -EAGAIN : -ERESTARTSYS; |
3315 | break; | |
3316 | } | |
fef062cb | 3317 | |
31f35939 | 3318 | dcd = tty_port_carrier_raised(&info->port); |
fef062cb PH |
3319 | if (do_clocal || dcd) |
3320 | break; | |
3321 | ||
1da177e4 LT |
3322 | if (signal_pending(current)) { |
3323 | retval = -ERESTARTSYS; | |
3324 | break; | |
3325 | } | |
3326 | ||
3327 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3328 | printk("%s(%d):block_til_ready blocking on %s count=%d\n", | |
31f35939 | 3329 | __FILE__,__LINE__, tty->driver->name, port->count ); |
1da177e4 | 3330 | |
89c8d91e | 3331 | tty_unlock(tty); |
1da177e4 | 3332 | schedule(); |
89c8d91e | 3333 | tty_lock(tty); |
1da177e4 LT |
3334 | } |
3335 | ||
3336 | set_current_state(TASK_RUNNING); | |
31f35939 | 3337 | remove_wait_queue(&port->open_wait, &wait); |
1da177e4 | 3338 | |
36c621d8 | 3339 | /* FIXME: Racy on hangup during close wait */ |
e359a4e3 | 3340 | if (!tty_hung_up_p(filp)) |
31f35939 AC |
3341 | port->count++; |
3342 | port->blocked_open--; | |
1da177e4 LT |
3343 | |
3344 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3345 | printk("%s(%d):block_til_ready after blocking on %s count=%d\n", | |
31f35939 | 3346 | __FILE__,__LINE__, tty->driver->name, port->count ); |
1da177e4 LT |
3347 | |
3348 | if (!retval) | |
31f35939 | 3349 | port->flags |= ASYNC_NORMAL_ACTIVE; |
1da177e4 LT |
3350 | |
3351 | return retval; | |
3352 | ||
3353 | } /* end of block_til_ready() */ | |
3354 | ||
8a3ad104 JS |
3355 | static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty) |
3356 | { | |
3357 | struct mgsl_struct *info; | |
3358 | int line = tty->index; | |
3359 | ||
3360 | /* verify range of specified line number */ | |
3361 | if (line >= mgsl_device_count) { | |
3362 | printk("%s(%d):mgsl_open with invalid line #%d.\n", | |
3363 | __FILE__, __LINE__, line); | |
3364 | return -ENODEV; | |
3365 | } | |
3366 | ||
3367 | /* find the info structure for the specified line */ | |
3368 | info = mgsl_device_list; | |
3369 | while (info && info->line != line) | |
3370 | info = info->next_device; | |
3371 | if (mgsl_paranoia_check(info, tty->name, "mgsl_open")) | |
3372 | return -ENODEV; | |
3373 | tty->driver_data = info; | |
3374 | ||
3375 | return tty_port_install(&info->port, driver, tty); | |
3376 | } | |
3377 | ||
1da177e4 LT |
3378 | /* mgsl_open() |
3379 | * | |
3380 | * Called when a port is opened. Init and enable port. | |
3381 | * Perform serial-specific initialization for the tty structure. | |
3382 | * | |
3383 | * Arguments: tty pointer to tty info structure | |
3384 | * filp associated file pointer | |
3385 | * | |
3386 | * Return Value: 0 if success, otherwise error code | |
3387 | */ | |
3388 | static int mgsl_open(struct tty_struct *tty, struct file * filp) | |
3389 | { | |
8a3ad104 | 3390 | struct mgsl_struct *info = tty->driver_data; |
1da177e4 | 3391 | unsigned long flags; |
8a3ad104 | 3392 | int retval; |
1da177e4 | 3393 | |
8fb06c77 | 3394 | info->port.tty = tty; |
1da177e4 LT |
3395 | |
3396 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3397 | printk("%s(%d):mgsl_open(%s), old ref count = %d\n", | |
8fb06c77 | 3398 | __FILE__,__LINE__,tty->driver->name, info->port.count); |
1da177e4 | 3399 | |
d6c53c0e | 3400 | info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0; |
1da177e4 LT |
3401 | |
3402 | spin_lock_irqsave(&info->netlock, flags); | |
3403 | if (info->netcount) { | |
3404 | retval = -EBUSY; | |
3405 | spin_unlock_irqrestore(&info->netlock, flags); | |
3406 | goto cleanup; | |
3407 | } | |
8fb06c77 | 3408 | info->port.count++; |
1da177e4 LT |
3409 | spin_unlock_irqrestore(&info->netlock, flags); |
3410 | ||
8fb06c77 | 3411 | if (info->port.count == 1) { |
1da177e4 LT |
3412 | /* 1st open on this device, init hardware */ |
3413 | retval = startup(info); | |
3414 | if (retval < 0) | |
3415 | goto cleanup; | |
3416 | } | |
3417 | ||
3418 | retval = block_til_ready(tty, filp, info); | |
3419 | if (retval) { | |
3420 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3421 | printk("%s(%d):block_til_ready(%s) returned %d\n", | |
3422 | __FILE__,__LINE__, info->device_name, retval); | |
3423 | goto cleanup; | |
3424 | } | |
3425 | ||
3426 | if (debug_level >= DEBUG_LEVEL_INFO) | |
3427 | printk("%s(%d):mgsl_open(%s) success\n", | |
3428 | __FILE__,__LINE__, info->device_name); | |
3429 | retval = 0; | |
3430 | ||
3431 | cleanup: | |
3432 | if (retval) { | |
3433 | if (tty->count == 1) | |
8fb06c77 AC |
3434 | info->port.tty = NULL; /* tty layer will release tty struct */ |
3435 | if(info->port.count) | |
3436 | info->port.count--; | |
1da177e4 LT |
3437 | } |
3438 | ||
3439 | return retval; | |
3440 | ||
3441 | } /* end of mgsl_open() */ | |
3442 | ||
3443 | /* | |
3444 | * /proc fs routines.... | |
3445 | */ | |
3446 | ||
d337829b | 3447 | static inline void line_info(struct seq_file *m, struct mgsl_struct *info) |
1da177e4 LT |
3448 | { |
3449 | char stat_buf[30]; | |
1da177e4 LT |
3450 | unsigned long flags; |
3451 | ||
3452 | if (info->bus_type == MGSL_BUS_TYPE_PCI) { | |
d337829b | 3453 | seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X", |
1da177e4 LT |
3454 | info->device_name, info->io_base, info->irq_level, |
3455 | info->phys_memory_base, info->phys_lcr_base); | |
3456 | } else { | |
d337829b | 3457 | seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d", |
1da177e4 LT |
3458 | info->device_name, info->io_base, |
3459 | info->irq_level, info->dma_level); | |
3460 | } | |
3461 | ||
3462 | /* output current serial signal states */ | |
3463 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
3464 | usc_get_serial_signals(info); | |
3465 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
3466 | ||
3467 | stat_buf[0] = 0; | |
3468 | stat_buf[1] = 0; | |
3469 | if (info->serial_signals & SerialSignal_RTS) | |
3470 | strcat(stat_buf, "|RTS"); | |
3471 | if (info->serial_signals & SerialSignal_CTS) | |
3472 | strcat(stat_buf, "|CTS"); | |
3473 | if (info->serial_signals & SerialSignal_DTR) | |
3474 | strcat(stat_buf, "|DTR"); | |
3475 | if (info->serial_signals & SerialSignal_DSR) | |
3476 | strcat(stat_buf, "|DSR"); | |
3477 | if (info->serial_signals & SerialSignal_DCD) | |
3478 | strcat(stat_buf, "|CD"); | |
3479 | if (info->serial_signals & SerialSignal_RI) | |
3480 | strcat(stat_buf, "|RI"); | |
3481 | ||
3482 | if (info->params.mode == MGSL_MODE_HDLC || | |
3483 | info->params.mode == MGSL_MODE_RAW ) { | |
d337829b | 3484 | seq_printf(m, " HDLC txok:%d rxok:%d", |
1da177e4 LT |
3485 | info->icount.txok, info->icount.rxok); |
3486 | if (info->icount.txunder) | |
d337829b | 3487 | seq_printf(m, " txunder:%d", info->icount.txunder); |
1da177e4 | 3488 | if (info->icount.txabort) |
d337829b | 3489 | seq_printf(m, " txabort:%d", info->icount.txabort); |
1da177e4 | 3490 | if (info->icount.rxshort) |
d337829b | 3491 | seq_printf(m, " rxshort:%d", info->icount.rxshort); |
1da177e4 | 3492 | if (info->icount.rxlong) |
d337829b | 3493 | seq_printf(m, " rxlong:%d", info->icount.rxlong); |
1da177e4 | 3494 | if (info->icount.rxover) |
d337829b | 3495 | seq_printf(m, " rxover:%d", info->icount.rxover); |
1da177e4 | 3496 | if (info->icount.rxcrc) |
d337829b | 3497 | seq_printf(m, " rxcrc:%d", info->icount.rxcrc); |
1da177e4 | 3498 | } else { |
d337829b | 3499 | seq_printf(m, " ASYNC tx:%d rx:%d", |
1da177e4 LT |
3500 | info->icount.tx, info->icount.rx); |
3501 | if (info->icount.frame) | |
d337829b | 3502 | seq_printf(m, " fe:%d", info->icount.frame); |
1da177e4 | 3503 | if (info->icount.parity) |
d337829b | 3504 | seq_printf(m, " pe:%d", info->icount.parity); |
1da177e4 | 3505 | if (info->icount.brk) |
d337829b | 3506 | seq_printf(m, " brk:%d", info->icount.brk); |
1da177e4 | 3507 | if (info->icount.overrun) |
d337829b | 3508 | seq_printf(m, " oe:%d", info->icount.overrun); |
1da177e4 LT |
3509 | } |
3510 | ||
3511 | /* Append serial signal status to end */ | |
d337829b | 3512 | seq_printf(m, " %s\n", stat_buf+1); |
1da177e4 | 3513 | |
d337829b | 3514 | seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n", |
1da177e4 LT |
3515 | info->tx_active,info->bh_requested,info->bh_running, |
3516 | info->pending_bh); | |
3517 | ||
3518 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
3519 | { | |
3520 | u16 Tcsr = usc_InReg( info, TCSR ); | |
3521 | u16 Tdmr = usc_InDmaReg( info, TDMR ); | |
3522 | u16 Ticr = usc_InReg( info, TICR ); | |
3523 | u16 Rscr = usc_InReg( info, RCSR ); | |
3524 | u16 Rdmr = usc_InDmaReg( info, RDMR ); | |
3525 | u16 Ricr = usc_InReg( info, RICR ); | |
3526 | u16 Icr = usc_InReg( info, ICR ); | |
3527 | u16 Dccr = usc_InReg( info, DCCR ); | |
3528 | u16 Tmr = usc_InReg( info, TMR ); | |
3529 | u16 Tccr = usc_InReg( info, TCCR ); | |
3530 | u16 Ccar = inw( info->io_base + CCAR ); | |
d337829b | 3531 | seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n" |
1da177e4 LT |
3532 | "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n", |
3533 | Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar ); | |
3534 | } | |
3535 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
d337829b | 3536 | } |
1da177e4 | 3537 | |
d337829b AD |
3538 | /* Called to print information about devices */ |
3539 | static int mgsl_proc_show(struct seq_file *m, void *v) | |
1da177e4 | 3540 | { |
1da177e4 LT |
3541 | struct mgsl_struct *info; |
3542 | ||
d337829b | 3543 | seq_printf(m, "synclink driver:%s\n", driver_version); |
1da177e4 LT |
3544 | |
3545 | info = mgsl_device_list; | |
3546 | while( info ) { | |
d337829b | 3547 | line_info(m, info); |
1da177e4 LT |
3548 | info = info->next_device; |
3549 | } | |
d337829b AD |
3550 | return 0; |
3551 | } | |
1da177e4 | 3552 | |
d337829b AD |
3553 | static int mgsl_proc_open(struct inode *inode, struct file *file) |
3554 | { | |
3555 | return single_open(file, mgsl_proc_show, NULL); | |
3556 | } | |
3557 | ||
3558 | static const struct file_operations mgsl_proc_fops = { | |
3559 | .owner = THIS_MODULE, | |
3560 | .open = mgsl_proc_open, | |
3561 | .read = seq_read, | |
3562 | .llseek = seq_lseek, | |
3563 | .release = single_release, | |
3564 | }; | |
1da177e4 LT |
3565 | |
3566 | /* mgsl_allocate_dma_buffers() | |
3567 | * | |
3568 | * Allocate and format DMA buffers (ISA adapter) | |
3569 | * or format shared memory buffers (PCI adapter). | |
3570 | * | |
3571 | * Arguments: info pointer to device instance data | |
3572 | * Return Value: 0 if success, otherwise error | |
3573 | */ | |
3574 | static int mgsl_allocate_dma_buffers(struct mgsl_struct *info) | |
3575 | { | |
3576 | unsigned short BuffersPerFrame; | |
3577 | ||
3578 | info->last_mem_alloc = 0; | |
3579 | ||
3580 | /* Calculate the number of DMA buffers necessary to hold the */ | |
3581 | /* largest allowable frame size. Note: If the max frame size is */ | |
3582 | /* not an even multiple of the DMA buffer size then we need to */ | |
3583 | /* round the buffer count per frame up one. */ | |
3584 | ||
3585 | BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE); | |
3586 | if ( info->max_frame_size % DMABUFFERSIZE ) | |
3587 | BuffersPerFrame++; | |
3588 | ||
3589 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
3590 | /* | |
3591 | * The PCI adapter has 256KBytes of shared memory to use. | |
3592 | * This is 64 PAGE_SIZE buffers. | |
3593 | * | |
3594 | * The first page is used for padding at this time so the | |
3595 | * buffer list does not begin at offset 0 of the PCI | |
3596 | * adapter's shared memory. | |
3597 | * | |
3598 | * The 2nd page is used for the buffer list. A 4K buffer | |
3599 | * list can hold 128 DMA_BUFFER structures at 32 bytes | |
3600 | * each. | |
3601 | * | |
3602 | * This leaves 62 4K pages. | |
3603 | * | |
3604 | * The next N pages are used for transmit frame(s). We | |
3605 | * reserve enough 4K page blocks to hold the required | |
3606 | * number of transmit dma buffers (num_tx_dma_buffers), | |
3607 | * each of MaxFrameSize size. | |
3608 | * | |
3609 | * Of the remaining pages (62-N), determine how many can | |
3610 | * be used to receive full MaxFrameSize inbound frames | |
3611 | */ | |
3612 | info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame; | |
3613 | info->rx_buffer_count = 62 - info->tx_buffer_count; | |
3614 | } else { | |
3615 | /* Calculate the number of PAGE_SIZE buffers needed for */ | |
3616 | /* receive and transmit DMA buffers. */ | |
3617 | ||
3618 | ||
3619 | /* Calculate the number of DMA buffers necessary to */ | |
3620 | /* hold 7 max size receive frames and one max size transmit frame. */ | |
3621 | /* The receive buffer count is bumped by one so we avoid an */ | |
3622 | /* End of List condition if all receive buffers are used when */ | |
3623 | /* using linked list DMA buffers. */ | |
3624 | ||
3625 | info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame; | |
3626 | info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6; | |
3627 | ||
3628 | /* | |
3629 | * limit total TxBuffers & RxBuffers to 62 4K total | |
3630 | * (ala PCI Allocation) | |
3631 | */ | |
3632 | ||
3633 | if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 ) | |
3634 | info->rx_buffer_count = 62 - info->tx_buffer_count; | |
3635 | ||
3636 | } | |
3637 | ||
3638 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3639 | printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n", | |
3640 | __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count); | |
3641 | ||
3642 | if ( mgsl_alloc_buffer_list_memory( info ) < 0 || | |
3643 | mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 || | |
3644 | mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 || | |
3645 | mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 || | |
3646 | mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) { | |
3647 | printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__); | |
3648 | return -ENOMEM; | |
3649 | } | |
3650 | ||
3651 | mgsl_reset_rx_dma_buffers( info ); | |
3652 | mgsl_reset_tx_dma_buffers( info ); | |
3653 | ||
3654 | return 0; | |
3655 | ||
3656 | } /* end of mgsl_allocate_dma_buffers() */ | |
3657 | ||
3658 | /* | |
3659 | * mgsl_alloc_buffer_list_memory() | |
3660 | * | |
3661 | * Allocate a common DMA buffer for use as the | |
3662 | * receive and transmit buffer lists. | |
3663 | * | |
3664 | * A buffer list is a set of buffer entries where each entry contains | |
3665 | * a pointer to an actual buffer and a pointer to the next buffer entry | |
3666 | * (plus some other info about the buffer). | |
3667 | * | |
3668 | * The buffer entries for a list are built to form a circular list so | |
3669 | * that when the entire list has been traversed you start back at the | |
3670 | * beginning. | |
3671 | * | |
3672 | * This function allocates memory for just the buffer entries. | |
3673 | * The links (pointer to next entry) are filled in with the physical | |
3674 | * address of the next entry so the adapter can navigate the list | |
3675 | * using bus master DMA. The pointers to the actual buffers are filled | |
3676 | * out later when the actual buffers are allocated. | |
3677 | * | |
3678 | * Arguments: info pointer to device instance data | |
3679 | * Return Value: 0 if success, otherwise error | |
3680 | */ | |
3681 | static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info ) | |
3682 | { | |
3683 | unsigned int i; | |
3684 | ||
3685 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
3686 | /* PCI adapter uses shared memory. */ | |
3687 | info->buffer_list = info->memory_base + info->last_mem_alloc; | |
3688 | info->buffer_list_phys = info->last_mem_alloc; | |
3689 | info->last_mem_alloc += BUFFERLISTSIZE; | |
3690 | } else { | |
3691 | /* ISA adapter uses system memory. */ | |
3692 | /* The buffer lists are allocated as a common buffer that both */ | |
3693 | /* the processor and adapter can access. This allows the driver to */ | |
3694 | /* inspect portions of the buffer while other portions are being */ | |
3695 | /* updated by the adapter using Bus Master DMA. */ | |
3696 | ||
0ff1b2c8 PF |
3697 | info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL); |
3698 | if (info->buffer_list == NULL) | |
1da177e4 | 3699 | return -ENOMEM; |
0ff1b2c8 | 3700 | info->buffer_list_phys = (u32)(info->buffer_list_dma_addr); |
1da177e4 LT |
3701 | } |
3702 | ||
3703 | /* We got the memory for the buffer entry lists. */ | |
3704 | /* Initialize the memory block to all zeros. */ | |
3705 | memset( info->buffer_list, 0, BUFFERLISTSIZE ); | |
3706 | ||
3707 | /* Save virtual address pointers to the receive and */ | |
3708 | /* transmit buffer lists. (Receive 1st). These pointers will */ | |
3709 | /* be used by the processor to access the lists. */ | |
3710 | info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list; | |
3711 | info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list; | |
3712 | info->tx_buffer_list += info->rx_buffer_count; | |
3713 | ||
3714 | /* | |
3715 | * Build the links for the buffer entry lists such that | |
3716 | * two circular lists are built. (Transmit and Receive). | |
3717 | * | |
3718 | * Note: the links are physical addresses | |
3719 | * which are read by the adapter to determine the next | |
3720 | * buffer entry to use. | |
3721 | */ | |
3722 | ||
3723 | for ( i = 0; i < info->rx_buffer_count; i++ ) { | |
3724 | /* calculate and store physical address of this buffer entry */ | |
3725 | info->rx_buffer_list[i].phys_entry = | |
3726 | info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY)); | |
3727 | ||
3728 | /* calculate and store physical address of */ | |
3729 | /* next entry in cirular list of entries */ | |
3730 | ||
3731 | info->rx_buffer_list[i].link = info->buffer_list_phys; | |
3732 | ||
3733 | if ( i < info->rx_buffer_count - 1 ) | |
3734 | info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY); | |
3735 | } | |
3736 | ||
3737 | for ( i = 0; i < info->tx_buffer_count; i++ ) { | |
3738 | /* calculate and store physical address of this buffer entry */ | |
3739 | info->tx_buffer_list[i].phys_entry = info->buffer_list_phys + | |
3740 | ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY)); | |
3741 | ||
3742 | /* calculate and store physical address of */ | |
3743 | /* next entry in cirular list of entries */ | |
3744 | ||
3745 | info->tx_buffer_list[i].link = info->buffer_list_phys + | |
3746 | info->rx_buffer_count * sizeof(DMABUFFERENTRY); | |
3747 | ||
3748 | if ( i < info->tx_buffer_count - 1 ) | |
3749 | info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY); | |
3750 | } | |
3751 | ||
3752 | return 0; | |
3753 | ||
3754 | } /* end of mgsl_alloc_buffer_list_memory() */ | |
3755 | ||
3756 | /* Free DMA buffers allocated for use as the | |
3757 | * receive and transmit buffer lists. | |
3758 | * Warning: | |
3759 | * | |
3760 | * The data transfer buffers associated with the buffer list | |
3761 | * MUST be freed before freeing the buffer list itself because | |
3762 | * the buffer list contains the information necessary to free | |
3763 | * the individual buffers! | |
3764 | */ | |
3765 | static void mgsl_free_buffer_list_memory( struct mgsl_struct *info ) | |
3766 | { | |
0ff1b2c8 PF |
3767 | if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI) |
3768 | dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr); | |
1da177e4 LT |
3769 | |
3770 | info->buffer_list = NULL; | |
3771 | info->rx_buffer_list = NULL; | |
3772 | info->tx_buffer_list = NULL; | |
3773 | ||
3774 | } /* end of mgsl_free_buffer_list_memory() */ | |
3775 | ||
3776 | /* | |
3777 | * mgsl_alloc_frame_memory() | |
3778 | * | |
3779 | * Allocate the frame DMA buffers used by the specified buffer list. | |
3780 | * Each DMA buffer will be one memory page in size. This is necessary | |
3781 | * because memory can fragment enough that it may be impossible | |
3782 | * contiguous pages. | |
3783 | * | |
3784 | * Arguments: | |
3785 | * | |
3786 | * info pointer to device instance data | |
3787 | * BufferList pointer to list of buffer entries | |
3788 | * Buffercount count of buffer entries in buffer list | |
3789 | * | |
3790 | * Return Value: 0 if success, otherwise -ENOMEM | |
3791 | */ | |
3792 | static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount) | |
3793 | { | |
3794 | int i; | |
0ff1b2c8 | 3795 | u32 phys_addr; |
1da177e4 LT |
3796 | |
3797 | /* Allocate page sized buffers for the receive buffer list */ | |
3798 | ||
3799 | for ( i = 0; i < Buffercount; i++ ) { | |
3800 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
3801 | /* PCI adapter uses shared memory buffers. */ | |
3802 | BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc; | |
3803 | phys_addr = info->last_mem_alloc; | |
3804 | info->last_mem_alloc += DMABUFFERSIZE; | |
3805 | } else { | |
3806 | /* ISA adapter uses system memory. */ | |
0ff1b2c8 PF |
3807 | BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL); |
3808 | if (BufferList[i].virt_addr == NULL) | |
1da177e4 | 3809 | return -ENOMEM; |
0ff1b2c8 | 3810 | phys_addr = (u32)(BufferList[i].dma_addr); |
1da177e4 LT |
3811 | } |
3812 | BufferList[i].phys_addr = phys_addr; | |
3813 | } | |
3814 | ||
3815 | return 0; | |
3816 | ||
3817 | } /* end of mgsl_alloc_frame_memory() */ | |
3818 | ||
3819 | /* | |
3820 | * mgsl_free_frame_memory() | |
3821 | * | |
3822 | * Free the buffers associated with | |
3823 | * each buffer entry of a buffer list. | |
3824 | * | |
3825 | * Arguments: | |
3826 | * | |
3827 | * info pointer to device instance data | |
3828 | * BufferList pointer to list of buffer entries | |
3829 | * Buffercount count of buffer entries in buffer list | |
3830 | * | |
3831 | * Return Value: None | |
3832 | */ | |
3833 | static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount) | |
3834 | { | |
3835 | int i; | |
3836 | ||
3837 | if ( BufferList ) { | |
3838 | for ( i = 0 ; i < Buffercount ; i++ ) { | |
3839 | if ( BufferList[i].virt_addr ) { | |
3840 | if ( info->bus_type != MGSL_BUS_TYPE_PCI ) | |
0ff1b2c8 | 3841 | dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr); |
1da177e4 LT |
3842 | BufferList[i].virt_addr = NULL; |
3843 | } | |
3844 | } | |
3845 | } | |
3846 | ||
3847 | } /* end of mgsl_free_frame_memory() */ | |
3848 | ||
3849 | /* mgsl_free_dma_buffers() | |
3850 | * | |
3851 | * Free DMA buffers | |
3852 | * | |
3853 | * Arguments: info pointer to device instance data | |
3854 | * Return Value: None | |
3855 | */ | |
3856 | static void mgsl_free_dma_buffers( struct mgsl_struct *info ) | |
3857 | { | |
3858 | mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count ); | |
3859 | mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count ); | |
3860 | mgsl_free_buffer_list_memory( info ); | |
3861 | ||
3862 | } /* end of mgsl_free_dma_buffers() */ | |
3863 | ||
3864 | ||
3865 | /* | |
3866 | * mgsl_alloc_intermediate_rxbuffer_memory() | |
3867 | * | |
3868 | * Allocate a buffer large enough to hold max_frame_size. This buffer | |
3869 | * is used to pass an assembled frame to the line discipline. | |
3870 | * | |
3871 | * Arguments: | |
3872 | * | |
3873 | * info pointer to device instance data | |
3874 | * | |
3875 | * Return Value: 0 if success, otherwise -ENOMEM | |
3876 | */ | |
3877 | static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info) | |
3878 | { | |
3879 | info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA); | |
3880 | if ( info->intermediate_rxbuffer == NULL ) | |
3881 | return -ENOMEM; | |
a6b68a69 PF |
3882 | /* unused flag buffer to satisfy receive_buf calling interface */ |
3883 | info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL); | |
3884 | if (!info->flag_buf) { | |
3885 | kfree(info->intermediate_rxbuffer); | |
3886 | info->intermediate_rxbuffer = NULL; | |
3887 | return -ENOMEM; | |
3888 | } | |
1da177e4 LT |
3889 | return 0; |
3890 | ||
3891 | } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */ | |
3892 | ||
3893 | /* | |
3894 | * mgsl_free_intermediate_rxbuffer_memory() | |
3895 | * | |
3896 | * | |
3897 | * Arguments: | |
3898 | * | |
3899 | * info pointer to device instance data | |
3900 | * | |
3901 | * Return Value: None | |
3902 | */ | |
3903 | static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info) | |
3904 | { | |
735d5661 | 3905 | kfree(info->intermediate_rxbuffer); |
1da177e4 | 3906 | info->intermediate_rxbuffer = NULL; |
a6b68a69 PF |
3907 | kfree(info->flag_buf); |
3908 | info->flag_buf = NULL; | |
1da177e4 LT |
3909 | |
3910 | } /* end of mgsl_free_intermediate_rxbuffer_memory() */ | |
3911 | ||
3912 | /* | |
3913 | * mgsl_alloc_intermediate_txbuffer_memory() | |
3914 | * | |
3915 | * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size. | |
3916 | * This buffer is used to load transmit frames into the adapter's dma transfer | |
3917 | * buffers when there is sufficient space. | |
3918 | * | |
3919 | * Arguments: | |
3920 | * | |
3921 | * info pointer to device instance data | |
3922 | * | |
3923 | * Return Value: 0 if success, otherwise -ENOMEM | |
3924 | */ | |
3925 | static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info) | |
3926 | { | |
3927 | int i; | |
3928 | ||
3929 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
3930 | printk("%s %s(%d) allocating %d tx holding buffers\n", | |
3931 | info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers); | |
3932 | ||
3933 | memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers)); | |
3934 | ||
3935 | for ( i=0; i<info->num_tx_holding_buffers; ++i) { | |
3936 | info->tx_holding_buffers[i].buffer = | |
3937 | kmalloc(info->max_frame_size, GFP_KERNEL); | |
d9a2f4a4 AC |
3938 | if (info->tx_holding_buffers[i].buffer == NULL) { |
3939 | for (--i; i >= 0; i--) { | |
3940 | kfree(info->tx_holding_buffers[i].buffer); | |
3941 | info->tx_holding_buffers[i].buffer = NULL; | |
3942 | } | |
1da177e4 | 3943 | return -ENOMEM; |
d9a2f4a4 | 3944 | } |
1da177e4 LT |
3945 | } |
3946 | ||
3947 | return 0; | |
3948 | ||
3949 | } /* end of mgsl_alloc_intermediate_txbuffer_memory() */ | |
3950 | ||
3951 | /* | |
3952 | * mgsl_free_intermediate_txbuffer_memory() | |
3953 | * | |
3954 | * | |
3955 | * Arguments: | |
3956 | * | |
3957 | * info pointer to device instance data | |
3958 | * | |
3959 | * Return Value: None | |
3960 | */ | |
3961 | static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info) | |
3962 | { | |
3963 | int i; | |
3964 | ||
3965 | for ( i=0; i<info->num_tx_holding_buffers; ++i ) { | |
735d5661 JJ |
3966 | kfree(info->tx_holding_buffers[i].buffer); |
3967 | info->tx_holding_buffers[i].buffer = NULL; | |
1da177e4 LT |
3968 | } |
3969 | ||
3970 | info->get_tx_holding_index = 0; | |
3971 | info->put_tx_holding_index = 0; | |
3972 | info->tx_holding_count = 0; | |
3973 | ||
3974 | } /* end of mgsl_free_intermediate_txbuffer_memory() */ | |
3975 | ||
3976 | ||
3977 | /* | |
3978 | * load_next_tx_holding_buffer() | |
3979 | * | |
3980 | * attempts to load the next buffered tx request into the | |
3981 | * tx dma buffers | |
3982 | * | |
3983 | * Arguments: | |
3984 | * | |
3985 | * info pointer to device instance data | |
3986 | * | |
0fab6de0 | 3987 | * Return Value: true if next buffered tx request loaded |
1da177e4 | 3988 | * into adapter's tx dma buffer, |
0fab6de0 | 3989 | * false otherwise |
1da177e4 | 3990 | */ |
0fab6de0 | 3991 | static bool load_next_tx_holding_buffer(struct mgsl_struct *info) |
1da177e4 | 3992 | { |
0fab6de0 | 3993 | bool ret = false; |
1da177e4 LT |
3994 | |
3995 | if ( info->tx_holding_count ) { | |
3996 | /* determine if we have enough tx dma buffers | |
3997 | * to accommodate the next tx frame | |
3998 | */ | |
3999 | struct tx_holding_buffer *ptx = | |
4000 | &info->tx_holding_buffers[info->get_tx_holding_index]; | |
4001 | int num_free = num_free_tx_dma_buffers(info); | |
4002 | int num_needed = ptx->buffer_size / DMABUFFERSIZE; | |
4003 | if ( ptx->buffer_size % DMABUFFERSIZE ) | |
4004 | ++num_needed; | |
4005 | ||
4006 | if (num_needed <= num_free) { | |
4007 | info->xmit_cnt = ptx->buffer_size; | |
4008 | mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size); | |
4009 | ||
4010 | --info->tx_holding_count; | |
4011 | if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers) | |
4012 | info->get_tx_holding_index=0; | |
4013 | ||
4014 | /* restart transmit timer */ | |
4015 | mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000)); | |
4016 | ||
0fab6de0 | 4017 | ret = true; |
1da177e4 LT |
4018 | } |
4019 | } | |
4020 | ||
4021 | return ret; | |
4022 | } | |
4023 | ||
4024 | /* | |
4025 | * save_tx_buffer_request() | |
4026 | * | |
4027 | * attempt to store transmit frame request for later transmission | |
4028 | * | |
4029 | * Arguments: | |
4030 | * | |
4031 | * info pointer to device instance data | |
4032 | * Buffer pointer to buffer containing frame to load | |
4033 | * BufferSize size in bytes of frame in Buffer | |
4034 | * | |
4035 | * Return Value: 1 if able to store, 0 otherwise | |
4036 | */ | |
4037 | static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize) | |
4038 | { | |
4039 | struct tx_holding_buffer *ptx; | |
4040 | ||
4041 | if ( info->tx_holding_count >= info->num_tx_holding_buffers ) { | |
4042 | return 0; /* all buffers in use */ | |
4043 | } | |
4044 | ||
4045 | ptx = &info->tx_holding_buffers[info->put_tx_holding_index]; | |
4046 | ptx->buffer_size = BufferSize; | |
4047 | memcpy( ptx->buffer, Buffer, BufferSize); | |
4048 | ||
4049 | ++info->tx_holding_count; | |
4050 | if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers) | |
4051 | info->put_tx_holding_index=0; | |
4052 | ||
4053 | return 1; | |
4054 | } | |
4055 | ||
4056 | static int mgsl_claim_resources(struct mgsl_struct *info) | |
4057 | { | |
4058 | if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) { | |
4059 | printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n", | |
4060 | __FILE__,__LINE__,info->device_name, info->io_base); | |
4061 | return -ENODEV; | |
4062 | } | |
0fab6de0 | 4063 | info->io_addr_requested = true; |
1da177e4 LT |
4064 | |
4065 | if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags, | |
4066 | info->device_name, info ) < 0 ) { | |
25985edc | 4067 | printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n", |
1da177e4 LT |
4068 | __FILE__,__LINE__,info->device_name, info->irq_level ); |
4069 | goto errout; | |
4070 | } | |
0fab6de0 | 4071 | info->irq_requested = true; |
1da177e4 LT |
4072 | |
4073 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
4074 | if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) { | |
4075 | printk( "%s(%d):mem addr conflict device %s Addr=%08X\n", | |
4076 | __FILE__,__LINE__,info->device_name, info->phys_memory_base); | |
4077 | goto errout; | |
4078 | } | |
0fab6de0 | 4079 | info->shared_mem_requested = true; |
1da177e4 LT |
4080 | if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) { |
4081 | printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n", | |
4082 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset); | |
4083 | goto errout; | |
4084 | } | |
0fab6de0 | 4085 | info->lcr_mem_requested = true; |
1da177e4 | 4086 | |
24cb2335 AC |
4087 | info->memory_base = ioremap_nocache(info->phys_memory_base, |
4088 | 0x40000); | |
1da177e4 | 4089 | if (!info->memory_base) { |
25985edc | 4090 | printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n", |
1da177e4 LT |
4091 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); |
4092 | goto errout; | |
4093 | } | |
4094 | ||
4095 | if ( !mgsl_memory_test(info) ) { | |
4096 | printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n", | |
4097 | __FILE__,__LINE__,info->device_name, info->phys_memory_base ); | |
4098 | goto errout; | |
4099 | } | |
4100 | ||
24cb2335 AC |
4101 | info->lcr_base = ioremap_nocache(info->phys_lcr_base, |
4102 | PAGE_SIZE); | |
1da177e4 | 4103 | if (!info->lcr_base) { |
25985edc | 4104 | printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n", |
1da177e4 LT |
4105 | __FILE__,__LINE__,info->device_name, info->phys_lcr_base ); |
4106 | goto errout; | |
4107 | } | |
24cb2335 | 4108 | info->lcr_base += info->lcr_offset; |
1da177e4 LT |
4109 | |
4110 | } else { | |
4111 | /* claim DMA channel */ | |
4112 | ||
4113 | if (request_dma(info->dma_level,info->device_name) < 0){ | |
25985edc | 4114 | printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n", |
1da177e4 LT |
4115 | __FILE__,__LINE__,info->device_name, info->dma_level ); |
4116 | mgsl_release_resources( info ); | |
4117 | return -ENODEV; | |
4118 | } | |
0fab6de0 | 4119 | info->dma_requested = true; |
1da177e4 LT |
4120 | |
4121 | /* ISA adapter uses bus master DMA */ | |
4122 | set_dma_mode(info->dma_level,DMA_MODE_CASCADE); | |
4123 | enable_dma(info->dma_level); | |
4124 | } | |
4125 | ||
4126 | if ( mgsl_allocate_dma_buffers(info) < 0 ) { | |
25985edc | 4127 | printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n", |
1da177e4 LT |
4128 | __FILE__,__LINE__,info->device_name, info->dma_level ); |
4129 | goto errout; | |
4130 | } | |
4131 | ||
4132 | return 0; | |
4133 | errout: | |
4134 | mgsl_release_resources(info); | |
4135 | return -ENODEV; | |
4136 | ||
4137 | } /* end of mgsl_claim_resources() */ | |
4138 | ||
4139 | static void mgsl_release_resources(struct mgsl_struct *info) | |
4140 | { | |
4141 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
4142 | printk( "%s(%d):mgsl_release_resources(%s) entry\n", | |
4143 | __FILE__,__LINE__,info->device_name ); | |
4144 | ||
4145 | if ( info->irq_requested ) { | |
4146 | free_irq(info->irq_level, info); | |
0fab6de0 | 4147 | info->irq_requested = false; |
1da177e4 LT |
4148 | } |
4149 | if ( info->dma_requested ) { | |
4150 | disable_dma(info->dma_level); | |
4151 | free_dma(info->dma_level); | |
0fab6de0 | 4152 | info->dma_requested = false; |
1da177e4 LT |
4153 | } |
4154 | mgsl_free_dma_buffers(info); | |
4155 | mgsl_free_intermediate_rxbuffer_memory(info); | |
4156 | mgsl_free_intermediate_txbuffer_memory(info); | |
4157 | ||
4158 | if ( info->io_addr_requested ) { | |
4159 | release_region(info->io_base,info->io_addr_size); | |
0fab6de0 | 4160 | info->io_addr_requested = false; |
1da177e4 LT |
4161 | } |
4162 | if ( info->shared_mem_requested ) { | |
4163 | release_mem_region(info->phys_memory_base,0x40000); | |
0fab6de0 | 4164 | info->shared_mem_requested = false; |
1da177e4 LT |
4165 | } |
4166 | if ( info->lcr_mem_requested ) { | |
4167 | release_mem_region(info->phys_lcr_base + info->lcr_offset,128); | |
0fab6de0 | 4168 | info->lcr_mem_requested = false; |
1da177e4 LT |
4169 | } |
4170 | if (info->memory_base){ | |
4171 | iounmap(info->memory_base); | |
4172 | info->memory_base = NULL; | |
4173 | } | |
4174 | if (info->lcr_base){ | |
4175 | iounmap(info->lcr_base - info->lcr_offset); | |
4176 | info->lcr_base = NULL; | |
4177 | } | |
4178 | ||
4179 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
4180 | printk( "%s(%d):mgsl_release_resources(%s) exit\n", | |
4181 | __FILE__,__LINE__,info->device_name ); | |
4182 | ||
4183 | } /* end of mgsl_release_resources() */ | |
4184 | ||
4185 | /* mgsl_add_device() | |
4186 | * | |
4187 | * Add the specified device instance data structure to the | |
4188 | * global linked list of devices and increment the device count. | |
4189 | * | |
4190 | * Arguments: info pointer to device instance data | |
4191 | * Return Value: None | |
4192 | */ | |
4193 | static void mgsl_add_device( struct mgsl_struct *info ) | |
4194 | { | |
4195 | info->next_device = NULL; | |
4196 | info->line = mgsl_device_count; | |
4197 | sprintf(info->device_name,"ttySL%d",info->line); | |
4198 | ||
4199 | if (info->line < MAX_TOTAL_DEVICES) { | |
4200 | if (maxframe[info->line]) | |
4201 | info->max_frame_size = maxframe[info->line]; | |
1da177e4 LT |
4202 | |
4203 | if (txdmabufs[info->line]) { | |
4204 | info->num_tx_dma_buffers = txdmabufs[info->line]; | |
4205 | if (info->num_tx_dma_buffers < 1) | |
4206 | info->num_tx_dma_buffers = 1; | |
4207 | } | |
4208 | ||
4209 | if (txholdbufs[info->line]) { | |
4210 | info->num_tx_holding_buffers = txholdbufs[info->line]; | |
4211 | if (info->num_tx_holding_buffers < 1) | |
4212 | info->num_tx_holding_buffers = 1; | |
4213 | else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS) | |
4214 | info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS; | |
4215 | } | |
4216 | } | |
4217 | ||
4218 | mgsl_device_count++; | |
4219 | ||
4220 | if ( !mgsl_device_list ) | |
4221 | mgsl_device_list = info; | |
4222 | else { | |
4223 | struct mgsl_struct *current_dev = mgsl_device_list; | |
4224 | while( current_dev->next_device ) | |
4225 | current_dev = current_dev->next_device; | |
4226 | current_dev->next_device = info; | |
4227 | } | |
4228 | ||
4229 | if ( info->max_frame_size < 4096 ) | |
4230 | info->max_frame_size = 4096; | |
4231 | else if ( info->max_frame_size > 65535 ) | |
4232 | info->max_frame_size = 65535; | |
4233 | ||
4234 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
4235 | printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n", | |
4236 | info->hw_version + 1, info->device_name, info->io_base, info->irq_level, | |
4237 | info->phys_memory_base, info->phys_lcr_base, | |
4238 | info->max_frame_size ); | |
4239 | } else { | |
4240 | printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n", | |
4241 | info->device_name, info->io_base, info->irq_level, info->dma_level, | |
4242 | info->max_frame_size ); | |
4243 | } | |
4244 | ||
af69c7f9 | 4245 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
4246 | hdlcdev_init(info); |
4247 | #endif | |
4248 | ||
4249 | } /* end of mgsl_add_device() */ | |
4250 | ||
31f35939 AC |
4251 | static const struct tty_port_operations mgsl_port_ops = { |
4252 | .carrier_raised = carrier_raised, | |
fcc8ac18 | 4253 | .dtr_rts = dtr_rts, |
31f35939 AC |
4254 | }; |
4255 | ||
4256 | ||
1da177e4 LT |
4257 | /* mgsl_allocate_device() |
4258 | * | |
4259 | * Allocate and initialize a device instance structure | |
4260 | * | |
4261 | * Arguments: none | |
4262 | * Return Value: pointer to mgsl_struct if success, otherwise NULL | |
4263 | */ | |
4264 | static struct mgsl_struct* mgsl_allocate_device(void) | |
4265 | { | |
4266 | struct mgsl_struct *info; | |
4267 | ||
dd00cc48 | 4268 | info = kzalloc(sizeof(struct mgsl_struct), |
1da177e4 LT |
4269 | GFP_KERNEL); |
4270 | ||
4271 | if (!info) { | |
4272 | printk("Error can't allocate device instance data\n"); | |
4273 | } else { | |
44b7d1b3 | 4274 | tty_port_init(&info->port); |
31f35939 | 4275 | info->port.ops = &mgsl_port_ops; |
1da177e4 | 4276 | info->magic = MGSL_MAGIC; |
c4028958 | 4277 | INIT_WORK(&info->task, mgsl_bh_handler); |
1da177e4 | 4278 | info->max_frame_size = 4096; |
44b7d1b3 AC |
4279 | info->port.close_delay = 5*HZ/10; |
4280 | info->port.closing_wait = 30*HZ; | |
1da177e4 LT |
4281 | init_waitqueue_head(&info->status_event_wait_q); |
4282 | init_waitqueue_head(&info->event_wait_q); | |
4283 | spin_lock_init(&info->irq_spinlock); | |
4284 | spin_lock_init(&info->netlock); | |
4285 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
e06922aa | 4286 | info->idle_mode = HDLC_TXIDLE_FLAGS; |
1da177e4 LT |
4287 | info->num_tx_dma_buffers = 1; |
4288 | info->num_tx_holding_buffers = 0; | |
4289 | } | |
4290 | ||
4291 | return info; | |
4292 | ||
4293 | } /* end of mgsl_allocate_device()*/ | |
4294 | ||
b68e31d0 | 4295 | static const struct tty_operations mgsl_ops = { |
8a3ad104 | 4296 | .install = mgsl_install, |
1da177e4 LT |
4297 | .open = mgsl_open, |
4298 | .close = mgsl_close, | |
4299 | .write = mgsl_write, | |
4300 | .put_char = mgsl_put_char, | |
4301 | .flush_chars = mgsl_flush_chars, | |
4302 | .write_room = mgsl_write_room, | |
4303 | .chars_in_buffer = mgsl_chars_in_buffer, | |
4304 | .flush_buffer = mgsl_flush_buffer, | |
4305 | .ioctl = mgsl_ioctl, | |
4306 | .throttle = mgsl_throttle, | |
4307 | .unthrottle = mgsl_unthrottle, | |
4308 | .send_xchar = mgsl_send_xchar, | |
4309 | .break_ctl = mgsl_break, | |
4310 | .wait_until_sent = mgsl_wait_until_sent, | |
1da177e4 LT |
4311 | .set_termios = mgsl_set_termios, |
4312 | .stop = mgsl_stop, | |
4313 | .start = mgsl_start, | |
4314 | .hangup = mgsl_hangup, | |
4315 | .tiocmget = tiocmget, | |
4316 | .tiocmset = tiocmset, | |
0587102c | 4317 | .get_icount = msgl_get_icount, |
d337829b | 4318 | .proc_fops = &mgsl_proc_fops, |
1da177e4 LT |
4319 | }; |
4320 | ||
4321 | /* | |
4322 | * perform tty device initialization | |
4323 | */ | |
4324 | static int mgsl_init_tty(void) | |
4325 | { | |
4326 | int rc; | |
4327 | ||
4328 | serial_driver = alloc_tty_driver(128); | |
4329 | if (!serial_driver) | |
4330 | return -ENOMEM; | |
4331 | ||
1da177e4 LT |
4332 | serial_driver->driver_name = "synclink"; |
4333 | serial_driver->name = "ttySL"; | |
4334 | serial_driver->major = ttymajor; | |
4335 | serial_driver->minor_start = 64; | |
4336 | serial_driver->type = TTY_DRIVER_TYPE_SERIAL; | |
4337 | serial_driver->subtype = SERIAL_TYPE_NORMAL; | |
4338 | serial_driver->init_termios = tty_std_termios; | |
4339 | serial_driver->init_termios.c_cflag = | |
4340 | B9600 | CS8 | CREAD | HUPCL | CLOCAL; | |
606d099c AC |
4341 | serial_driver->init_termios.c_ispeed = 9600; |
4342 | serial_driver->init_termios.c_ospeed = 9600; | |
1da177e4 LT |
4343 | serial_driver->flags = TTY_DRIVER_REAL_RAW; |
4344 | tty_set_operations(serial_driver, &mgsl_ops); | |
4345 | if ((rc = tty_register_driver(serial_driver)) < 0) { | |
4346 | printk("%s(%d):Couldn't register serial driver\n", | |
4347 | __FILE__,__LINE__); | |
4348 | put_tty_driver(serial_driver); | |
4349 | serial_driver = NULL; | |
4350 | return rc; | |
4351 | } | |
4352 | ||
4353 | printk("%s %s, tty major#%d\n", | |
4354 | driver_name, driver_version, | |
4355 | serial_driver->major); | |
4356 | return 0; | |
4357 | } | |
4358 | ||
4359 | /* enumerate user specified ISA adapters | |
4360 | */ | |
4361 | static void mgsl_enum_isa_devices(void) | |
4362 | { | |
4363 | struct mgsl_struct *info; | |
4364 | int i; | |
4365 | ||
4366 | /* Check for user specified ISA devices */ | |
4367 | ||
4368 | for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){ | |
4369 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
4370 | printk("ISA device specified io=%04X,irq=%d,dma=%d\n", | |
4371 | io[i], irq[i], dma[i] ); | |
4372 | ||
4373 | info = mgsl_allocate_device(); | |
4374 | if ( !info ) { | |
4375 | /* error allocating device instance data */ | |
4376 | if ( debug_level >= DEBUG_LEVEL_ERROR ) | |
4377 | printk( "can't allocate device instance data.\n"); | |
4378 | continue; | |
4379 | } | |
4380 | ||
4381 | /* Copy user configuration info to device instance data */ | |
4382 | info->io_base = (unsigned int)io[i]; | |
4383 | info->irq_level = (unsigned int)irq[i]; | |
4384 | info->irq_level = irq_canonicalize(info->irq_level); | |
4385 | info->dma_level = (unsigned int)dma[i]; | |
4386 | info->bus_type = MGSL_BUS_TYPE_ISA; | |
4387 | info->io_addr_size = 16; | |
4388 | info->irq_flags = 0; | |
4389 | ||
4390 | mgsl_add_device( info ); | |
4391 | } | |
4392 | } | |
4393 | ||
4394 | static void synclink_cleanup(void) | |
4395 | { | |
4396 | int rc; | |
4397 | struct mgsl_struct *info; | |
4398 | struct mgsl_struct *tmp; | |
4399 | ||
4400 | printk("Unloading %s: %s\n", driver_name, driver_version); | |
4401 | ||
4402 | if (serial_driver) { | |
a271ca37 GKH |
4403 | rc = tty_unregister_driver(serial_driver); |
4404 | if (rc) | |
1da177e4 LT |
4405 | printk("%s(%d) failed to unregister tty driver err=%d\n", |
4406 | __FILE__,__LINE__,rc); | |
4407 | put_tty_driver(serial_driver); | |
4408 | } | |
4409 | ||
4410 | info = mgsl_device_list; | |
4411 | while(info) { | |
af69c7f9 | 4412 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
4413 | hdlcdev_exit(info); |
4414 | #endif | |
4415 | mgsl_release_resources(info); | |
4416 | tmp = info; | |
4417 | info = info->next_device; | |
191c5f10 | 4418 | tty_port_destroy(&tmp->port); |
1da177e4 LT |
4419 | kfree(tmp); |
4420 | } | |
4421 | ||
1da177e4 LT |
4422 | if (pci_registered) |
4423 | pci_unregister_driver(&synclink_pci_driver); | |
4424 | } | |
4425 | ||
4426 | static int __init synclink_init(void) | |
4427 | { | |
4428 | int rc; | |
4429 | ||
4430 | if (break_on_load) { | |
4431 | mgsl_get_text_ptr(); | |
4432 | BREAKPOINT(); | |
4433 | } | |
4434 | ||
4435 | printk("%s %s\n", driver_name, driver_version); | |
4436 | ||
4437 | mgsl_enum_isa_devices(); | |
4438 | if ((rc = pci_register_driver(&synclink_pci_driver)) < 0) | |
4439 | printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc); | |
4440 | else | |
0fab6de0 | 4441 | pci_registered = true; |
1da177e4 LT |
4442 | |
4443 | if ((rc = mgsl_init_tty()) < 0) | |
4444 | goto error; | |
4445 | ||
4446 | return 0; | |
4447 | ||
4448 | error: | |
4449 | synclink_cleanup(); | |
4450 | return rc; | |
4451 | } | |
4452 | ||
4453 | static void __exit synclink_exit(void) | |
4454 | { | |
4455 | synclink_cleanup(); | |
4456 | } | |
4457 | ||
4458 | module_init(synclink_init); | |
4459 | module_exit(synclink_exit); | |
4460 | ||
4461 | /* | |
4462 | * usc_RTCmd() | |
4463 | * | |
4464 | * Issue a USC Receive/Transmit command to the | |
4465 | * Channel Command/Address Register (CCAR). | |
4466 | * | |
4467 | * Notes: | |
4468 | * | |
4469 | * The command is encoded in the most significant 5 bits <15..11> | |
4470 | * of the CCAR value. Bits <10..7> of the CCAR must be preserved | |
4471 | * and Bits <6..0> must be written as zeros. | |
4472 | * | |
4473 | * Arguments: | |
4474 | * | |
4475 | * info pointer to device information structure | |
4476 | * Cmd command mask (use symbolic macros) | |
4477 | * | |
4478 | * Return Value: | |
4479 | * | |
4480 | * None | |
4481 | */ | |
4482 | static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd ) | |
4483 | { | |
4484 | /* output command to CCAR in bits <15..11> */ | |
4485 | /* preserve bits <10..7>, bits <6..0> must be zero */ | |
4486 | ||
4487 | outw( Cmd + info->loopback_bits, info->io_base + CCAR ); | |
4488 | ||
4489 | /* Read to flush write to CCAR */ | |
4490 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
4491 | inw( info->io_base + CCAR ); | |
4492 | ||
4493 | } /* end of usc_RTCmd() */ | |
4494 | ||
4495 | /* | |
4496 | * usc_DmaCmd() | |
4497 | * | |
4498 | * Issue a DMA command to the DMA Command/Address Register (DCAR). | |
4499 | * | |
4500 | * Arguments: | |
4501 | * | |
4502 | * info pointer to device information structure | |
4503 | * Cmd DMA command mask (usc_DmaCmd_XX Macros) | |
4504 | * | |
4505 | * Return Value: | |
4506 | * | |
4507 | * None | |
4508 | */ | |
4509 | static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd ) | |
4510 | { | |
4511 | /* write command mask to DCAR */ | |
4512 | outw( Cmd + info->mbre_bit, info->io_base ); | |
4513 | ||
4514 | /* Read to flush write to DCAR */ | |
4515 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
4516 | inw( info->io_base ); | |
4517 | ||
4518 | } /* end of usc_DmaCmd() */ | |
4519 | ||
4520 | /* | |
4521 | * usc_OutDmaReg() | |
4522 | * | |
4523 | * Write a 16-bit value to a USC DMA register | |
4524 | * | |
4525 | * Arguments: | |
4526 | * | |
4527 | * info pointer to device info structure | |
4528 | * RegAddr register address (number) for write | |
4529 | * RegValue 16-bit value to write to register | |
4530 | * | |
4531 | * Return Value: | |
4532 | * | |
4533 | * None | |
4534 | * | |
4535 | */ | |
4536 | static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) | |
4537 | { | |
4538 | /* Note: The DCAR is located at the adapter base address */ | |
4539 | /* Note: must preserve state of BIT8 in DCAR */ | |
4540 | ||
4541 | outw( RegAddr + info->mbre_bit, info->io_base ); | |
4542 | outw( RegValue, info->io_base ); | |
4543 | ||
4544 | /* Read to flush write to DCAR */ | |
4545 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
4546 | inw( info->io_base ); | |
4547 | ||
4548 | } /* end of usc_OutDmaReg() */ | |
4549 | ||
4550 | /* | |
4551 | * usc_InDmaReg() | |
4552 | * | |
4553 | * Read a 16-bit value from a DMA register | |
4554 | * | |
4555 | * Arguments: | |
4556 | * | |
4557 | * info pointer to device info structure | |
4558 | * RegAddr register address (number) to read from | |
4559 | * | |
4560 | * Return Value: | |
4561 | * | |
4562 | * The 16-bit value read from register | |
4563 | * | |
4564 | */ | |
4565 | static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr ) | |
4566 | { | |
4567 | /* Note: The DCAR is located at the adapter base address */ | |
4568 | /* Note: must preserve state of BIT8 in DCAR */ | |
4569 | ||
4570 | outw( RegAddr + info->mbre_bit, info->io_base ); | |
4571 | return inw( info->io_base ); | |
4572 | ||
4573 | } /* end of usc_InDmaReg() */ | |
4574 | ||
4575 | /* | |
4576 | * | |
4577 | * usc_OutReg() | |
4578 | * | |
4579 | * Write a 16-bit value to a USC serial channel register | |
4580 | * | |
4581 | * Arguments: | |
4582 | * | |
4583 | * info pointer to device info structure | |
4584 | * RegAddr register address (number) to write to | |
4585 | * RegValue 16-bit value to write to register | |
4586 | * | |
4587 | * Return Value: | |
4588 | * | |
4589 | * None | |
4590 | * | |
4591 | */ | |
4592 | static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) | |
4593 | { | |
4594 | outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); | |
4595 | outw( RegValue, info->io_base + CCAR ); | |
4596 | ||
4597 | /* Read to flush write to CCAR */ | |
4598 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
4599 | inw( info->io_base + CCAR ); | |
4600 | ||
4601 | } /* end of usc_OutReg() */ | |
4602 | ||
4603 | /* | |
4604 | * usc_InReg() | |
4605 | * | |
4606 | * Reads a 16-bit value from a USC serial channel register | |
4607 | * | |
4608 | * Arguments: | |
4609 | * | |
4610 | * info pointer to device extension | |
4611 | * RegAddr register address (number) to read from | |
4612 | * | |
4613 | * Return Value: | |
4614 | * | |
4615 | * 16-bit value read from register | |
4616 | */ | |
4617 | static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr ) | |
4618 | { | |
4619 | outw( RegAddr + info->loopback_bits, info->io_base + CCAR ); | |
4620 | return inw( info->io_base + CCAR ); | |
4621 | ||
4622 | } /* end of usc_InReg() */ | |
4623 | ||
4624 | /* usc_set_sdlc_mode() | |
4625 | * | |
4626 | * Set up the adapter for SDLC DMA communications. | |
4627 | * | |
4628 | * Arguments: info pointer to device instance data | |
4629 | * Return Value: NONE | |
4630 | */ | |
4631 | static void usc_set_sdlc_mode( struct mgsl_struct *info ) | |
4632 | { | |
4633 | u16 RegValue; | |
0fab6de0 | 4634 | bool PreSL1660; |
1da177e4 LT |
4635 | |
4636 | /* | |
4637 | * determine if the IUSC on the adapter is pre-SL1660. If | |
4638 | * not, take advantage of the UnderWait feature of more | |
4639 | * modern chips. If an underrun occurs and this bit is set, | |
4640 | * the transmitter will idle the programmed idle pattern | |
4641 | * until the driver has time to service the underrun. Otherwise, | |
4642 | * the dma controller may get the cycles previously requested | |
4643 | * and begin transmitting queued tx data. | |
4644 | */ | |
4645 | usc_OutReg(info,TMCR,0x1f); | |
4646 | RegValue=usc_InReg(info,TMDR); | |
0fab6de0 | 4647 | PreSL1660 = (RegValue == IUSC_PRE_SL1660); |
1da177e4 LT |
4648 | |
4649 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) | |
4650 | { | |
4651 | /* | |
4652 | ** Channel Mode Register (CMR) | |
4653 | ** | |
4654 | ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun | |
4655 | ** <13> 0 0 = Transmit Disabled (initially) | |
4656 | ** <12> 0 1 = Consecutive Idles share common 0 | |
4657 | ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop | |
4658 | ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling | |
4659 | ** <3..0> 0110 Receiver Mode = HDLC/SDLC | |
4660 | ** | |
4661 | ** 1000 1110 0000 0110 = 0x8e06 | |
4662 | */ | |
4663 | RegValue = 0x8e06; | |
4664 | ||
4665 | /*-------------------------------------------------- | |
4666 | * ignore user options for UnderRun Actions and | |
4667 | * preambles | |
4668 | *--------------------------------------------------*/ | |
4669 | } | |
4670 | else | |
4671 | { | |
4672 | /* Channel mode Register (CMR) | |
4673 | * | |
4674 | * <15..14> 00 Tx Sub modes, Underrun Action | |
4675 | * <13> 0 1 = Send Preamble before opening flag | |
4676 | * <12> 0 1 = Consecutive Idles share common 0 | |
4677 | * <11..8> 0110 Transmitter mode = HDLC/SDLC | |
4678 | * <7..4> 0000 Rx Sub modes, addr/ctrl field handling | |
4679 | * <3..0> 0110 Receiver mode = HDLC/SDLC | |
4680 | * | |
4681 | * 0000 0110 0000 0110 = 0x0606 | |
4682 | */ | |
4683 | if (info->params.mode == MGSL_MODE_RAW) { | |
4684 | RegValue = 0x0001; /* Set Receive mode = external sync */ | |
4685 | ||
4686 | usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */ | |
4687 | (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); | |
4688 | ||
4689 | /* | |
4690 | * TxSubMode: | |
4691 | * CMR <15> 0 Don't send CRC on Tx Underrun | |
4692 | * CMR <14> x undefined | |
4693 | * CMR <13> 0 Send preamble before openning sync | |
4694 | * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength | |
4695 | * | |
4696 | * TxMode: | |
4697 | * CMR <11-8) 0100 MonoSync | |
4698 | * | |
4699 | * 0x00 0100 xxxx xxxx 04xx | |
4700 | */ | |
4701 | RegValue |= 0x0400; | |
4702 | } | |
4703 | else { | |
4704 | ||
4705 | RegValue = 0x0606; | |
4706 | ||
4707 | if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 ) | |
4708 | RegValue |= BIT14; | |
4709 | else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG ) | |
4710 | RegValue |= BIT15; | |
4711 | else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC ) | |
e06922aa | 4712 | RegValue |= BIT15 | BIT14; |
1da177e4 LT |
4713 | } |
4714 | ||
4715 | if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE ) | |
4716 | RegValue |= BIT13; | |
4717 | } | |
4718 | ||
4719 | if ( info->params.mode == MGSL_MODE_HDLC && | |
4720 | (info->params.flags & HDLC_FLAG_SHARE_ZERO) ) | |
4721 | RegValue |= BIT12; | |
4722 | ||
4723 | if ( info->params.addr_filter != 0xff ) | |
4724 | { | |
4725 | /* set up receive address filtering */ | |
4726 | usc_OutReg( info, RSR, info->params.addr_filter ); | |
4727 | RegValue |= BIT4; | |
4728 | } | |
4729 | ||
4730 | usc_OutReg( info, CMR, RegValue ); | |
4731 | info->cmr_value = RegValue; | |
4732 | ||
4733 | /* Receiver mode Register (RMR) | |
4734 | * | |
4735 | * <15..13> 000 encoding | |
4736 | * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1) | |
4737 | * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC) | |
4738 | * <9> 0 1 = Include Receive chars in CRC | |
4739 | * <8> 1 1 = Use Abort/PE bit as abort indicator | |
4740 | * <7..6> 00 Even parity | |
4741 | * <5> 0 parity disabled | |
4742 | * <4..2> 000 Receive Char Length = 8 bits | |
4743 | * <1..0> 00 Disable Receiver | |
4744 | * | |
4745 | * 0000 0101 0000 0000 = 0x0500 | |
4746 | */ | |
4747 | ||
4748 | RegValue = 0x0500; | |
4749 | ||
4750 | switch ( info->params.encoding ) { | |
4751 | case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; | |
4752 | case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; | |
e06922aa | 4753 | case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; |
1da177e4 | 4754 | case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; |
e06922aa AJ |
4755 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; |
4756 | case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; | |
4757 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; | |
1da177e4 LT |
4758 | } |
4759 | ||
4760 | if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT ) | |
4761 | RegValue |= BIT9; | |
4762 | else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT ) | |
4763 | RegValue |= ( BIT12 | BIT10 | BIT9 ); | |
4764 | ||
4765 | usc_OutReg( info, RMR, RegValue ); | |
4766 | ||
4767 | /* Set the Receive count Limit Register (RCLR) to 0xffff. */ | |
4768 | /* When an opening flag of an SDLC frame is recognized the */ | |
4769 | /* Receive Character count (RCC) is loaded with the value in */ | |
4770 | /* RCLR. The RCC is decremented for each received byte. The */ | |
4771 | /* value of RCC is stored after the closing flag of the frame */ | |
4772 | /* allowing the frame size to be computed. */ | |
4773 | ||
4774 | usc_OutReg( info, RCLR, RCLRVALUE ); | |
4775 | ||
4776 | usc_RCmd( info, RCmd_SelectRicrdma_level ); | |
4777 | ||
4778 | /* Receive Interrupt Control Register (RICR) | |
4779 | * | |
4780 | * <15..8> ? RxFIFO DMA Request Level | |
4781 | * <7> 0 Exited Hunt IA (Interrupt Arm) | |
4782 | * <6> 0 Idle Received IA | |
4783 | * <5> 0 Break/Abort IA | |
4784 | * <4> 0 Rx Bound IA | |
4785 | * <3> 1 Queued status reflects oldest 2 bytes in FIFO | |
4786 | * <2> 0 Abort/PE IA | |
4787 | * <1> 1 Rx Overrun IA | |
4788 | * <0> 0 Select TC0 value for readback | |
4789 | * | |
4790 | * 0000 0000 0000 1000 = 0x000a | |
4791 | */ | |
4792 | ||
4793 | /* Carry over the Exit Hunt and Idle Received bits */ | |
4794 | /* in case they have been armed by usc_ArmEvents. */ | |
4795 | ||
4796 | RegValue = usc_InReg( info, RICR ) & 0xc0; | |
4797 | ||
4798 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
4799 | usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); | |
4800 | else | |
4801 | usc_OutReg( info, RICR, (u16)(0x140a | RegValue) ); | |
4802 | ||
4803 | /* Unlatch all Rx status bits and clear Rx status IRQ Pending */ | |
4804 | ||
4805 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); | |
4806 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); | |
4807 | ||
4808 | /* Transmit mode Register (TMR) | |
4809 | * | |
4810 | * <15..13> 000 encoding | |
4811 | * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1) | |
4812 | * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC) | |
4813 | * <9> 0 1 = Tx CRC Enabled | |
4814 | * <8> 0 1 = Append CRC to end of transmit frame | |
4815 | * <7..6> 00 Transmit parity Even | |
4816 | * <5> 0 Transmit parity Disabled | |
4817 | * <4..2> 000 Tx Char Length = 8 bits | |
4818 | * <1..0> 00 Disable Transmitter | |
4819 | * | |
4820 | * 0000 0100 0000 0000 = 0x0400 | |
4821 | */ | |
4822 | ||
4823 | RegValue = 0x0400; | |
4824 | ||
4825 | switch ( info->params.encoding ) { | |
4826 | case HDLC_ENCODING_NRZB: RegValue |= BIT13; break; | |
4827 | case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break; | |
e06922aa | 4828 | case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 | BIT13; break; |
1da177e4 | 4829 | case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; |
e06922aa AJ |
4830 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; |
4831 | case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; | |
4832 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break; | |
1da177e4 LT |
4833 | } |
4834 | ||
4835 | if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT ) | |
e06922aa | 4836 | RegValue |= BIT9 | BIT8; |
1da177e4 LT |
4837 | else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT ) |
4838 | RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); | |
4839 | ||
4840 | usc_OutReg( info, TMR, RegValue ); | |
4841 | ||
4842 | usc_set_txidle( info ); | |
4843 | ||
4844 | ||
4845 | usc_TCmd( info, TCmd_SelectTicrdma_level ); | |
4846 | ||
4847 | /* Transmit Interrupt Control Register (TICR) | |
4848 | * | |
4849 | * <15..8> ? Transmit FIFO DMA Level | |
4850 | * <7> 0 Present IA (Interrupt Arm) | |
4851 | * <6> 0 Idle Sent IA | |
4852 | * <5> 1 Abort Sent IA | |
4853 | * <4> 1 EOF/EOM Sent IA | |
4854 | * <3> 0 CRC Sent IA | |
4855 | * <2> 1 1 = Wait for SW Trigger to Start Frame | |
4856 | * <1> 1 Tx Underrun IA | |
4857 | * <0> 0 TC0 constant on read back | |
4858 | * | |
4859 | * 0000 0000 0011 0110 = 0x0036 | |
4860 | */ | |
4861 | ||
4862 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
4863 | usc_OutReg( info, TICR, 0x0736 ); | |
4864 | else | |
4865 | usc_OutReg( info, TICR, 0x1436 ); | |
4866 | ||
4867 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); | |
4868 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); | |
4869 | ||
4870 | /* | |
4871 | ** Transmit Command/Status Register (TCSR) | |
4872 | ** | |
4873 | ** <15..12> 0000 TCmd | |
4874 | ** <11> 0/1 UnderWait | |
4875 | ** <10..08> 000 TxIdle | |
4876 | ** <7> x PreSent | |
4877 | ** <6> x IdleSent | |
4878 | ** <5> x AbortSent | |
4879 | ** <4> x EOF/EOM Sent | |
4880 | ** <3> x CRC Sent | |
4881 | ** <2> x All Sent | |
4882 | ** <1> x TxUnder | |
4883 | ** <0> x TxEmpty | |
4884 | ** | |
4885 | ** 0000 0000 0000 0000 = 0x0000 | |
4886 | */ | |
4887 | info->tcsr_value = 0; | |
4888 | ||
4889 | if ( !PreSL1660 ) | |
4890 | info->tcsr_value |= TCSR_UNDERWAIT; | |
4891 | ||
4892 | usc_OutReg( info, TCSR, info->tcsr_value ); | |
4893 | ||
4894 | /* Clock mode Control Register (CMCR) | |
4895 | * | |
4896 | * <15..14> 00 counter 1 Source = Disabled | |
4897 | * <13..12> 00 counter 0 Source = Disabled | |
4898 | * <11..10> 11 BRG1 Input is TxC Pin | |
4899 | * <9..8> 11 BRG0 Input is TxC Pin | |
4900 | * <7..6> 01 DPLL Input is BRG1 Output | |
4901 | * <5..3> XXX TxCLK comes from Port 0 | |
4902 | * <2..0> XXX RxCLK comes from Port 1 | |
4903 | * | |
4904 | * 0000 1111 0111 0111 = 0x0f77 | |
4905 | */ | |
4906 | ||
4907 | RegValue = 0x0f40; | |
4908 | ||
4909 | if ( info->params.flags & HDLC_FLAG_RXC_DPLL ) | |
4910 | RegValue |= 0x0003; /* RxCLK from DPLL */ | |
4911 | else if ( info->params.flags & HDLC_FLAG_RXC_BRG ) | |
4912 | RegValue |= 0x0004; /* RxCLK from BRG0 */ | |
4913 | else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN) | |
4914 | RegValue |= 0x0006; /* RxCLK from TXC Input */ | |
4915 | else | |
4916 | RegValue |= 0x0007; /* RxCLK from Port1 */ | |
4917 | ||
4918 | if ( info->params.flags & HDLC_FLAG_TXC_DPLL ) | |
4919 | RegValue |= 0x0018; /* TxCLK from DPLL */ | |
4920 | else if ( info->params.flags & HDLC_FLAG_TXC_BRG ) | |
4921 | RegValue |= 0x0020; /* TxCLK from BRG0 */ | |
4922 | else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN) | |
4923 | RegValue |= 0x0038; /* RxCLK from TXC Input */ | |
4924 | else | |
4925 | RegValue |= 0x0030; /* TxCLK from Port0 */ | |
4926 | ||
4927 | usc_OutReg( info, CMCR, RegValue ); | |
4928 | ||
4929 | ||
4930 | /* Hardware Configuration Register (HCR) | |
4931 | * | |
4932 | * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4 | |
4933 | * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div | |
4934 | * <12> 0 CVOK:0=report code violation in biphase | |
4935 | * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4 | |
4936 | * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level | |
4937 | * <7..6> 00 reserved | |
4938 | * <5> 0 BRG1 mode:0=continuous,1=single cycle | |
4939 | * <4> X BRG1 Enable | |
4940 | * <3..2> 00 reserved | |
4941 | * <1> 0 BRG0 mode:0=continuous,1=single cycle | |
4942 | * <0> 0 BRG0 Enable | |
4943 | */ | |
4944 | ||
4945 | RegValue = 0x0000; | |
4946 | ||
e06922aa | 4947 | if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) { |
1da177e4 LT |
4948 | u32 XtalSpeed; |
4949 | u32 DpllDivisor; | |
4950 | u16 Tc; | |
4951 | ||
4952 | /* DPLL is enabled. Use BRG1 to provide continuous reference clock */ | |
4953 | /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */ | |
4954 | ||
4955 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
4956 | XtalSpeed = 11059200; | |
4957 | else | |
4958 | XtalSpeed = 14745600; | |
4959 | ||
4960 | if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) { | |
4961 | DpllDivisor = 16; | |
4962 | RegValue |= BIT10; | |
4963 | } | |
4964 | else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) { | |
4965 | DpllDivisor = 8; | |
4966 | RegValue |= BIT11; | |
4967 | } | |
4968 | else | |
4969 | DpllDivisor = 32; | |
4970 | ||
4971 | /* Tc = (Xtal/Speed) - 1 */ | |
4972 | /* If twice the remainder of (Xtal/Speed) is greater than Speed */ | |
4973 | /* then rounding up gives a more precise time constant. Instead */ | |
4974 | /* of rounding up and then subtracting 1 we just don't subtract */ | |
4975 | /* the one in this case. */ | |
4976 | ||
4977 | /*-------------------------------------------------- | |
4978 | * ejz: for DPLL mode, application should use the | |
4979 | * same clock speed as the partner system, even | |
4980 | * though clocking is derived from the input RxData. | |
4981 | * In case the user uses a 0 for the clock speed, | |
4982 | * default to 0xffffffff and don't try to divide by | |
4983 | * zero | |
4984 | *--------------------------------------------------*/ | |
4985 | if ( info->params.clock_speed ) | |
4986 | { | |
4987 | Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed); | |
4988 | if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2) | |
4989 | / info->params.clock_speed) ) | |
4990 | Tc--; | |
4991 | } | |
4992 | else | |
4993 | Tc = -1; | |
4994 | ||
4995 | ||
4996 | /* Write 16-bit Time Constant for BRG1 */ | |
4997 | usc_OutReg( info, TC1R, Tc ); | |
4998 | ||
4999 | RegValue |= BIT4; /* enable BRG1 */ | |
5000 | ||
5001 | switch ( info->params.encoding ) { | |
5002 | case HDLC_ENCODING_NRZ: | |
5003 | case HDLC_ENCODING_NRZB: | |
5004 | case HDLC_ENCODING_NRZI_MARK: | |
5005 | case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; | |
5006 | case HDLC_ENCODING_BIPHASE_MARK: | |
5007 | case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break; | |
5008 | case HDLC_ENCODING_BIPHASE_LEVEL: | |
e06922aa | 5009 | case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; |
1da177e4 LT |
5010 | } |
5011 | } | |
5012 | ||
5013 | usc_OutReg( info, HCR, RegValue ); | |
5014 | ||
5015 | ||
5016 | /* Channel Control/status Register (CCSR) | |
5017 | * | |
5018 | * <15> X RCC FIFO Overflow status (RO) | |
5019 | * <14> X RCC FIFO Not Empty status (RO) | |
5020 | * <13> 0 1 = Clear RCC FIFO (WO) | |
5021 | * <12> X DPLL Sync (RW) | |
5022 | * <11> X DPLL 2 Missed Clocks status (RO) | |
5023 | * <10> X DPLL 1 Missed Clock status (RO) | |
5024 | * <9..8> 00 DPLL Resync on rising and falling edges (RW) | |
5025 | * <7> X SDLC Loop On status (RO) | |
5026 | * <6> X SDLC Loop Send status (RO) | |
5027 | * <5> 1 Bypass counters for TxClk and RxClk (RW) | |
5028 | * <4..2> 000 Last Char of SDLC frame has 8 bits (RW) | |
5029 | * <1..0> 00 reserved | |
5030 | * | |
5031 | * 0000 0000 0010 0000 = 0x0020 | |
5032 | */ | |
5033 | ||
5034 | usc_OutReg( info, CCSR, 0x1020 ); | |
5035 | ||
5036 | ||
5037 | if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) { | |
5038 | usc_OutReg( info, SICR, | |
5039 | (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) ); | |
5040 | } | |
5041 | ||
5042 | ||
5043 | /* enable Master Interrupt Enable bit (MIE) */ | |
5044 | usc_EnableMasterIrqBit( info ); | |
5045 | ||
e06922aa AJ |
5046 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA | |
5047 | TRANSMIT_STATUS | TRANSMIT_DATA | MISC); | |
1da177e4 LT |
5048 | |
5049 | /* arm RCC underflow interrupt */ | |
5050 | usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); | |
5051 | usc_EnableInterrupts(info, MISC); | |
5052 | ||
5053 | info->mbre_bit = 0; | |
5054 | outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */ | |
5055 | usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */ | |
5056 | info->mbre_bit = BIT8; | |
5057 | outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */ | |
5058 | ||
5059 | if (info->bus_type == MGSL_BUS_TYPE_ISA) { | |
5060 | /* Enable DMAEN (Port 7, Bit 14) */ | |
5061 | /* This connects the DMA request signal to the ISA bus */ | |
5062 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14)); | |
5063 | } | |
5064 | ||
5065 | /* DMA Control Register (DCR) | |
5066 | * | |
5067 | * <15..14> 10 Priority mode = Alternating Tx/Rx | |
5068 | * 01 Rx has priority | |
5069 | * 00 Tx has priority | |
5070 | * | |
5071 | * <13> 1 Enable Priority Preempt per DCR<15..14> | |
5072 | * (WARNING DCR<11..10> must be 00 when this is 1) | |
5073 | * 0 Choose activate channel per DCR<11..10> | |
5074 | * | |
5075 | * <12> 0 Little Endian for Array/List | |
5076 | * <11..10> 00 Both Channels can use each bus grant | |
5077 | * <9..6> 0000 reserved | |
5078 | * <5> 0 7 CLK - Minimum Bus Re-request Interval | |
5079 | * <4> 0 1 = drive D/C and S/D pins | |
5080 | * <3> 1 1 = Add one wait state to all DMA cycles. | |
5081 | * <2> 0 1 = Strobe /UAS on every transfer. | |
5082 | * <1..0> 11 Addr incrementing only affects LS24 bits | |
5083 | * | |
5084 | * 0110 0000 0000 1011 = 0x600b | |
5085 | */ | |
5086 | ||
5087 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
5088 | /* PCI adapter does not need DMA wait state */ | |
5089 | usc_OutDmaReg( info, DCR, 0xa00b ); | |
5090 | } | |
5091 | else | |
5092 | usc_OutDmaReg( info, DCR, 0x800b ); | |
5093 | ||
5094 | ||
5095 | /* Receive DMA mode Register (RDMR) | |
5096 | * | |
5097 | * <15..14> 11 DMA mode = Linked List Buffer mode | |
5098 | * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry | |
5099 | * <12> 1 Clear count of List Entry after fetching | |
5100 | * <11..10> 00 Address mode = Increment | |
5101 | * <9> 1 Terminate Buffer on RxBound | |
5102 | * <8> 0 Bus Width = 16bits | |
5103 | * <7..0> ? status Bits (write as 0s) | |
5104 | * | |
5105 | * 1111 0010 0000 0000 = 0xf200 | |
5106 | */ | |
5107 | ||
5108 | usc_OutDmaReg( info, RDMR, 0xf200 ); | |
5109 | ||
5110 | ||
5111 | /* Transmit DMA mode Register (TDMR) | |
5112 | * | |
5113 | * <15..14> 11 DMA mode = Linked List Buffer mode | |
5114 | * <13> 1 TCBinA/L = fetch Tx Control Block from List entry | |
5115 | * <12> 1 Clear count of List Entry after fetching | |
5116 | * <11..10> 00 Address mode = Increment | |
5117 | * <9> 1 Terminate Buffer on end of frame | |
5118 | * <8> 0 Bus Width = 16bits | |
5119 | * <7..0> ? status Bits (Read Only so write as 0) | |
5120 | * | |
5121 | * 1111 0010 0000 0000 = 0xf200 | |
5122 | */ | |
5123 | ||
5124 | usc_OutDmaReg( info, TDMR, 0xf200 ); | |
5125 | ||
5126 | ||
5127 | /* DMA Interrupt Control Register (DICR) | |
5128 | * | |
5129 | * <15> 1 DMA Interrupt Enable | |
5130 | * <14> 0 1 = Disable IEO from USC | |
5131 | * <13> 0 1 = Don't provide vector during IntAck | |
5132 | * <12> 1 1 = Include status in Vector | |
5133 | * <10..2> 0 reserved, Must be 0s | |
5134 | * <1> 0 1 = Rx DMA Interrupt Enabled | |
5135 | * <0> 0 1 = Tx DMA Interrupt Enabled | |
5136 | * | |
5137 | * 1001 0000 0000 0000 = 0x9000 | |
5138 | */ | |
5139 | ||
5140 | usc_OutDmaReg( info, DICR, 0x9000 ); | |
5141 | ||
5142 | usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */ | |
5143 | usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */ | |
5144 | usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */ | |
5145 | ||
5146 | /* Channel Control Register (CCR) | |
5147 | * | |
5148 | * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs) | |
5149 | * <13> 0 Trigger Tx on SW Command Disabled | |
5150 | * <12> 0 Flag Preamble Disabled | |
5151 | * <11..10> 00 Preamble Length | |
5152 | * <9..8> 00 Preamble Pattern | |
5153 | * <7..6> 10 Use 32-bit Rx status Blocks (RSBs) | |
5154 | * <5> 0 Trigger Rx on SW Command Disabled | |
5155 | * <4..0> 0 reserved | |
5156 | * | |
5157 | * 1000 0000 1000 0000 = 0x8080 | |
5158 | */ | |
5159 | ||
5160 | RegValue = 0x8080; | |
5161 | ||
5162 | switch ( info->params.preamble_length ) { | |
5163 | case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; | |
5164 | case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; | |
e06922aa | 5165 | case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; |
1da177e4 LT |
5166 | } |
5167 | ||
5168 | switch ( info->params.preamble ) { | |
e06922aa | 5169 | case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break; |
1da177e4 LT |
5170 | case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break; |
5171 | case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break; | |
e06922aa | 5172 | case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break; |
1da177e4 LT |
5173 | } |
5174 | ||
5175 | usc_OutReg( info, CCR, RegValue ); | |
5176 | ||
5177 | ||
5178 | /* | |
5179 | * Burst/Dwell Control Register | |
5180 | * | |
5181 | * <15..8> 0x20 Maximum number of transfers per bus grant | |
5182 | * <7..0> 0x00 Maximum number of clock cycles per bus grant | |
5183 | */ | |
5184 | ||
5185 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
5186 | /* don't limit bus occupancy on PCI adapter */ | |
5187 | usc_OutDmaReg( info, BDCR, 0x0000 ); | |
5188 | } | |
5189 | else | |
5190 | usc_OutDmaReg( info, BDCR, 0x2000 ); | |
5191 | ||
5192 | usc_stop_transmitter(info); | |
5193 | usc_stop_receiver(info); | |
5194 | ||
5195 | } /* end of usc_set_sdlc_mode() */ | |
5196 | ||
5197 | /* usc_enable_loopback() | |
5198 | * | |
5199 | * Set the 16C32 for internal loopback mode. | |
5200 | * The TxCLK and RxCLK signals are generated from the BRG0 and | |
5201 | * the TxD is looped back to the RxD internally. | |
5202 | * | |
5203 | * Arguments: info pointer to device instance data | |
5204 | * enable 1 = enable loopback, 0 = disable | |
5205 | * Return Value: None | |
5206 | */ | |
5207 | static void usc_enable_loopback(struct mgsl_struct *info, int enable) | |
5208 | { | |
5209 | if (enable) { | |
5210 | /* blank external TXD output */ | |
e06922aa | 5211 | usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); |
1da177e4 LT |
5212 | |
5213 | /* Clock mode Control Register (CMCR) | |
5214 | * | |
5215 | * <15..14> 00 counter 1 Disabled | |
5216 | * <13..12> 00 counter 0 Disabled | |
5217 | * <11..10> 11 BRG1 Input is TxC Pin | |
5218 | * <9..8> 11 BRG0 Input is TxC Pin | |
5219 | * <7..6> 01 DPLL Input is BRG1 Output | |
5220 | * <5..3> 100 TxCLK comes from BRG0 | |
5221 | * <2..0> 100 RxCLK comes from BRG0 | |
5222 | * | |
5223 | * 0000 1111 0110 0100 = 0x0f64 | |
5224 | */ | |
5225 | ||
5226 | usc_OutReg( info, CMCR, 0x0f64 ); | |
5227 | ||
5228 | /* Write 16-bit Time Constant for BRG0 */ | |
5229 | /* use clock speed if available, otherwise use 8 for diagnostics */ | |
5230 | if (info->params.clock_speed) { | |
5231 | if (info->bus_type == MGSL_BUS_TYPE_PCI) | |
5232 | usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1)); | |
5233 | else | |
5234 | usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1)); | |
5235 | } else | |
5236 | usc_OutReg(info, TC0R, (u16)8); | |
5237 | ||
5238 | /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0 | |
5239 | mode = Continuous Set Bit 0 to enable BRG0. */ | |
5240 | usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); | |
5241 | ||
5242 | /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */ | |
5243 | usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004)); | |
5244 | ||
5245 | /* set Internal Data loopback mode */ | |
5246 | info->loopback_bits = 0x300; | |
5247 | outw( 0x0300, info->io_base + CCAR ); | |
5248 | } else { | |
5249 | /* enable external TXD output */ | |
e06922aa | 5250 | usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); |
1da177e4 LT |
5251 | |
5252 | /* clear Internal Data loopback mode */ | |
5253 | info->loopback_bits = 0; | |
5254 | outw( 0,info->io_base + CCAR ); | |
5255 | } | |
5256 | ||
5257 | } /* end of usc_enable_loopback() */ | |
5258 | ||
5259 | /* usc_enable_aux_clock() | |
5260 | * | |
5261 | * Enabled the AUX clock output at the specified frequency. | |
5262 | * | |
5263 | * Arguments: | |
5264 | * | |
5265 | * info pointer to device extension | |
5266 | * data_rate data rate of clock in bits per second | |
5267 | * A data rate of 0 disables the AUX clock. | |
5268 | * | |
5269 | * Return Value: None | |
5270 | */ | |
5271 | static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate ) | |
5272 | { | |
5273 | u32 XtalSpeed; | |
5274 | u16 Tc; | |
5275 | ||
5276 | if ( data_rate ) { | |
5277 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
5278 | XtalSpeed = 11059200; | |
5279 | else | |
5280 | XtalSpeed = 14745600; | |
5281 | ||
5282 | ||
5283 | /* Tc = (Xtal/Speed) - 1 */ | |
5284 | /* If twice the remainder of (Xtal/Speed) is greater than Speed */ | |
5285 | /* then rounding up gives a more precise time constant. Instead */ | |
5286 | /* of rounding up and then subtracting 1 we just don't subtract */ | |
5287 | /* the one in this case. */ | |
5288 | ||
5289 | ||
5290 | Tc = (u16)(XtalSpeed/data_rate); | |
5291 | if ( !(((XtalSpeed % data_rate) * 2) / data_rate) ) | |
5292 | Tc--; | |
5293 | ||
5294 | /* Write 16-bit Time Constant for BRG0 */ | |
5295 | usc_OutReg( info, TC0R, Tc ); | |
5296 | ||
5297 | /* | |
5298 | * Hardware Configuration Register (HCR) | |
5299 | * Clear Bit 1, BRG0 mode = Continuous | |
5300 | * Set Bit 0 to enable BRG0. | |
5301 | */ | |
5302 | ||
5303 | usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); | |
5304 | ||
5305 | /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */ | |
5306 | usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); | |
5307 | } else { | |
5308 | /* data rate == 0 so turn off BRG0 */ | |
5309 | usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); | |
5310 | } | |
5311 | ||
5312 | } /* end of usc_enable_aux_clock() */ | |
5313 | ||
5314 | /* | |
5315 | * | |
5316 | * usc_process_rxoverrun_sync() | |
5317 | * | |
5318 | * This function processes a receive overrun by resetting the | |
5319 | * receive DMA buffers and issuing a Purge Rx FIFO command | |
5320 | * to allow the receiver to continue receiving. | |
5321 | * | |
5322 | * Arguments: | |
5323 | * | |
5324 | * info pointer to device extension | |
5325 | * | |
5326 | * Return Value: None | |
5327 | */ | |
5328 | static void usc_process_rxoverrun_sync( struct mgsl_struct *info ) | |
5329 | { | |
5330 | int start_index; | |
5331 | int end_index; | |
5332 | int frame_start_index; | |
0fab6de0 JP |
5333 | bool start_of_frame_found = false; |
5334 | bool end_of_frame_found = false; | |
5335 | bool reprogram_dma = false; | |
1da177e4 LT |
5336 | |
5337 | DMABUFFERENTRY *buffer_list = info->rx_buffer_list; | |
5338 | u32 phys_addr; | |
5339 | ||
5340 | usc_DmaCmd( info, DmaCmd_PauseRxChannel ); | |
5341 | usc_RCmd( info, RCmd_EnterHuntmode ); | |
5342 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | |
5343 | ||
5344 | /* CurrentRxBuffer points to the 1st buffer of the next */ | |
5345 | /* possibly available receive frame. */ | |
5346 | ||
5347 | frame_start_index = start_index = end_index = info->current_rx_buffer; | |
5348 | ||
5349 | /* Search for an unfinished string of buffers. This means */ | |
5350 | /* that a receive frame started (at least one buffer with */ | |
5351 | /* count set to zero) but there is no terminiting buffer */ | |
5352 | /* (status set to non-zero). */ | |
5353 | ||
5354 | while( !buffer_list[end_index].count ) | |
5355 | { | |
5356 | /* Count field has been reset to zero by 16C32. */ | |
5357 | /* This buffer is currently in use. */ | |
5358 | ||
5359 | if ( !start_of_frame_found ) | |
5360 | { | |
0fab6de0 | 5361 | start_of_frame_found = true; |
1da177e4 | 5362 | frame_start_index = end_index; |
0fab6de0 | 5363 | end_of_frame_found = false; |
1da177e4 LT |
5364 | } |
5365 | ||
5366 | if ( buffer_list[end_index].status ) | |
5367 | { | |
5368 | /* Status field has been set by 16C32. */ | |
5369 | /* This is the last buffer of a received frame. */ | |
5370 | ||
5371 | /* We want to leave the buffers for this frame intact. */ | |
5372 | /* Move on to next possible frame. */ | |
5373 | ||
0fab6de0 JP |
5374 | start_of_frame_found = false; |
5375 | end_of_frame_found = true; | |
1da177e4 LT |
5376 | } |
5377 | ||
5378 | /* advance to next buffer entry in linked list */ | |
5379 | end_index++; | |
5380 | if ( end_index == info->rx_buffer_count ) | |
5381 | end_index = 0; | |
5382 | ||
5383 | if ( start_index == end_index ) | |
5384 | { | |
5385 | /* The entire list has been searched with all Counts == 0 and */ | |
5386 | /* all Status == 0. The receive buffers are */ | |
5387 | /* completely screwed, reset all receive buffers! */ | |
5388 | mgsl_reset_rx_dma_buffers( info ); | |
5389 | frame_start_index = 0; | |
0fab6de0 JP |
5390 | start_of_frame_found = false; |
5391 | reprogram_dma = true; | |
1da177e4 LT |
5392 | break; |
5393 | } | |
5394 | } | |
5395 | ||
5396 | if ( start_of_frame_found && !end_of_frame_found ) | |
5397 | { | |
5398 | /* There is an unfinished string of receive DMA buffers */ | |
5399 | /* as a result of the receiver overrun. */ | |
5400 | ||
5401 | /* Reset the buffers for the unfinished frame */ | |
5402 | /* and reprogram the receive DMA controller to start */ | |
5403 | /* at the 1st buffer of unfinished frame. */ | |
5404 | ||
5405 | start_index = frame_start_index; | |
5406 | ||
5407 | do | |
5408 | { | |
5409 | *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE; | |
5410 | ||
5411 | /* Adjust index for wrap around. */ | |
5412 | if ( start_index == info->rx_buffer_count ) | |
5413 | start_index = 0; | |
5414 | ||
5415 | } while( start_index != end_index ); | |
5416 | ||
0fab6de0 | 5417 | reprogram_dma = true; |
1da177e4 LT |
5418 | } |
5419 | ||
5420 | if ( reprogram_dma ) | |
5421 | { | |
5422 | usc_UnlatchRxstatusBits(info,RXSTATUS_ALL); | |
5423 | usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS); | |
5424 | usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS); | |
5425 | ||
5426 | usc_EnableReceiver(info,DISABLE_UNCONDITIONAL); | |
5427 | ||
5428 | /* This empties the receive FIFO and loads the RCC with RCLR */ | |
5429 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); | |
5430 | ||
5431 | /* program 16C32 with physical address of 1st DMA buffer entry */ | |
5432 | phys_addr = info->rx_buffer_list[frame_start_index].phys_entry; | |
5433 | usc_OutDmaReg( info, NRARL, (u16)phys_addr ); | |
5434 | usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) ); | |
5435 | ||
5436 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); | |
e06922aa | 5437 | usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS ); |
1da177e4 LT |
5438 | usc_EnableInterrupts( info, RECEIVE_STATUS ); |
5439 | ||
5440 | /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */ | |
5441 | /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */ | |
5442 | ||
e06922aa | 5443 | usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); |
1da177e4 LT |
5444 | usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); |
5445 | usc_DmaCmd( info, DmaCmd_InitRxChannel ); | |
5446 | if ( info->params.flags & HDLC_FLAG_AUTO_DCD ) | |
5447 | usc_EnableReceiver(info,ENABLE_AUTO_DCD); | |
5448 | else | |
5449 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); | |
5450 | } | |
5451 | else | |
5452 | { | |
5453 | /* This empties the receive FIFO and loads the RCC with RCLR */ | |
5454 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); | |
5455 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | |
5456 | } | |
5457 | ||
5458 | } /* end of usc_process_rxoverrun_sync() */ | |
5459 | ||
5460 | /* usc_stop_receiver() | |
5461 | * | |
5462 | * Disable USC receiver | |
5463 | * | |
5464 | * Arguments: info pointer to device instance data | |
5465 | * Return Value: None | |
5466 | */ | |
5467 | static void usc_stop_receiver( struct mgsl_struct *info ) | |
5468 | { | |
5469 | if (debug_level >= DEBUG_LEVEL_ISR) | |
5470 | printk("%s(%d):usc_stop_receiver(%s)\n", | |
5471 | __FILE__,__LINE__, info->device_name ); | |
5472 | ||
5473 | /* Disable receive DMA channel. */ | |
5474 | /* This also disables receive DMA channel interrupts */ | |
5475 | usc_DmaCmd( info, DmaCmd_ResetRxChannel ); | |
5476 | ||
5477 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); | |
e06922aa AJ |
5478 | usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS ); |
5479 | usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS ); | |
1da177e4 LT |
5480 | |
5481 | usc_EnableReceiver(info,DISABLE_UNCONDITIONAL); | |
5482 | ||
5483 | /* This empties the receive FIFO and loads the RCC with RCLR */ | |
5484 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); | |
5485 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | |
5486 | ||
0fab6de0 JP |
5487 | info->rx_enabled = false; |
5488 | info->rx_overflow = false; | |
5489 | info->rx_rcc_underrun = false; | |
1da177e4 LT |
5490 | |
5491 | } /* end of stop_receiver() */ | |
5492 | ||
5493 | /* usc_start_receiver() | |
5494 | * | |
5495 | * Enable the USC receiver | |
5496 | * | |
5497 | * Arguments: info pointer to device instance data | |
5498 | * Return Value: None | |
5499 | */ | |
5500 | static void usc_start_receiver( struct mgsl_struct *info ) | |
5501 | { | |
5502 | u32 phys_addr; | |
5503 | ||
5504 | if (debug_level >= DEBUG_LEVEL_ISR) | |
5505 | printk("%s(%d):usc_start_receiver(%s)\n", | |
5506 | __FILE__,__LINE__, info->device_name ); | |
5507 | ||
5508 | mgsl_reset_rx_dma_buffers( info ); | |
5509 | usc_stop_receiver( info ); | |
5510 | ||
5511 | usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); | |
5512 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | |
5513 | ||
5514 | if ( info->params.mode == MGSL_MODE_HDLC || | |
5515 | info->params.mode == MGSL_MODE_RAW ) { | |
5516 | /* DMA mode Transfers */ | |
5517 | /* Program the DMA controller. */ | |
5518 | /* Enable the DMA controller end of buffer interrupt. */ | |
5519 | ||
5520 | /* program 16C32 with physical address of 1st DMA buffer entry */ | |
5521 | phys_addr = info->rx_buffer_list[0].phys_entry; | |
5522 | usc_OutDmaReg( info, NRARL, (u16)phys_addr ); | |
5523 | usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) ); | |
5524 | ||
5525 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); | |
e06922aa | 5526 | usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS ); |
1da177e4 LT |
5527 | usc_EnableInterrupts( info, RECEIVE_STATUS ); |
5528 | ||
5529 | /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */ | |
5530 | /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */ | |
5531 | ||
e06922aa | 5532 | usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 ); |
1da177e4 LT |
5533 | usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) ); |
5534 | usc_DmaCmd( info, DmaCmd_InitRxChannel ); | |
5535 | if ( info->params.flags & HDLC_FLAG_AUTO_DCD ) | |
5536 | usc_EnableReceiver(info,ENABLE_AUTO_DCD); | |
5537 | else | |
5538 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); | |
5539 | } else { | |
5540 | usc_UnlatchRxstatusBits(info, RXSTATUS_ALL); | |
e06922aa | 5541 | usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS); |
1da177e4 LT |
5542 | usc_EnableInterrupts(info, RECEIVE_DATA); |
5543 | ||
5544 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | |
5545 | usc_RCmd( info, RCmd_EnterHuntmode ); | |
5546 | ||
5547 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); | |
5548 | } | |
5549 | ||
5550 | usc_OutReg( info, CCSR, 0x1020 ); | |
5551 | ||
0fab6de0 | 5552 | info->rx_enabled = true; |
1da177e4 LT |
5553 | |
5554 | } /* end of usc_start_receiver() */ | |
5555 | ||
5556 | /* usc_start_transmitter() | |
5557 | * | |
5558 | * Enable the USC transmitter and send a transmit frame if | |
5559 | * one is loaded in the DMA buffers. | |
5560 | * | |
5561 | * Arguments: info pointer to device instance data | |
5562 | * Return Value: None | |
5563 | */ | |
5564 | static void usc_start_transmitter( struct mgsl_struct *info ) | |
5565 | { | |
5566 | u32 phys_addr; | |
5567 | unsigned int FrameSize; | |
5568 | ||
5569 | if (debug_level >= DEBUG_LEVEL_ISR) | |
5570 | printk("%s(%d):usc_start_transmitter(%s)\n", | |
5571 | __FILE__,__LINE__, info->device_name ); | |
5572 | ||
5573 | if ( info->xmit_cnt ) { | |
5574 | ||
5575 | /* If auto RTS enabled and RTS is inactive, then assert */ | |
5576 | /* RTS and set a flag indicating that the driver should */ | |
5577 | /* negate RTS when the transmission completes. */ | |
5578 | ||
0fab6de0 | 5579 | info->drop_rts_on_tx_done = false; |
1da177e4 LT |
5580 | |
5581 | if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) { | |
5582 | usc_get_serial_signals( info ); | |
5583 | if ( !(info->serial_signals & SerialSignal_RTS) ) { | |
5584 | info->serial_signals |= SerialSignal_RTS; | |
5585 | usc_set_serial_signals( info ); | |
0fab6de0 | 5586 | info->drop_rts_on_tx_done = true; |
1da177e4 LT |
5587 | } |
5588 | } | |
5589 | ||
5590 | ||
5591 | if ( info->params.mode == MGSL_MODE_ASYNC ) { | |
5592 | if ( !info->tx_active ) { | |
5593 | usc_UnlatchTxstatusBits(info, TXSTATUS_ALL); | |
5594 | usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA); | |
5595 | usc_EnableInterrupts(info, TRANSMIT_DATA); | |
5596 | usc_load_txfifo(info); | |
5597 | } | |
5598 | } else { | |
5599 | /* Disable transmit DMA controller while programming. */ | |
5600 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); | |
5601 | ||
5602 | /* Transmit DMA buffer is loaded, so program USC */ | |
5603 | /* to send the frame contained in the buffers. */ | |
5604 | ||
5605 | FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc; | |
5606 | ||
5607 | /* if operating in Raw sync mode, reset the rcc component | |
5608 | * of the tx dma buffer entry, otherwise, the serial controller | |
5609 | * will send a closing sync char after this count. | |
5610 | */ | |
5611 | if ( info->params.mode == MGSL_MODE_RAW ) | |
5612 | info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0; | |
5613 | ||
5614 | /* Program the Transmit Character Length Register (TCLR) */ | |
5615 | /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */ | |
5616 | usc_OutReg( info, TCLR, (u16)FrameSize ); | |
5617 | ||
5618 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); | |
5619 | ||
5620 | /* Program the address of the 1st DMA Buffer Entry in linked list */ | |
5621 | phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry; | |
5622 | usc_OutDmaReg( info, NTARL, (u16)phys_addr ); | |
5623 | usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) ); | |
5624 | ||
5625 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); | |
5626 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); | |
5627 | usc_EnableInterrupts( info, TRANSMIT_STATUS ); | |
5628 | ||
5629 | if ( info->params.mode == MGSL_MODE_RAW && | |
5630 | info->num_tx_dma_buffers > 1 ) { | |
5631 | /* When running external sync mode, attempt to 'stream' transmit */ | |
5632 | /* by filling tx dma buffers as they become available. To do this */ | |
5633 | /* we need to enable Tx DMA EOB Status interrupts : */ | |
5634 | /* */ | |
5635 | /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */ | |
5636 | /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */ | |
5637 | ||
5638 | usc_OutDmaReg( info, TDIAR, BIT2|BIT3 ); | |
5639 | usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) ); | |
5640 | } | |
5641 | ||
5642 | /* Initialize Transmit DMA Channel */ | |
5643 | usc_DmaCmd( info, DmaCmd_InitTxChannel ); | |
5644 | ||
5645 | usc_TCmd( info, TCmd_SendFrame ); | |
5646 | ||
40565f19 JS |
5647 | mod_timer(&info->tx_timer, jiffies + |
5648 | msecs_to_jiffies(5000)); | |
1da177e4 | 5649 | } |
0fab6de0 | 5650 | info->tx_active = true; |
1da177e4 LT |
5651 | } |
5652 | ||
5653 | if ( !info->tx_enabled ) { | |
0fab6de0 | 5654 | info->tx_enabled = true; |
1da177e4 LT |
5655 | if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) |
5656 | usc_EnableTransmitter(info,ENABLE_AUTO_CTS); | |
5657 | else | |
5658 | usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL); | |
5659 | } | |
5660 | ||
5661 | } /* end of usc_start_transmitter() */ | |
5662 | ||
5663 | /* usc_stop_transmitter() | |
5664 | * | |
5665 | * Stops the transmitter and DMA | |
5666 | * | |
5667 | * Arguments: info pointer to device isntance data | |
5668 | * Return Value: None | |
5669 | */ | |
5670 | static void usc_stop_transmitter( struct mgsl_struct *info ) | |
5671 | { | |
5672 | if (debug_level >= DEBUG_LEVEL_ISR) | |
5673 | printk("%s(%d):usc_stop_transmitter(%s)\n", | |
5674 | __FILE__,__LINE__, info->device_name ); | |
5675 | ||
5676 | del_timer(&info->tx_timer); | |
5677 | ||
5678 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); | |
5679 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA ); | |
5680 | usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA ); | |
5681 | ||
5682 | usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL); | |
5683 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); | |
5684 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); | |
5685 | ||
0fab6de0 JP |
5686 | info->tx_enabled = false; |
5687 | info->tx_active = false; | |
1da177e4 LT |
5688 | |
5689 | } /* end of usc_stop_transmitter() */ | |
5690 | ||
5691 | /* usc_load_txfifo() | |
5692 | * | |
5693 | * Fill the transmit FIFO until the FIFO is full or | |
5694 | * there is no more data to load. | |
5695 | * | |
5696 | * Arguments: info pointer to device extension (instance data) | |
5697 | * Return Value: None | |
5698 | */ | |
5699 | static void usc_load_txfifo( struct mgsl_struct *info ) | |
5700 | { | |
5701 | int Fifocount; | |
5702 | u8 TwoBytes[2]; | |
5703 | ||
5704 | if ( !info->xmit_cnt && !info->x_char ) | |
5705 | return; | |
5706 | ||
5707 | /* Select transmit FIFO status readback in TICR */ | |
5708 | usc_TCmd( info, TCmd_SelectTicrTxFifostatus ); | |
5709 | ||
5710 | /* load the Transmit FIFO until FIFOs full or all data sent */ | |
5711 | ||
5712 | while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) { | |
5713 | /* there is more space in the transmit FIFO and */ | |
5714 | /* there is more data in transmit buffer */ | |
5715 | ||
5716 | if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) { | |
5717 | /* write a 16-bit word from transmit buffer to 16C32 */ | |
5718 | ||
5719 | TwoBytes[0] = info->xmit_buf[info->xmit_tail++]; | |
5720 | info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1); | |
5721 | TwoBytes[1] = info->xmit_buf[info->xmit_tail++]; | |
5722 | info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1); | |
5723 | ||
5724 | outw( *((u16 *)TwoBytes), info->io_base + DATAREG); | |
5725 | ||
5726 | info->xmit_cnt -= 2; | |
5727 | info->icount.tx += 2; | |
5728 | } else { | |
5729 | /* only 1 byte left to transmit or 1 FIFO slot left */ | |
5730 | ||
5731 | outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY), | |
5732 | info->io_base + CCAR ); | |
5733 | ||
5734 | if (info->x_char) { | |
5735 | /* transmit pending high priority char */ | |
5736 | outw( info->x_char,info->io_base + CCAR ); | |
5737 | info->x_char = 0; | |
5738 | } else { | |
5739 | outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR ); | |
5740 | info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1); | |
5741 | info->xmit_cnt--; | |
5742 | } | |
5743 | info->icount.tx++; | |
5744 | } | |
5745 | } | |
5746 | ||
5747 | } /* end of usc_load_txfifo() */ | |
5748 | ||
5749 | /* usc_reset() | |
5750 | * | |
5751 | * Reset the adapter to a known state and prepare it for further use. | |
5752 | * | |
5753 | * Arguments: info pointer to device instance data | |
5754 | * Return Value: None | |
5755 | */ | |
5756 | static void usc_reset( struct mgsl_struct *info ) | |
5757 | { | |
5758 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) { | |
5759 | int i; | |
5760 | u32 readval; | |
5761 | ||
5762 | /* Set BIT30 of Misc Control Register */ | |
5763 | /* (Local Control Register 0x50) to force reset of USC. */ | |
5764 | ||
5765 | volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50); | |
5766 | u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28); | |
5767 | ||
5768 | info->misc_ctrl_value |= BIT30; | |
5769 | *MiscCtrl = info->misc_ctrl_value; | |
5770 | ||
5771 | /* | |
5772 | * Force at least 170ns delay before clearing | |
5773 | * reset bit. Each read from LCR takes at least | |
5774 | * 30ns so 10 times for 300ns to be safe. | |
5775 | */ | |
5776 | for(i=0;i<10;i++) | |
5777 | readval = *MiscCtrl; | |
5778 | ||
5779 | info->misc_ctrl_value &= ~BIT30; | |
5780 | *MiscCtrl = info->misc_ctrl_value; | |
5781 | ||
5782 | *LCR0BRDR = BUS_DESCRIPTOR( | |
5783 | 1, // Write Strobe Hold (0-3) | |
5784 | 2, // Write Strobe Delay (0-3) | |
5785 | 2, // Read Strobe Delay (0-3) | |
5786 | 0, // NWDD (Write data-data) (0-3) | |
5787 | 4, // NWAD (Write Addr-data) (0-31) | |
5788 | 0, // NXDA (Read/Write Data-Addr) (0-3) | |
5789 | 0, // NRDD (Read Data-Data) (0-3) | |
5790 | 5 // NRAD (Read Addr-Data) (0-31) | |
5791 | ); | |
5792 | } else { | |
5793 | /* do HW reset */ | |
5794 | outb( 0,info->io_base + 8 ); | |
5795 | } | |
5796 | ||
5797 | info->mbre_bit = 0; | |
5798 | info->loopback_bits = 0; | |
5799 | info->usc_idle_mode = 0; | |
5800 | ||
5801 | /* | |
5802 | * Program the Bus Configuration Register (BCR) | |
5803 | * | |
5804 | * <15> 0 Don't use separate address | |
5805 | * <14..6> 0 reserved | |
5806 | * <5..4> 00 IAckmode = Default, don't care | |
5807 | * <3> 1 Bus Request Totem Pole output | |
5808 | * <2> 1 Use 16 Bit data bus | |
5809 | * <1> 0 IRQ Totem Pole output | |
5810 | * <0> 0 Don't Shift Right Addr | |
5811 | * | |
5812 | * 0000 0000 0000 1100 = 0x000c | |
5813 | * | |
5814 | * By writing to io_base + SDPIN the Wait/Ack pin is | |
5815 | * programmed to work as a Wait pin. | |
5816 | */ | |
5817 | ||
5818 | outw( 0x000c,info->io_base + SDPIN ); | |
5819 | ||
5820 | ||
5821 | outw( 0,info->io_base ); | |
5822 | outw( 0,info->io_base + CCAR ); | |
5823 | ||
5824 | /* select little endian byte ordering */ | |
5825 | usc_RTCmd( info, RTCmd_SelectLittleEndian ); | |
5826 | ||
5827 | ||
5828 | /* Port Control Register (PCR) | |
5829 | * | |
5830 | * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled) | |
5831 | * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled) | |
5832 | * <11..10> 00 Port 5 is Input (No Connect, Don't Care) | |
5833 | * <9..8> 00 Port 4 is Input (No Connect, Don't Care) | |
5834 | * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled ) | |
5835 | * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled ) | |
5836 | * <3..2> 01 Port 1 is Input (Dedicated RxC) | |
5837 | * <1..0> 01 Port 0 is Input (Dedicated TxC) | |
5838 | * | |
5839 | * 1111 0000 1111 0101 = 0xf0f5 | |
5840 | */ | |
5841 | ||
5842 | usc_OutReg( info, PCR, 0xf0f5 ); | |
5843 | ||
5844 | ||
5845 | /* | |
5846 | * Input/Output Control Register | |
5847 | * | |
5848 | * <15..14> 00 CTS is active low input | |
5849 | * <13..12> 00 DCD is active low input | |
5850 | * <11..10> 00 TxREQ pin is input (DSR) | |
5851 | * <9..8> 00 RxREQ pin is input (RI) | |
5852 | * <7..6> 00 TxD is output (Transmit Data) | |
5853 | * <5..3> 000 TxC Pin in Input (14.7456MHz Clock) | |
5854 | * <2..0> 100 RxC is Output (drive with BRG0) | |
5855 | * | |
5856 | * 0000 0000 0000 0100 = 0x0004 | |
5857 | */ | |
5858 | ||
5859 | usc_OutReg( info, IOCR, 0x0004 ); | |
5860 | ||
5861 | } /* end of usc_reset() */ | |
5862 | ||
5863 | /* usc_set_async_mode() | |
5864 | * | |
5865 | * Program adapter for asynchronous communications. | |
5866 | * | |
5867 | * Arguments: info pointer to device instance data | |
5868 | * Return Value: None | |
5869 | */ | |
5870 | static void usc_set_async_mode( struct mgsl_struct *info ) | |
5871 | { | |
5872 | u16 RegValue; | |
5873 | ||
5874 | /* disable interrupts while programming USC */ | |
5875 | usc_DisableMasterIrqBit( info ); | |
5876 | ||
5877 | outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */ | |
5878 | usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */ | |
5879 | ||
5880 | usc_loopback_frame( info ); | |
5881 | ||
5882 | /* Channel mode Register (CMR) | |
5883 | * | |
5884 | * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit | |
5885 | * <13..12> 00 00 = 16X Clock | |
5886 | * <11..8> 0000 Transmitter mode = Asynchronous | |
5887 | * <7..6> 00 reserved? | |
5888 | * <5..4> 00 Rx Sub modes, 00 = 16X Clock | |
5889 | * <3..0> 0000 Receiver mode = Asynchronous | |
5890 | * | |
5891 | * 0000 0000 0000 0000 = 0x0 | |
5892 | */ | |
5893 | ||
5894 | RegValue = 0; | |
5895 | if ( info->params.stop_bits != 1 ) | |
5896 | RegValue |= BIT14; | |
5897 | usc_OutReg( info, CMR, RegValue ); | |
5898 | ||
5899 | ||
5900 | /* Receiver mode Register (RMR) | |
5901 | * | |
5902 | * <15..13> 000 encoding = None | |
5903 | * <12..08> 00000 reserved (Sync Only) | |
5904 | * <7..6> 00 Even parity | |
5905 | * <5> 0 parity disabled | |
5906 | * <4..2> 000 Receive Char Length = 8 bits | |
5907 | * <1..0> 00 Disable Receiver | |
5908 | * | |
5909 | * 0000 0000 0000 0000 = 0x0 | |
5910 | */ | |
5911 | ||
5912 | RegValue = 0; | |
5913 | ||
5914 | if ( info->params.data_bits != 8 ) | |
e06922aa | 5915 | RegValue |= BIT4 | BIT3 | BIT2; |
1da177e4 LT |
5916 | |
5917 | if ( info->params.parity != ASYNC_PARITY_NONE ) { | |
5918 | RegValue |= BIT5; | |
5919 | if ( info->params.parity != ASYNC_PARITY_ODD ) | |
5920 | RegValue |= BIT6; | |
5921 | } | |
5922 | ||
5923 | usc_OutReg( info, RMR, RegValue ); | |
5924 | ||
5925 | ||
5926 | /* Set IRQ trigger level */ | |
5927 | ||
5928 | usc_RCmd( info, RCmd_SelectRicrIntLevel ); | |
5929 | ||
5930 | ||
5931 | /* Receive Interrupt Control Register (RICR) | |
5932 | * | |
5933 | * <15..8> ? RxFIFO IRQ Request Level | |
5934 | * | |
5935 | * Note: For async mode the receive FIFO level must be set | |
7f927fcc | 5936 | * to 0 to avoid the situation where the FIFO contains fewer bytes |
1da177e4 LT |
5937 | * than the trigger level and no more data is expected. |
5938 | * | |
5939 | * <7> 0 Exited Hunt IA (Interrupt Arm) | |
5940 | * <6> 0 Idle Received IA | |
5941 | * <5> 0 Break/Abort IA | |
5942 | * <4> 0 Rx Bound IA | |
5943 | * <3> 0 Queued status reflects oldest byte in FIFO | |
5944 | * <2> 0 Abort/PE IA | |
5945 | * <1> 0 Rx Overrun IA | |
5946 | * <0> 0 Select TC0 value for readback | |
5947 | * | |
5948 | * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB) | |
5949 | */ | |
5950 | ||
5951 | usc_OutReg( info, RICR, 0x0000 ); | |
5952 | ||
5953 | usc_UnlatchRxstatusBits( info, RXSTATUS_ALL ); | |
5954 | usc_ClearIrqPendingBits( info, RECEIVE_STATUS ); | |
5955 | ||
5956 | ||
5957 | /* Transmit mode Register (TMR) | |
5958 | * | |
5959 | * <15..13> 000 encoding = None | |
5960 | * <12..08> 00000 reserved (Sync Only) | |
5961 | * <7..6> 00 Transmit parity Even | |
5962 | * <5> 0 Transmit parity Disabled | |
5963 | * <4..2> 000 Tx Char Length = 8 bits | |
5964 | * <1..0> 00 Disable Transmitter | |
5965 | * | |
5966 | * 0000 0000 0000 0000 = 0x0 | |
5967 | */ | |
5968 | ||
5969 | RegValue = 0; | |
5970 | ||
5971 | if ( info->params.data_bits != 8 ) | |
e06922aa | 5972 | RegValue |= BIT4 | BIT3 | BIT2; |
1da177e4 LT |
5973 | |
5974 | if ( info->params.parity != ASYNC_PARITY_NONE ) { | |
5975 | RegValue |= BIT5; | |
5976 | if ( info->params.parity != ASYNC_PARITY_ODD ) | |
5977 | RegValue |= BIT6; | |
5978 | } | |
5979 | ||
5980 | usc_OutReg( info, TMR, RegValue ); | |
5981 | ||
5982 | usc_set_txidle( info ); | |
5983 | ||
5984 | ||
5985 | /* Set IRQ trigger level */ | |
5986 | ||
5987 | usc_TCmd( info, TCmd_SelectTicrIntLevel ); | |
5988 | ||
5989 | ||
5990 | /* Transmit Interrupt Control Register (TICR) | |
5991 | * | |
5992 | * <15..8> ? Transmit FIFO IRQ Level | |
5993 | * <7> 0 Present IA (Interrupt Arm) | |
5994 | * <6> 1 Idle Sent IA | |
5995 | * <5> 0 Abort Sent IA | |
5996 | * <4> 0 EOF/EOM Sent IA | |
5997 | * <3> 0 CRC Sent IA | |
5998 | * <2> 0 1 = Wait for SW Trigger to Start Frame | |
5999 | * <1> 0 Tx Underrun IA | |
6000 | * <0> 0 TC0 constant on read back | |
6001 | * | |
6002 | * 0000 0000 0100 0000 = 0x0040 | |
6003 | */ | |
6004 | ||
6005 | usc_OutReg( info, TICR, 0x1f40 ); | |
6006 | ||
6007 | usc_UnlatchTxstatusBits( info, TXSTATUS_ALL ); | |
6008 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS ); | |
6009 | ||
6010 | usc_enable_async_clock( info, info->params.data_rate ); | |
6011 | ||
6012 | ||
6013 | /* Channel Control/status Register (CCSR) | |
6014 | * | |
6015 | * <15> X RCC FIFO Overflow status (RO) | |
6016 | * <14> X RCC FIFO Not Empty status (RO) | |
6017 | * <13> 0 1 = Clear RCC FIFO (WO) | |
6018 | * <12> X DPLL in Sync status (RO) | |
6019 | * <11> X DPLL 2 Missed Clocks status (RO) | |
6020 | * <10> X DPLL 1 Missed Clock status (RO) | |
6021 | * <9..8> 00 DPLL Resync on rising and falling edges (RW) | |
6022 | * <7> X SDLC Loop On status (RO) | |
6023 | * <6> X SDLC Loop Send status (RO) | |
6024 | * <5> 1 Bypass counters for TxClk and RxClk (RW) | |
6025 | * <4..2> 000 Last Char of SDLC frame has 8 bits (RW) | |
6026 | * <1..0> 00 reserved | |
6027 | * | |
6028 | * 0000 0000 0010 0000 = 0x0020 | |
6029 | */ | |
6030 | ||
6031 | usc_OutReg( info, CCSR, 0x0020 ); | |
6032 | ||
6033 | usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA + | |
6034 | RECEIVE_DATA + RECEIVE_STATUS ); | |
6035 | ||
6036 | usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA + | |
6037 | RECEIVE_DATA + RECEIVE_STATUS ); | |
6038 | ||
6039 | usc_EnableMasterIrqBit( info ); | |
6040 | ||
6041 | if (info->bus_type == MGSL_BUS_TYPE_ISA) { | |
6042 | /* Enable INTEN (Port 6, Bit12) */ | |
6043 | /* This connects the IRQ request signal to the ISA bus */ | |
6044 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); | |
6045 | } | |
6046 | ||
7c1fff58 PF |
6047 | if (info->params.loopback) { |
6048 | info->loopback_bits = 0x300; | |
6049 | outw(0x0300, info->io_base + CCAR); | |
6050 | } | |
6051 | ||
1da177e4 LT |
6052 | } /* end of usc_set_async_mode() */ |
6053 | ||
6054 | /* usc_loopback_frame() | |
6055 | * | |
6056 | * Loop back a small (2 byte) dummy SDLC frame. | |
6057 | * Interrupts and DMA are NOT used. The purpose of this is to | |
6058 | * clear any 'stale' status info left over from running in async mode. | |
6059 | * | |
6060 | * The 16C32 shows the strange behaviour of marking the 1st | |
6061 | * received SDLC frame with a CRC error even when there is no | |
6062 | * CRC error. To get around this a small dummy from of 2 bytes | |
6063 | * is looped back when switching from async to sync mode. | |
6064 | * | |
6065 | * Arguments: info pointer to device instance data | |
6066 | * Return Value: None | |
6067 | */ | |
6068 | static void usc_loopback_frame( struct mgsl_struct *info ) | |
6069 | { | |
6070 | int i; | |
6071 | unsigned long oldmode = info->params.mode; | |
6072 | ||
6073 | info->params.mode = MGSL_MODE_HDLC; | |
6074 | ||
6075 | usc_DisableMasterIrqBit( info ); | |
6076 | ||
6077 | usc_set_sdlc_mode( info ); | |
6078 | usc_enable_loopback( info, 1 ); | |
6079 | ||
6080 | /* Write 16-bit Time Constant for BRG0 */ | |
6081 | usc_OutReg( info, TC0R, 0 ); | |
6082 | ||
6083 | /* Channel Control Register (CCR) | |
6084 | * | |
6085 | * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs) | |
6086 | * <13> 0 Trigger Tx on SW Command Disabled | |
6087 | * <12> 0 Flag Preamble Disabled | |
6088 | * <11..10> 00 Preamble Length = 8-Bits | |
6089 | * <9..8> 01 Preamble Pattern = flags | |
6090 | * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs) | |
6091 | * <5> 0 Trigger Rx on SW Command Disabled | |
6092 | * <4..0> 0 reserved | |
6093 | * | |
6094 | * 0000 0001 0000 0000 = 0x0100 | |
6095 | */ | |
6096 | ||
6097 | usc_OutReg( info, CCR, 0x0100 ); | |
6098 | ||
6099 | /* SETUP RECEIVER */ | |
6100 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | |
6101 | usc_EnableReceiver(info,ENABLE_UNCONDITIONAL); | |
6102 | ||
6103 | /* SETUP TRANSMITTER */ | |
6104 | /* Program the Transmit Character Length Register (TCLR) */ | |
6105 | /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */ | |
6106 | usc_OutReg( info, TCLR, 2 ); | |
6107 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); | |
6108 | ||
6109 | /* unlatch Tx status bits, and start transmit channel. */ | |
6110 | usc_UnlatchTxstatusBits(info,TXSTATUS_ALL); | |
6111 | outw(0,info->io_base + DATAREG); | |
6112 | ||
6113 | /* ENABLE TRANSMITTER */ | |
6114 | usc_TCmd( info, TCmd_SendFrame ); | |
6115 | usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL); | |
6116 | ||
6117 | /* WAIT FOR RECEIVE COMPLETE */ | |
6118 | for (i=0 ; i<1000 ; i++) | |
e06922aa | 6119 | if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) |
1da177e4 LT |
6120 | break; |
6121 | ||
6122 | /* clear Internal Data loopback mode */ | |
6123 | usc_enable_loopback(info, 0); | |
6124 | ||
6125 | usc_EnableMasterIrqBit(info); | |
6126 | ||
6127 | info->params.mode = oldmode; | |
6128 | ||
6129 | } /* end of usc_loopback_frame() */ | |
6130 | ||
6131 | /* usc_set_sync_mode() Programs the USC for SDLC communications. | |
6132 | * | |
6133 | * Arguments: info pointer to adapter info structure | |
6134 | * Return Value: None | |
6135 | */ | |
6136 | static void usc_set_sync_mode( struct mgsl_struct *info ) | |
6137 | { | |
6138 | usc_loopback_frame( info ); | |
6139 | usc_set_sdlc_mode( info ); | |
6140 | ||
6141 | if (info->bus_type == MGSL_BUS_TYPE_ISA) { | |
6142 | /* Enable INTEN (Port 6, Bit12) */ | |
6143 | /* This connects the IRQ request signal to the ISA bus */ | |
6144 | usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); | |
6145 | } | |
6146 | ||
6147 | usc_enable_aux_clock(info, info->params.clock_speed); | |
6148 | ||
6149 | if (info->params.loopback) | |
6150 | usc_enable_loopback(info,1); | |
6151 | ||
6152 | } /* end of mgsl_set_sync_mode() */ | |
6153 | ||
6154 | /* usc_set_txidle() Set the HDLC idle mode for the transmitter. | |
6155 | * | |
6156 | * Arguments: info pointer to device instance data | |
6157 | * Return Value: None | |
6158 | */ | |
6159 | static void usc_set_txidle( struct mgsl_struct *info ) | |
6160 | { | |
6161 | u16 usc_idle_mode = IDLEMODE_FLAGS; | |
6162 | ||
6163 | /* Map API idle mode to USC register bits */ | |
6164 | ||
6165 | switch( info->idle_mode ){ | |
6166 | case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break; | |
6167 | case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break; | |
6168 | case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break; | |
6169 | case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break; | |
6170 | case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break; | |
6171 | case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break; | |
6172 | case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break; | |
6173 | } | |
6174 | ||
6175 | info->usc_idle_mode = usc_idle_mode; | |
6176 | //usc_OutReg(info, TCSR, usc_idle_mode); | |
6177 | info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */ | |
6178 | info->tcsr_value += usc_idle_mode; | |
6179 | usc_OutReg(info, TCSR, info->tcsr_value); | |
6180 | ||
6181 | /* | |
6182 | * if SyncLink WAN adapter is running in external sync mode, the | |
6183 | * transmitter has been set to Monosync in order to try to mimic | |
6184 | * a true raw outbound bit stream. Monosync still sends an open/close | |
6185 | * sync char at the start/end of a frame. Try to match those sync | |
6186 | * patterns to the idle mode set here | |
6187 | */ | |
6188 | if ( info->params.mode == MGSL_MODE_RAW ) { | |
6189 | unsigned char syncpat = 0; | |
6190 | switch( info->idle_mode ) { | |
6191 | case HDLC_TXIDLE_FLAGS: | |
6192 | syncpat = 0x7e; | |
6193 | break; | |
6194 | case HDLC_TXIDLE_ALT_ZEROS_ONES: | |
6195 | syncpat = 0x55; | |
6196 | break; | |
6197 | case HDLC_TXIDLE_ZEROS: | |
6198 | case HDLC_TXIDLE_SPACE: | |
6199 | syncpat = 0x00; | |
6200 | break; | |
6201 | case HDLC_TXIDLE_ONES: | |
6202 | case HDLC_TXIDLE_MARK: | |
6203 | syncpat = 0xff; | |
6204 | break; | |
6205 | case HDLC_TXIDLE_ALT_MARK_SPACE: | |
6206 | syncpat = 0xaa; | |
6207 | break; | |
6208 | } | |
6209 | ||
6210 | usc_SetTransmitSyncChars(info,syncpat,syncpat); | |
6211 | } | |
6212 | ||
6213 | } /* end of usc_set_txidle() */ | |
6214 | ||
6215 | /* usc_get_serial_signals() | |
6216 | * | |
6217 | * Query the adapter for the state of the V24 status (input) signals. | |
6218 | * | |
6219 | * Arguments: info pointer to device instance data | |
6220 | * Return Value: None | |
6221 | */ | |
6222 | static void usc_get_serial_signals( struct mgsl_struct *info ) | |
6223 | { | |
6224 | u16 status; | |
6225 | ||
9fe8074b JP |
6226 | /* clear all serial signals except RTS and DTR */ |
6227 | info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR; | |
1da177e4 LT |
6228 | |
6229 | /* Read the Misc Interrupt status Register (MISR) to get */ | |
6230 | /* the V24 status signals. */ | |
6231 | ||
6232 | status = usc_InReg( info, MISR ); | |
6233 | ||
6234 | /* set serial signal bits to reflect MISR */ | |
6235 | ||
6236 | if ( status & MISCSTATUS_CTS ) | |
6237 | info->serial_signals |= SerialSignal_CTS; | |
6238 | ||
6239 | if ( status & MISCSTATUS_DCD ) | |
6240 | info->serial_signals |= SerialSignal_DCD; | |
6241 | ||
6242 | if ( status & MISCSTATUS_RI ) | |
6243 | info->serial_signals |= SerialSignal_RI; | |
6244 | ||
6245 | if ( status & MISCSTATUS_DSR ) | |
6246 | info->serial_signals |= SerialSignal_DSR; | |
6247 | ||
6248 | } /* end of usc_get_serial_signals() */ | |
6249 | ||
6250 | /* usc_set_serial_signals() | |
6251 | * | |
9fe8074b | 6252 | * Set the state of RTS and DTR based on contents of |
1da177e4 LT |
6253 | * serial_signals member of device extension. |
6254 | * | |
6255 | * Arguments: info pointer to device instance data | |
6256 | * Return Value: None | |
6257 | */ | |
6258 | static void usc_set_serial_signals( struct mgsl_struct *info ) | |
6259 | { | |
6260 | u16 Control; | |
6261 | unsigned char V24Out = info->serial_signals; | |
6262 | ||
6263 | /* get the current value of the Port Control Register (PCR) */ | |
6264 | ||
6265 | Control = usc_InReg( info, PCR ); | |
6266 | ||
6267 | if ( V24Out & SerialSignal_RTS ) | |
6268 | Control &= ~(BIT6); | |
6269 | else | |
6270 | Control |= BIT6; | |
6271 | ||
6272 | if ( V24Out & SerialSignal_DTR ) | |
6273 | Control &= ~(BIT4); | |
6274 | else | |
6275 | Control |= BIT4; | |
6276 | ||
6277 | usc_OutReg( info, PCR, Control ); | |
6278 | ||
6279 | } /* end of usc_set_serial_signals() */ | |
6280 | ||
6281 | /* usc_enable_async_clock() | |
6282 | * | |
6283 | * Enable the async clock at the specified frequency. | |
6284 | * | |
6285 | * Arguments: info pointer to device instance data | |
6286 | * data_rate data rate of clock in bps | |
6287 | * 0 disables the AUX clock. | |
6288 | * Return Value: None | |
6289 | */ | |
6290 | static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate ) | |
6291 | { | |
6292 | if ( data_rate ) { | |
6293 | /* | |
6294 | * Clock mode Control Register (CMCR) | |
6295 | * | |
6296 | * <15..14> 00 counter 1 Disabled | |
6297 | * <13..12> 00 counter 0 Disabled | |
6298 | * <11..10> 11 BRG1 Input is TxC Pin | |
6299 | * <9..8> 11 BRG0 Input is TxC Pin | |
6300 | * <7..6> 01 DPLL Input is BRG1 Output | |
6301 | * <5..3> 100 TxCLK comes from BRG0 | |
6302 | * <2..0> 100 RxCLK comes from BRG0 | |
6303 | * | |
6304 | * 0000 1111 0110 0100 = 0x0f64 | |
6305 | */ | |
6306 | ||
6307 | usc_OutReg( info, CMCR, 0x0f64 ); | |
6308 | ||
6309 | ||
6310 | /* | |
6311 | * Write 16-bit Time Constant for BRG0 | |
6312 | * Time Constant = (ClkSpeed / data_rate) - 1 | |
6313 | * ClkSpeed = 921600 (ISA), 691200 (PCI) | |
6314 | */ | |
6315 | ||
6316 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
6317 | usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) ); | |
6318 | else | |
6319 | usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) ); | |
6320 | ||
6321 | ||
6322 | /* | |
6323 | * Hardware Configuration Register (HCR) | |
6324 | * Clear Bit 1, BRG0 mode = Continuous | |
6325 | * Set Bit 0 to enable BRG0. | |
6326 | */ | |
6327 | ||
6328 | usc_OutReg( info, HCR, | |
6329 | (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); | |
6330 | ||
6331 | ||
6332 | /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */ | |
6333 | ||
6334 | usc_OutReg( info, IOCR, | |
6335 | (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); | |
6336 | } else { | |
6337 | /* data rate == 0 so turn off BRG0 */ | |
6338 | usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); | |
6339 | } | |
6340 | ||
6341 | } /* end of usc_enable_async_clock() */ | |
6342 | ||
6343 | /* | |
6344 | * Buffer Structures: | |
6345 | * | |
6346 | * Normal memory access uses virtual addresses that can make discontiguous | |
6347 | * physical memory pages appear to be contiguous in the virtual address | |
6348 | * space (the processors memory mapping handles the conversions). | |
6349 | * | |
6350 | * DMA transfers require physically contiguous memory. This is because | |
6351 | * the DMA system controller and DMA bus masters deal with memory using | |
6352 | * only physical addresses. | |
6353 | * | |
6354 | * This causes a problem under Windows NT when large DMA buffers are | |
6355 | * needed. Fragmentation of the nonpaged pool prevents allocations of | |
6356 | * physically contiguous buffers larger than the PAGE_SIZE. | |
6357 | * | |
6358 | * However the 16C32 supports Bus Master Scatter/Gather DMA which | |
6359 | * allows DMA transfers to physically discontiguous buffers. Information | |
6360 | * about each data transfer buffer is contained in a memory structure | |
6361 | * called a 'buffer entry'. A list of buffer entries is maintained | |
6362 | * to track and control the use of the data transfer buffers. | |
6363 | * | |
6364 | * To support this strategy we will allocate sufficient PAGE_SIZE | |
6365 | * contiguous memory buffers to allow for the total required buffer | |
6366 | * space. | |
6367 | * | |
6368 | * The 16C32 accesses the list of buffer entries using Bus Master | |
6369 | * DMA. Control information is read from the buffer entries by the | |
6370 | * 16C32 to control data transfers. status information is written to | |
6371 | * the buffer entries by the 16C32 to indicate the status of completed | |
6372 | * transfers. | |
6373 | * | |
6374 | * The CPU writes control information to the buffer entries to control | |
6375 | * the 16C32 and reads status information from the buffer entries to | |
6376 | * determine information about received and transmitted frames. | |
6377 | * | |
6378 | * Because the CPU and 16C32 (adapter) both need simultaneous access | |
6379 | * to the buffer entries, the buffer entry memory is allocated with | |
6380 | * HalAllocateCommonBuffer(). This restricts the size of the buffer | |
6381 | * entry list to PAGE_SIZE. | |
6382 | * | |
6383 | * The actual data buffers on the other hand will only be accessed | |
6384 | * by the CPU or the adapter but not by both simultaneously. This allows | |
6385 | * Scatter/Gather packet based DMA procedures for using physically | |
6386 | * discontiguous pages. | |
6387 | */ | |
6388 | ||
6389 | /* | |
6390 | * mgsl_reset_tx_dma_buffers() | |
6391 | * | |
6392 | * Set the count for all transmit buffers to 0 to indicate the | |
6393 | * buffer is available for use and set the current buffer to the | |
6394 | * first buffer. This effectively makes all buffers free and | |
6395 | * discards any data in buffers. | |
6396 | * | |
6397 | * Arguments: info pointer to device instance data | |
6398 | * Return Value: None | |
6399 | */ | |
6400 | static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info ) | |
6401 | { | |
6402 | unsigned int i; | |
6403 | ||
6404 | for ( i = 0; i < info->tx_buffer_count; i++ ) { | |
6405 | *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0; | |
6406 | } | |
6407 | ||
6408 | info->current_tx_buffer = 0; | |
6409 | info->start_tx_dma_buffer = 0; | |
6410 | info->tx_dma_buffers_used = 0; | |
6411 | ||
6412 | info->get_tx_holding_index = 0; | |
6413 | info->put_tx_holding_index = 0; | |
6414 | info->tx_holding_count = 0; | |
6415 | ||
6416 | } /* end of mgsl_reset_tx_dma_buffers() */ | |
6417 | ||
6418 | /* | |
6419 | * num_free_tx_dma_buffers() | |
6420 | * | |
6421 | * returns the number of free tx dma buffers available | |
6422 | * | |
6423 | * Arguments: info pointer to device instance data | |
6424 | * Return Value: number of free tx dma buffers | |
6425 | */ | |
6426 | static int num_free_tx_dma_buffers(struct mgsl_struct *info) | |
6427 | { | |
6428 | return info->tx_buffer_count - info->tx_dma_buffers_used; | |
6429 | } | |
6430 | ||
6431 | /* | |
6432 | * mgsl_reset_rx_dma_buffers() | |
6433 | * | |
6434 | * Set the count for all receive buffers to DMABUFFERSIZE | |
6435 | * and set the current buffer to the first buffer. This effectively | |
6436 | * makes all buffers free and discards any data in buffers. | |
6437 | * | |
6438 | * Arguments: info pointer to device instance data | |
6439 | * Return Value: None | |
6440 | */ | |
6441 | static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info ) | |
6442 | { | |
6443 | unsigned int i; | |
6444 | ||
6445 | for ( i = 0; i < info->rx_buffer_count; i++ ) { | |
6446 | *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE; | |
6447 | // info->rx_buffer_list[i].count = DMABUFFERSIZE; | |
6448 | // info->rx_buffer_list[i].status = 0; | |
6449 | } | |
6450 | ||
6451 | info->current_rx_buffer = 0; | |
6452 | ||
6453 | } /* end of mgsl_reset_rx_dma_buffers() */ | |
6454 | ||
6455 | /* | |
6456 | * mgsl_free_rx_frame_buffers() | |
6457 | * | |
6458 | * Free the receive buffers used by a received SDLC | |
6459 | * frame such that the buffers can be reused. | |
6460 | * | |
6461 | * Arguments: | |
6462 | * | |
6463 | * info pointer to device instance data | |
6464 | * StartIndex index of 1st receive buffer of frame | |
6465 | * EndIndex index of last receive buffer of frame | |
6466 | * | |
6467 | * Return Value: None | |
6468 | */ | |
6469 | static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex ) | |
6470 | { | |
0fab6de0 | 6471 | bool Done = false; |
1da177e4 LT |
6472 | DMABUFFERENTRY *pBufEntry; |
6473 | unsigned int Index; | |
6474 | ||
6475 | /* Starting with 1st buffer entry of the frame clear the status */ | |
6476 | /* field and set the count field to DMA Buffer Size. */ | |
6477 | ||
6478 | Index = StartIndex; | |
6479 | ||
6480 | while( !Done ) { | |
6481 | pBufEntry = &(info->rx_buffer_list[Index]); | |
6482 | ||
6483 | if ( Index == EndIndex ) { | |
6484 | /* This is the last buffer of the frame! */ | |
0fab6de0 | 6485 | Done = true; |
1da177e4 LT |
6486 | } |
6487 | ||
6488 | /* reset current buffer for reuse */ | |
6489 | // pBufEntry->status = 0; | |
6490 | // pBufEntry->count = DMABUFFERSIZE; | |
6491 | *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE; | |
6492 | ||
6493 | /* advance to next buffer entry in linked list */ | |
6494 | Index++; | |
6495 | if ( Index == info->rx_buffer_count ) | |
6496 | Index = 0; | |
6497 | } | |
6498 | ||
6499 | /* set current buffer to next buffer after last buffer of frame */ | |
6500 | info->current_rx_buffer = Index; | |
6501 | ||
6502 | } /* end of free_rx_frame_buffers() */ | |
6503 | ||
6504 | /* mgsl_get_rx_frame() | |
6505 | * | |
6506 | * This function attempts to return a received SDLC frame from the | |
6507 | * receive DMA buffers. Only frames received without errors are returned. | |
6508 | * | |
6509 | * Arguments: info pointer to device extension | |
0fab6de0 | 6510 | * Return Value: true if frame returned, otherwise false |
1da177e4 | 6511 | */ |
0fab6de0 | 6512 | static bool mgsl_get_rx_frame(struct mgsl_struct *info) |
1da177e4 LT |
6513 | { |
6514 | unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */ | |
6515 | unsigned short status; | |
6516 | DMABUFFERENTRY *pBufEntry; | |
6517 | unsigned int framesize = 0; | |
0fab6de0 | 6518 | bool ReturnCode = false; |
1da177e4 | 6519 | unsigned long flags; |
8fb06c77 | 6520 | struct tty_struct *tty = info->port.tty; |
0fab6de0 | 6521 | bool return_frame = false; |
1da177e4 LT |
6522 | |
6523 | /* | |
6524 | * current_rx_buffer points to the 1st buffer of the next available | |
6525 | * receive frame. To find the last buffer of the frame look for | |
6526 | * a non-zero status field in the buffer entries. (The status | |
6527 | * field is set by the 16C32 after completing a receive frame. | |
6528 | */ | |
6529 | ||
6530 | StartIndex = EndIndex = info->current_rx_buffer; | |
6531 | ||
6532 | while( !info->rx_buffer_list[EndIndex].status ) { | |
6533 | /* | |
6534 | * If the count field of the buffer entry is non-zero then | |
6535 | * this buffer has not been used. (The 16C32 clears the count | |
6536 | * field when it starts using the buffer.) If an unused buffer | |
6537 | * is encountered then there are no frames available. | |
6538 | */ | |
6539 | ||
6540 | if ( info->rx_buffer_list[EndIndex].count ) | |
6541 | goto Cleanup; | |
6542 | ||
6543 | /* advance to next buffer entry in linked list */ | |
6544 | EndIndex++; | |
6545 | if ( EndIndex == info->rx_buffer_count ) | |
6546 | EndIndex = 0; | |
6547 | ||
6548 | /* if entire list searched then no frame available */ | |
6549 | if ( EndIndex == StartIndex ) { | |
6550 | /* If this occurs then something bad happened, | |
6551 | * all buffers have been 'used' but none mark | |
6552 | * the end of a frame. Reset buffers and receiver. | |
6553 | */ | |
6554 | ||
6555 | if ( info->rx_enabled ){ | |
6556 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
6557 | usc_start_receiver(info); | |
6558 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
6559 | } | |
6560 | goto Cleanup; | |
6561 | } | |
6562 | } | |
6563 | ||
6564 | ||
6565 | /* check status of receive frame */ | |
6566 | ||
6567 | status = info->rx_buffer_list[EndIndex].status; | |
6568 | ||
e06922aa AJ |
6569 | if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN | |
6570 | RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) { | |
1da177e4 LT |
6571 | if ( status & RXSTATUS_SHORT_FRAME ) |
6572 | info->icount.rxshort++; | |
6573 | else if ( status & RXSTATUS_ABORT ) | |
6574 | info->icount.rxabort++; | |
6575 | else if ( status & RXSTATUS_OVERRUN ) | |
6576 | info->icount.rxover++; | |
6577 | else { | |
6578 | info->icount.rxcrc++; | |
6579 | if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) | |
0fab6de0 | 6580 | return_frame = true; |
1da177e4 LT |
6581 | } |
6582 | framesize = 0; | |
af69c7f9 | 6583 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 | 6584 | { |
198191c4 KH |
6585 | info->netdev->stats.rx_errors++; |
6586 | info->netdev->stats.rx_frame_errors++; | |
1da177e4 LT |
6587 | } |
6588 | #endif | |
6589 | } else | |
0fab6de0 | 6590 | return_frame = true; |
1da177e4 LT |
6591 | |
6592 | if ( return_frame ) { | |
6593 | /* receive frame has no errors, get frame size. | |
6594 | * The frame size is the starting value of the RCC (which was | |
6595 | * set to 0xffff) minus the ending value of the RCC (decremented | |
6596 | * once for each receive character) minus 2 for the 16-bit CRC. | |
6597 | */ | |
6598 | ||
6599 | framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc; | |
6600 | ||
6601 | /* adjust frame size for CRC if any */ | |
6602 | if ( info->params.crc_type == HDLC_CRC_16_CCITT ) | |
6603 | framesize -= 2; | |
6604 | else if ( info->params.crc_type == HDLC_CRC_32_CCITT ) | |
6605 | framesize -= 4; | |
6606 | } | |
6607 | ||
6608 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
6609 | printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n", | |
6610 | __FILE__,__LINE__,info->device_name,status,framesize); | |
6611 | ||
6612 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
6613 | mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr, | |
6614 | min_t(int, framesize, DMABUFFERSIZE),0); | |
6615 | ||
6616 | if (framesize) { | |
6617 | if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) && | |
6618 | ((framesize+1) > info->max_frame_size) ) || | |
6619 | (framesize > info->max_frame_size) ) | |
6620 | info->icount.rxlong++; | |
6621 | else { | |
6622 | /* copy dma buffer(s) to contiguous intermediate buffer */ | |
6623 | int copy_count = framesize; | |
6624 | int index = StartIndex; | |
6625 | unsigned char *ptmp = info->intermediate_rxbuffer; | |
6626 | ||
6627 | if ( !(status & RXSTATUS_CRC_ERROR)) | |
4bd01622 | 6628 | info->icount.rxok++; |
1da177e4 LT |
6629 | |
6630 | while(copy_count) { | |
6631 | int partial_count; | |
6632 | if ( copy_count > DMABUFFERSIZE ) | |
6633 | partial_count = DMABUFFERSIZE; | |
6634 | else | |
6635 | partial_count = copy_count; | |
6636 | ||
6637 | pBufEntry = &(info->rx_buffer_list[index]); | |
6638 | memcpy( ptmp, pBufEntry->virt_addr, partial_count ); | |
6639 | ptmp += partial_count; | |
6640 | copy_count -= partial_count; | |
6641 | ||
6642 | if ( ++index == info->rx_buffer_count ) | |
6643 | index = 0; | |
6644 | } | |
6645 | ||
6646 | if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) { | |
6647 | ++framesize; | |
6648 | *ptmp = (status & RXSTATUS_CRC_ERROR ? | |
6649 | RX_CRC_ERROR : | |
6650 | RX_OK); | |
6651 | ||
6652 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
6653 | printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n", | |
6654 | __FILE__,__LINE__,info->device_name, | |
6655 | *ptmp); | |
6656 | } | |
6657 | ||
af69c7f9 | 6658 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
6659 | if (info->netcount) |
6660 | hdlcdev_rx(info,info->intermediate_rxbuffer,framesize); | |
6661 | else | |
6662 | #endif | |
6663 | ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize); | |
6664 | } | |
6665 | } | |
6666 | /* Free the buffers used by this frame. */ | |
6667 | mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex ); | |
6668 | ||
0fab6de0 | 6669 | ReturnCode = true; |
1da177e4 LT |
6670 | |
6671 | Cleanup: | |
6672 | ||
6673 | if ( info->rx_enabled && info->rx_overflow ) { | |
6674 | /* The receiver needs to restarted because of | |
6675 | * a receive overflow (buffer or FIFO). If the | |
6676 | * receive buffers are now empty, then restart receiver. | |
6677 | */ | |
6678 | ||
6679 | if ( !info->rx_buffer_list[EndIndex].status && | |
6680 | info->rx_buffer_list[EndIndex].count ) { | |
6681 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
6682 | usc_start_receiver(info); | |
6683 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
6684 | } | |
6685 | } | |
6686 | ||
6687 | return ReturnCode; | |
6688 | ||
6689 | } /* end of mgsl_get_rx_frame() */ | |
6690 | ||
6691 | /* mgsl_get_raw_rx_frame() | |
6692 | * | |
6693 | * This function attempts to return a received frame from the | |
6694 | * receive DMA buffers when running in external loop mode. In this mode, | |
6695 | * we will return at most one DMABUFFERSIZE frame to the application. | |
6696 | * The USC receiver is triggering off of DCD going active to start a new | |
6697 | * frame, and DCD going inactive to terminate the frame (similar to | |
6698 | * processing a closing flag character). | |
6699 | * | |
6700 | * In this routine, we will return DMABUFFERSIZE "chunks" at a time. | |
6701 | * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero | |
6702 | * status field and the RCC field will indicate the length of the | |
6703 | * entire received frame. We take this RCC field and get the modulus | |
6704 | * of RCC and DMABUFFERSIZE to determine if number of bytes in the | |
6705 | * last Rx DMA buffer and return that last portion of the frame. | |
6706 | * | |
6707 | * Arguments: info pointer to device extension | |
0fab6de0 | 6708 | * Return Value: true if frame returned, otherwise false |
1da177e4 | 6709 | */ |
0fab6de0 | 6710 | static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info) |
1da177e4 LT |
6711 | { |
6712 | unsigned int CurrentIndex, NextIndex; | |
6713 | unsigned short status; | |
6714 | DMABUFFERENTRY *pBufEntry; | |
6715 | unsigned int framesize = 0; | |
0fab6de0 | 6716 | bool ReturnCode = false; |
1da177e4 | 6717 | unsigned long flags; |
8fb06c77 | 6718 | struct tty_struct *tty = info->port.tty; |
1da177e4 LT |
6719 | |
6720 | /* | |
6721 | * current_rx_buffer points to the 1st buffer of the next available | |
6722 | * receive frame. The status field is set by the 16C32 after | |
6723 | * completing a receive frame. If the status field of this buffer | |
6724 | * is zero, either the USC is still filling this buffer or this | |
6725 | * is one of a series of buffers making up a received frame. | |
6726 | * | |
6727 | * If the count field of this buffer is zero, the USC is either | |
6728 | * using this buffer or has used this buffer. Look at the count | |
6729 | * field of the next buffer. If that next buffer's count is | |
6730 | * non-zero, the USC is still actively using the current buffer. | |
6731 | * Otherwise, if the next buffer's count field is zero, the | |
6732 | * current buffer is complete and the USC is using the next | |
6733 | * buffer. | |
6734 | */ | |
6735 | CurrentIndex = NextIndex = info->current_rx_buffer; | |
6736 | ++NextIndex; | |
6737 | if ( NextIndex == info->rx_buffer_count ) | |
6738 | NextIndex = 0; | |
6739 | ||
6740 | if ( info->rx_buffer_list[CurrentIndex].status != 0 || | |
6741 | (info->rx_buffer_list[CurrentIndex].count == 0 && | |
6742 | info->rx_buffer_list[NextIndex].count == 0)) { | |
6743 | /* | |
6744 | * Either the status field of this dma buffer is non-zero | |
6745 | * (indicating the last buffer of a receive frame) or the next | |
6746 | * buffer is marked as in use -- implying this buffer is complete | |
6747 | * and an intermediate buffer for this received frame. | |
6748 | */ | |
6749 | ||
6750 | status = info->rx_buffer_list[CurrentIndex].status; | |
6751 | ||
e06922aa AJ |
6752 | if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN | |
6753 | RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) { | |
1da177e4 LT |
6754 | if ( status & RXSTATUS_SHORT_FRAME ) |
6755 | info->icount.rxshort++; | |
6756 | else if ( status & RXSTATUS_ABORT ) | |
6757 | info->icount.rxabort++; | |
6758 | else if ( status & RXSTATUS_OVERRUN ) | |
6759 | info->icount.rxover++; | |
6760 | else | |
6761 | info->icount.rxcrc++; | |
6762 | framesize = 0; | |
6763 | } else { | |
6764 | /* | |
6765 | * A receive frame is available, get frame size and status. | |
6766 | * | |
6767 | * The frame size is the starting value of the RCC (which was | |
6768 | * set to 0xffff) minus the ending value of the RCC (decremented | |
6769 | * once for each receive character) minus 2 or 4 for the 16-bit | |
6770 | * or 32-bit CRC. | |
6771 | * | |
6772 | * If the status field is zero, this is an intermediate buffer. | |
6773 | * It's size is 4K. | |
6774 | * | |
6775 | * If the DMA Buffer Entry's Status field is non-zero, the | |
6776 | * receive operation completed normally (ie: DCD dropped). The | |
6777 | * RCC field is valid and holds the received frame size. | |
6778 | * It is possible that the RCC field will be zero on a DMA buffer | |
6779 | * entry with a non-zero status. This can occur if the total | |
6780 | * frame size (number of bytes between the time DCD goes active | |
6781 | * to the time DCD goes inactive) exceeds 65535 bytes. In this | |
6782 | * case the 16C32 has underrun on the RCC count and appears to | |
6783 | * stop updating this counter to let us know the actual received | |
6784 | * frame size. If this happens (non-zero status and zero RCC), | |
6785 | * simply return the entire RxDMA Buffer | |
6786 | */ | |
6787 | if ( status ) { | |
6788 | /* | |
6789 | * In the event that the final RxDMA Buffer is | |
6790 | * terminated with a non-zero status and the RCC | |
6791 | * field is zero, we interpret this as the RCC | |
6792 | * having underflowed (received frame > 65535 bytes). | |
6793 | * | |
6794 | * Signal the event to the user by passing back | |
6795 | * a status of RxStatus_CrcError returning the full | |
6796 | * buffer and let the app figure out what data is | |
6797 | * actually valid | |
6798 | */ | |
6799 | if ( info->rx_buffer_list[CurrentIndex].rcc ) | |
6800 | framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc; | |
6801 | else | |
6802 | framesize = DMABUFFERSIZE; | |
6803 | } | |
6804 | else | |
6805 | framesize = DMABUFFERSIZE; | |
6806 | } | |
6807 | ||
6808 | if ( framesize > DMABUFFERSIZE ) { | |
6809 | /* | |
6810 | * if running in raw sync mode, ISR handler for | |
6811 | * End Of Buffer events terminates all buffers at 4K. | |
6812 | * If this frame size is said to be >4K, get the | |
6813 | * actual number of bytes of the frame in this buffer. | |
6814 | */ | |
6815 | framesize = framesize % DMABUFFERSIZE; | |
6816 | } | |
6817 | ||
6818 | ||
6819 | if ( debug_level >= DEBUG_LEVEL_BH ) | |
6820 | printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n", | |
6821 | __FILE__,__LINE__,info->device_name,status,framesize); | |
6822 | ||
6823 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
6824 | mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr, | |
6825 | min_t(int, framesize, DMABUFFERSIZE),0); | |
6826 | ||
6827 | if (framesize) { | |
6828 | /* copy dma buffer(s) to contiguous intermediate buffer */ | |
6829 | /* NOTE: we never copy more than DMABUFFERSIZE bytes */ | |
6830 | ||
6831 | pBufEntry = &(info->rx_buffer_list[CurrentIndex]); | |
6832 | memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize); | |
6833 | info->icount.rxok++; | |
6834 | ||
6835 | ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize); | |
6836 | } | |
6837 | ||
6838 | /* Free the buffers used by this frame. */ | |
6839 | mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex ); | |
6840 | ||
0fab6de0 | 6841 | ReturnCode = true; |
1da177e4 LT |
6842 | } |
6843 | ||
6844 | ||
6845 | if ( info->rx_enabled && info->rx_overflow ) { | |
6846 | /* The receiver needs to restarted because of | |
6847 | * a receive overflow (buffer or FIFO). If the | |
6848 | * receive buffers are now empty, then restart receiver. | |
6849 | */ | |
6850 | ||
6851 | if ( !info->rx_buffer_list[CurrentIndex].status && | |
6852 | info->rx_buffer_list[CurrentIndex].count ) { | |
6853 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
6854 | usc_start_receiver(info); | |
6855 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
6856 | } | |
6857 | } | |
6858 | ||
6859 | return ReturnCode; | |
6860 | ||
6861 | } /* end of mgsl_get_raw_rx_frame() */ | |
6862 | ||
6863 | /* mgsl_load_tx_dma_buffer() | |
6864 | * | |
6865 | * Load the transmit DMA buffer with the specified data. | |
6866 | * | |
6867 | * Arguments: | |
6868 | * | |
6869 | * info pointer to device extension | |
6870 | * Buffer pointer to buffer containing frame to load | |
6871 | * BufferSize size in bytes of frame in Buffer | |
6872 | * | |
6873 | * Return Value: None | |
6874 | */ | |
6875 | static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, | |
6876 | const char *Buffer, unsigned int BufferSize) | |
6877 | { | |
6878 | unsigned short Copycount; | |
6879 | unsigned int i = 0; | |
6880 | DMABUFFERENTRY *pBufEntry; | |
6881 | ||
6882 | if ( debug_level >= DEBUG_LEVEL_DATA ) | |
6883 | mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1); | |
6884 | ||
6885 | if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) { | |
6886 | /* set CMR:13 to start transmit when | |
6887 | * next GoAhead (abort) is received | |
6888 | */ | |
e06922aa | 6889 | info->cmr_value |= BIT13; |
1da177e4 LT |
6890 | } |
6891 | ||
6892 | /* begin loading the frame in the next available tx dma | |
6893 | * buffer, remember it's starting location for setting | |
6894 | * up tx dma operation | |
6895 | */ | |
6896 | i = info->current_tx_buffer; | |
6897 | info->start_tx_dma_buffer = i; | |
6898 | ||
6899 | /* Setup the status and RCC (Frame Size) fields of the 1st */ | |
6900 | /* buffer entry in the transmit DMA buffer list. */ | |
6901 | ||
6902 | info->tx_buffer_list[i].status = info->cmr_value & 0xf000; | |
6903 | info->tx_buffer_list[i].rcc = BufferSize; | |
6904 | info->tx_buffer_list[i].count = BufferSize; | |
6905 | ||
6906 | /* Copy frame data from 1st source buffer to the DMA buffers. */ | |
6907 | /* The frame data may span multiple DMA buffers. */ | |
6908 | ||
6909 | while( BufferSize ){ | |
6910 | /* Get a pointer to next DMA buffer entry. */ | |
6911 | pBufEntry = &info->tx_buffer_list[i++]; | |
6912 | ||
6913 | if ( i == info->tx_buffer_count ) | |
6914 | i=0; | |
6915 | ||
6916 | /* Calculate the number of bytes that can be copied from */ | |
6917 | /* the source buffer to this DMA buffer. */ | |
6918 | if ( BufferSize > DMABUFFERSIZE ) | |
6919 | Copycount = DMABUFFERSIZE; | |
6920 | else | |
6921 | Copycount = BufferSize; | |
6922 | ||
6923 | /* Actually copy data from source buffer to DMA buffer. */ | |
6924 | /* Also set the data count for this individual DMA buffer. */ | |
6925 | if ( info->bus_type == MGSL_BUS_TYPE_PCI ) | |
6926 | mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount); | |
6927 | else | |
6928 | memcpy(pBufEntry->virt_addr, Buffer, Copycount); | |
6929 | ||
6930 | pBufEntry->count = Copycount; | |
6931 | ||
6932 | /* Advance source pointer and reduce remaining data count. */ | |
6933 | Buffer += Copycount; | |
6934 | BufferSize -= Copycount; | |
6935 | ||
6936 | ++info->tx_dma_buffers_used; | |
6937 | } | |
6938 | ||
6939 | /* remember next available tx dma buffer */ | |
6940 | info->current_tx_buffer = i; | |
6941 | ||
6942 | } /* end of mgsl_load_tx_dma_buffer() */ | |
6943 | ||
6944 | /* | |
6945 | * mgsl_register_test() | |
6946 | * | |
6947 | * Performs a register test of the 16C32. | |
6948 | * | |
6949 | * Arguments: info pointer to device instance data | |
0fab6de0 | 6950 | * Return Value: true if test passed, otherwise false |
1da177e4 | 6951 | */ |
0fab6de0 | 6952 | static bool mgsl_register_test( struct mgsl_struct *info ) |
1da177e4 LT |
6953 | { |
6954 | static unsigned short BitPatterns[] = | |
6955 | { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f }; | |
fe971071 | 6956 | static unsigned int Patterncount = ARRAY_SIZE(BitPatterns); |
1da177e4 | 6957 | unsigned int i; |
0fab6de0 | 6958 | bool rc = true; |
1da177e4 LT |
6959 | unsigned long flags; |
6960 | ||
6961 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
6962 | usc_reset(info); | |
6963 | ||
6964 | /* Verify the reset state of some registers. */ | |
6965 | ||
6966 | if ( (usc_InReg( info, SICR ) != 0) || | |
6967 | (usc_InReg( info, IVR ) != 0) || | |
6968 | (usc_InDmaReg( info, DIVR ) != 0) ){ | |
0fab6de0 | 6969 | rc = false; |
1da177e4 LT |
6970 | } |
6971 | ||
0fab6de0 | 6972 | if ( rc ){ |
1da177e4 LT |
6973 | /* Write bit patterns to various registers but do it out of */ |
6974 | /* sync, then read back and verify values. */ | |
6975 | ||
6976 | for ( i = 0 ; i < Patterncount ; i++ ) { | |
6977 | usc_OutReg( info, TC0R, BitPatterns[i] ); | |
6978 | usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] ); | |
6979 | usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] ); | |
6980 | usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] ); | |
6981 | usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] ); | |
6982 | usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] ); | |
6983 | ||
6984 | if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) || | |
6985 | (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) || | |
6986 | (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) || | |
6987 | (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) || | |
6988 | (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) || | |
6989 | (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){ | |
0fab6de0 | 6990 | rc = false; |
1da177e4 LT |
6991 | break; |
6992 | } | |
6993 | } | |
6994 | } | |
6995 | ||
6996 | usc_reset(info); | |
6997 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
6998 | ||
6999 | return rc; | |
7000 | ||
7001 | } /* end of mgsl_register_test() */ | |
7002 | ||
7003 | /* mgsl_irq_test() Perform interrupt test of the 16C32. | |
7004 | * | |
7005 | * Arguments: info pointer to device instance data | |
0fab6de0 | 7006 | * Return Value: true if test passed, otherwise false |
1da177e4 | 7007 | */ |
0fab6de0 | 7008 | static bool mgsl_irq_test( struct mgsl_struct *info ) |
1da177e4 LT |
7009 | { |
7010 | unsigned long EndTime; | |
7011 | unsigned long flags; | |
7012 | ||
7013 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7014 | usc_reset(info); | |
7015 | ||
7016 | /* | |
7017 | * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition. | |
0fab6de0 | 7018 | * The ISR sets irq_occurred to true. |
1da177e4 LT |
7019 | */ |
7020 | ||
0fab6de0 | 7021 | info->irq_occurred = false; |
1da177e4 LT |
7022 | |
7023 | /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */ | |
7024 | /* Enable INTEN (Port 6, Bit12) */ | |
7025 | /* This connects the IRQ request signal to the ISA bus */ | |
7026 | /* on the ISA adapter. This has no effect for the PCI adapter */ | |
7027 | usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) ); | |
7028 | ||
7029 | usc_EnableMasterIrqBit(info); | |
7030 | usc_EnableInterrupts(info, IO_PIN); | |
7031 | usc_ClearIrqPendingBits(info, IO_PIN); | |
7032 | ||
7033 | usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED); | |
7034 | usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE); | |
7035 | ||
7036 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7037 | ||
7038 | EndTime=100; | |
7039 | while( EndTime-- && !info->irq_occurred ) { | |
7040 | msleep_interruptible(10); | |
7041 | } | |
7042 | ||
7043 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7044 | usc_reset(info); | |
7045 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7046 | ||
0fab6de0 | 7047 | return info->irq_occurred; |
1da177e4 LT |
7048 | |
7049 | } /* end of mgsl_irq_test() */ | |
7050 | ||
7051 | /* mgsl_dma_test() | |
7052 | * | |
7053 | * Perform a DMA test of the 16C32. A small frame is | |
7054 | * transmitted via DMA from a transmit buffer to a receive buffer | |
7055 | * using single buffer DMA mode. | |
7056 | * | |
7057 | * Arguments: info pointer to device instance data | |
0fab6de0 | 7058 | * Return Value: true if test passed, otherwise false |
1da177e4 | 7059 | */ |
0fab6de0 | 7060 | static bool mgsl_dma_test( struct mgsl_struct *info ) |
1da177e4 LT |
7061 | { |
7062 | unsigned short FifoLevel; | |
7063 | unsigned long phys_addr; | |
7064 | unsigned int FrameSize; | |
7065 | unsigned int i; | |
7066 | char *TmpPtr; | |
0fab6de0 | 7067 | bool rc = true; |
1da177e4 LT |
7068 | unsigned short status=0; |
7069 | unsigned long EndTime; | |
7070 | unsigned long flags; | |
7071 | MGSL_PARAMS tmp_params; | |
7072 | ||
7073 | /* save current port options */ | |
7074 | memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS)); | |
7075 | /* load default port options */ | |
7076 | memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS)); | |
7077 | ||
7078 | #define TESTFRAMESIZE 40 | |
7079 | ||
7080 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7081 | ||
7082 | /* setup 16C32 for SDLC DMA transfer mode */ | |
7083 | ||
7084 | usc_reset(info); | |
7085 | usc_set_sdlc_mode(info); | |
7086 | usc_enable_loopback(info,1); | |
7087 | ||
7088 | /* Reprogram the RDMR so that the 16C32 does NOT clear the count | |
7089 | * field of the buffer entry after fetching buffer address. This | |
7090 | * way we can detect a DMA failure for a DMA read (which should be | |
7091 | * non-destructive to system memory) before we try and write to | |
7092 | * memory (where a failure could corrupt system memory). | |
7093 | */ | |
7094 | ||
7095 | /* Receive DMA mode Register (RDMR) | |
7096 | * | |
7097 | * <15..14> 11 DMA mode = Linked List Buffer mode | |
7098 | * <13> 1 RSBinA/L = store Rx status Block in List entry | |
7099 | * <12> 0 1 = Clear count of List Entry after fetching | |
7100 | * <11..10> 00 Address mode = Increment | |
7101 | * <9> 1 Terminate Buffer on RxBound | |
7102 | * <8> 0 Bus Width = 16bits | |
7103 | * <7..0> ? status Bits (write as 0s) | |
7104 | * | |
7105 | * 1110 0010 0000 0000 = 0xe200 | |
7106 | */ | |
7107 | ||
7108 | usc_OutDmaReg( info, RDMR, 0xe200 ); | |
7109 | ||
7110 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7111 | ||
7112 | ||
7113 | /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */ | |
7114 | ||
7115 | FrameSize = TESTFRAMESIZE; | |
7116 | ||
7117 | /* setup 1st transmit buffer entry: */ | |
7118 | /* with frame size and transmit control word */ | |
7119 | ||
7120 | info->tx_buffer_list[0].count = FrameSize; | |
7121 | info->tx_buffer_list[0].rcc = FrameSize; | |
7122 | info->tx_buffer_list[0].status = 0x4000; | |
7123 | ||
7124 | /* build a transmit frame in 1st transmit DMA buffer */ | |
7125 | ||
7126 | TmpPtr = info->tx_buffer_list[0].virt_addr; | |
7127 | for (i = 0; i < FrameSize; i++ ) | |
7128 | *TmpPtr++ = i; | |
7129 | ||
7130 | /* setup 1st receive buffer entry: */ | |
7131 | /* clear status, set max receive buffer size */ | |
7132 | ||
7133 | info->rx_buffer_list[0].status = 0; | |
7134 | info->rx_buffer_list[0].count = FrameSize + 4; | |
7135 | ||
7136 | /* zero out the 1st receive buffer */ | |
7137 | ||
7138 | memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 ); | |
7139 | ||
7140 | /* Set count field of next buffer entries to prevent */ | |
7141 | /* 16C32 from using buffers after the 1st one. */ | |
7142 | ||
7143 | info->tx_buffer_list[1].count = 0; | |
7144 | info->rx_buffer_list[1].count = 0; | |
7145 | ||
7146 | ||
7147 | /***************************/ | |
7148 | /* Program 16C32 receiver. */ | |
7149 | /***************************/ | |
7150 | ||
7151 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7152 | ||
7153 | /* setup DMA transfers */ | |
7154 | usc_RTCmd( info, RTCmd_PurgeRxFifo ); | |
7155 | ||
7156 | /* program 16C32 receiver with physical address of 1st DMA buffer entry */ | |
7157 | phys_addr = info->rx_buffer_list[0].phys_entry; | |
7158 | usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr ); | |
7159 | usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) ); | |
7160 | ||
7161 | /* Clear the Rx DMA status bits (read RDMR) and start channel */ | |
7162 | usc_InDmaReg( info, RDMR ); | |
7163 | usc_DmaCmd( info, DmaCmd_InitRxChannel ); | |
7164 | ||
7165 | /* Enable Receiver (RMR <1..0> = 10) */ | |
7166 | usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) ); | |
7167 | ||
7168 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7169 | ||
7170 | ||
7171 | /*************************************************************/ | |
7172 | /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */ | |
7173 | /*************************************************************/ | |
7174 | ||
7175 | /* Wait 100ms for interrupt. */ | |
7176 | EndTime = jiffies + msecs_to_jiffies(100); | |
7177 | ||
7178 | for(;;) { | |
7179 | if (time_after(jiffies, EndTime)) { | |
0fab6de0 | 7180 | rc = false; |
1da177e4 LT |
7181 | break; |
7182 | } | |
7183 | ||
7184 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7185 | status = usc_InDmaReg( info, RDMR ); | |
7186 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7187 | ||
7188 | if ( !(status & BIT4) && (status & BIT5) ) { | |
7189 | /* INITG (BIT 4) is inactive (no entry read in progress) AND */ | |
7190 | /* BUSY (BIT 5) is active (channel still active). */ | |
7191 | /* This means the buffer entry read has completed. */ | |
7192 | break; | |
7193 | } | |
7194 | } | |
7195 | ||
7196 | ||
7197 | /******************************/ | |
7198 | /* Program 16C32 transmitter. */ | |
7199 | /******************************/ | |
7200 | ||
7201 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7202 | ||
7203 | /* Program the Transmit Character Length Register (TCLR) */ | |
7204 | /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */ | |
7205 | ||
7206 | usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count ); | |
7207 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); | |
7208 | ||
7209 | /* Program the address of the 1st DMA Buffer Entry in linked list */ | |
7210 | ||
7211 | phys_addr = info->tx_buffer_list[0].phys_entry; | |
7212 | usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr ); | |
7213 | usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) ); | |
7214 | ||
7215 | /* unlatch Tx status bits, and start transmit channel. */ | |
7216 | ||
7217 | usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) ); | |
7218 | usc_DmaCmd( info, DmaCmd_InitTxChannel ); | |
7219 | ||
7220 | /* wait for DMA controller to fill transmit FIFO */ | |
7221 | ||
7222 | usc_TCmd( info, TCmd_SelectTicrTxFifostatus ); | |
7223 | ||
7224 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7225 | ||
7226 | ||
7227 | /**********************************/ | |
7228 | /* WAIT FOR TRANSMIT FIFO TO FILL */ | |
7229 | /**********************************/ | |
7230 | ||
7231 | /* Wait 100ms */ | |
7232 | EndTime = jiffies + msecs_to_jiffies(100); | |
7233 | ||
7234 | for(;;) { | |
7235 | if (time_after(jiffies, EndTime)) { | |
0fab6de0 | 7236 | rc = false; |
1da177e4 LT |
7237 | break; |
7238 | } | |
7239 | ||
7240 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7241 | FifoLevel = usc_InReg(info, TICR) >> 8; | |
7242 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7243 | ||
7244 | if ( FifoLevel < 16 ) | |
7245 | break; | |
7246 | else | |
7247 | if ( FrameSize < 32 ) { | |
7248 | /* This frame is smaller than the entire transmit FIFO */ | |
7249 | /* so wait for the entire frame to be loaded. */ | |
7250 | if ( FifoLevel <= (32 - FrameSize) ) | |
7251 | break; | |
7252 | } | |
7253 | } | |
7254 | ||
7255 | ||
0fab6de0 | 7256 | if ( rc ) |
1da177e4 LT |
7257 | { |
7258 | /* Enable 16C32 transmitter. */ | |
7259 | ||
7260 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7261 | ||
7262 | /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */ | |
7263 | usc_TCmd( info, TCmd_SendFrame ); | |
7264 | usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) ); | |
7265 | ||
7266 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7267 | ||
e06922aa | 7268 | |
1da177e4 LT |
7269 | /******************************/ |
7270 | /* WAIT FOR TRANSMIT COMPLETE */ | |
7271 | /******************************/ | |
7272 | ||
7273 | /* Wait 100ms */ | |
7274 | EndTime = jiffies + msecs_to_jiffies(100); | |
7275 | ||
7276 | /* While timer not expired wait for transmit complete */ | |
7277 | ||
7278 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7279 | status = usc_InReg( info, TCSR ); | |
7280 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7281 | ||
e06922aa | 7282 | while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { |
1da177e4 | 7283 | if (time_after(jiffies, EndTime)) { |
0fab6de0 | 7284 | rc = false; |
1da177e4 LT |
7285 | break; |
7286 | } | |
7287 | ||
7288 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7289 | status = usc_InReg( info, TCSR ); | |
7290 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7291 | } | |
7292 | } | |
7293 | ||
7294 | ||
0fab6de0 | 7295 | if ( rc ){ |
1da177e4 | 7296 | /* CHECK FOR TRANSMIT ERRORS */ |
e06922aa | 7297 | if ( status & (BIT5 | BIT1) ) |
0fab6de0 | 7298 | rc = false; |
1da177e4 LT |
7299 | } |
7300 | ||
0fab6de0 | 7301 | if ( rc ) { |
1da177e4 LT |
7302 | /* WAIT FOR RECEIVE COMPLETE */ |
7303 | ||
7304 | /* Wait 100ms */ | |
7305 | EndTime = jiffies + msecs_to_jiffies(100); | |
7306 | ||
7307 | /* Wait for 16C32 to write receive status to buffer entry. */ | |
7308 | status=info->rx_buffer_list[0].status; | |
7309 | while ( status == 0 ) { | |
7310 | if (time_after(jiffies, EndTime)) { | |
0fab6de0 | 7311 | rc = false; |
1da177e4 LT |
7312 | break; |
7313 | } | |
7314 | status=info->rx_buffer_list[0].status; | |
7315 | } | |
7316 | } | |
7317 | ||
7318 | ||
0fab6de0 | 7319 | if ( rc ) { |
1da177e4 LT |
7320 | /* CHECK FOR RECEIVE ERRORS */ |
7321 | status = info->rx_buffer_list[0].status; | |
7322 | ||
e06922aa | 7323 | if ( status & (BIT8 | BIT3 | BIT1) ) { |
1da177e4 | 7324 | /* receive error has occurred */ |
0fab6de0 | 7325 | rc = false; |
1da177e4 LT |
7326 | } else { |
7327 | if ( memcmp( info->tx_buffer_list[0].virt_addr , | |
7328 | info->rx_buffer_list[0].virt_addr, FrameSize ) ){ | |
0fab6de0 | 7329 | rc = false; |
1da177e4 LT |
7330 | } |
7331 | } | |
7332 | } | |
7333 | ||
7334 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7335 | usc_reset( info ); | |
7336 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7337 | ||
7338 | /* restore current port options */ | |
7339 | memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS)); | |
7340 | ||
7341 | return rc; | |
7342 | ||
7343 | } /* end of mgsl_dma_test() */ | |
7344 | ||
7345 | /* mgsl_adapter_test() | |
7346 | * | |
7347 | * Perform the register, IRQ, and DMA tests for the 16C32. | |
7348 | * | |
7349 | * Arguments: info pointer to device instance data | |
7350 | * Return Value: 0 if success, otherwise -ENODEV | |
7351 | */ | |
7352 | static int mgsl_adapter_test( struct mgsl_struct *info ) | |
7353 | { | |
7354 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
7355 | printk( "%s(%d):Testing device %s\n", | |
7356 | __FILE__,__LINE__,info->device_name ); | |
7357 | ||
7358 | if ( !mgsl_register_test( info ) ) { | |
7359 | info->init_error = DiagStatus_AddressFailure; | |
7360 | printk( "%s(%d):Register test failure for device %s Addr=%04X\n", | |
7361 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) ); | |
7362 | return -ENODEV; | |
7363 | } | |
7364 | ||
7365 | if ( !mgsl_irq_test( info ) ) { | |
7366 | info->init_error = DiagStatus_IrqFailure; | |
7367 | printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n", | |
7368 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) ); | |
7369 | return -ENODEV; | |
7370 | } | |
7371 | ||
7372 | if ( !mgsl_dma_test( info ) ) { | |
7373 | info->init_error = DiagStatus_DmaFailure; | |
7374 | printk( "%s(%d):DMA test failure for device %s DMA=%d\n", | |
7375 | __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) ); | |
7376 | return -ENODEV; | |
7377 | } | |
7378 | ||
7379 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
7380 | printk( "%s(%d):device %s passed diagnostics\n", | |
7381 | __FILE__,__LINE__,info->device_name ); | |
7382 | ||
7383 | return 0; | |
7384 | ||
7385 | } /* end of mgsl_adapter_test() */ | |
7386 | ||
7387 | /* mgsl_memory_test() | |
7388 | * | |
7389 | * Test the shared memory on a PCI adapter. | |
7390 | * | |
7391 | * Arguments: info pointer to device instance data | |
0fab6de0 | 7392 | * Return Value: true if test passed, otherwise false |
1da177e4 | 7393 | */ |
0fab6de0 | 7394 | static bool mgsl_memory_test( struct mgsl_struct *info ) |
1da177e4 | 7395 | { |
fe971071 TK |
7396 | static unsigned long BitPatterns[] = |
7397 | { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 }; | |
7398 | unsigned long Patterncount = ARRAY_SIZE(BitPatterns); | |
1da177e4 LT |
7399 | unsigned long i; |
7400 | unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long); | |
7401 | unsigned long * TestAddr; | |
7402 | ||
7403 | if ( info->bus_type != MGSL_BUS_TYPE_PCI ) | |
0fab6de0 | 7404 | return true; |
1da177e4 LT |
7405 | |
7406 | TestAddr = (unsigned long *)info->memory_base; | |
7407 | ||
7408 | /* Test data lines with test pattern at one location. */ | |
7409 | ||
7410 | for ( i = 0 ; i < Patterncount ; i++ ) { | |
7411 | *TestAddr = BitPatterns[i]; | |
7412 | if ( *TestAddr != BitPatterns[i] ) | |
0fab6de0 | 7413 | return false; |
1da177e4 LT |
7414 | } |
7415 | ||
7416 | /* Test address lines with incrementing pattern over */ | |
7417 | /* entire address range. */ | |
7418 | ||
7419 | for ( i = 0 ; i < TestLimit ; i++ ) { | |
7420 | *TestAddr = i * 4; | |
7421 | TestAddr++; | |
7422 | } | |
7423 | ||
7424 | TestAddr = (unsigned long *)info->memory_base; | |
7425 | ||
7426 | for ( i = 0 ; i < TestLimit ; i++ ) { | |
7427 | if ( *TestAddr != i * 4 ) | |
0fab6de0 | 7428 | return false; |
1da177e4 LT |
7429 | TestAddr++; |
7430 | } | |
7431 | ||
7432 | memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE ); | |
7433 | ||
0fab6de0 | 7434 | return true; |
1da177e4 LT |
7435 | |
7436 | } /* End Of mgsl_memory_test() */ | |
7437 | ||
7438 | ||
7439 | /* mgsl_load_pci_memory() | |
7440 | * | |
7441 | * Load a large block of data into the PCI shared memory. | |
7442 | * Use this instead of memcpy() or memmove() to move data | |
7443 | * into the PCI shared memory. | |
7444 | * | |
7445 | * Notes: | |
7446 | * | |
7447 | * This function prevents the PCI9050 interface chip from hogging | |
7448 | * the adapter local bus, which can starve the 16C32 by preventing | |
7449 | * 16C32 bus master cycles. | |
7450 | * | |
7451 | * The PCI9050 documentation says that the 9050 will always release | |
7452 | * control of the local bus after completing the current read | |
7453 | * or write operation. | |
7454 | * | |
7455 | * It appears that as long as the PCI9050 write FIFO is full, the | |
7456 | * PCI9050 treats all of the writes as a single burst transaction | |
7457 | * and will not release the bus. This causes DMA latency problems | |
7458 | * at high speeds when copying large data blocks to the shared | |
7459 | * memory. | |
7460 | * | |
7461 | * This function in effect, breaks the a large shared memory write | |
7462 | * into multiple transations by interleaving a shared memory read | |
7463 | * which will flush the write FIFO and 'complete' the write | |
7464 | * transation. This allows any pending DMA request to gain control | |
7465 | * of the local bus in a timely fasion. | |
7466 | * | |
7467 | * Arguments: | |
7468 | * | |
7469 | * TargetPtr pointer to target address in PCI shared memory | |
7470 | * SourcePtr pointer to source buffer for data | |
7471 | * count count in bytes of data to copy | |
7472 | * | |
7473 | * Return Value: None | |
7474 | */ | |
7475 | static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr, | |
7476 | unsigned short count ) | |
7477 | { | |
7478 | /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */ | |
7479 | #define PCI_LOAD_INTERVAL 64 | |
7480 | ||
7481 | unsigned short Intervalcount = count / PCI_LOAD_INTERVAL; | |
7482 | unsigned short Index; | |
7483 | unsigned long Dummy; | |
7484 | ||
7485 | for ( Index = 0 ; Index < Intervalcount ; Index++ ) | |
7486 | { | |
7487 | memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL); | |
7488 | Dummy = *((volatile unsigned long *)TargetPtr); | |
7489 | TargetPtr += PCI_LOAD_INTERVAL; | |
7490 | SourcePtr += PCI_LOAD_INTERVAL; | |
7491 | } | |
7492 | ||
7493 | memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL ); | |
7494 | ||
7495 | } /* End Of mgsl_load_pci_memory() */ | |
7496 | ||
7497 | static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit) | |
7498 | { | |
7499 | int i; | |
7500 | int linecount; | |
7501 | if (xmit) | |
7502 | printk("%s tx data:\n",info->device_name); | |
7503 | else | |
7504 | printk("%s rx data:\n",info->device_name); | |
7505 | ||
7506 | while(count) { | |
7507 | if (count > 16) | |
7508 | linecount = 16; | |
7509 | else | |
7510 | linecount = count; | |
7511 | ||
7512 | for(i=0;i<linecount;i++) | |
7513 | printk("%02X ",(unsigned char)data[i]); | |
7514 | for(;i<17;i++) | |
7515 | printk(" "); | |
7516 | for(i=0;i<linecount;i++) { | |
7517 | if (data[i]>=040 && data[i]<=0176) | |
7518 | printk("%c",data[i]); | |
7519 | else | |
7520 | printk("."); | |
7521 | } | |
7522 | printk("\n"); | |
7523 | ||
7524 | data += linecount; | |
7525 | count -= linecount; | |
7526 | } | |
7527 | } /* end of mgsl_trace_block() */ | |
7528 | ||
7529 | /* mgsl_tx_timeout() | |
7530 | * | |
7531 | * called when HDLC frame times out | |
7532 | * update stats and do tx completion processing | |
7533 | * | |
7534 | * Arguments: context pointer to device instance data | |
7535 | * Return Value: None | |
7536 | */ | |
7537 | static void mgsl_tx_timeout(unsigned long context) | |
7538 | { | |
7539 | struct mgsl_struct *info = (struct mgsl_struct*)context; | |
7540 | unsigned long flags; | |
7541 | ||
7542 | if ( debug_level >= DEBUG_LEVEL_INFO ) | |
7543 | printk( "%s(%d):mgsl_tx_timeout(%s)\n", | |
7544 | __FILE__,__LINE__,info->device_name); | |
7545 | if(info->tx_active && | |
7546 | (info->params.mode == MGSL_MODE_HDLC || | |
7547 | info->params.mode == MGSL_MODE_RAW) ) { | |
7548 | info->icount.txtimeout++; | |
7549 | } | |
7550 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
0fab6de0 | 7551 | info->tx_active = false; |
1da177e4 LT |
7552 | info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; |
7553 | ||
7554 | if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE ) | |
7555 | usc_loopmode_cancel_transmit( info ); | |
7556 | ||
7557 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7558 | ||
af69c7f9 | 7559 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
7560 | if (info->netcount) |
7561 | hdlcdev_tx_done(info); | |
7562 | else | |
7563 | #endif | |
7564 | mgsl_bh_transmit(info); | |
7565 | ||
7566 | } /* end of mgsl_tx_timeout() */ | |
7567 | ||
7568 | /* signal that there are no more frames to send, so that | |
7569 | * line is 'released' by echoing RxD to TxD when current | |
7570 | * transmission is complete (or immediately if no tx in progress). | |
7571 | */ | |
7572 | static int mgsl_loopmode_send_done( struct mgsl_struct * info ) | |
7573 | { | |
7574 | unsigned long flags; | |
7575 | ||
7576 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7577 | if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) { | |
7578 | if (info->tx_active) | |
0fab6de0 | 7579 | info->loopmode_send_done_requested = true; |
1da177e4 LT |
7580 | else |
7581 | usc_loopmode_send_done(info); | |
7582 | } | |
7583 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7584 | ||
7585 | return 0; | |
7586 | } | |
7587 | ||
7588 | /* release the line by echoing RxD to TxD | |
7589 | * upon completion of a transmit frame | |
7590 | */ | |
7591 | static void usc_loopmode_send_done( struct mgsl_struct * info ) | |
7592 | { | |
0fab6de0 | 7593 | info->loopmode_send_done_requested = false; |
1da177e4 | 7594 | /* clear CMR:13 to 0 to start echoing RxData to TxData */ |
e06922aa | 7595 | info->cmr_value &= ~BIT13; |
1da177e4 LT |
7596 | usc_OutReg(info, CMR, info->cmr_value); |
7597 | } | |
7598 | ||
7599 | /* abort a transmit in progress while in HDLC LoopMode | |
7600 | */ | |
7601 | static void usc_loopmode_cancel_transmit( struct mgsl_struct * info ) | |
7602 | { | |
7603 | /* reset tx dma channel and purge TxFifo */ | |
7604 | usc_RTCmd( info, RTCmd_PurgeTxFifo ); | |
7605 | usc_DmaCmd( info, DmaCmd_ResetTxChannel ); | |
7606 | usc_loopmode_send_done( info ); | |
7607 | } | |
7608 | ||
7609 | /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled | |
7610 | * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort) | |
7611 | * we must clear CMR:13 to begin repeating TxData to RxData | |
7612 | */ | |
7613 | static void usc_loopmode_insert_request( struct mgsl_struct * info ) | |
7614 | { | |
0fab6de0 | 7615 | info->loopmode_insert_requested = true; |
1da177e4 LT |
7616 | |
7617 | /* enable RxAbort irq. On next RxAbort, clear CMR:13 to | |
7618 | * begin repeating TxData on RxData (complete insertion) | |
7619 | */ | |
7620 | usc_OutReg( info, RICR, | |
7621 | (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) ); | |
7622 | ||
7623 | /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */ | |
7624 | info->cmr_value |= BIT13; | |
7625 | usc_OutReg(info, CMR, info->cmr_value); | |
7626 | } | |
7627 | ||
7628 | /* return 1 if station is inserted into the loop, otherwise 0 | |
7629 | */ | |
7630 | static int usc_loopmode_active( struct mgsl_struct * info) | |
7631 | { | |
7632 | return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ; | |
7633 | } | |
7634 | ||
af69c7f9 | 7635 | #if SYNCLINK_GENERIC_HDLC |
1da177e4 LT |
7636 | |
7637 | /** | |
7638 | * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.) | |
7639 | * set encoding and frame check sequence (FCS) options | |
7640 | * | |
7641 | * dev pointer to network device structure | |
7642 | * encoding serial encoding setting | |
7643 | * parity FCS setting | |
7644 | * | |
7645 | * returns 0 if success, otherwise error code | |
7646 | */ | |
7647 | static int hdlcdev_attach(struct net_device *dev, unsigned short encoding, | |
7648 | unsigned short parity) | |
7649 | { | |
7650 | struct mgsl_struct *info = dev_to_port(dev); | |
7651 | unsigned char new_encoding; | |
7652 | unsigned short new_crctype; | |
7653 | ||
7654 | /* return error if TTY interface open */ | |
8fb06c77 | 7655 | if (info->port.count) |
1da177e4 LT |
7656 | return -EBUSY; |
7657 | ||
7658 | switch (encoding) | |
7659 | { | |
7660 | case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break; | |
7661 | case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break; | |
7662 | case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break; | |
7663 | case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break; | |
7664 | case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break; | |
7665 | default: return -EINVAL; | |
7666 | } | |
7667 | ||
7668 | switch (parity) | |
7669 | { | |
7670 | case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break; | |
7671 | case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break; | |
7672 | case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break; | |
7673 | default: return -EINVAL; | |
7674 | } | |
7675 | ||
7676 | info->params.encoding = new_encoding; | |
53b3531b | 7677 | info->params.crc_type = new_crctype; |
1da177e4 LT |
7678 | |
7679 | /* if network interface up, reprogram hardware */ | |
7680 | if (info->netcount) | |
7681 | mgsl_program_hw(info); | |
7682 | ||
7683 | return 0; | |
7684 | } | |
7685 | ||
7686 | /** | |
7687 | * called by generic HDLC layer to send frame | |
7688 | * | |
7689 | * skb socket buffer containing HDLC frame | |
7690 | * dev pointer to network device structure | |
1da177e4 | 7691 | */ |
4c5d502d SH |
7692 | static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb, |
7693 | struct net_device *dev) | |
1da177e4 LT |
7694 | { |
7695 | struct mgsl_struct *info = dev_to_port(dev); | |
1da177e4 LT |
7696 | unsigned long flags; |
7697 | ||
7698 | if (debug_level >= DEBUG_LEVEL_INFO) | |
7699 | printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name); | |
7700 | ||
7701 | /* stop sending until this frame completes */ | |
7702 | netif_stop_queue(dev); | |
7703 | ||
7704 | /* copy data to device buffers */ | |
7705 | info->xmit_cnt = skb->len; | |
7706 | mgsl_load_tx_dma_buffer(info, skb->data, skb->len); | |
7707 | ||
7708 | /* update network statistics */ | |
198191c4 KH |
7709 | dev->stats.tx_packets++; |
7710 | dev->stats.tx_bytes += skb->len; | |
1da177e4 LT |
7711 | |
7712 | /* done with socket buffer, so free it */ | |
7713 | dev_kfree_skb(skb); | |
7714 | ||
7715 | /* save start time for transmit timeout detection */ | |
7716 | dev->trans_start = jiffies; | |
7717 | ||
7718 | /* start hardware transmitter if necessary */ | |
7719 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7720 | if (!info->tx_active) | |
7721 | usc_start_transmitter(info); | |
7722 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7723 | ||
4c5d502d | 7724 | return NETDEV_TX_OK; |
1da177e4 LT |
7725 | } |
7726 | ||
7727 | /** | |
7728 | * called by network layer when interface enabled | |
7729 | * claim resources and initialize hardware | |
7730 | * | |
7731 | * dev pointer to network device structure | |
7732 | * | |
7733 | * returns 0 if success, otherwise error code | |
7734 | */ | |
7735 | static int hdlcdev_open(struct net_device *dev) | |
7736 | { | |
7737 | struct mgsl_struct *info = dev_to_port(dev); | |
7738 | int rc; | |
7739 | unsigned long flags; | |
7740 | ||
7741 | if (debug_level >= DEBUG_LEVEL_INFO) | |
7742 | printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name); | |
7743 | ||
7744 | /* generic HDLC layer open processing */ | |
a271ca37 GKH |
7745 | rc = hdlc_open(dev); |
7746 | if (rc) | |
1da177e4 LT |
7747 | return rc; |
7748 | ||
7749 | /* arbitrate between network and tty opens */ | |
7750 | spin_lock_irqsave(&info->netlock, flags); | |
8fb06c77 | 7751 | if (info->port.count != 0 || info->netcount != 0) { |
1da177e4 LT |
7752 | printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name); |
7753 | spin_unlock_irqrestore(&info->netlock, flags); | |
7754 | return -EBUSY; | |
7755 | } | |
7756 | info->netcount=1; | |
7757 | spin_unlock_irqrestore(&info->netlock, flags); | |
7758 | ||
7759 | /* claim resources and init adapter */ | |
7760 | if ((rc = startup(info)) != 0) { | |
7761 | spin_lock_irqsave(&info->netlock, flags); | |
7762 | info->netcount=0; | |
7763 | spin_unlock_irqrestore(&info->netlock, flags); | |
7764 | return rc; | |
7765 | } | |
7766 | ||
9fe8074b JP |
7767 | /* assert RTS and DTR, apply hardware settings */ |
7768 | info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR; | |
1da177e4 LT |
7769 | mgsl_program_hw(info); |
7770 | ||
7771 | /* enable network layer transmit */ | |
7772 | dev->trans_start = jiffies; | |
7773 | netif_start_queue(dev); | |
7774 | ||
7775 | /* inform generic HDLC layer of current DCD status */ | |
7776 | spin_lock_irqsave(&info->irq_spinlock, flags); | |
7777 | usc_get_serial_signals(info); | |
7778 | spin_unlock_irqrestore(&info->irq_spinlock, flags); | |
fbeff3c1 KH |
7779 | if (info->serial_signals & SerialSignal_DCD) |
7780 | netif_carrier_on(dev); | |
7781 | else | |
7782 | netif_carrier_off(dev); | |
1da177e4 LT |
7783 | return 0; |
7784 | } | |
7785 | ||
7786 | /** | |
7787 | * called by network layer when interface is disabled | |
7788 | * shutdown hardware and release resources | |
7789 | * | |
7790 | * dev pointer to network device structure | |
7791 | * | |
7792 | * returns 0 if success, otherwise error code | |
7793 | */ | |
7794 | static int hdlcdev_close(struct net_device *dev) | |
7795 | { | |
7796 | struct mgsl_struct *info = dev_to_port(dev); | |
7797 | unsigned long flags; | |
7798 | ||
7799 | if (debug_level >= DEBUG_LEVEL_INFO) | |
7800 | printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name); | |
7801 | ||
7802 | netif_stop_queue(dev); | |
7803 | ||
7804 | /* shutdown adapter and release resources */ | |
7805 | shutdown(info); | |
7806 | ||
7807 | hdlc_close(dev); | |
7808 | ||
7809 | spin_lock_irqsave(&info->netlock, flags); | |
7810 | info->netcount=0; | |
7811 | spin_unlock_irqrestore(&info->netlock, flags); | |
7812 | ||
7813 | return 0; | |
7814 | } | |
7815 | ||
7816 | /** | |
7817 | * called by network layer to process IOCTL call to network device | |
7818 | * | |
7819 | * dev pointer to network device structure | |
7820 | * ifr pointer to network interface request structure | |
7821 | * cmd IOCTL command code | |
7822 | * | |
7823 | * returns 0 if success, otherwise error code | |
7824 | */ | |
7825 | static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
7826 | { | |
7827 | const size_t size = sizeof(sync_serial_settings); | |
7828 | sync_serial_settings new_line; | |
7829 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
7830 | struct mgsl_struct *info = dev_to_port(dev); | |
7831 | unsigned int flags; | |
7832 | ||
7833 | if (debug_level >= DEBUG_LEVEL_INFO) | |
7834 | printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name); | |
7835 | ||
7836 | /* return error if TTY interface open */ | |
8fb06c77 | 7837 | if (info->port.count) |
1da177e4 LT |
7838 | return -EBUSY; |
7839 | ||
7840 | if (cmd != SIOCWANDEV) | |
7841 | return hdlc_ioctl(dev, ifr, cmd); | |
7842 | ||
7843 | switch(ifr->ifr_settings.type) { | |
7844 | case IF_GET_IFACE: /* return current sync_serial_settings */ | |
7845 | ||
7846 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
7847 | if (ifr->ifr_settings.size < size) { | |
7848 | ifr->ifr_settings.size = size; /* data size wanted */ | |
7849 | return -ENOBUFS; | |
7850 | } | |
7851 | ||
7852 | flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
7853 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
7854 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
7855 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
7856 | ||
b19a47e0 | 7857 | memset(&new_line, 0, sizeof(new_line)); |
1da177e4 LT |
7858 | switch (flags){ |
7859 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break; | |
7860 | case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break; | |
7861 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break; | |
7862 | case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break; | |
7863 | default: new_line.clock_type = CLOCK_DEFAULT; | |
7864 | } | |
7865 | ||
7866 | new_line.clock_rate = info->params.clock_speed; | |
7867 | new_line.loopback = info->params.loopback ? 1:0; | |
7868 | ||
7869 | if (copy_to_user(line, &new_line, size)) | |
7870 | return -EFAULT; | |
7871 | return 0; | |
7872 | ||
7873 | case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */ | |
7874 | ||
7875 | if(!capable(CAP_NET_ADMIN)) | |
7876 | return -EPERM; | |
7877 | if (copy_from_user(&new_line, line, size)) | |
7878 | return -EFAULT; | |
7879 | ||
7880 | switch (new_line.clock_type) | |
7881 | { | |
7882 | case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break; | |
7883 | case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break; | |
7884 | case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break; | |
7885 | case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break; | |
7886 | case CLOCK_DEFAULT: flags = info->params.flags & | |
7887 | (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
7888 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
7889 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
7890 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break; | |
7891 | default: return -EINVAL; | |
7892 | } | |
7893 | ||
7894 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
7895 | return -EINVAL; | |
7896 | ||
7897 | info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL | | |
7898 | HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN | | |
7899 | HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL | | |
7900 | HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); | |
7901 | info->params.flags |= flags; | |
7902 | ||
7903 | info->params.loopback = new_line.loopback; | |
7904 | ||
7905 | if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG)) | |
7906 | info->params.clock_speed = new_line.clock_rate; | |
7907 | else | |
7908 | info->params.clock_speed = 0; | |
7909 | ||
7910 | /* if network interface up, reprogram hardware */ | |
7911 | if (info->netcount) | |
7912 | mgsl_program_hw(info); | |
7913 | return 0; | |
7914 | ||
7915 | default: | |
7916 | return hdlc_ioctl(dev, ifr, cmd); | |
7917 | } | |
7918 | } | |
7919 | ||
7920 | /** | |
7921 | * called by network layer when transmit timeout is detected | |
7922 | * | |
7923 | * dev pointer to network device structure | |
7924 | */ | |
7925 | static void hdlcdev_tx_timeout(struct net_device *dev) | |
7926 | { | |
7927 | struct mgsl_struct *info = dev_to_port(dev); | |
1da177e4 LT |
7928 | unsigned long flags; |
7929 | ||
7930 | if (debug_level >= DEBUG_LEVEL_INFO) | |
7931 | printk("hdlcdev_tx_timeout(%s)\n",dev->name); | |
7932 | ||
198191c4 KH |
7933 | dev->stats.tx_errors++; |
7934 | dev->stats.tx_aborted_errors++; | |
1da177e4 LT |
7935 | |
7936 | spin_lock_irqsave(&info->irq_spinlock,flags); | |
7937 | usc_stop_transmitter(info); | |
7938 | spin_unlock_irqrestore(&info->irq_spinlock,flags); | |
7939 | ||
7940 | netif_wake_queue(dev); | |
7941 | } | |
7942 | ||
7943 | /** | |
7944 | * called by device driver when transmit completes | |
7945 | * reenable network layer transmit if stopped | |
7946 | * | |
7947 | * info pointer to device instance information | |
7948 | */ | |
7949 | static void hdlcdev_tx_done(struct mgsl_struct *info) | |
7950 | { | |
7951 | if (netif_queue_stopped(info->netdev)) | |
7952 | netif_wake_queue(info->netdev); | |
7953 | } | |
7954 | ||
7955 | /** | |
7956 | * called by device driver when frame received | |
7957 | * pass frame to network layer | |
7958 | * | |
7959 | * info pointer to device instance information | |
7960 | * buf pointer to buffer contianing frame data | |
7961 | * size count of data bytes in buf | |
7962 | */ | |
7963 | static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size) | |
7964 | { | |
7965 | struct sk_buff *skb = dev_alloc_skb(size); | |
7966 | struct net_device *dev = info->netdev; | |
1da177e4 LT |
7967 | |
7968 | if (debug_level >= DEBUG_LEVEL_INFO) | |
198191c4 | 7969 | printk("hdlcdev_rx(%s)\n", dev->name); |
1da177e4 LT |
7970 | |
7971 | if (skb == NULL) { | |
198191c4 KH |
7972 | printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", |
7973 | dev->name); | |
7974 | dev->stats.rx_dropped++; | |
1da177e4 LT |
7975 | return; |
7976 | } | |
7977 | ||
198191c4 | 7978 | memcpy(skb_put(skb, size), buf, size); |
1da177e4 | 7979 | |
198191c4 | 7980 | skb->protocol = hdlc_type_trans(skb, dev); |
1da177e4 | 7981 | |
198191c4 KH |
7982 | dev->stats.rx_packets++; |
7983 | dev->stats.rx_bytes += size; | |
1da177e4 LT |
7984 | |
7985 | netif_rx(skb); | |
1da177e4 LT |
7986 | } |
7987 | ||
991990a1 KH |
7988 | static const struct net_device_ops hdlcdev_ops = { |
7989 | .ndo_open = hdlcdev_open, | |
7990 | .ndo_stop = hdlcdev_close, | |
7991 | .ndo_change_mtu = hdlc_change_mtu, | |
7992 | .ndo_start_xmit = hdlc_start_xmit, | |
7993 | .ndo_do_ioctl = hdlcdev_ioctl, | |
7994 | .ndo_tx_timeout = hdlcdev_tx_timeout, | |
7995 | }; | |
7996 | ||
1da177e4 LT |
7997 | /** |
7998 | * called by device driver when adding device instance | |
7999 | * do generic HDLC initialization | |
8000 | * | |
8001 | * info pointer to device instance information | |
8002 | * | |
8003 | * returns 0 if success, otherwise error code | |
8004 | */ | |
8005 | static int hdlcdev_init(struct mgsl_struct *info) | |
8006 | { | |
8007 | int rc; | |
8008 | struct net_device *dev; | |
8009 | hdlc_device *hdlc; | |
8010 | ||
8011 | /* allocate and initialize network and HDLC layer objects */ | |
8012 | ||
a271ca37 GKH |
8013 | dev = alloc_hdlcdev(info); |
8014 | if (!dev) { | |
1da177e4 LT |
8015 | printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__); |
8016 | return -ENOMEM; | |
8017 | } | |
8018 | ||
8019 | /* for network layer reporting purposes only */ | |
8020 | dev->base_addr = info->io_base; | |
8021 | dev->irq = info->irq_level; | |
8022 | dev->dma = info->dma_level; | |
8023 | ||
8024 | /* network layer callbacks and settings */ | |
991990a1 KH |
8025 | dev->netdev_ops = &hdlcdev_ops; |
8026 | dev->watchdog_timeo = 10 * HZ; | |
1da177e4 LT |
8027 | dev->tx_queue_len = 50; |
8028 | ||
8029 | /* generic HDLC layer callbacks and settings */ | |
8030 | hdlc = dev_to_hdlc(dev); | |
8031 | hdlc->attach = hdlcdev_attach; | |
8032 | hdlc->xmit = hdlcdev_xmit; | |
8033 | ||
8034 | /* register objects with HDLC layer */ | |
a271ca37 GKH |
8035 | rc = register_hdlc_device(dev); |
8036 | if (rc) { | |
1da177e4 LT |
8037 | printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__); |
8038 | free_netdev(dev); | |
8039 | return rc; | |
8040 | } | |
8041 | ||
8042 | info->netdev = dev; | |
8043 | return 0; | |
8044 | } | |
8045 | ||
8046 | /** | |
8047 | * called by device driver when removing device instance | |
8048 | * do generic HDLC cleanup | |
8049 | * | |
8050 | * info pointer to device instance information | |
8051 | */ | |
8052 | static void hdlcdev_exit(struct mgsl_struct *info) | |
8053 | { | |
8054 | unregister_hdlc_device(info->netdev); | |
8055 | free_netdev(info->netdev); | |
8056 | info->netdev = NULL; | |
8057 | } | |
8058 | ||
8059 | #endif /* CONFIG_HDLC */ | |
8060 | ||
8061 | ||
9671f099 | 8062 | static int synclink_init_one (struct pci_dev *dev, |
1da177e4 LT |
8063 | const struct pci_device_id *ent) |
8064 | { | |
8065 | struct mgsl_struct *info; | |
8066 | ||
8067 | if (pci_enable_device(dev)) { | |
8068 | printk("error enabling pci device %p\n", dev); | |
8069 | return -EIO; | |
8070 | } | |
8071 | ||
a271ca37 GKH |
8072 | info = mgsl_allocate_device(); |
8073 | if (!info) { | |
1da177e4 LT |
8074 | printk("can't allocate device instance data.\n"); |
8075 | return -EIO; | |
8076 | } | |
8077 | ||
8078 | /* Copy user configuration info to device instance data */ | |
8079 | ||
8080 | info->io_base = pci_resource_start(dev, 2); | |
8081 | info->irq_level = dev->irq; | |
8082 | info->phys_memory_base = pci_resource_start(dev, 3); | |
8083 | ||
8084 | /* Because veremap only works on page boundaries we must map | |
8085 | * a larger area than is actually implemented for the LCR | |
8086 | * memory range. We map a full page starting at the page boundary. | |
8087 | */ | |
8088 | info->phys_lcr_base = pci_resource_start(dev, 0); | |
8089 | info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1); | |
8090 | info->phys_lcr_base &= ~(PAGE_SIZE-1); | |
8091 | ||
8092 | info->bus_type = MGSL_BUS_TYPE_PCI; | |
8093 | info->io_addr_size = 8; | |
0f2ed4c6 | 8094 | info->irq_flags = IRQF_SHARED; |
1da177e4 LT |
8095 | |
8096 | if (dev->device == 0x0210) { | |
8097 | /* Version 1 PCI9030 based universal PCI adapter */ | |
8098 | info->misc_ctrl_value = 0x007c4080; | |
8099 | info->hw_version = 1; | |
8100 | } else { | |
8101 | /* Version 0 PCI9050 based 5V PCI adapter | |
8102 | * A PCI9050 bug prevents reading LCR registers if | |
8103 | * LCR base address bit 7 is set. Maintain shadow | |
8104 | * value so we can write to LCR misc control reg. | |
8105 | */ | |
8106 | info->misc_ctrl_value = 0x087e4546; | |
8107 | info->hw_version = 0; | |
8108 | } | |
8109 | ||
8110 | mgsl_add_device(info); | |
8111 | ||
8112 | return 0; | |
8113 | } | |
8114 | ||
ae8d8a14 | 8115 | static void synclink_remove_one (struct pci_dev *dev) |
1da177e4 LT |
8116 | { |
8117 | } | |
8118 |