[deliverable/linux.git] / drivers / usb / chipidea / ci.h

/*
 * ci.h - common structures, functions, and macros of the ChipIdea driver
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
#define __DRIVERS_USB_CHIPIDEA_CI_H

#include <linux/list.h>
#include <linux/irqreturn.h>
#include <linux/usb.h>
#include <linux/usb/gadget.h>

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          32

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/**
 * struct ci13xxx_ep - endpoint representation
 * @ep: endpoint structure for gadget drivers
 * @dir: endpoint direction (TX/RX)
 * @num: endpoint number
 * @type: endpoint type
 * @name: string description of the endpoint
 * @qh: queue head for this endpoint
 * @wedge: is the endpoint wedged
 * @ci: pointer to the controller
 * @lock: pointer to controller's spinlock
 * @td_pool: pointer to controller's TD pool
 */
struct ci13xxx_ep {
	struct usb_ep				ep;
	u8					dir;
	u8					num;
	u8					type;
	char					name[16];
	struct {
		struct list_head	queue;
		struct ci13xxx_qh	*ptr;
		dma_addr_t		dma;
	}					qh;
	int					wedge;

	/* global resources */
	struct ci13xxx				*ci;
	spinlock_t				*lock;
	struct dma_pool				*td_pool;
};

enum ci_role {
	CI_ROLE_HOST = 0,
	CI_ROLE_GADGET,
	CI_ROLE_END,
};

/**
 * struct ci_role_driver - host/gadget role driver
 * start: start this role
 * stop: stop this role
 * irq: irq handler for this role
 * name: role name string (host/gadget)
 */
struct ci_role_driver {
	int		(*start)(struct ci13xxx *);
	void		(*stop)(struct ci13xxx *);
	irqreturn_t	(*irq)(struct ci13xxx *);
	const char	*name;
};

/**
 * struct hw_bank - hardware register mapping representation
 * @lpm: set if the device is LPM capable
 * @phys: physical address of the controller's registers
 * @abs: absolute address of the beginning of register window
 * @cap: capability registers
 * @op: operational registers
 * @size: size of the register window
 * @regmap: register lookup table
 */
struct hw_bank {
	unsigned	lpm;
	resource_size_t	phys;
	void __iomem	*abs;
	void __iomem	*cap;
	void __iomem	*op;
	size_t		size;
	void __iomem	**regmap;
};

/**
 * struct ci13xxx - chipidea device representation
 * @dev: pointer to parent device
 * @lock: access synchronization
 * @hw_bank: hardware register mapping
 * @irq: IRQ number
 * @roles: array of supported roles for this controller
 * @role: current role
 * @is_otg: if the device is otg-capable
 * @work: work for role changing
 * @wq: workqueue thread
 * @qh_pool: allocation pool for queue heads
 * @td_pool: allocation pool for transfer descriptors
 * @gadget: device side representation for peripheral controller
 * @driver: gadget driver
 * @hw_ep_max: total number of endpoints supported by hardware
 * @ci13xxx_ep: array of endpoints
 * @ep0_dir: ep0 direction
 * @ep0out: pointer to ep0 OUT endpoint
 * @ep0in: pointer to ep0 IN endpoint
 * @status: ep0 status request
 * @setaddr: if we should set the address on status completion
 * @address: usb address received from the host
 * @remote_wakeup: host-enabled remote wakeup
 * @suspended: suspended by host
 * @test_mode: the selected test mode
 * @platdata: platform specific information supplied by parent device
 * @vbus_active: is VBUS active
 * @transceiver: pointer to USB PHY, if any
 * @hcd: pointer to usb_hcd for ehci host driver
 * @debugfs: root dentry for this controller in debugfs
 */
struct ci13xxx {
	struct device			*dev;
	spinlock_t			lock;
	struct hw_bank			hw_bank;
	int				irq;
	struct ci_role_driver		*roles[CI_ROLE_END];
	enum ci_role			role;
	bool				is_otg;
	struct work_struct		work;
	struct workqueue_struct		*wq;

	struct dma_pool			*qh_pool;
	struct dma_pool			*td_pool;

	struct usb_gadget		gadget;
	struct usb_gadget_driver	*driver;
	unsigned			hw_ep_max;
	struct ci13xxx_ep		ci13xxx_ep[ENDPT_MAX];
	u32				ep0_dir;
	struct ci13xxx_ep		*ep0out, *ep0in;

	struct usb_request		*status;
	bool				setaddr;
	u8				address;
	u8				remote_wakeup;
	u8				suspended;
	u8				test_mode;

	struct ci13xxx_platform_data	*platdata;
	int				vbus_active;
	/* FIXME: some day, we'll not use global phy */
	bool				global_phy;
	struct usb_phy			*transceiver;
	struct usb_hcd			*hcd;
	struct dentry			*debugfs;
};

static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
{
	BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
	return ci->roles[ci->role];
}

static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
{
	int ret;

	if (role >= CI_ROLE_END)
		return -EINVAL;

	if (!ci->roles[role])
		return -ENXIO;

	ret = ci->roles[role]->start(ci);
	if (!ret)
		ci->role = role;
	return ret;
}

static inline void ci_role_stop(struct ci13xxx *ci)
{
	enum ci_role role = ci->role;

	if (role == CI_ROLE_END)
		return;

	ci->role = CI_ROLE_END;

	ci->roles[role]->stop(ci);
}

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* register size */
#define REG_BITS   (32)

/* register indices */
enum ci13xxx_regs {
	CAP_CAPLENGTH,
	CAP_HCCPARAMS,
	CAP_DCCPARAMS,
	CAP_TESTMODE,
	CAP_LAST = CAP_TESTMODE,
	OP_USBCMD,
	OP_USBSTS,
	OP_USBINTR,
	OP_DEVICEADDR,
	OP_ENDPTLISTADDR,
	OP_PORTSC,
	OP_DEVLC,
	OP_OTGSC,
	OP_USBMODE,
	OP_ENDPTSETUPSTAT,
	OP_ENDPTPRIME,
	OP_ENDPTFLUSH,
	OP_ENDPTSTAT,
	OP_ENDPTCOMPLETE,
	OP_ENDPTCTRL,
	/* endptctrl1..15 follow */
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
};

/**
 * hw_read: reads from a hw register
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
{
	return ioread32(ci->hw_bank.regmap[reg]) & mask;
}

/**
 * hw_write: writes to a hw register
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 */
static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
			    u32 mask, u32 data)
{
	if (~mask)
		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
			| (data & mask);

	iowrite32(data, ci->hw_bank.regmap[reg]);
}

/**
 * hw_test_and_clear: tests & clears a hw register
 * @reg:  register index
 * @mask: bitfield mask
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
				    u32 mask)
{
	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;

	iowrite32(val, ci->hw_bank.regmap[reg]);
	return val;
}

/**
 * hw_test_and_write: tests & writes a hw register
 * @reg:  register index
 * @mask: bitfield mask
 * @data: new value
 *
 * This function returns register contents
 */
static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
				    u32 mask, u32 data)
{
	u32 val = hw_read(ci, reg, ~0);

	hw_write(ci, reg, mask, data);
	return (val & mask) >> __ffs(mask);
}

int hw_device_reset(struct ci13xxx *ci, u32 mode);

int hw_port_test_set(struct ci13xxx *ci, u8 mode);

u8 hw_port_test_get(struct ci13xxx *ci);

#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */
Commit	Line	Data
e443b333 AS	1	/*
	2	* ci.h - common structures, functions, and macros of the ChipIdea driver
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#ifndef __DRIVERS_USB_CHIPIDEA_CI_H
	14	#define __DRIVERS_USB_CHIPIDEA_CI_H
	15
	16	#include <linux/list.h>
5f36e231	17	#include <linux/irqreturn.h>
eb70e5ab	18	#include <linux/usb.h>
e443b333 AS	19	#include <linux/usb/gadget.h>
	20
	21	/******************************************************************************
	22	* DEFINE
	23	*****************************************************************************/
e443b333 AS	24	#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
	25	#define ENDPT_MAX 32
	26
	27	/******************************************************************************
	28	* STRUCTURES
	29	*****************************************************************************/
551a8ac6 AS	30	/**
	31	* struct ci13xxx_ep - endpoint representation
	32	* @ep: endpoint structure for gadget drivers
	33	* @dir: endpoint direction (TX/RX)
	34	* @num: endpoint number
	35	* @type: endpoint type
	36	* @name: string description of the endpoint
	37	* @qh: queue head for this endpoint
	38	* @wedge: is the endpoint wedged
26c696c6	39	* @ci: pointer to the controller
551a8ac6	40	* @lock: pointer to controller's spinlock
551a8ac6 AS	41	* @td_pool: pointer to controller's TD pool
551a8ac6 AS	42	*/
e443b333	43	struct ci13xxx_ep {
551a8ac6 AS	44	struct usb_ep ep;
	45	u8 dir;
	46	u8 num;
	47	u8 type;
	48	char name[16];
e443b333	49	struct {
551a8ac6 AS	50	struct list_head queue;
	51	struct ci13xxx_qh *ptr;
	52	dma_addr_t dma;
	53	} qh;
	54	int wedge;
e443b333 AS	55
e443b333 AS	56	/* global resources */
26c696c6	57	struct ci13xxx *ci;
551a8ac6	58	spinlock_t *lock;
551a8ac6	59	struct dma_pool *td_pool;
e443b333 AS	60	};
e443b333 AS	61
5f36e231 AS	62	enum ci_role {
	63	CI_ROLE_HOST = 0,
	64	CI_ROLE_GADGET,
	65	CI_ROLE_END,
	66	};
	67
	68	/**
	69	* struct ci_role_driver - host/gadget role driver
	70	* start: start this role
	71	* stop: stop this role
	72	* irq: irq handler for this role
	73	* name: role name string (host/gadget)
	74	*/
	75	struct ci_role_driver {
	76	int (start)(struct ci13xxx );
	77	void (stop)(struct ci13xxx );
	78	irqreturn_t (irq)(struct ci13xxx );
	79	const char *name;
	80	};
	81
551a8ac6 AS	82	/**
	83	* struct hw_bank - hardware register mapping representation
	84	* @lpm: set if the device is LPM capable
eb70e5ab	85	* @phys: physical address of the controller's registers
551a8ac6 AS	86	* @abs: absolute address of the beginning of register window
	87	* @cap: capability registers
	88	* @op: operational registers
	89	* @size: size of the register window
	90	* @regmap: register lookup table
	91	*/
e443b333	92	struct hw_bank {
551a8ac6	93	unsigned lpm;
eb70e5ab	94	resource_size_t phys;
551a8ac6 AS	95	void __iomem *abs;
	96	void __iomem *cap;
	97	void __iomem *op;
	98	size_t size;
	99	void __iomem **regmap;
e443b333 AS	100	};
e443b333 AS	101
551a8ac6 AS	102	/**
	103	* struct ci13xxx - chipidea device representation
	104	* @dev: pointer to parent device
	105	* @lock: access synchronization
	106	* @hw_bank: hardware register mapping
	107	* @irq: IRQ number
	108	* @roles: array of supported roles for this controller
	109	* @role: current role
	110	* @is_otg: if the device is otg-capable
	111	* @work: work for role changing
	112	* @wq: workqueue thread
	113	* @qh_pool: allocation pool for queue heads
	114	* @td_pool: allocation pool for transfer descriptors
	115	* @gadget: device side representation for peripheral controller
	116	* @driver: gadget driver
	117	* @hw_ep_max: total number of endpoints supported by hardware
	118	* @ci13xxx_ep: array of endpoints
	119	* @ep0_dir: ep0 direction
	120	* @ep0out: pointer to ep0 OUT endpoint
	121	* @ep0in: pointer to ep0 IN endpoint
	122	* @status: ep0 status request
	123	* @setaddr: if we should set the address on status completion
	124	* @address: usb address received from the host
	125	* @remote_wakeup: host-enabled remote wakeup
	126	* @suspended: suspended by host
	127	* @test_mode: the selected test mode
77c4400f	128	* @platdata: platform specific information supplied by parent device
551a8ac6 AS	129	* @vbus_active: is VBUS active
551a8ac6 AS	130	* @transceiver: pointer to USB PHY, if any
eb70e5ab	131	* @hcd: pointer to usb_hcd for ehci host driver
2d651289	132	* @debugfs: root dentry for this controller in debugfs
551a8ac6	133	*/
e443b333	134	struct ci13xxx {
551a8ac6 AS	135	struct device *dev;
	136	spinlock_t lock;
	137	struct hw_bank hw_bank;
	138	int irq;
	139	struct ci_role_driver *roles[CI_ROLE_END];
	140	enum ci_role role;
	141	bool is_otg;
	142	struct work_struct work;
	143	struct workqueue_struct *wq;
	144
	145	struct dma_pool *qh_pool;
	146	struct dma_pool *td_pool;
	147
	148	struct usb_gadget gadget;
	149	struct usb_gadget_driver *driver;
	150	unsigned hw_ep_max;
	151	struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX];
	152	u32 ep0_dir;
	153	struct ci13xxx_ep ep0out, ep0in;
	154
	155	struct usb_request *status;
	156	bool setaddr;
	157	u8 address;
	158	u8 remote_wakeup;
	159	u8 suspended;
	160	u8 test_mode;
	161
77c4400f	162	struct ci13xxx_platform_data *platdata;
551a8ac6	163	int vbus_active;
a2c3d690 RZ	164	/* FIXME: some day, we'll not use global phy */
a2c3d690 RZ	165	bool global_phy;
551a8ac6	166	struct usb_phy *transceiver;
eb70e5ab	167	struct usb_hcd *hcd;
2d651289	168	struct dentry *debugfs;
e443b333 AS	169	};
e443b333 AS	170
5f36e231 AS	171	static inline struct ci_role_driver ci_role(struct ci13xxx ci)
	172	{
	173	BUG_ON(ci->role >= CI_ROLE_END \|\| !ci->roles[ci->role]);
	174	return ci->roles[ci->role];
	175	}
	176
	177	static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
	178	{
	179	int ret;
	180
	181	if (role >= CI_ROLE_END)
	182	return -EINVAL;
	183
	184	if (!ci->roles[role])
	185	return -ENXIO;
	186
	187	ret = ci->roles[role]->start(ci);
	188	if (!ret)
	189	ci->role = role;
	190	return ret;
	191	}
	192
	193	static inline void ci_role_stop(struct ci13xxx *ci)
	194	{
	195	enum ci_role role = ci->role;
	196
	197	if (role == CI_ROLE_END)
	198	return;
	199
	200	ci->role = CI_ROLE_END;
	201
	202	ci->roles[role]->stop(ci);
	203	}
	204
e443b333 AS	205	/******************************************************************************
	206	* REGISTERS
	207	*****************************************************************************/
	208	/* register size */
	209	#define REG_BITS (32)
	210
	211	/* register indices */
	212	enum ci13xxx_regs {
	213	CAP_CAPLENGTH,
	214	CAP_HCCPARAMS,
	215	CAP_DCCPARAMS,
	216	CAP_TESTMODE,
	217	CAP_LAST = CAP_TESTMODE,
	218	OP_USBCMD,
	219	OP_USBSTS,
	220	OP_USBINTR,
	221	OP_DEVICEADDR,
	222	OP_ENDPTLISTADDR,
	223	OP_PORTSC,
	224	OP_DEVLC,
5f36e231	225	OP_OTGSC,
e443b333 AS	226	OP_USBMODE,
	227	OP_ENDPTSETUPSTAT,
	228	OP_ENDPTPRIME,
	229	OP_ENDPTFLUSH,
	230	OP_ENDPTSTAT,
	231	OP_ENDPTCOMPLETE,
	232	OP_ENDPTCTRL,
	233	/* endptctrl1..15 follow */
	234	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
	235	};
	236
e443b333 AS	237	/**
	238	* hw_read: reads from a hw register
	239	* @reg: register index
	240	* @mask: bitfield mask
	241	*
	242	* This function returns register contents
	243	*/
26c696c6	244	static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
e443b333	245	{
26c696c6	246	return ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333 AS	247	}
	248
	249	/**
	250	* hw_write: writes to a hw register
	251	* @reg: register index
	252	* @mask: bitfield mask
	253	* @data: new value
	254	*/
26c696c6	255	static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
e443b333 AS	256	u32 mask, u32 data)
	257	{
	258	if (~mask)
26c696c6	259	data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
e443b333 AS	260	\| (data & mask);
e443b333 AS	261
26c696c6	262	iowrite32(data, ci->hw_bank.regmap[reg]);
e443b333 AS	263	}
	264
	265	/**
	266	* hw_test_and_clear: tests & clears a hw register
	267	* @reg: register index
	268	* @mask: bitfield mask
	269	*
	270	* This function returns register contents
	271	*/
26c696c6	272	static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
e443b333 AS	273	u32 mask)
e443b333 AS	274	{
26c696c6	275	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
e443b333	276
26c696c6	277	iowrite32(val, ci->hw_bank.regmap[reg]);
e443b333 AS	278	return val;
	279	}
	280
	281	/**
	282	* hw_test_and_write: tests & writes a hw register
	283	* @reg: register index
	284	* @mask: bitfield mask
	285	* @data: new value
	286	*
	287	* This function returns register contents
	288	*/
26c696c6	289	static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
e443b333 AS	290	u32 mask, u32 data)
e443b333 AS	291	{
26c696c6	292	u32 val = hw_read(ci, reg, ~0);
e443b333	293
26c696c6	294	hw_write(ci, reg, mask, data);
727b4ddb	295	return (val & mask) >> __ffs(mask);
e443b333 AS	296	}
e443b333 AS	297
eb70e5ab	298	int hw_device_reset(struct ci13xxx *ci, u32 mode);
e443b333 AS	299
	300	int hw_port_test_set(struct ci13xxx *ci, u8 mode);
	301
	302	u8 hw_port_test_get(struct ci13xxx *ci);
	303
	304	#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */