[deliverable/linux.git] / drivers / usb / chipidea / ci13xxx_udc.h

/*
 * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Description: MIPS USB IP core family device controller
 *              Structures, registers and logging macros
 */

#ifndef _CI13XXX_h_
#define _CI13XXX_h_

/******************************************************************************
 * DEFINE
 *****************************************************************************/
#define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */
#define ENDPT_MAX          32
#define CTRL_PAYLOAD_MAX   64
#define RX        0  /* similar to USB_DIR_OUT but can be used as an index */
#define TX        1  /* similar to USB_DIR_IN  but can be used as an index */

/******************************************************************************
 * STRUCTURES
 *****************************************************************************/
/* DMA layout of transfer descriptors */
struct ci13xxx_td {
	/* 0 */
	u32 next;
#define TD_TERMINATE          BIT(0)
#define TD_ADDR_MASK          (0xFFFFFFEUL << 5)
	/* 1 */
	u32 token;
#define TD_STATUS             (0x00FFUL <<  0)
#define TD_STATUS_TR_ERR      BIT(3)
#define TD_STATUS_DT_ERR      BIT(5)
#define TD_STATUS_HALTED      BIT(6)
#define TD_STATUS_ACTIVE      BIT(7)
#define TD_MULTO              (0x0003UL << 10)
#define TD_IOC                BIT(15)
#define TD_TOTAL_BYTES        (0x7FFFUL << 16)
	/* 2 */
	u32 page[5];
#define TD_CURR_OFFSET        (0x0FFFUL <<  0)
#define TD_FRAME_NUM          (0x07FFUL <<  0)
#define TD_RESERVED_MASK      (0x0FFFUL <<  0)
} __attribute__ ((packed));

/* DMA layout of queue heads */
struct ci13xxx_qh {
	/* 0 */
	u32 cap;
#define QH_IOS                BIT(15)
#define QH_MAX_PKT            (0x07FFUL << 16)
#define QH_ZLT                BIT(29)
#define QH_MULT               (0x0003UL << 30)
	/* 1 */
	u32 curr;
	/* 2 - 8 */
	struct ci13xxx_td        td;
	/* 9 */
	u32 RESERVED;
	struct usb_ctrlrequest   setup;
} __attribute__ ((packed));

/* Extension of usb_request */
struct ci13xxx_req {
	struct usb_request   req;
	unsigned             map;
	struct list_head     queue;
	struct ci13xxx_td   *ptr;
	dma_addr_t           dma;
	struct ci13xxx_td   *zptr;
	dma_addr_t           zdma;
};

/* Extension of usb_ep */
struct ci13xxx_ep {
	struct usb_ep                          ep;
	u8                                     dir;
	u8                                     num;
	u8                                     type;
	char                                   name[16];
	struct {
		struct list_head   queue;
		struct ci13xxx_qh *ptr;
		dma_addr_t         dma;
	}                                      qh;
	int                                    wedge;

	/* global resources */
	struct ci13xxx                        *udc;
	spinlock_t                            *lock;
	struct device                         *device;
	struct dma_pool                       *td_pool;
};

struct ci13xxx;
struct ci13xxx_udc_driver {
	const char	*name;
	/* offset of the capability registers */
	uintptr_t	 capoffset;
	unsigned long	 flags;
#define CI13XXX_REGS_SHARED		BIT(0)
#define CI13XXX_REQUIRE_TRANSCEIVER	BIT(1)
#define CI13XXX_PULLUP_ON_VBUS		BIT(2)
#define CI13XXX_DISABLE_STREAMING	BIT(3)

#define CI13XXX_CONTROLLER_RESET_EVENT		0
#define CI13XXX_CONTROLLER_STOPPED_EVENT	1
	void	(*notify_event) (struct ci13xxx *udc, unsigned event);
};

struct hw_bank {
	unsigned      lpm;    /* is LPM? */
	void __iomem *abs;    /* bus map offset */
	void __iomem *cap;    /* bus map offset + CAP offset */
	void __iomem *op;     /* bus map offset + OP offset */
	size_t        size;   /* bank size */
	void __iomem **regmap;
};

/* CI13XXX UDC descriptor & global resources */
struct ci13xxx {
	spinlock_t		   lock;      /* ctrl register bank access */
	void __iomem              *regs;      /* registers address space */

	struct dma_pool           *qh_pool;   /* DMA pool for queue heads */
	struct dma_pool           *td_pool;   /* DMA pool for transfer descs */
	struct usb_request        *status;    /* ep0 status request */

	struct device             *dev;
	struct usb_gadget          gadget;     /* USB slave device */
	struct ci13xxx_ep          ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
	u32                        ep0_dir;    /* ep0 direction */
	struct ci13xxx_ep          *ep0out, *ep0in;
	unsigned		   hw_ep_max;  /* number of hw endpoints */

	bool			   setaddr;
	u8			   address;
	u8                         remote_wakeup; /* Is remote wakeup feature
							enabled by the host? */
	u8                         suspended;  /* suspended by the host */
	u8                         test_mode;  /* the selected test mode */

	struct hw_bank             hw_bank;
	int			   irq;
	struct usb_gadget_driver  *driver;     /* 3rd party gadget driver */
	struct ci13xxx_udc_driver *udc_driver; /* device controller driver */
	int                        vbus_active; /* is VBUS active */
	struct usb_phy            *transceiver; /* Transceiver struct */
};

/******************************************************************************
 * REGISTERS
 *****************************************************************************/
/* Default offset of capability registers */
#define DEF_CAPOFFSET		0x100

/* register size */
#define REG_BITS   (32)

/* register indices */
enum ci13xxx_regs {
	CAP_CAPLENGTH,
	CAP_HCCPARAMS,
	CAP_DCCPARAMS,
	CAP_TESTMODE,
	CAP_LAST = CAP_TESTMODE,
	OP_USBCMD,
	OP_USBSTS,
	OP_USBINTR,
	OP_DEVICEADDR,
	OP_ENDPTLISTADDR,
	OP_PORTSC,
	OP_DEVLC,
	OP_USBMODE,
	OP_ENDPTSETUPSTAT,
	OP_ENDPTPRIME,
	OP_ENDPTFLUSH,
	OP_ENDPTSTAT,
	OP_ENDPTCOMPLETE,
	OP_ENDPTCTRL,
	/* endptctrl1..15 follow */
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
};

/* HCCPARAMS */
#define HCCPARAMS_LEN         BIT(17)

/* DCCPARAMS */
#define DCCPARAMS_DEN         (0x1F << 0)
#define DCCPARAMS_DC          BIT(7)

/* TESTMODE */
#define TESTMODE_FORCE        BIT(0)

/* USBCMD */
#define USBCMD_RS             BIT(0)
#define USBCMD_RST            BIT(1)
#define USBCMD_SUTW           BIT(13)
#define USBCMD_ATDTW          BIT(14)

/* USBSTS & USBINTR */
#define USBi_UI               BIT(0)
#define USBi_UEI              BIT(1)
#define USBi_PCI              BIT(2)
#define USBi_URI              BIT(6)
#define USBi_SLI              BIT(8)

/* DEVICEADDR */
#define DEVICEADDR_USBADRA    BIT(24)
#define DEVICEADDR_USBADR     (0x7FUL << 25)

/* PORTSC */
#define PORTSC_FPR            BIT(6)
#define PORTSC_SUSP           BIT(7)
#define PORTSC_HSP            BIT(9)
#define PORTSC_PTC            (0x0FUL << 16)

/* DEVLC */
#define DEVLC_PSPD            (0x03UL << 25)
#define    DEVLC_PSPD_HS      (0x02UL << 25)

/* USBMODE */
#define USBMODE_CM            (0x03UL <<  0)
#define    USBMODE_CM_IDLE    (0x00UL <<  0)
#define    USBMODE_CM_DEVICE  (0x02UL <<  0)
#define    USBMODE_CM_HOST    (0x03UL <<  0)
#define USBMODE_SLOM          BIT(3)
#define USBMODE_SDIS          BIT(4)

/* ENDPTCTRL */
#define ENDPTCTRL_RXS         BIT(0)
#define ENDPTCTRL_RXT         (0x03UL <<  2)
#define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
#define ENDPTCTRL_RXE         BIT(7)
#define ENDPTCTRL_TXS         BIT(16)
#define ENDPTCTRL_TXT         (0x03UL << 18)
#define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
#define ENDPTCTRL_TXE         BIT(23)

#endif	/* _CI13XXX_h_ */
Commit	Line	Data
aa69a809 DL	1	/*
	2	* ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* Description: MIPS USB IP core family device controller
	13	* Structures, registers and logging macros
	14	*/
	15
	16	#ifndef _CI13XXX_h_
	17	#define _CI13XXX_h_
	18
	19	/******************************************************************************
	20	* DEFINE
	21	*****************************************************************************/
0a313c4d	22	#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
1155a7b8 AS	23	#define ENDPT_MAX 32
	24	#define CTRL_PAYLOAD_MAX 64
	25	#define RX 0 /* similar to USB_DIR_OUT but can be used as an index */
	26	#define TX 1 /* similar to USB_DIR_IN but can be used as an index */
aa69a809 DL	27
	28	/******************************************************************************
	29	* STRUCTURES
	30	*****************************************************************************/
	31	/* DMA layout of transfer descriptors */
	32	struct ci13xxx_td {
	33	/* 0 */
	34	u32 next;
	35	#define TD_TERMINATE BIT(0)
0e6ca199	36	#define TD_ADDR_MASK (0xFFFFFFEUL << 5)
aa69a809 DL	37	/* 1 */
	38	u32 token;
	39	#define TD_STATUS (0x00FFUL << 0)
	40	#define TD_STATUS_TR_ERR BIT(3)
	41	#define TD_STATUS_DT_ERR BIT(5)
	42	#define TD_STATUS_HALTED BIT(6)
	43	#define TD_STATUS_ACTIVE BIT(7)
	44	#define TD_MULTO (0x0003UL << 10)
	45	#define TD_IOC BIT(15)
	46	#define TD_TOTAL_BYTES (0x7FFFUL << 16)
	47	/* 2 */
	48	u32 page[5];
	49	#define TD_CURR_OFFSET (0x0FFFUL << 0)
	50	#define TD_FRAME_NUM (0x07FFUL << 0)
	51	#define TD_RESERVED_MASK (0x0FFFUL << 0)
	52	} __attribute__ ((packed));
	53
	54	/* DMA layout of queue heads */
	55	struct ci13xxx_qh {
	56	/* 0 */
	57	u32 cap;
	58	#define QH_IOS BIT(15)
	59	#define QH_MAX_PKT (0x07FFUL << 16)
	60	#define QH_ZLT BIT(29)
	61	#define QH_MULT (0x0003UL << 30)
	62	/* 1 */
	63	u32 curr;
	64	/* 2 - 8 */
	65	struct ci13xxx_td td;
	66	/* 9 */
	67	u32 RESERVED;
	68	struct usb_ctrlrequest setup;
	69	} __attribute__ ((packed));
	70
	71	/* Extension of usb_request */
	72	struct ci13xxx_req {
	73	struct usb_request req;
	74	unsigned map;
	75	struct list_head queue;
	76	struct ci13xxx_td *ptr;
	77	dma_addr_t dma;
0e6ca199 PK	78	struct ci13xxx_td *zptr;
0e6ca199 PK	79	dma_addr_t zdma;
aa69a809 DL	80	};
	81
	82	/* Extension of usb_ep */
	83	struct ci13xxx_ep {
	84	struct usb_ep ep;
aa69a809 DL	85	u8 dir;
	86	u8 num;
	87	u8 type;
	88	char name[16];
	89	struct {
	90	struct list_head queue;
	91	struct ci13xxx_qh *ptr;
	92	dma_addr_t dma;
ca9cfea0	93	} qh;
aa69a809 DL	94	int wedge;
	95
	96	/* global resources */
d3595d13	97	struct ci13xxx *udc;
aa69a809 DL	98	spinlock_t *lock;
	99	struct device *device;
	100	struct dma_pool *td_pool;
	101	};
	102
f01ef574 PK	103	struct ci13xxx;
	104	struct ci13xxx_udc_driver {
	105	const char *name;
62bb84ed AS	106	/* offset of the capability registers */
62bb84ed AS	107	uintptr_t capoffset;
f01ef574 PK	108	unsigned long flags;
	109	#define CI13XXX_REGS_SHARED BIT(0)
	110	#define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
	111	#define CI13XXX_PULLUP_ON_VBUS BIT(2)
	112	#define CI13XXX_DISABLE_STREAMING BIT(3)
	113
	114	#define CI13XXX_CONTROLLER_RESET_EVENT 0
	115	#define CI13XXX_CONTROLLER_STOPPED_EVENT 1
	116	void (notify_event) (struct ci13xxx udc, unsigned event);
	117	};
	118
d3595d13 AS	119	struct hw_bank {
	120	unsigned lpm; /* is LPM? */
	121	void __iomem abs; / bus map offset */
	122	void __iomem cap; / bus map offset + CAP offset */
	123	void __iomem op; / bus map offset + OP offset */
	124	size_t size; /* bank size */
405b8448	125	void __iomem **regmap;
d3595d13 AS	126	};
d3595d13 AS	127
aa69a809 DL	128	/* CI13XXX UDC descriptor & global resources */
aa69a809 DL	129	struct ci13xxx {
d3595d13	130	spinlock_t lock; /* ctrl register bank access */
f01ef574	131	void __iomem regs; / registers address space */
aa69a809 DL	132
	133	struct dma_pool qh_pool; / DMA pool for queue heads */
	134	struct dma_pool td_pool; / DMA pool for transfer descs */
ca9cfea0	135	struct usb_request status; / ep0 status request */
aa69a809	136
0f089094	137	struct device *dev;
aa69a809 DL	138	struct usb_gadget gadget; /* USB slave device */
aa69a809 DL	139	struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
ca9cfea0	140	u32 ep0_dir; /* ep0 direction */
d36ade60	141	struct ci13xxx_ep ep0out, ep0in;
d3595d13 AS	142	unsigned hw_ep_max; /* number of hw endpoints */
d3595d13 AS	143
ef15e549 AS	144	bool setaddr;
ef15e549 AS	145	u8 address;
e2b61c1d PK	146	u8 remote_wakeup; /* Is remote wakeup feature
	147	enabled by the host? */
	148	u8 suspended; /* suspended by the host */
541cace8	149	u8 test_mode; /* the selected test mode */
aa69a809	150
d3595d13	151	struct hw_bank hw_bank;
62bb84ed	152	int irq;
aa69a809	153	struct usb_gadget_driver driver; / 3rd party gadget driver */
f01ef574 PK	154	struct ci13xxx_udc_driver udc_driver; / device controller driver */
f01ef574 PK	155	int vbus_active; /* is VBUS active */
86753811	156	struct usb_phy transceiver; / Transceiver struct */
aa69a809 DL	157	};
	158
	159	/******************************************************************************
	160	* REGISTERS
	161	*****************************************************************************/
f9df8395 AS	162	/* Default offset of capability registers */
	163	#define DEF_CAPOFFSET 0x100
	164
aa69a809 DL	165	/* register size */
	166	#define REG_BITS (32)
	167
262c1632 AS	168	/* register indices */
	169	enum ci13xxx_regs {
	170	CAP_CAPLENGTH,
	171	CAP_HCCPARAMS,
	172	CAP_DCCPARAMS,
	173	CAP_TESTMODE,
	174	CAP_LAST = CAP_TESTMODE,
	175	OP_USBCMD,
	176	OP_USBSTS,
	177	OP_USBINTR,
	178	OP_DEVICEADDR,
	179	OP_ENDPTLISTADDR,
	180	OP_PORTSC,
	181	OP_DEVLC,
	182	OP_USBMODE,
	183	OP_ENDPTSETUPSTAT,
	184	OP_ENDPTPRIME,
	185	OP_ENDPTFLUSH,
	186	OP_ENDPTSTAT,
	187	OP_ENDPTCOMPLETE,
	188	OP_ENDPTCTRL,
	189	/* endptctrl1..15 follow */
	190	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
	191	};
	192
aa69a809 DL	193	/* HCCPARAMS */
	194	#define HCCPARAMS_LEN BIT(17)
	195
	196	/* DCCPARAMS */
	197	#define DCCPARAMS_DEN (0x1F << 0)
	198	#define DCCPARAMS_DC BIT(7)
	199
	200	/* TESTMODE */
	201	#define TESTMODE_FORCE BIT(0)
	202
	203	/* USBCMD */
	204	#define USBCMD_RS BIT(0)
	205	#define USBCMD_RST BIT(1)
	206	#define USBCMD_SUTW BIT(13)
0e6ca199	207	#define USBCMD_ATDTW BIT(14)
aa69a809 DL	208
	209	/* USBSTS & USBINTR */
	210	#define USBi_UI BIT(0)
	211	#define USBi_UEI BIT(1)
	212	#define USBi_PCI BIT(2)
	213	#define USBi_URI BIT(6)
	214	#define USBi_SLI BIT(8)
	215
	216	/* DEVICEADDR */
	217	#define DEVICEADDR_USBADRA BIT(24)
	218	#define DEVICEADDR_USBADR (0x7FUL << 25)
	219
	220	/* PORTSC */
e2b61c1d	221	#define PORTSC_FPR BIT(6)
aa69a809 DL	222	#define PORTSC_SUSP BIT(7)
	223	#define PORTSC_HSP BIT(9)
	224	#define PORTSC_PTC (0x0FUL << 16)
	225
	226	/* DEVLC */
	227	#define DEVLC_PSPD (0x03UL << 25)
	228	#define DEVLC_PSPD_HS (0x02UL << 25)
	229
	230	/* USBMODE */
	231	#define USBMODE_CM (0x03UL << 0)
	232	#define USBMODE_CM_IDLE (0x00UL << 0)
	233	#define USBMODE_CM_DEVICE (0x02UL << 0)
	234	#define USBMODE_CM_HOST (0x03UL << 0)
	235	#define USBMODE_SLOM BIT(3)
f01ef574	236	#define USBMODE_SDIS BIT(4)
aa69a809 DL	237
	238	/* ENDPTCTRL */
	239	#define ENDPTCTRL_RXS BIT(0)
	240	#define ENDPTCTRL_RXT (0x03UL << 2)
	241	#define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
	242	#define ENDPTCTRL_RXE BIT(7)
	243	#define ENDPTCTRL_TXS BIT(16)
	244	#define ENDPTCTRL_TXT (0x03UL << 18)
	245	#define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
	246	#define ENDPTCTRL_TXE BIT(23)
	247
aa69a809	248	#endif /* _CI13XXX_h_ */