[deliverable/linux.git] / drivers / usb / chipidea / core.c

/*
 * core.c - ChipIdea USB IP core family device controller
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Description: ChipIdea USB IP core family device controller
 *
 * This driver is composed of several blocks:
 * - HW:     hardware interface
 * - DBG:    debug facilities (optional)
 * - UTIL:   utilities
 * - ISR:    interrupts handling
 * - ENDPT:  endpoint operations (Gadget API)
 * - GADGET: gadget operations (Gadget API)
 * - BUS:    bus glue code, bus abstraction layer
 *
 * Compile Options
 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 *              if defined mass storage compliance succeeds but with warnings
 *              => case 4: Hi >  Dn
 *              => case 5: Hi >  Di
 *              => case 8: Hi <> Do
 *              if undefined usbtest 13 fails
 * - TRACE:     enable function tracing (depends on DEBUG)
 *
 * Main Features
 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 * - Normal & LPM support
 *
 * USBTEST Report
 * - OK: 0-12, 13 (STALL_IN defined) & 14
 * - Not Supported: 15 & 16 (ISO)
 *
 * TODO List
 * - OTG
 * - Interrupt Traffic
 * - GET_STATUS(device) - always reports 0
 * - Gadget API (majority of optional features)
 * - Suspend & Remote Wakeup
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/usb/chipidea.h>
#include <linux/usb/of.h>
#include <linux/phy.h>
#include <linux/regulator/consumer.h>

#include "ci.h"
#include "udc.h"
#include "bits.h"
#include "host.h"
#include "debug.h"
#include "otg.h"

/* Controller register map */
static uintptr_t ci_regs_nolpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x038UL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x064UL,
	[OP_USBMODE]		= 0x068UL,
	[OP_ENDPTSETUPSTAT]	= 0x06CUL,
	[OP_ENDPTPRIME]		= 0x070UL,
	[OP_ENDPTFLUSH]		= 0x074UL,
	[OP_ENDPTSTAT]		= 0x078UL,
	[OP_ENDPTCOMPLETE]	= 0x07CUL,
	[OP_ENDPTCTRL]		= 0x080UL,
};

static uintptr_t ci_regs_lpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x0FCUL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x0C4UL,
	[OP_USBMODE]		= 0x0C8UL,
	[OP_ENDPTSETUPSTAT]	= 0x0D8UL,
	[OP_ENDPTPRIME]		= 0x0DCUL,
	[OP_ENDPTFLUSH]		= 0x0E0UL,
	[OP_ENDPTSTAT]		= 0x0E4UL,
	[OP_ENDPTCOMPLETE]	= 0x0E8UL,
	[OP_ENDPTCTRL]		= 0x0ECUL,
};

static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
{
	int i;

	kfree(ci->hw_bank.regmap);

	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
				     GFP_KERNEL);
	if (!ci->hw_bank.regmap)
		return -ENOMEM;

	for (i = 0; i < OP_ENDPTCTRL; i++)
		ci->hw_bank.regmap[i] =
			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);

	for (; i <= OP_LAST; i++)
		ci->hw_bank.regmap[i] = ci->hw_bank.op +
			4 * (i - OP_ENDPTCTRL) +
			(is_lpm
			 ? ci_regs_lpm[OP_ENDPTCTRL]
			 : ci_regs_nolpm[OP_ENDPTCTRL]);

	return 0;
}

/**
 * hw_port_test_set: writes port test mode (execute without interruption)
 * @mode: new value
 *
 * This function returns an error code
 */
int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
{
	const u8 TEST_MODE_MAX = 7;

	if (mode > TEST_MODE_MAX)
		return -EINVAL;

	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
	return 0;
}

/**
 * hw_port_test_get: reads port test mode value
 *
 * This function returns port test mode value
 */
u8 hw_port_test_get(struct ci_hdrc *ci)
{
	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
}

static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
{
	u32 reg;

	/* bank is a module variable */
	ci->hw_bank.abs = base;

	ci->hw_bank.cap = ci->hw_bank.abs;
	ci->hw_bank.cap += ci->platdata->capoffset;
	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);

	hw_alloc_regmap(ci, false);
	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
		__ffs(HCCPARAMS_LEN);
	ci->hw_bank.lpm  = reg;
	hw_alloc_regmap(ci, !!reg);
	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	ci->hw_bank.size += OP_LAST;
	ci->hw_bank.size /= sizeof(u32);

	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
		__ffs(DCCPARAMS_DEN);
	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */

	if (ci->hw_ep_max > ENDPT_MAX)
		return -ENODEV;

	/* Disable all interrupts bits */
	hw_write(ci, OP_USBINTR, 0xffffffff, 0);

	/* Clear all interrupts status bits*/
	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);

	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
		ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);

	/* setup lock mode ? */

	/* ENDPTSETUPSTAT is '0' by default */

	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */

	return 0;
}

static void hw_phymode_configure(struct ci_hdrc *ci)
{
	u32 portsc, lpm, sts;

	switch (ci->platdata->phy_mode) {
	case USBPHY_INTERFACE_MODE_UTMI:
		portsc = PORTSC_PTS(PTS_UTMI);
		lpm = DEVLC_PTS(PTS_UTMI);
		break;
	case USBPHY_INTERFACE_MODE_UTMIW:
		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
		break;
	case USBPHY_INTERFACE_MODE_ULPI:
		portsc = PORTSC_PTS(PTS_ULPI);
		lpm = DEVLC_PTS(PTS_ULPI);
		break;
	case USBPHY_INTERFACE_MODE_SERIAL:
		portsc = PORTSC_PTS(PTS_SERIAL);
		lpm = DEVLC_PTS(PTS_SERIAL);
		sts = 1;
		break;
	case USBPHY_INTERFACE_MODE_HSIC:
		portsc = PORTSC_PTS(PTS_HSIC);
		lpm = DEVLC_PTS(PTS_HSIC);
		break;
	default:
		return;
	}

	if (ci->hw_bank.lpm) {
		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
		hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	} else {
		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
		hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	}
}

/**
 * hw_device_reset: resets chip (execute without interruption)
 * @ci: the controller
  *
 * This function returns an error code
 */
int hw_device_reset(struct ci_hdrc *ci, u32 mode)
{
	/* should flush & stop before reset */
	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);

	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
		udelay(10);		/* not RTOS friendly */

	if (ci->platdata->notify_event)
		ci->platdata->notify_event(ci,
			CI_HDRC_CONTROLLER_RESET_EVENT);

	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
		hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);

	/* USBMODE should be configured step by step */
	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
	/* HW >= 2.3 */
	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);

	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
		pr_err("cannot enter in %s mode", ci_role(ci)->name);
		pr_err("lpm = %i", ci->hw_bank.lpm);
		return -ENODEV;
	}

	return 0;
}

/**
 * hw_wait_reg: wait the register value
 *
 * Sometimes, it needs to wait register value before going on.
 * Eg, when switch to device mode, the vbus value should be lower
 * than OTGSC_BSV before connects to host.
 *
 * @ci: the controller
 * @reg: register index
 * @mask: mast bit
 * @value: the bit value to wait
 * @timeout_ms: timeout in millisecond
 *
 * This function returns an error code if timeout
 */
int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
				u32 value, unsigned int timeout_ms)
{
	unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);

	while (hw_read(ci, reg, mask) != value) {
		if (time_after(jiffies, elapse)) {
			dev_err(ci->dev, "timeout waiting for %08x in %d\n",
					mask, reg);
			return -ETIMEDOUT;
		}
		msleep(20);
	}

	return 0;
}

static irqreturn_t ci_irq(int irq, void *data)
{
	struct ci_hdrc *ci = data;
	irqreturn_t ret = IRQ_NONE;
	u32 otgsc = 0;

	if (ci->is_otg)
		otgsc = hw_read(ci, OP_OTGSC, ~0);

	/*
	 * Handle id change interrupt, it indicates device/host function
	 * switch.
	 */
	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
		ci->id_event = true;
		ci_clear_otg_interrupt(ci, OTGSC_IDIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		return IRQ_HANDLED;
	}

	/*
	 * Handle vbus change interrupt, it indicates device connection
	 * and disconnection events.
	 */
	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
		ci->b_sess_valid_event = true;
		ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		return IRQ_HANDLED;
	}

	/* Handle device/host interrupt */
	if (ci->role != CI_ROLE_END)
		ret = ci_role(ci)->irq(ci);

	return ret;
}

static int ci_get_platdata(struct device *dev,
		struct ci_hdrc_platform_data *platdata)
{
	/* Get the vbus regulator */
	platdata->reg_vbus = devm_regulator_get(dev, "vbus");
	if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
		return -EPROBE_DEFER;
	} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
		platdata->reg_vbus = NULL; /* no vbus regualator is needed */
	} else if (IS_ERR(platdata->reg_vbus)) {
		dev_err(dev, "Getting regulator error: %ld\n",
			PTR_ERR(platdata->reg_vbus));
		return PTR_ERR(platdata->reg_vbus);
	}

	return 0;
}

static DEFINE_IDA(ci_ida);

struct platform_device *ci_hdrc_add_device(struct device *dev,
			struct resource *res, int nres,
			struct ci_hdrc_platform_data *platdata)
{
	struct platform_device *pdev;
	int id, ret;

	ret = ci_get_platdata(dev, platdata);
	if (ret)
		return ERR_PTR(ret);

	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	if (id < 0)
		return ERR_PTR(id);

	pdev = platform_device_alloc("ci_hdrc", id);
	if (!pdev) {
		ret = -ENOMEM;
		goto put_id;
	}

	pdev->dev.parent = dev;
	pdev->dev.dma_mask = dev->dma_mask;
	pdev->dev.dma_parms = dev->dma_parms;
	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);

	ret = platform_device_add_resources(pdev, res, nres);
	if (ret)
		goto err;

	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	if (ret)
		goto err;

	ret = platform_device_add(pdev);
	if (ret)
		goto err;

	return pdev;

err:
	platform_device_put(pdev);
put_id:
	ida_simple_remove(&ci_ida, id);
	return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(ci_hdrc_add_device);

void ci_hdrc_remove_device(struct platform_device *pdev)
{
	int id = pdev->id;
	platform_device_unregister(pdev);
	ida_simple_remove(&ci_ida, id);
}
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);

static inline void ci_role_destroy(struct ci_hdrc *ci)
{
	ci_hdrc_gadget_destroy(ci);
	ci_hdrc_host_destroy(ci);
	if (ci->is_otg)
		ci_hdrc_otg_destroy(ci);
}

static void ci_get_otg_capable(struct ci_hdrc *ci)
{
	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
		ci->is_otg = false;
	else
		ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
				DCCPARAMS_DC | DCCPARAMS_HC)
					== (DCCPARAMS_DC | DCCPARAMS_HC));
	if (ci->is_otg) {
		dev_dbg(ci->dev, "It is OTG capable controller\n");
		ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
		ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
	}
}

static int ci_hdrc_probe(struct platform_device *pdev)
{
	struct device	*dev = &pdev->dev;
	struct ci_hdrc	*ci;
	struct resource	*res;
	void __iomem	*base;
	int		ret;
	enum usb_dr_mode dr_mode;
	struct device_node *of_node = dev->of_node ?: dev->parent->of_node;

	if (!dev->platform_data) {
		dev_err(dev, "platform data missing\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		dev_err(dev, "can't allocate device\n");
		return -ENOMEM;
	}

	ci->dev = dev;
	ci->platdata = dev->platform_data;
	if (ci->platdata->phy)
		ci->transceiver = ci->platdata->phy;
	else
		ci->global_phy = true;

	ret = hw_device_init(ci, base);
	if (ret < 0) {
		dev_err(dev, "can't initialize hardware\n");
		return -ENODEV;
	}

	ci->hw_bank.phys = res->start;

	ci->irq = platform_get_irq(pdev, 0);
	if (ci->irq < 0) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}

	ci_get_otg_capable(ci);

	if (!ci->platdata->phy_mode)
		ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);

	hw_phymode_configure(ci);

	if (!ci->platdata->dr_mode)
		ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);

	if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
		ci->platdata->dr_mode = USB_DR_MODE_OTG;

	dr_mode = ci->platdata->dr_mode;
	/* initialize role(s) before the interrupt is requested */
	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
		ret = ci_hdrc_host_init(ci);
		if (ret)
			dev_info(dev, "doesn't support host\n");
	}

	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
		ret = ci_hdrc_gadget_init(ci);
		if (ret)
			dev_info(dev, "doesn't support gadget\n");
	}

	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
		dev_err(dev, "no supported roles\n");
		return -ENODEV;
	}

	if (ci->is_otg) {
		ret = ci_hdrc_otg_init(ci);
		if (ret) {
			dev_err(dev, "init otg fails, ret = %d\n", ret);
			goto stop;
		}
	}

	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
		if (ci->is_otg) {
			/*
			 * ID pin needs 1ms debouce time,
			 * we delay 2ms for safe.
			 */
			mdelay(2);
			ci->role = ci_otg_role(ci);
			ci_enable_otg_interrupt(ci, OTGSC_IDIE);
		} else {
			/*
			 * If the controller is not OTG capable, but support
			 * role switch, the defalt role is gadget, and the
			 * user can switch it through debugfs.
			 */
			ci->role = CI_ROLE_GADGET;
		}
	} else {
		ci->role = ci->roles[CI_ROLE_HOST]
			? CI_ROLE_HOST
			: CI_ROLE_GADGET;
	}

	ret = ci_role_start(ci, ci->role);
	if (ret) {
		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
		goto stop;
	}

	platform_set_drvdata(pdev, ci);
	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
			  ci);
	if (ret)
		goto stop;

	ret = dbg_create_files(ci);
	if (!ret)
		return 0;

	free_irq(ci->irq, ci);
stop:
	ci_role_destroy(ci);

	return ret;
}

static int ci_hdrc_remove(struct platform_device *pdev)
{
	struct ci_hdrc *ci = platform_get_drvdata(pdev);

	dbg_remove_files(ci);
	free_irq(ci->irq, ci);
	ci_role_destroy(ci);
	kfree(ci->hw_bank.regmap);

	return 0;
}

static struct platform_driver ci_hdrc_driver = {
	.probe	= ci_hdrc_probe,
	.remove	= ci_hdrc_remove,
	.driver	= {
		.name	= "ci_hdrc",
	},
};

module_platform_driver(ci_hdrc_driver);

MODULE_ALIAS("platform:ci_hdrc");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Commit	Line	Data
e443b333 AS	1	/*
	2	* core.c - ChipIdea USB IP core family device controller
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	/*
	14	* Description: ChipIdea USB IP core family device controller
	15	*
	16	* This driver is composed of several blocks:
	17	* - HW: hardware interface
	18	* - DBG: debug facilities (optional)
	19	* - UTIL: utilities
	20	* - ISR: interrupts handling
	21	* - ENDPT: endpoint operations (Gadget API)
	22	* - GADGET: gadget operations (Gadget API)
	23	* - BUS: bus glue code, bus abstraction layer
	24	*
	25	* Compile Options
	26	* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
	27	* - STALL_IN: non-empty bulk-in pipes cannot be halted
	28	* if defined mass storage compliance succeeds but with warnings
	29	* => case 4: Hi > Dn
	30	* => case 5: Hi > Di
	31	* => case 8: Hi <> Do
	32	* if undefined usbtest 13 fails
	33	* - TRACE: enable function tracing (depends on DEBUG)
	34	*
	35	* Main Features
	36	* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
	37	* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
	38	* - Normal & LPM support
	39	*
	40	* USBTEST Report
	41	* - OK: 0-12, 13 (STALL_IN defined) & 14
	42	* - Not Supported: 15 & 16 (ISO)
	43	*
	44	* TODO List
	45	* - OTG
e4ce4ecd	46	* - Interrupt Traffic
e443b333 AS	47	* - GET_STATUS(device) - always reports 0
	48	* - Gadget API (majority of optional features)
	49	* - Suspend & Remote Wakeup
	50	*/
	51	#include <linux/delay.h>
	52	#include <linux/device.h>
e443b333	53	#include <linux/dma-mapping.h>
e443b333 AS	54	#include <linux/platform_device.h>
e443b333 AS	55	#include <linux/module.h>
fe6e125e	56	#include <linux/idr.h>
e443b333 AS	57	#include <linux/interrupt.h>
e443b333 AS	58	#include <linux/io.h>
e443b333 AS	59	#include <linux/kernel.h>
	60	#include <linux/slab.h>
	61	#include <linux/pm_runtime.h>
	62	#include <linux/usb/ch9.h>
	63	#include <linux/usb/gadget.h>
	64	#include <linux/usb/otg.h>
	65	#include <linux/usb/chipidea.h>
40dcd0e8 MG	66	#include <linux/usb/of.h>
40dcd0e8 MG	67	#include <linux/phy.h>
1542d9c3	68	#include <linux/regulator/consumer.h>
e443b333 AS	69
	70	#include "ci.h"
	71	#include "udc.h"
	72	#include "bits.h"
eb70e5ab	73	#include "host.h"
e443b333	74	#include "debug.h"
c10b4f03	75	#include "otg.h"
e443b333	76
5f36e231	77	/* Controller register map */
e443b333 AS	78	static uintptr_t ci_regs_nolpm[] = {
	79	[CAP_CAPLENGTH] = 0x000UL,
	80	[CAP_HCCPARAMS] = 0x008UL,
	81	[CAP_DCCPARAMS] = 0x024UL,
	82	[CAP_TESTMODE] = 0x038UL,
	83	[OP_USBCMD] = 0x000UL,
	84	[OP_USBSTS] = 0x004UL,
	85	[OP_USBINTR] = 0x008UL,
	86	[OP_DEVICEADDR] = 0x014UL,
	87	[OP_ENDPTLISTADDR] = 0x018UL,
	88	[OP_PORTSC] = 0x044UL,
	89	[OP_DEVLC] = 0x084UL,
5f36e231	90	[OP_OTGSC] = 0x064UL,
e443b333 AS	91	[OP_USBMODE] = 0x068UL,
	92	[OP_ENDPTSETUPSTAT] = 0x06CUL,
	93	[OP_ENDPTPRIME] = 0x070UL,
	94	[OP_ENDPTFLUSH] = 0x074UL,
	95	[OP_ENDPTSTAT] = 0x078UL,
	96	[OP_ENDPTCOMPLETE] = 0x07CUL,
	97	[OP_ENDPTCTRL] = 0x080UL,
	98	};
	99
	100	static uintptr_t ci_regs_lpm[] = {
	101	[CAP_CAPLENGTH] = 0x000UL,
	102	[CAP_HCCPARAMS] = 0x008UL,
	103	[CAP_DCCPARAMS] = 0x024UL,
	104	[CAP_TESTMODE] = 0x0FCUL,
	105	[OP_USBCMD] = 0x000UL,
	106	[OP_USBSTS] = 0x004UL,
	107	[OP_USBINTR] = 0x008UL,
	108	[OP_DEVICEADDR] = 0x014UL,
	109	[OP_ENDPTLISTADDR] = 0x018UL,
	110	[OP_PORTSC] = 0x044UL,
	111	[OP_DEVLC] = 0x084UL,
5f36e231	112	[OP_OTGSC] = 0x0C4UL,
e443b333 AS	113	[OP_USBMODE] = 0x0C8UL,
	114	[OP_ENDPTSETUPSTAT] = 0x0D8UL,
	115	[OP_ENDPTPRIME] = 0x0DCUL,
	116	[OP_ENDPTFLUSH] = 0x0E0UL,
	117	[OP_ENDPTSTAT] = 0x0E4UL,
	118	[OP_ENDPTCOMPLETE] = 0x0E8UL,
	119	[OP_ENDPTCTRL] = 0x0ECUL,
	120	};
	121
8e22978c	122	static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
e443b333 AS	123	{
	124	int i;
	125
5f36e231	126	kfree(ci->hw_bank.regmap);
e443b333	127
5f36e231 AS	128	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
	129	GFP_KERNEL);
	130	if (!ci->hw_bank.regmap)
e443b333 AS	131	return -ENOMEM;
	132
	133	for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231 AS	134	ci->hw_bank.regmap[i] =
5f36e231 AS	135	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333 AS	136	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
	137
	138	for (; i <= OP_LAST; i++)
5f36e231	139	ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333 AS	140	4 * (i - OP_ENDPTCTRL) +
	141	(is_lpm
	142	? ci_regs_lpm[OP_ENDPTCTRL]
	143	: ci_regs_nolpm[OP_ENDPTCTRL]);
	144
	145	return 0;
	146	}
	147
	148	/**
	149	* hw_port_test_set: writes port test mode (execute without interruption)
	150	* @mode: new value
	151	*
	152	* This function returns an error code
	153	*/
8e22978c	154	int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
e443b333 AS	155	{
	156	const u8 TEST_MODE_MAX = 7;
	157
	158	if (mode > TEST_MODE_MAX)
	159	return -EINVAL;
	160
727b4ddb	161	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
e443b333 AS	162	return 0;
	163	}
	164
	165	/**
	166	* hw_port_test_get: reads port test mode value
	167	*
	168	* This function returns port test mode value
	169	*/
8e22978c	170	u8 hw_port_test_get(struct ci_hdrc *ci)
e443b333	171	{
727b4ddb	172	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
e443b333 AS	173	}
e443b333 AS	174
8e22978c	175	static int hw_device_init(struct ci_hdrc ci, void __iomem base)
e443b333 AS	176	{
	177	u32 reg;
	178
	179	/* bank is a module variable */
5f36e231	180	ci->hw_bank.abs = base;
e443b333	181
5f36e231	182	ci->hw_bank.cap = ci->hw_bank.abs;
77c4400f	183	ci->hw_bank.cap += ci->platdata->capoffset;
938d323f	184	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
e443b333	185
5f36e231 AS	186	hw_alloc_regmap(ci, false);
5f36e231 AS	187	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
727b4ddb	188	__ffs(HCCPARAMS_LEN);
5f36e231 AS	189	ci->hw_bank.lpm = reg;
	190	hw_alloc_regmap(ci, !!reg);
	191	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	192	ci->hw_bank.size += OP_LAST;
	193	ci->hw_bank.size /= sizeof(u32);
e443b333	194
5f36e231	195	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
727b4ddb	196	__ffs(DCCPARAMS_DEN);
5f36e231	197	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333	198
09c94e62	199	if (ci->hw_ep_max > ENDPT_MAX)
e443b333 AS	200	return -ENODEV;
e443b333 AS	201
c344b518 PC	202	/* Disable all interrupts bits */
	203	hw_write(ci, OP_USBINTR, 0xffffffff, 0);
	204
	205	/* Clear all interrupts status bits*/
	206	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
	207
5f36e231 AS	208	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
5f36e231 AS	209	ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333 AS	210
	211	/* setup lock mode ? */
	212
	213	/* ENDPTSETUPSTAT is '0' by default */
	214
	215	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
	216
	217	return 0;
	218	}
	219
8e22978c	220	static void hw_phymode_configure(struct ci_hdrc *ci)
40dcd0e8 MG	221	{
	222	u32 portsc, lpm, sts;
	223
	224	switch (ci->platdata->phy_mode) {
	225	case USBPHY_INTERFACE_MODE_UTMI:
	226	portsc = PORTSC_PTS(PTS_UTMI);
	227	lpm = DEVLC_PTS(PTS_UTMI);
	228	break;
	229	case USBPHY_INTERFACE_MODE_UTMIW:
	230	portsc = PORTSC_PTS(PTS_UTMI) \| PORTSC_PTW;
	231	lpm = DEVLC_PTS(PTS_UTMI) \| DEVLC_PTW;
	232	break;
	233	case USBPHY_INTERFACE_MODE_ULPI:
	234	portsc = PORTSC_PTS(PTS_ULPI);
	235	lpm = DEVLC_PTS(PTS_ULPI);
	236	break;
	237	case USBPHY_INTERFACE_MODE_SERIAL:
	238	portsc = PORTSC_PTS(PTS_SERIAL);
	239	lpm = DEVLC_PTS(PTS_SERIAL);
	240	sts = 1;
	241	break;
	242	case USBPHY_INTERFACE_MODE_HSIC:
	243	portsc = PORTSC_PTS(PTS_HSIC);
	244	lpm = DEVLC_PTS(PTS_HSIC);
	245	break;
	246	default:
	247	return;
	248	}
	249
	250	if (ci->hw_bank.lpm) {
	251	hw_write(ci, OP_DEVLC, DEVLC_PTS(7) \| DEVLC_PTW, lpm);
	252	hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	253	} else {
	254	hw_write(ci, OP_PORTSC, PORTSC_PTS(7) \| PORTSC_PTW, portsc);
	255	hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	256	}
	257	}
	258
e443b333 AS	259	/**
	260	* hw_device_reset: resets chip (execute without interruption)
	261	* @ci: the controller
	262	*
	263	* This function returns an error code
	264	*/
8e22978c	265	int hw_device_reset(struct ci_hdrc *ci, u32 mode)
e443b333 AS	266	{
	267	/* should flush & stop before reset */
	268	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	269	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
	270
	271	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	272	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
	273	udelay(10); /* not RTOS friendly */
	274
77c4400f RZ	275	if (ci->platdata->notify_event)
77c4400f RZ	276	ci->platdata->notify_event(ci,
8e22978c	277	CI_HDRC_CONTROLLER_RESET_EVENT);
e443b333	278
8e22978c	279	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
758fc986	280	hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 AS	281
	282	/* USBMODE should be configured step by step */
	283	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab	284	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333 AS	285	/* HW >= 2.3 */
	286	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
	287
eb70e5ab AS	288	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
eb70e5ab AS	289	pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333 AS	290	pr_err("lpm = %i", ci->hw_bank.lpm);
	291	return -ENODEV;
	292	}
	293
	294	return 0;
	295	}
	296
22fa8445 PC	297	/**
	298	* hw_wait_reg: wait the register value
	299	*
	300	* Sometimes, it needs to wait register value before going on.
	301	* Eg, when switch to device mode, the vbus value should be lower
	302	* than OTGSC_BSV before connects to host.
	303	*
	304	* @ci: the controller
	305	* @reg: register index
	306	* @mask: mast bit
	307	* @value: the bit value to wait
	308	* @timeout_ms: timeout in millisecond
	309	*
	310	* This function returns an error code if timeout
	311	*/
	312	int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
	313	u32 value, unsigned int timeout_ms)
	314	{
	315	unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
	316
	317	while (hw_read(ci, reg, mask) != value) {
	318	if (time_after(jiffies, elapse)) {
	319	dev_err(ci->dev, "timeout waiting for %08x in %d\n",
	320	mask, reg);
	321	return -ETIMEDOUT;
	322	}
	323	msleep(20);
	324	}
	325
	326	return 0;
	327	}
	328
5f36e231 AS	329	static irqreturn_t ci_irq(int irq, void *data)
5f36e231 AS	330	{
8e22978c	331	struct ci_hdrc *ci = data;
5f36e231	332	irqreturn_t ret = IRQ_NONE;
b183c19f	333	u32 otgsc = 0;
5f36e231	334
b183c19f RZ	335	if (ci->is_otg)
b183c19f RZ	336	otgsc = hw_read(ci, OP_OTGSC, ~0);
5f36e231	337
a107f8c5 PC	338	/*
	339	* Handle id change interrupt, it indicates device/host function
	340	* switch.
	341	*/
	342	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
	343	ci->id_event = true;
	344	ci_clear_otg_interrupt(ci, OTGSC_IDIS);
	345	disable_irq_nosync(ci->irq);
	346	queue_work(ci->wq, &ci->work);
	347	return IRQ_HANDLED;
	348	}
b183c19f	349
a107f8c5 PC	350	/*
	351	* Handle vbus change interrupt, it indicates device connection
	352	* and disconnection events.
	353	*/
	354	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
	355	ci->b_sess_valid_event = true;
	356	ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
b183c19f RZ	357	disable_irq_nosync(ci->irq);
b183c19f RZ	358	queue_work(ci->wq, &ci->work);
a107f8c5	359	return IRQ_HANDLED;
5f36e231 AS	360	}
5f36e231 AS	361
a107f8c5 PC	362	/* Handle device/host interrupt */
	363	if (ci->role != CI_ROLE_END)
	364	ret = ci_role(ci)->irq(ci);
	365
b183c19f	366	return ret;
5f36e231 AS	367	}
5f36e231 AS	368
1542d9c3 PC	369	static int ci_get_platdata(struct device *dev,
	370	struct ci_hdrc_platform_data *platdata)
	371	{
	372	/* Get the vbus regulator */
	373	platdata->reg_vbus = devm_regulator_get(dev, "vbus");
	374	if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
	375	return -EPROBE_DEFER;
	376	} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
	377	platdata->reg_vbus = NULL; /* no vbus regualator is needed */
	378	} else if (IS_ERR(platdata->reg_vbus)) {
	379	dev_err(dev, "Getting regulator error: %ld\n",
	380	PTR_ERR(platdata->reg_vbus));
	381	return PTR_ERR(platdata->reg_vbus);
	382	}
	383
	384	return 0;
	385	}
	386
fe6e125e RZ	387	static DEFINE_IDA(ci_ida);
fe6e125e RZ	388
8e22978c	389	struct platform_device ci_hdrc_add_device(struct device dev,
cbc6dc2a	390	struct resource *res, int nres,
8e22978c	391	struct ci_hdrc_platform_data *platdata)
cbc6dc2a RZ	392	{
cbc6dc2a RZ	393	struct platform_device *pdev;
fe6e125e	394	int id, ret;
cbc6dc2a	395
1542d9c3 PC	396	ret = ci_get_platdata(dev, platdata);
	397	if (ret)
	398	return ERR_PTR(ret);
	399
fe6e125e RZ	400	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	401	if (id < 0)
	402	return ERR_PTR(id);
	403
	404	pdev = platform_device_alloc("ci_hdrc", id);
	405	if (!pdev) {
	406	ret = -ENOMEM;
	407	goto put_id;
	408	}
cbc6dc2a RZ	409
	410	pdev->dev.parent = dev;
	411	pdev->dev.dma_mask = dev->dma_mask;
	412	pdev->dev.dma_parms = dev->dma_parms;
	413	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
	414
	415	ret = platform_device_add_resources(pdev, res, nres);
	416	if (ret)
	417	goto err;
	418
	419	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	420	if (ret)
	421	goto err;
	422
	423	ret = platform_device_add(pdev);
	424	if (ret)
	425	goto err;
	426
	427	return pdev;
	428
	429	err:
	430	platform_device_put(pdev);
fe6e125e RZ	431	put_id:
fe6e125e RZ	432	ida_simple_remove(&ci_ida, id);
cbc6dc2a RZ	433	return ERR_PTR(ret);
cbc6dc2a RZ	434	}
8e22978c	435	EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
cbc6dc2a	436
8e22978c	437	void ci_hdrc_remove_device(struct platform_device *pdev)
cbc6dc2a	438	{
98c35534	439	int id = pdev->id;
cbc6dc2a	440	platform_device_unregister(pdev);
98c35534	441	ida_simple_remove(&ci_ida, id);
cbc6dc2a	442	}
8e22978c	443	EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
cbc6dc2a	444
3f124d23 PC	445	static inline void ci_role_destroy(struct ci_hdrc *ci)
	446	{
	447	ci_hdrc_gadget_destroy(ci);
	448	ci_hdrc_host_destroy(ci);
cbec6bd5 PC	449	if (ci->is_otg)
cbec6bd5 PC	450	ci_hdrc_otg_destroy(ci);
3f124d23 PC	451	}
3f124d23 PC	452
577b232f PC	453	static void ci_get_otg_capable(struct ci_hdrc *ci)
	454	{
	455	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
	456	ci->is_otg = false;
	457	else
	458	ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
	459	DCCPARAMS_DC \| DCCPARAMS_HC)
	460	== (DCCPARAMS_DC \| DCCPARAMS_HC));
c344b518	461	if (ci->is_otg) {
577b232f	462	dev_dbg(ci->dev, "It is OTG capable controller\n");
c344b518 PC	463	ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
	464	ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
	465	}
577b232f PC	466	}
577b232f PC	467
41ac7b3a	468	static int ci_hdrc_probe(struct platform_device *pdev)
e443b333 AS	469	{
e443b333 AS	470	struct device *dev = &pdev->dev;
8e22978c	471	struct ci_hdrc *ci;
e443b333 AS	472	struct resource *res;
	473	void __iomem *base;
	474	int ret;
691962d1	475	enum usb_dr_mode dr_mode;
e98b44e9	476	struct device_node *of_node = dev->of_node ?: dev->parent->of_node;
e443b333	477
5f36e231	478	if (!dev->platform_data) {
e443b333 AS	479	dev_err(dev, "platform data missing\n");
	480	return -ENODEV;
	481	}
	482
	483	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
19290816 FB	484	base = devm_ioremap_resource(dev, res);
	485	if (IS_ERR(base))
	486	return PTR_ERR(base);
e443b333	487
5f36e231 AS	488	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	489	if (!ci) {
	490	dev_err(dev, "can't allocate device\n");
	491	return -ENOMEM;
	492	}
	493
	494	ci->dev = dev;
77c4400f	495	ci->platdata = dev->platform_data;
a2c3d690 RZ	496	if (ci->platdata->phy)
	497	ci->transceiver = ci->platdata->phy;
	498	else
	499	ci->global_phy = true;
5f36e231 AS	500
	501	ret = hw_device_init(ci, base);
	502	if (ret < 0) {
	503	dev_err(dev, "can't initialize hardware\n");
	504	return -ENODEV;
	505	}
e443b333	506
eb70e5ab AS	507	ci->hw_bank.phys = res->start;
eb70e5ab AS	508
5f36e231 AS	509	ci->irq = platform_get_irq(pdev, 0);
5f36e231 AS	510	if (ci->irq < 0) {
e443b333	511	dev_err(dev, "missing IRQ\n");
5f36e231 AS	512	return -ENODEV;
	513	}
	514
577b232f PC	515	ci_get_otg_capable(ci);
577b232f PC	516
40dcd0e8	517	if (!ci->platdata->phy_mode)
e98b44e9	518	ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
40dcd0e8	519
03779f05 FE	520	hw_phymode_configure(ci);
03779f05 FE	521
691962d1	522	if (!ci->platdata->dr_mode)
e98b44e9	523	ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);
691962d1 SH	524
	525	if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
	526	ci->platdata->dr_mode = USB_DR_MODE_OTG;
	527
	528	dr_mode = ci->platdata->dr_mode;
5f36e231	529	/* initialize role(s) before the interrupt is requested */
691962d1 SH	530	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_HOST) {
	531	ret = ci_hdrc_host_init(ci);
	532	if (ret)
	533	dev_info(dev, "doesn't support host\n");
	534	}
eb70e5ab	535
691962d1 SH	536	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_PERIPHERAL) {
	537	ret = ci_hdrc_gadget_init(ci);
	538	if (ret)
	539	dev_info(dev, "doesn't support gadget\n");
	540	}
5f36e231 AS	541
	542	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
	543	dev_err(dev, "no supported roles\n");
cbec6bd5 PC	544	return -ENODEV;
	545	}
	546
	547	if (ci->is_otg) {
	548	ret = ci_hdrc_otg_init(ci);
	549	if (ret) {
	550	dev_err(dev, "init otg fails, ret = %d\n", ret);
	551	goto stop;
	552	}
5f36e231 AS	553	}
	554
	555	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
577b232f PC	556	if (ci->is_otg) {
	557	/*
	558	* ID pin needs 1ms debouce time,
	559	* we delay 2ms for safe.
	560	*/
	561	mdelay(2);
	562	ci->role = ci_otg_role(ci);
cbec6bd5	563	ci_enable_otg_interrupt(ci, OTGSC_IDIE);
577b232f PC	564	} else {
	565	/*
	566	* If the controller is not OTG capable, but support
	567	* role switch, the defalt role is gadget, and the
	568	* user can switch it through debugfs.
	569	*/
	570	ci->role = CI_ROLE_GADGET;
	571	}
5f36e231 AS	572	} else {
	573	ci->role = ci->roles[CI_ROLE_HOST]
	574	? CI_ROLE_HOST
	575	: CI_ROLE_GADGET;
	576	}
	577
	578	ret = ci_role_start(ci, ci->role);
	579	if (ret) {
	580	dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
cbec6bd5	581	goto stop;
e443b333 AS	582	}
e443b333 AS	583
5f36e231	584	platform_set_drvdata(pdev, ci);
77c4400f	585	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
5f36e231 AS	586	ci);
	587	if (ret)
	588	goto stop;
e443b333	589
adf0f735 AS	590	ret = dbg_create_files(ci);
	591	if (!ret)
	592	return 0;
5f36e231	593
adf0f735	594	free_irq(ci->irq, ci);
5f36e231	595	stop:
3f124d23	596	ci_role_destroy(ci);
e443b333 AS	597
	598	return ret;
	599	}
	600
fb4e98ab	601	static int ci_hdrc_remove(struct platform_device *pdev)
e443b333	602	{
8e22978c	603	struct ci_hdrc *ci = platform_get_drvdata(pdev);
e443b333	604
adf0f735	605	dbg_remove_files(ci);
5f36e231	606	free_irq(ci->irq, ci);
3f124d23	607	ci_role_destroy(ci);
222bed9b	608	kfree(ci->hw_bank.regmap);
e443b333 AS	609
	610	return 0;
	611	}
	612
5f36e231 AS	613	static struct platform_driver ci_hdrc_driver = {
5f36e231 AS	614	.probe = ci_hdrc_probe,
7690417d	615	.remove = ci_hdrc_remove,
e443b333	616	.driver = {
5f36e231	617	.name = "ci_hdrc",
e443b333 AS	618	},
	619	};
	620
5f36e231	621	module_platform_driver(ci_hdrc_driver);
e443b333	622
5f36e231	623	MODULE_ALIAS("platform:ci_hdrc");
e443b333 AS	624	MODULE_LICENSE("GPL v2");
e443b333 AS	625	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231	626	MODULE_DESCRIPTION("ChipIdea HDRC Driver");