[deliverable/linux.git] / drivers / usb / chipidea / core.c

/*
 * core.c - ChipIdea USB IP core family device controller
 *
 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
 *
 * Author: David Lopo
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Description: ChipIdea USB IP core family device controller
 *
 * This driver is composed of several blocks:
 * - HW:     hardware interface
 * - DBG:    debug facilities (optional)
 * - UTIL:   utilities
 * - ISR:    interrupts handling
 * - ENDPT:  endpoint operations (Gadget API)
 * - GADGET: gadget operations (Gadget API)
 * - BUS:    bus glue code, bus abstraction layer
 *
 * Compile Options
 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
 * - STALL_IN:  non-empty bulk-in pipes cannot be halted
 *              if defined mass storage compliance succeeds but with warnings
 *              => case 4: Hi >  Dn
 *              => case 5: Hi >  Di
 *              => case 8: Hi <> Do
 *              if undefined usbtest 13 fails
 * - TRACE:     enable function tracing (depends on DEBUG)
 *
 * Main Features
 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
 * - Normal & LPM support
 *
 * USBTEST Report
 * - OK: 0-12, 13 (STALL_IN defined) & 14
 * - Not Supported: 15 & 16 (ISO)
 *
 * TODO List
 * - OTG
 * - Interrupt Traffic
 * - GET_STATUS(device) - always reports 0
 * - Gadget API (majority of optional features)
 * - Suspend & Remote Wakeup
 */
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/idr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/otg.h>
#include <linux/usb/chipidea.h>
#include <linux/usb/of.h>
#include <linux/phy.h>
#include <linux/regulator/consumer.h>

#include "ci.h"
#include "udc.h"
#include "bits.h"
#include "host.h"
#include "debug.h"
#include "otg.h"

/* Controller register map */
static uintptr_t ci_regs_nolpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x038UL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x064UL,
	[OP_USBMODE]		= 0x068UL,
	[OP_ENDPTSETUPSTAT]	= 0x06CUL,
	[OP_ENDPTPRIME]		= 0x070UL,
	[OP_ENDPTFLUSH]		= 0x074UL,
	[OP_ENDPTSTAT]		= 0x078UL,
	[OP_ENDPTCOMPLETE]	= 0x07CUL,
	[OP_ENDPTCTRL]		= 0x080UL,
};

static uintptr_t ci_regs_lpm[] = {
	[CAP_CAPLENGTH]		= 0x000UL,
	[CAP_HCCPARAMS]		= 0x008UL,
	[CAP_DCCPARAMS]		= 0x024UL,
	[CAP_TESTMODE]		= 0x0FCUL,
	[OP_USBCMD]		= 0x000UL,
	[OP_USBSTS]		= 0x004UL,
	[OP_USBINTR]		= 0x008UL,
	[OP_DEVICEADDR]		= 0x014UL,
	[OP_ENDPTLISTADDR]	= 0x018UL,
	[OP_PORTSC]		= 0x044UL,
	[OP_DEVLC]		= 0x084UL,
	[OP_OTGSC]		= 0x0C4UL,
	[OP_USBMODE]		= 0x0C8UL,
	[OP_ENDPTSETUPSTAT]	= 0x0D8UL,
	[OP_ENDPTPRIME]		= 0x0DCUL,
	[OP_ENDPTFLUSH]		= 0x0E0UL,
	[OP_ENDPTSTAT]		= 0x0E4UL,
	[OP_ENDPTCOMPLETE]	= 0x0E8UL,
	[OP_ENDPTCTRL]		= 0x0ECUL,
};

static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
{
	int i;

	kfree(ci->hw_bank.regmap);

	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
				     GFP_KERNEL);
	if (!ci->hw_bank.regmap)
		return -ENOMEM;

	for (i = 0; i < OP_ENDPTCTRL; i++)
		ci->hw_bank.regmap[i] =
			(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
			(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);

	for (; i <= OP_LAST; i++)
		ci->hw_bank.regmap[i] = ci->hw_bank.op +
			4 * (i - OP_ENDPTCTRL) +
			(is_lpm
			 ? ci_regs_lpm[OP_ENDPTCTRL]
			 : ci_regs_nolpm[OP_ENDPTCTRL]);

	return 0;
}

/**
 * hw_port_test_set: writes port test mode (execute without interruption)
 * @mode: new value
 *
 * This function returns an error code
 */
int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
{
	const u8 TEST_MODE_MAX = 7;

	if (mode > TEST_MODE_MAX)
		return -EINVAL;

	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
	return 0;
}

/**
 * hw_port_test_get: reads port test mode value
 *
 * This function returns port test mode value
 */
u8 hw_port_test_get(struct ci_hdrc *ci)
{
	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
}

/* The PHY enters/leaves low power mode */
static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
{
	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));

	if (enable && !lpm) {
		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
				PORTSC_PHCD(ci->hw_bank.lpm));
	} else  if (!enable && lpm) {
		hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
				0);
		/* 
		 * The controller needs at least 1ms to reflect
		 * PHY's status, the PHY also needs some time (less
		 * than 1ms) to leave low power mode.
		 */
		usleep_range(1500, 2000);
	}
}

static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
{
	u32 reg;

	/* bank is a module variable */
	ci->hw_bank.abs = base;

	ci->hw_bank.cap = ci->hw_bank.abs;
	ci->hw_bank.cap += ci->platdata->capoffset;
	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);

	hw_alloc_regmap(ci, false);
	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
		__ffs(HCCPARAMS_LEN);
	ci->hw_bank.lpm  = reg;
	hw_alloc_regmap(ci, !!reg);
	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	ci->hw_bank.size += OP_LAST;
	ci->hw_bank.size /= sizeof(u32);

	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
		__ffs(DCCPARAMS_DEN);
	ci->hw_ep_max = reg * 2;   /* cache hw ENDPT_MAX */

	if (ci->hw_ep_max > ENDPT_MAX)
		return -ENODEV;

	ci_hdrc_enter_lpm(ci, false);

	/* Disable all interrupts bits */
	hw_write(ci, OP_USBINTR, 0xffffffff, 0);

	/* Clear all interrupts status bits*/
	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);

	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
		ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);

	/* setup lock mode ? */

	/* ENDPTSETUPSTAT is '0' by default */

	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */

	return 0;
}

static void hw_phymode_configure(struct ci_hdrc *ci)
{
	u32 portsc, lpm, sts;

	switch (ci->platdata->phy_mode) {
	case USBPHY_INTERFACE_MODE_UTMI:
		portsc = PORTSC_PTS(PTS_UTMI);
		lpm = DEVLC_PTS(PTS_UTMI);
		break;
	case USBPHY_INTERFACE_MODE_UTMIW:
		portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
		lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
		break;
	case USBPHY_INTERFACE_MODE_ULPI:
		portsc = PORTSC_PTS(PTS_ULPI);
		lpm = DEVLC_PTS(PTS_ULPI);
		break;
	case USBPHY_INTERFACE_MODE_SERIAL:
		portsc = PORTSC_PTS(PTS_SERIAL);
		lpm = DEVLC_PTS(PTS_SERIAL);
		sts = 1;
		break;
	case USBPHY_INTERFACE_MODE_HSIC:
		portsc = PORTSC_PTS(PTS_HSIC);
		lpm = DEVLC_PTS(PTS_HSIC);
		break;
	default:
		return;
	}

	if (ci->hw_bank.lpm) {
		hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
		hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	} else {
		hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
		hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	}
}

/**
 * hw_device_reset: resets chip (execute without interruption)
 * @ci: the controller
  *
 * This function returns an error code
 */
int hw_device_reset(struct ci_hdrc *ci, u32 mode)
{
	/* should flush & stop before reset */
	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);

	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
		udelay(10);		/* not RTOS friendly */

	if (ci->platdata->notify_event)
		ci->platdata->notify_event(ci,
			CI_HDRC_CONTROLLER_RESET_EVENT);

	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
		hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);

	/* USBMODE should be configured step by step */
	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
	/* HW >= 2.3 */
	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);

	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
		pr_err("cannot enter in %s mode", ci_role(ci)->name);
		pr_err("lpm = %i", ci->hw_bank.lpm);
		return -ENODEV;
	}

	return 0;
}

/**
 * hw_wait_reg: wait the register value
 *
 * Sometimes, it needs to wait register value before going on.
 * Eg, when switch to device mode, the vbus value should be lower
 * than OTGSC_BSV before connects to host.
 *
 * @ci: the controller
 * @reg: register index
 * @mask: mast bit
 * @value: the bit value to wait
 * @timeout_ms: timeout in millisecond
 *
 * This function returns an error code if timeout
 */
int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
				u32 value, unsigned int timeout_ms)
{
	unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);

	while (hw_read(ci, reg, mask) != value) {
		if (time_after(jiffies, elapse)) {
			dev_err(ci->dev, "timeout waiting for %08x in %d\n",
					mask, reg);
			return -ETIMEDOUT;
		}
		msleep(20);
	}

	return 0;
}

static irqreturn_t ci_irq(int irq, void *data)
{
	struct ci_hdrc *ci = data;
	irqreturn_t ret = IRQ_NONE;
	u32 otgsc = 0;

	if (ci->is_otg)
		otgsc = hw_read(ci, OP_OTGSC, ~0);

	/*
	 * Handle id change interrupt, it indicates device/host function
	 * switch.
	 */
	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
		ci->id_event = true;
		ci_clear_otg_interrupt(ci, OTGSC_IDIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		return IRQ_HANDLED;
	}

	/*
	 * Handle vbus change interrupt, it indicates device connection
	 * and disconnection events.
	 */
	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
		ci->b_sess_valid_event = true;
		ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
		disable_irq_nosync(ci->irq);
		queue_work(ci->wq, &ci->work);
		return IRQ_HANDLED;
	}

	/* Handle device/host interrupt */
	if (ci->role != CI_ROLE_END)
		ret = ci_role(ci)->irq(ci);

	return ret;
}

static int ci_get_platdata(struct device *dev,
		struct ci_hdrc_platform_data *platdata)
{
	if (!platdata->phy_mode)
		platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);

	if (!platdata->dr_mode)
		platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);

	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
		platdata->dr_mode = USB_DR_MODE_OTG;

	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
		/* Get the vbus regulator */
		platdata->reg_vbus = devm_regulator_get(dev, "vbus");
		if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
			return -EPROBE_DEFER;
		} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
			/* no vbus regualator is needed */
			platdata->reg_vbus = NULL;
		} else if (IS_ERR(platdata->reg_vbus)) {
			dev_err(dev, "Getting regulator error: %ld\n",
				PTR_ERR(platdata->reg_vbus));
			return PTR_ERR(platdata->reg_vbus);
		}
	}

	return 0;
}

static DEFINE_IDA(ci_ida);

struct platform_device *ci_hdrc_add_device(struct device *dev,
			struct resource *res, int nres,
			struct ci_hdrc_platform_data *platdata)
{
	struct platform_device *pdev;
	int id, ret;

	ret = ci_get_platdata(dev, platdata);
	if (ret)
		return ERR_PTR(ret);

	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	if (id < 0)
		return ERR_PTR(id);

	pdev = platform_device_alloc("ci_hdrc", id);
	if (!pdev) {
		ret = -ENOMEM;
		goto put_id;
	}

	pdev->dev.parent = dev;
	pdev->dev.dma_mask = dev->dma_mask;
	pdev->dev.dma_parms = dev->dma_parms;
	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);

	ret = platform_device_add_resources(pdev, res, nres);
	if (ret)
		goto err;

	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	if (ret)
		goto err;

	ret = platform_device_add(pdev);
	if (ret)
		goto err;

	return pdev;

err:
	platform_device_put(pdev);
put_id:
	ida_simple_remove(&ci_ida, id);
	return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(ci_hdrc_add_device);

void ci_hdrc_remove_device(struct platform_device *pdev)
{
	int id = pdev->id;
	platform_device_unregister(pdev);
	ida_simple_remove(&ci_ida, id);
}
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);

static inline void ci_role_destroy(struct ci_hdrc *ci)
{
	ci_hdrc_gadget_destroy(ci);
	ci_hdrc_host_destroy(ci);
	if (ci->is_otg)
		ci_hdrc_otg_destroy(ci);
}

static void ci_get_otg_capable(struct ci_hdrc *ci)
{
	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
		ci->is_otg = false;
	else
		ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
				DCCPARAMS_DC | DCCPARAMS_HC)
					== (DCCPARAMS_DC | DCCPARAMS_HC));
	if (ci->is_otg) {
		dev_dbg(ci->dev, "It is OTG capable controller\n");
		ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
		ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
	}
}

static int ci_usb_phy_init(struct ci_hdrc *ci)
{
	if (ci->platdata->phy) {
		ci->transceiver = ci->platdata->phy;
		return usb_phy_init(ci->transceiver);
	} else {
		ci->global_phy = true;
		ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
		if (IS_ERR(ci->transceiver))
			ci->transceiver = NULL;

		return 0;
	}
}

static void ci_usb_phy_destroy(struct ci_hdrc *ci)
{
	if (!ci->transceiver)
		return;

	otg_set_peripheral(ci->transceiver->otg, NULL);
	if (ci->global_phy)
		usb_put_phy(ci->transceiver);
	else
		usb_phy_shutdown(ci->transceiver);
}

static int ci_hdrc_probe(struct platform_device *pdev)
{
	struct device	*dev = &pdev->dev;
	struct ci_hdrc	*ci;
	struct resource	*res;
	void __iomem	*base;
	int		ret;
	enum usb_dr_mode dr_mode;

	if (!dev->platform_data) {
		dev_err(dev, "platform data missing\n");
		return -ENODEV;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	if (!ci) {
		dev_err(dev, "can't allocate device\n");
		return -ENOMEM;
	}

	ci->dev = dev;
	ci->platdata = dev->platform_data;

	ret = hw_device_init(ci, base);
	if (ret < 0) {
		dev_err(dev, "can't initialize hardware\n");
		return -ENODEV;
	}

	ret = ci_usb_phy_init(ci);
	if (ret) {
		dev_err(dev, "unable to init phy: %d\n", ret);
		return ret;
	}

	ci->hw_bank.phys = res->start;

	ci->irq = platform_get_irq(pdev, 0);
	if (ci->irq < 0) {
		dev_err(dev, "missing IRQ\n");
		ret = -ENODEV;
		goto destroy_phy;
	}

	ci_get_otg_capable(ci);

	hw_phymode_configure(ci);

	dr_mode = ci->platdata->dr_mode;
	/* initialize role(s) before the interrupt is requested */
	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
		ret = ci_hdrc_host_init(ci);
		if (ret)
			dev_info(dev, "doesn't support host\n");
	}

	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
		ret = ci_hdrc_gadget_init(ci);
		if (ret)
			dev_info(dev, "doesn't support gadget\n");
		if (!ret && ci->transceiver) {
			ret = otg_set_peripheral(ci->transceiver->otg,
							&ci->gadget);
			/*
			 * If we implement all USB functions using chipidea drivers,
			 * it doesn't need to call above API, meanwhile, if we only
			 * use gadget function, calling above API is useless.
			 */
			if (ret && ret != -ENOTSUPP)
				goto destroy_phy;
		}
	}

	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
		dev_err(dev, "no supported roles\n");
		ret = -ENODEV;
		goto destroy_phy;
	}

	if (ci->is_otg) {
		ret = ci_hdrc_otg_init(ci);
		if (ret) {
			dev_err(dev, "init otg fails, ret = %d\n", ret);
			goto stop;
		}
	}

	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
		if (ci->is_otg) {
			/*
			 * ID pin needs 1ms debouce time,
			 * we delay 2ms for safe.
			 */
			mdelay(2);
			ci->role = ci_otg_role(ci);
			ci_enable_otg_interrupt(ci, OTGSC_IDIE);
		} else {
			/*
			 * If the controller is not OTG capable, but support
			 * role switch, the defalt role is gadget, and the
			 * user can switch it through debugfs.
			 */
			ci->role = CI_ROLE_GADGET;
		}
	} else {
		ci->role = ci->roles[CI_ROLE_HOST]
			? CI_ROLE_HOST
			: CI_ROLE_GADGET;
	}

	ret = ci_role_start(ci, ci->role);
	if (ret) {
		dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
		goto stop;
	}

	platform_set_drvdata(pdev, ci);
	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
			  ci);
	if (ret)
		goto stop;

	ret = dbg_create_files(ci);
	if (!ret)
		return 0;

	free_irq(ci->irq, ci);
stop:
	ci_role_destroy(ci);
destroy_phy:
	ci_usb_phy_destroy(ci);

	return ret;
}

static int ci_hdrc_remove(struct platform_device *pdev)
{
	struct ci_hdrc *ci = platform_get_drvdata(pdev);

	dbg_remove_files(ci);
	free_irq(ci->irq, ci);
	ci_role_destroy(ci);
	ci_hdrc_enter_lpm(ci, true);
	ci_usb_phy_destroy(ci);
	kfree(ci->hw_bank.regmap);

	return 0;
}

static struct platform_driver ci_hdrc_driver = {
	.probe	= ci_hdrc_probe,
	.remove	= ci_hdrc_remove,
	.driver	= {
		.name	= "ci_hdrc",
	},
};

module_platform_driver(ci_hdrc_driver);

MODULE_ALIAS("platform:ci_hdrc");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
Commit	Line	Data
e443b333 AS	1	/*
	2	* core.c - ChipIdea USB IP core family device controller
	3	*
	4	* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
	5	*
	6	* Author: David Lopo
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	/*
	14	* Description: ChipIdea USB IP core family device controller
	15	*
	16	* This driver is composed of several blocks:
	17	* - HW: hardware interface
	18	* - DBG: debug facilities (optional)
	19	* - UTIL: utilities
	20	* - ISR: interrupts handling
	21	* - ENDPT: endpoint operations (Gadget API)
	22	* - GADGET: gadget operations (Gadget API)
	23	* - BUS: bus glue code, bus abstraction layer
	24	*
	25	* Compile Options
	26	* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
	27	* - STALL_IN: non-empty bulk-in pipes cannot be halted
	28	* if defined mass storage compliance succeeds but with warnings
	29	* => case 4: Hi > Dn
	30	* => case 5: Hi > Di
	31	* => case 8: Hi <> Do
	32	* if undefined usbtest 13 fails
	33	* - TRACE: enable function tracing (depends on DEBUG)
	34	*
	35	* Main Features
	36	* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
	37	* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
	38	* - Normal & LPM support
	39	*
	40	* USBTEST Report
	41	* - OK: 0-12, 13 (STALL_IN defined) & 14
	42	* - Not Supported: 15 & 16 (ISO)
	43	*
	44	* TODO List
	45	* - OTG
e4ce4ecd	46	* - Interrupt Traffic
e443b333 AS	47	* - GET_STATUS(device) - always reports 0
	48	* - Gadget API (majority of optional features)
	49	* - Suspend & Remote Wakeup
	50	*/
	51	#include <linux/delay.h>
	52	#include <linux/device.h>
e443b333	53	#include <linux/dma-mapping.h>
e443b333 AS	54	#include <linux/platform_device.h>
e443b333 AS	55	#include <linux/module.h>
fe6e125e	56	#include <linux/idr.h>
e443b333 AS	57	#include <linux/interrupt.h>
e443b333 AS	58	#include <linux/io.h>
e443b333 AS	59	#include <linux/kernel.h>
	60	#include <linux/slab.h>
	61	#include <linux/pm_runtime.h>
	62	#include <linux/usb/ch9.h>
	63	#include <linux/usb/gadget.h>
	64	#include <linux/usb/otg.h>
	65	#include <linux/usb/chipidea.h>
40dcd0e8 MG	66	#include <linux/usb/of.h>
40dcd0e8 MG	67	#include <linux/phy.h>
1542d9c3	68	#include <linux/regulator/consumer.h>
e443b333 AS	69
	70	#include "ci.h"
	71	#include "udc.h"
	72	#include "bits.h"
eb70e5ab	73	#include "host.h"
e443b333	74	#include "debug.h"
c10b4f03	75	#include "otg.h"
e443b333	76
5f36e231	77	/* Controller register map */
e443b333 AS	78	static uintptr_t ci_regs_nolpm[] = {
	79	[CAP_CAPLENGTH] = 0x000UL,
	80	[CAP_HCCPARAMS] = 0x008UL,
	81	[CAP_DCCPARAMS] = 0x024UL,
	82	[CAP_TESTMODE] = 0x038UL,
	83	[OP_USBCMD] = 0x000UL,
	84	[OP_USBSTS] = 0x004UL,
	85	[OP_USBINTR] = 0x008UL,
	86	[OP_DEVICEADDR] = 0x014UL,
	87	[OP_ENDPTLISTADDR] = 0x018UL,
	88	[OP_PORTSC] = 0x044UL,
	89	[OP_DEVLC] = 0x084UL,
5f36e231	90	[OP_OTGSC] = 0x064UL,
e443b333 AS	91	[OP_USBMODE] = 0x068UL,
	92	[OP_ENDPTSETUPSTAT] = 0x06CUL,
	93	[OP_ENDPTPRIME] = 0x070UL,
	94	[OP_ENDPTFLUSH] = 0x074UL,
	95	[OP_ENDPTSTAT] = 0x078UL,
	96	[OP_ENDPTCOMPLETE] = 0x07CUL,
	97	[OP_ENDPTCTRL] = 0x080UL,
	98	};
	99
	100	static uintptr_t ci_regs_lpm[] = {
	101	[CAP_CAPLENGTH] = 0x000UL,
	102	[CAP_HCCPARAMS] = 0x008UL,
	103	[CAP_DCCPARAMS] = 0x024UL,
	104	[CAP_TESTMODE] = 0x0FCUL,
	105	[OP_USBCMD] = 0x000UL,
	106	[OP_USBSTS] = 0x004UL,
	107	[OP_USBINTR] = 0x008UL,
	108	[OP_DEVICEADDR] = 0x014UL,
	109	[OP_ENDPTLISTADDR] = 0x018UL,
	110	[OP_PORTSC] = 0x044UL,
	111	[OP_DEVLC] = 0x084UL,
5f36e231	112	[OP_OTGSC] = 0x0C4UL,
e443b333 AS	113	[OP_USBMODE] = 0x0C8UL,
	114	[OP_ENDPTSETUPSTAT] = 0x0D8UL,
	115	[OP_ENDPTPRIME] = 0x0DCUL,
	116	[OP_ENDPTFLUSH] = 0x0E0UL,
	117	[OP_ENDPTSTAT] = 0x0E4UL,
	118	[OP_ENDPTCOMPLETE] = 0x0E8UL,
	119	[OP_ENDPTCTRL] = 0x0ECUL,
	120	};
	121
8e22978c	122	static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
e443b333 AS	123	{
	124	int i;
	125
5f36e231	126	kfree(ci->hw_bank.regmap);
e443b333	127
5f36e231 AS	128	ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
	129	GFP_KERNEL);
	130	if (!ci->hw_bank.regmap)
e443b333 AS	131	return -ENOMEM;
	132
	133	for (i = 0; i < OP_ENDPTCTRL; i++)
5f36e231 AS	134	ci->hw_bank.regmap[i] =
5f36e231 AS	135	(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
e443b333 AS	136	(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
	137
	138	for (; i <= OP_LAST; i++)
5f36e231	139	ci->hw_bank.regmap[i] = ci->hw_bank.op +
e443b333 AS	140	4 * (i - OP_ENDPTCTRL) +
	141	(is_lpm
	142	? ci_regs_lpm[OP_ENDPTCTRL]
	143	: ci_regs_nolpm[OP_ENDPTCTRL]);
	144
	145	return 0;
	146	}
	147
	148	/**
	149	* hw_port_test_set: writes port test mode (execute without interruption)
	150	* @mode: new value
	151	*
	152	* This function returns an error code
	153	*/
8e22978c	154	int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
e443b333 AS	155	{
	156	const u8 TEST_MODE_MAX = 7;
	157
	158	if (mode > TEST_MODE_MAX)
	159	return -EINVAL;
	160
727b4ddb	161	hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
e443b333 AS	162	return 0;
	163	}
	164
	165	/**
	166	* hw_port_test_get: reads port test mode value
	167	*
	168	* This function returns port test mode value
	169	*/
8e22978c	170	u8 hw_port_test_get(struct ci_hdrc *ci)
e443b333	171	{
727b4ddb	172	return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
e443b333 AS	173	}
e443b333 AS	174
864cf949 PC	175	/* The PHY enters/leaves low power mode */
	176	static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
	177	{
	178	enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
	179	bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
	180
	181	if (enable && !lpm) {
	182	hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
	183	PORTSC_PHCD(ci->hw_bank.lpm));
	184	} else if (!enable && lpm) {
	185	hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
	186	0);
	187	/*
	188	* The controller needs at least 1ms to reflect
	189	* PHY's status, the PHY also needs some time (less
	190	* than 1ms) to leave low power mode.
	191	*/
	192	usleep_range(1500, 2000);
	193	}
	194	}
	195
8e22978c	196	static int hw_device_init(struct ci_hdrc ci, void __iomem base)
e443b333 AS	197	{
	198	u32 reg;
	199
	200	/* bank is a module variable */
5f36e231	201	ci->hw_bank.abs = base;
e443b333	202
5f36e231	203	ci->hw_bank.cap = ci->hw_bank.abs;
77c4400f	204	ci->hw_bank.cap += ci->platdata->capoffset;
938d323f	205	ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
e443b333	206
5f36e231 AS	207	hw_alloc_regmap(ci, false);
5f36e231 AS	208	reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
727b4ddb	209	__ffs(HCCPARAMS_LEN);
5f36e231 AS	210	ci->hw_bank.lpm = reg;
	211	hw_alloc_regmap(ci, !!reg);
	212	ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
	213	ci->hw_bank.size += OP_LAST;
	214	ci->hw_bank.size /= sizeof(u32);
e443b333	215
5f36e231	216	reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
727b4ddb	217	__ffs(DCCPARAMS_DEN);
5f36e231	218	ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
e443b333	219
09c94e62	220	if (ci->hw_ep_max > ENDPT_MAX)
e443b333 AS	221	return -ENODEV;
e443b333 AS	222
864cf949 PC	223	ci_hdrc_enter_lpm(ci, false);
864cf949 PC	224
c344b518 PC	225	/* Disable all interrupts bits */
	226	hw_write(ci, OP_USBINTR, 0xffffffff, 0);
	227
	228	/* Clear all interrupts status bits*/
	229	hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
	230
5f36e231 AS	231	dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
5f36e231 AS	232	ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
e443b333 AS	233
	234	/* setup lock mode ? */
	235
	236	/* ENDPTSETUPSTAT is '0' by default */
	237
	238	/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
	239
	240	return 0;
	241	}
	242
8e22978c	243	static void hw_phymode_configure(struct ci_hdrc *ci)
40dcd0e8 MG	244	{
	245	u32 portsc, lpm, sts;
	246
	247	switch (ci->platdata->phy_mode) {
	248	case USBPHY_INTERFACE_MODE_UTMI:
	249	portsc = PORTSC_PTS(PTS_UTMI);
	250	lpm = DEVLC_PTS(PTS_UTMI);
	251	break;
	252	case USBPHY_INTERFACE_MODE_UTMIW:
	253	portsc = PORTSC_PTS(PTS_UTMI) \| PORTSC_PTW;
	254	lpm = DEVLC_PTS(PTS_UTMI) \| DEVLC_PTW;
	255	break;
	256	case USBPHY_INTERFACE_MODE_ULPI:
	257	portsc = PORTSC_PTS(PTS_ULPI);
	258	lpm = DEVLC_PTS(PTS_ULPI);
	259	break;
	260	case USBPHY_INTERFACE_MODE_SERIAL:
	261	portsc = PORTSC_PTS(PTS_SERIAL);
	262	lpm = DEVLC_PTS(PTS_SERIAL);
	263	sts = 1;
	264	break;
	265	case USBPHY_INTERFACE_MODE_HSIC:
	266	portsc = PORTSC_PTS(PTS_HSIC);
	267	lpm = DEVLC_PTS(PTS_HSIC);
	268	break;
	269	default:
	270	return;
	271	}
	272
	273	if (ci->hw_bank.lpm) {
	274	hw_write(ci, OP_DEVLC, DEVLC_PTS(7) \| DEVLC_PTW, lpm);
	275	hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
	276	} else {
	277	hw_write(ci, OP_PORTSC, PORTSC_PTS(7) \| PORTSC_PTW, portsc);
	278	hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
	279	}
	280	}
	281
e443b333 AS	282	/**
	283	* hw_device_reset: resets chip (execute without interruption)
	284	* @ci: the controller
	285	*
	286	* This function returns an error code
	287	*/
8e22978c	288	int hw_device_reset(struct ci_hdrc *ci, u32 mode)
e443b333 AS	289	{
	290	/* should flush & stop before reset */
	291	hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
	292	hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
	293
	294	hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
	295	while (hw_read(ci, OP_USBCMD, USBCMD_RST))
	296	udelay(10); /* not RTOS friendly */
	297
77c4400f RZ	298	if (ci->platdata->notify_event)
77c4400f RZ	299	ci->platdata->notify_event(ci,
8e22978c	300	CI_HDRC_CONTROLLER_RESET_EVENT);
e443b333	301
8e22978c	302	if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
758fc986	303	hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
e443b333 AS	304
	305	/* USBMODE should be configured step by step */
	306	hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
eb70e5ab	307	hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
e443b333 AS	308	/* HW >= 2.3 */
	309	hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
	310
eb70e5ab AS	311	if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
eb70e5ab AS	312	pr_err("cannot enter in %s mode", ci_role(ci)->name);
e443b333 AS	313	pr_err("lpm = %i", ci->hw_bank.lpm);
	314	return -ENODEV;
	315	}
	316
	317	return 0;
	318	}
	319
22fa8445 PC	320	/**
	321	* hw_wait_reg: wait the register value
	322	*
	323	* Sometimes, it needs to wait register value before going on.
	324	* Eg, when switch to device mode, the vbus value should be lower
	325	* than OTGSC_BSV before connects to host.
	326	*
	327	* @ci: the controller
	328	* @reg: register index
	329	* @mask: mast bit
	330	* @value: the bit value to wait
	331	* @timeout_ms: timeout in millisecond
	332	*
	333	* This function returns an error code if timeout
	334	*/
	335	int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
	336	u32 value, unsigned int timeout_ms)
	337	{
	338	unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
	339
	340	while (hw_read(ci, reg, mask) != value) {
	341	if (time_after(jiffies, elapse)) {
	342	dev_err(ci->dev, "timeout waiting for %08x in %d\n",
	343	mask, reg);
	344	return -ETIMEDOUT;
	345	}
	346	msleep(20);
	347	}
	348
	349	return 0;
	350	}
	351
5f36e231 AS	352	static irqreturn_t ci_irq(int irq, void *data)
5f36e231 AS	353	{
8e22978c	354	struct ci_hdrc *ci = data;
5f36e231	355	irqreturn_t ret = IRQ_NONE;
b183c19f	356	u32 otgsc = 0;
5f36e231	357
b183c19f RZ	358	if (ci->is_otg)
b183c19f RZ	359	otgsc = hw_read(ci, OP_OTGSC, ~0);
5f36e231	360
a107f8c5 PC	361	/*
	362	* Handle id change interrupt, it indicates device/host function
	363	* switch.
	364	*/
	365	if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
	366	ci->id_event = true;
	367	ci_clear_otg_interrupt(ci, OTGSC_IDIS);
	368	disable_irq_nosync(ci->irq);
	369	queue_work(ci->wq, &ci->work);
	370	return IRQ_HANDLED;
	371	}
b183c19f	372
a107f8c5 PC	373	/*
	374	* Handle vbus change interrupt, it indicates device connection
	375	* and disconnection events.
	376	*/
	377	if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
	378	ci->b_sess_valid_event = true;
	379	ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
b183c19f RZ	380	disable_irq_nosync(ci->irq);
b183c19f RZ	381	queue_work(ci->wq, &ci->work);
a107f8c5	382	return IRQ_HANDLED;
5f36e231 AS	383	}
5f36e231 AS	384
a107f8c5 PC	385	/* Handle device/host interrupt */
	386	if (ci->role != CI_ROLE_END)
	387	ret = ci_role(ci)->irq(ci);
	388
b183c19f	389	return ret;
5f36e231 AS	390	}
5f36e231 AS	391
1542d9c3 PC	392	static int ci_get_platdata(struct device *dev,
	393	struct ci_hdrc_platform_data *platdata)
	394	{
c22600c3 PC	395	if (!platdata->phy_mode)
	396	platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
	397
	398	if (!platdata->dr_mode)
	399	platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
	400
	401	if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
	402	platdata->dr_mode = USB_DR_MODE_OTG;
	403
c2ec3a73 PC	404	if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
	405	/* Get the vbus regulator */
	406	platdata->reg_vbus = devm_regulator_get(dev, "vbus");
	407	if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
	408	return -EPROBE_DEFER;
	409	} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
	410	/* no vbus regualator is needed */
	411	platdata->reg_vbus = NULL;
	412	} else if (IS_ERR(platdata->reg_vbus)) {
	413	dev_err(dev, "Getting regulator error: %ld\n",
	414	PTR_ERR(platdata->reg_vbus));
	415	return PTR_ERR(platdata->reg_vbus);
	416	}
	417	}
	418
1542d9c3 PC	419	return 0;
	420	}
	421
fe6e125e RZ	422	static DEFINE_IDA(ci_ida);
fe6e125e RZ	423
8e22978c	424	struct platform_device ci_hdrc_add_device(struct device dev,
cbc6dc2a	425	struct resource *res, int nres,
8e22978c	426	struct ci_hdrc_platform_data *platdata)
cbc6dc2a RZ	427	{
cbc6dc2a RZ	428	struct platform_device *pdev;
fe6e125e	429	int id, ret;
cbc6dc2a	430
1542d9c3 PC	431	ret = ci_get_platdata(dev, platdata);
	432	if (ret)
	433	return ERR_PTR(ret);
	434
fe6e125e RZ	435	id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
	436	if (id < 0)
	437	return ERR_PTR(id);
	438
	439	pdev = platform_device_alloc("ci_hdrc", id);
	440	if (!pdev) {
	441	ret = -ENOMEM;
	442	goto put_id;
	443	}
cbc6dc2a RZ	444
	445	pdev->dev.parent = dev;
	446	pdev->dev.dma_mask = dev->dma_mask;
	447	pdev->dev.dma_parms = dev->dma_parms;
	448	dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
	449
	450	ret = platform_device_add_resources(pdev, res, nres);
	451	if (ret)
	452	goto err;
	453
	454	ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
	455	if (ret)
	456	goto err;
	457
	458	ret = platform_device_add(pdev);
	459	if (ret)
	460	goto err;
	461
	462	return pdev;
	463
	464	err:
	465	platform_device_put(pdev);
fe6e125e RZ	466	put_id:
fe6e125e RZ	467	ida_simple_remove(&ci_ida, id);
cbc6dc2a RZ	468	return ERR_PTR(ret);
cbc6dc2a RZ	469	}
8e22978c	470	EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
cbc6dc2a	471
8e22978c	472	void ci_hdrc_remove_device(struct platform_device *pdev)
cbc6dc2a	473	{
98c35534	474	int id = pdev->id;
cbc6dc2a	475	platform_device_unregister(pdev);
98c35534	476	ida_simple_remove(&ci_ida, id);
cbc6dc2a	477	}
8e22978c	478	EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
cbc6dc2a	479
3f124d23 PC	480	static inline void ci_role_destroy(struct ci_hdrc *ci)
	481	{
	482	ci_hdrc_gadget_destroy(ci);
	483	ci_hdrc_host_destroy(ci);
cbec6bd5 PC	484	if (ci->is_otg)
cbec6bd5 PC	485	ci_hdrc_otg_destroy(ci);
3f124d23 PC	486	}
3f124d23 PC	487
577b232f PC	488	static void ci_get_otg_capable(struct ci_hdrc *ci)
	489	{
	490	if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
	491	ci->is_otg = false;
	492	else
	493	ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
	494	DCCPARAMS_DC \| DCCPARAMS_HC)
	495	== (DCCPARAMS_DC \| DCCPARAMS_HC));
c344b518	496	if (ci->is_otg) {
577b232f	497	dev_dbg(ci->dev, "It is OTG capable controller\n");
c344b518 PC	498	ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
	499	ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
	500	}
577b232f PC	501	}
577b232f PC	502
74475ede PC	503	static int ci_usb_phy_init(struct ci_hdrc *ci)
	504	{
	505	if (ci->platdata->phy) {
	506	ci->transceiver = ci->platdata->phy;
	507	return usb_phy_init(ci->transceiver);
	508	} else {
	509	ci->global_phy = true;
	510	ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
	511	if (IS_ERR(ci->transceiver))
	512	ci->transceiver = NULL;
	513
	514	return 0;
	515	}
	516	}
	517
	518	static void ci_usb_phy_destroy(struct ci_hdrc *ci)
	519	{
	520	if (!ci->transceiver)
	521	return;
	522
	523	otg_set_peripheral(ci->transceiver->otg, NULL);
	524	if (ci->global_phy)
	525	usb_put_phy(ci->transceiver);
	526	else
	527	usb_phy_shutdown(ci->transceiver);
	528	}
	529
41ac7b3a	530	static int ci_hdrc_probe(struct platform_device *pdev)
e443b333 AS	531	{
e443b333 AS	532	struct device *dev = &pdev->dev;
8e22978c	533	struct ci_hdrc *ci;
e443b333 AS	534	struct resource *res;
	535	void __iomem *base;
	536	int ret;
691962d1	537	enum usb_dr_mode dr_mode;
e443b333	538
5f36e231	539	if (!dev->platform_data) {
e443b333 AS	540	dev_err(dev, "platform data missing\n");
	541	return -ENODEV;
	542	}
	543
	544	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
19290816 FB	545	base = devm_ioremap_resource(dev, res);
	546	if (IS_ERR(base))
	547	return PTR_ERR(base);
e443b333	548
5f36e231 AS	549	ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
	550	if (!ci) {
	551	dev_err(dev, "can't allocate device\n");
	552	return -ENOMEM;
	553	}
	554
	555	ci->dev = dev;
77c4400f	556	ci->platdata = dev->platform_data;
5f36e231 AS	557
	558	ret = hw_device_init(ci, base);
	559	if (ret < 0) {
	560	dev_err(dev, "can't initialize hardware\n");
	561	return -ENODEV;
	562	}
e443b333	563
74475ede PC	564	ret = ci_usb_phy_init(ci);
	565	if (ret) {
	566	dev_err(dev, "unable to init phy: %d\n", ret);
	567	return ret;
	568	}
	569
eb70e5ab AS	570	ci->hw_bank.phys = res->start;
eb70e5ab AS	571
5f36e231 AS	572	ci->irq = platform_get_irq(pdev, 0);
5f36e231 AS	573	if (ci->irq < 0) {
e443b333	574	dev_err(dev, "missing IRQ\n");
74475ede PC	575	ret = -ENODEV;
74475ede PC	576	goto destroy_phy;
5f36e231 AS	577	}
5f36e231 AS	578
577b232f PC	579	ci_get_otg_capable(ci);
577b232f PC	580
03779f05 FE	581	hw_phymode_configure(ci);
03779f05 FE	582
691962d1	583	dr_mode = ci->platdata->dr_mode;
5f36e231	584	/* initialize role(s) before the interrupt is requested */
691962d1 SH	585	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_HOST) {
	586	ret = ci_hdrc_host_init(ci);
	587	if (ret)
	588	dev_info(dev, "doesn't support host\n");
	589	}
eb70e5ab	590
691962d1 SH	591	if (dr_mode == USB_DR_MODE_OTG \|\| dr_mode == USB_DR_MODE_PERIPHERAL) {
	592	ret = ci_hdrc_gadget_init(ci);
	593	if (ret)
	594	dev_info(dev, "doesn't support gadget\n");
74475ede PC	595	if (!ret && ci->transceiver) {
	596	ret = otg_set_peripheral(ci->transceiver->otg,
	597	&ci->gadget);
	598	/*
	599	* If we implement all USB functions using chipidea drivers,
	600	* it doesn't need to call above API, meanwhile, if we only
	601	* use gadget function, calling above API is useless.
	602	*/
	603	if (ret && ret != -ENOTSUPP)
	604	goto destroy_phy;
	605	}
691962d1	606	}
5f36e231 AS	607
	608	if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
	609	dev_err(dev, "no supported roles\n");
74475ede PC	610	ret = -ENODEV;
74475ede PC	611	goto destroy_phy;
cbec6bd5 PC	612	}
	613
	614	if (ci->is_otg) {
	615	ret = ci_hdrc_otg_init(ci);
	616	if (ret) {
	617	dev_err(dev, "init otg fails, ret = %d\n", ret);
	618	goto stop;
	619	}
5f36e231 AS	620	}
	621
	622	if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
577b232f PC	623	if (ci->is_otg) {
	624	/*
	625	* ID pin needs 1ms debouce time,
	626	* we delay 2ms for safe.
	627	*/
	628	mdelay(2);
	629	ci->role = ci_otg_role(ci);
cbec6bd5	630	ci_enable_otg_interrupt(ci, OTGSC_IDIE);
577b232f PC	631	} else {
	632	/*
	633	* If the controller is not OTG capable, but support
	634	* role switch, the defalt role is gadget, and the
	635	* user can switch it through debugfs.
	636	*/
	637	ci->role = CI_ROLE_GADGET;
	638	}
5f36e231 AS	639	} else {
	640	ci->role = ci->roles[CI_ROLE_HOST]
	641	? CI_ROLE_HOST
	642	: CI_ROLE_GADGET;
	643	}
	644
	645	ret = ci_role_start(ci, ci->role);
	646	if (ret) {
	647	dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
cbec6bd5	648	goto stop;
e443b333 AS	649	}
e443b333 AS	650
5f36e231	651	platform_set_drvdata(pdev, ci);
77c4400f	652	ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
5f36e231 AS	653	ci);
	654	if (ret)
	655	goto stop;
e443b333	656
adf0f735 AS	657	ret = dbg_create_files(ci);
	658	if (!ret)
	659	return 0;
5f36e231	660
adf0f735	661	free_irq(ci->irq, ci);
5f36e231	662	stop:
3f124d23	663	ci_role_destroy(ci);
74475ede PC	664	destroy_phy:
74475ede PC	665	ci_usb_phy_destroy(ci);
e443b333 AS	666
	667	return ret;
	668	}
	669
fb4e98ab	670	static int ci_hdrc_remove(struct platform_device *pdev)
e443b333	671	{
8e22978c	672	struct ci_hdrc *ci = platform_get_drvdata(pdev);
e443b333	673
adf0f735	674	dbg_remove_files(ci);
5f36e231	675	free_irq(ci->irq, ci);
3f124d23	676	ci_role_destroy(ci);
864cf949	677	ci_hdrc_enter_lpm(ci, true);
74475ede	678	ci_usb_phy_destroy(ci);
222bed9b	679	kfree(ci->hw_bank.regmap);
e443b333 AS	680
	681	return 0;
	682	}
	683
5f36e231 AS	684	static struct platform_driver ci_hdrc_driver = {
5f36e231 AS	685	.probe = ci_hdrc_probe,
7690417d	686	.remove = ci_hdrc_remove,
e443b333	687	.driver = {
5f36e231	688	.name = "ci_hdrc",
e443b333 AS	689	},
	690	};
	691
5f36e231	692	module_platform_driver(ci_hdrc_driver);
e443b333	693
5f36e231	694	MODULE_ALIAS("platform:ci_hdrc");
e443b333 AS	695	MODULE_LICENSE("GPL v2");
e443b333 AS	696	MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
5f36e231	697	MODULE_DESCRIPTION("ChipIdea HDRC Driver");