Commit | Line | Data |
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c10b4f03 PC |
1 | /* |
2 | * otg.c - ChipIdea USB IP core OTG driver | |
3 | * | |
4 | * Copyright (C) 2013 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Author: Peter Chen | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | /* | |
4dcf720c LJ |
14 | * This file mainly handles otgsc register, OTG fsm operations for HNP and SRP |
15 | * are also included. | |
c10b4f03 PC |
16 | */ |
17 | ||
18 | #include <linux/usb/otg.h> | |
19 | #include <linux/usb/gadget.h> | |
20 | #include <linux/usb/chipidea.h> | |
21 | ||
22 | #include "ci.h" | |
23 | #include "bits.h" | |
24 | #include "otg.h" | |
57677be5 | 25 | #include "otg_fsm.h" |
c10b4f03 | 26 | |
0c33bf78 LJ |
27 | /** |
28 | * hw_read_otgsc returns otgsc register bits value. | |
29 | * @mask: bitfield mask | |
30 | */ | |
31 | u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask) | |
32 | { | |
33 | return hw_read(ci, OP_OTGSC, mask); | |
34 | } | |
35 | ||
36 | /** | |
37 | * hw_write_otgsc updates target bits of OTGSC register. | |
38 | * @mask: bitfield mask | |
39 | * @data: to be written | |
40 | */ | |
41 | void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data) | |
42 | { | |
43 | hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data); | |
44 | } | |
45 | ||
c10b4f03 | 46 | /** |
cbec6bd5 PC |
47 | * ci_otg_role - pick role based on ID pin state |
48 | * @ci: the controller | |
49 | */ | |
50 | enum ci_role ci_otg_role(struct ci_hdrc *ci) | |
51 | { | |
0c33bf78 | 52 | enum ci_role role = hw_read_otgsc(ci, OTGSC_ID) |
cbec6bd5 PC |
53 | ? CI_ROLE_GADGET |
54 | : CI_ROLE_HOST; | |
55 | ||
56 | return role; | |
57 | } | |
58 | ||
a107f8c5 PC |
59 | void ci_handle_vbus_change(struct ci_hdrc *ci) |
60 | { | |
a107f8c5 PC |
61 | if (!ci->is_otg) |
62 | return; | |
63 | ||
0c33bf78 | 64 | if (hw_read_otgsc(ci, OTGSC_BSV)) |
a107f8c5 PC |
65 | usb_gadget_vbus_connect(&ci->gadget); |
66 | else | |
67 | usb_gadget_vbus_disconnect(&ci->gadget); | |
68 | } | |
69 | ||
22fa8445 | 70 | #define CI_VBUS_STABLE_TIMEOUT_MS 5000 |
a107f8c5 | 71 | static void ci_handle_id_switch(struct ci_hdrc *ci) |
cbec6bd5 | 72 | { |
cbec6bd5 PC |
73 | enum ci_role role = ci_otg_role(ci); |
74 | ||
75 | if (role != ci->role) { | |
76 | dev_dbg(ci->dev, "switching from %s to %s\n", | |
77 | ci_role(ci)->name, ci->roles[role]->name); | |
78 | ||
79 | ci_role_stop(ci); | |
22fa8445 PC |
80 | /* wait vbus lower than OTGSC_BSV */ |
81 | hw_wait_reg(ci, OP_OTGSC, OTGSC_BSV, 0, | |
82 | CI_VBUS_STABLE_TIMEOUT_MS); | |
cbec6bd5 PC |
83 | ci_role_start(ci, role); |
84 | } | |
a107f8c5 PC |
85 | } |
86 | /** | |
87 | * ci_otg_work - perform otg (vbus/id) event handle | |
88 | * @work: work struct | |
89 | */ | |
90 | static void ci_otg_work(struct work_struct *work) | |
91 | { | |
92 | struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work); | |
93 | ||
4dcf720c LJ |
94 | if (ci_otg_is_fsm_mode(ci) && !ci_otg_fsm_work(ci)) { |
95 | enable_irq(ci->irq); | |
96 | return; | |
97 | } | |
98 | ||
a107f8c5 PC |
99 | if (ci->id_event) { |
100 | ci->id_event = false; | |
101 | ci_handle_id_switch(ci); | |
102 | } else if (ci->b_sess_valid_event) { | |
103 | ci->b_sess_valid_event = false; | |
104 | ci_handle_vbus_change(ci); | |
105 | } else | |
106 | dev_err(ci->dev, "unexpected event occurs at %s\n", __func__); | |
cbec6bd5 PC |
107 | |
108 | enable_irq(ci->irq); | |
109 | } | |
110 | ||
a107f8c5 | 111 | |
cbec6bd5 PC |
112 | /** |
113 | * ci_hdrc_otg_init - initialize otg struct | |
c10b4f03 PC |
114 | * ci: the controller |
115 | */ | |
116 | int ci_hdrc_otg_init(struct ci_hdrc *ci) | |
117 | { | |
a107f8c5 | 118 | INIT_WORK(&ci->work, ci_otg_work); |
cbec6bd5 PC |
119 | ci->wq = create_singlethread_workqueue("ci_otg"); |
120 | if (!ci->wq) { | |
121 | dev_err(ci->dev, "can't create workqueue\n"); | |
122 | return -ENODEV; | |
123 | } | |
c10b4f03 | 124 | |
57677be5 LJ |
125 | if (ci_otg_is_fsm_mode(ci)) |
126 | return ci_hdrc_otg_fsm_init(ci); | |
127 | ||
c10b4f03 PC |
128 | return 0; |
129 | } | |
cbec6bd5 PC |
130 | |
131 | /** | |
132 | * ci_hdrc_otg_destroy - destroy otg struct | |
133 | * ci: the controller | |
134 | */ | |
135 | void ci_hdrc_otg_destroy(struct ci_hdrc *ci) | |
136 | { | |
137 | if (ci->wq) { | |
138 | flush_workqueue(ci->wq); | |
139 | destroy_workqueue(ci->wq); | |
140 | } | |
0c33bf78 LJ |
141 | /* Disable all OTG irq and clear status */ |
142 | hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS, | |
143 | OTGSC_INT_STATUS_BITS); | |
15f75def LJ |
144 | if (ci_otg_is_fsm_mode(ci)) |
145 | ci_hdrc_otg_fsm_remove(ci); | |
cbec6bd5 | 146 | } |