[deliverable/linux.git] / drivers / usb / dwc2 / core_intr.c

/*
 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
 *
 * Copyright (C) 2004-2013 Synopsys, Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation; either version 2 of the License, or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * This file contains the common interrupt handlers
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/usb.h>

#include <linux/usb/hcd.h>
#include <linux/usb/ch11.h>

#include "core.h"
#include "hcd.h"

static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
{
	switch (hsotg->op_state) {
	case OTG_STATE_A_HOST:
		return "a_host";
	case OTG_STATE_A_SUSPEND:
		return "a_suspend";
	case OTG_STATE_A_PERIPHERAL:
		return "a_peripheral";
	case OTG_STATE_B_PERIPHERAL:
		return "b_peripheral";
	case OTG_STATE_B_HOST:
		return "b_host";
	default:
		return "unknown";
	}
}

/**
 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
 * When the PRTINT interrupt fires, there are certain status bits in the Host
 * Port that needs to get cleared.
 *
 * @hsotg: Programming view of DWC_otg controller
 */
static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
{
	u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);

	if (hprt0 & HPRT0_ENACHG) {
		hprt0 &= ~HPRT0_ENA;
		dwc2_writel(hprt0, hsotg->regs + HPRT0);
	}

	/* Clear interrupt */
	dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
}

/**
 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
 *
 * @hsotg: Programming view of DWC_otg controller
 */
static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
{
	dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
		 dwc2_is_host_mode(hsotg) ? "Host" : "Device");

	/* Clear interrupt */
	dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
}

/**
 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
 *
 * @hsotg: Programming view of DWC_otg controller
 */
static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
{
	u32 gotgint;
	u32 gotgctl;
	u32 gintmsk;

	gotgint = dwc2_readl(hsotg->regs + GOTGINT);
	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
	dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
		dwc2_op_state_str(hsotg));

	if (gotgint & GOTGINT_SES_END_DET) {
		dev_dbg(hsotg->dev,
			" ++OTG Interrupt: Session End Detected++ (%s)\n",
			dwc2_op_state_str(hsotg));
		gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);

		if (dwc2_is_device_mode(hsotg))
			dwc2_hsotg_disconnect(hsotg);

		if (hsotg->op_state == OTG_STATE_B_HOST) {
			hsotg->op_state = OTG_STATE_B_PERIPHERAL;
		} else {
			/*
			 * If not B_HOST and Device HNP still set, HNP did
			 * not succeed!
			 */
			if (gotgctl & GOTGCTL_DEVHNPEN) {
				dev_dbg(hsotg->dev, "Session End Detected\n");
				dev_err(hsotg->dev,
					"Device Not Connected/Responding!\n");
			}

			/*
			 * If Session End Detected the B-Cable has been
			 * disconnected
			 */
			/* Reset to a clean state */
			hsotg->lx_state = DWC2_L0;
		}

		gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
		gotgctl &= ~GOTGCTL_DEVHNPEN;
		dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
	}

	if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
		dev_dbg(hsotg->dev,
			" ++OTG Interrupt: Session Request Success Status Change++\n");
		gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
		if (gotgctl & GOTGCTL_SESREQSCS) {
			if (hsotg->core_params->phy_type ==
					DWC2_PHY_TYPE_PARAM_FS
			    && hsotg->core_params->i2c_enable > 0) {
				hsotg->srp_success = 1;
			} else {
				/* Clear Session Request */
				gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
				gotgctl &= ~GOTGCTL_SESREQ;
				dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
			}
		}
	}

	if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
		/*
		 * Print statements during the HNP interrupt handling
		 * can cause it to fail
		 */
		gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
		/*
		 * WA for 3.00a- HW is not setting cur_mode, even sometimes
		 * this does not help
		 */
		if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
			udelay(100);
		if (gotgctl & GOTGCTL_HSTNEGSCS) {
			if (dwc2_is_host_mode(hsotg)) {
				hsotg->op_state = OTG_STATE_B_HOST;
				/*
				 * Need to disable SOF interrupt immediately.
				 * When switching from device to host, the PCD
				 * interrupt handler won't handle the interrupt
				 * if host mode is already set. The HCD
				 * interrupt handler won't get called if the
				 * HCD state is HALT. This means that the
				 * interrupt does not get handled and Linux
				 * complains loudly.
				 */
				gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
				gintmsk &= ~GINTSTS_SOF;
				dwc2_writel(gintmsk, hsotg->regs + GINTMSK);

				/*
				 * Call callback function with spin lock
				 * released
				 */
				spin_unlock(&hsotg->lock);

				/* Initialize the Core for Host mode */
				dwc2_hcd_start(hsotg);
				spin_lock(&hsotg->lock);
				hsotg->op_state = OTG_STATE_B_HOST;
			}
		} else {
			gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
			gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
			dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
			dev_dbg(hsotg->dev, "HNP Failed\n");
			dev_err(hsotg->dev,
				"Device Not Connected/Responding\n");
		}
	}

	if (gotgint & GOTGINT_HST_NEG_DET) {
		/*
		 * The disconnect interrupt is set at the same time as
		 * Host Negotiation Detected. During the mode switch all
		 * interrupts are cleared so the disconnect interrupt
		 * handler will not get executed.
		 */
		dev_dbg(hsotg->dev,
			" ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
			(dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
		if (dwc2_is_device_mode(hsotg)) {
			dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
				hsotg->op_state);
			spin_unlock(&hsotg->lock);
			dwc2_hcd_disconnect(hsotg);
			spin_lock(&hsotg->lock);
			hsotg->op_state = OTG_STATE_A_PERIPHERAL;
		} else {
			/* Need to disable SOF interrupt immediately */
			gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
			gintmsk &= ~GINTSTS_SOF;
			dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
			spin_unlock(&hsotg->lock);
			dwc2_hcd_start(hsotg);
			spin_lock(&hsotg->lock);
			hsotg->op_state = OTG_STATE_A_HOST;
		}
	}

	if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
		dev_dbg(hsotg->dev,
			" ++OTG Interrupt: A-Device Timeout Change++\n");
	if (gotgint & GOTGINT_DBNCE_DONE)
		dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");

	/* Clear GOTGINT */
	dwc2_writel(gotgint, hsotg->regs + GOTGINT);
}

/**
 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
 * Change Interrupt
 *
 * @hsotg: Programming view of DWC_otg controller
 *
 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
 * Device to Host Mode transition or a Host to Device Mode transition. This only
 * occurs when the cable is connected/removed from the PHY connector.
 */
static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
{
	u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);

	/* Need to disable SOF interrupt immediately */
	gintmsk &= ~GINTSTS_SOF;
	dwc2_writel(gintmsk, hsotg->regs + GINTMSK);

	dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++  (%s)\n",
		dwc2_is_host_mode(hsotg) ? "Host" : "Device");

	/*
	 * Need to schedule a work, as there are possible DELAY function calls.
	 * Release lock before scheduling workq as it holds spinlock during
	 * scheduling.
	 */
	if (hsotg->wq_otg) {
		spin_unlock(&hsotg->lock);
		queue_work(hsotg->wq_otg, &hsotg->wf_otg);
		spin_lock(&hsotg->lock);
	}

	/* Clear interrupt */
	dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
}

/**
 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
 * initiating the Session Request Protocol to request the host to turn on bus
 * power so a new session can begin
 *
 * @hsotg: Programming view of DWC_otg controller
 *
 * This handler responds by turning on bus power. If the DWC_otg controller is
 * in low power mode, this handler brings the controller out of low power mode
 * before turning on bus power.
 */
static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
{
	int ret;

	dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
							hsotg->lx_state);

	/* Clear interrupt */
	dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);

	if (dwc2_is_device_mode(hsotg)) {
		if (hsotg->lx_state == DWC2_L2) {
			ret = dwc2_exit_hibernation(hsotg, true);
			if (ret && (ret != -ENOTSUPP))
				dev_err(hsotg->dev,
					"exit hibernation failed\n");
		}

		/*
		 * Report disconnect if there is any previous session
		 * established
		 */
		dwc2_hsotg_disconnect(hsotg);
	}
}

/*
 * This interrupt indicates that the DWC_otg controller has detected a
 * resume or remote wakeup sequence. If the DWC_otg controller is in
 * low power mode, the handler must brings the controller out of low
 * power mode. The controller automatically begins resume signaling.
 * The handler schedules a time to stop resume signaling.
 */
static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
{
	int ret;
	dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
	dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);

	if (dwc2_is_device_mode(hsotg)) {
		dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
			dwc2_readl(hsotg->regs + DSTS));
		if (hsotg->lx_state == DWC2_L2) {
			u32 dctl = dwc2_readl(hsotg->regs + DCTL);

			/* Clear Remote Wakeup Signaling */
			dctl &= ~DCTL_RMTWKUPSIG;
			dwc2_writel(dctl, hsotg->regs + DCTL);
			ret = dwc2_exit_hibernation(hsotg, true);
			if (ret && (ret != -ENOTSUPP))
				dev_err(hsotg->dev, "exit hibernation failed\n");

			call_gadget(hsotg, resume);
		}
		/* Change to L0 state */
		hsotg->lx_state = DWC2_L0;
	} else {
		if (hsotg->core_params->hibernation) {
			dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
			return;
		}
		if (hsotg->lx_state != DWC2_L1) {
			u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);

			/* Restart the Phy Clock */
			pcgcctl &= ~PCGCTL_STOPPCLK;
			dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
			mod_timer(&hsotg->wkp_timer,
				  jiffies + msecs_to_jiffies(71));
		} else {
			/* Change to L0 state */
			hsotg->lx_state = DWC2_L0;
		}
	}

	/* Clear interrupt */
	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
}

/*
 * This interrupt indicates that a device has been disconnected from the
 * root port
 */
static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
{
	dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
		dwc2_is_host_mode(hsotg) ? "Host" : "Device",
		dwc2_op_state_str(hsotg));

	if (hsotg->op_state == OTG_STATE_A_HOST)
		dwc2_hcd_disconnect(hsotg);

	dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
}

/*
 * This interrupt indicates that SUSPEND state has been detected on the USB.
 *
 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
 * to "a_host".
 *
 * When power management is enabled the core will be put in low power mode.
 */
static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
{
	u32 dsts;
	int ret;

	dev_dbg(hsotg->dev, "USB SUSPEND\n");

	if (dwc2_is_device_mode(hsotg)) {
		/*
		 * Check the Device status register to determine if the Suspend
		 * state is active
		 */
		dsts = dwc2_readl(hsotg->regs + DSTS);
		dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
		dev_dbg(hsotg->dev,
			"DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
			!!(dsts & DSTS_SUSPSTS),
			hsotg->hw_params.power_optimized);
		if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) {
			/* Ignore suspend request before enumeration */
			if (!dwc2_is_device_connected(hsotg)) {
				dev_dbg(hsotg->dev,
						"ignore suspend request before enumeration\n");
				goto clear_int;
			}

			ret = dwc2_enter_hibernation(hsotg);
			if (ret) {
				if (ret != -ENOTSUPP)
					dev_err(hsotg->dev,
							"enter hibernation failed\n");
				goto skip_power_saving;
			}

			udelay(100);

			/* Ask phy to be suspended */
			if (!IS_ERR_OR_NULL(hsotg->uphy))
				usb_phy_set_suspend(hsotg->uphy, true);
skip_power_saving:
			/*
			 * Change to L2 (suspend) state before releasing
			 * spinlock
			 */
			hsotg->lx_state = DWC2_L2;

			/* Call gadget suspend callback */
			call_gadget(hsotg, suspend);
		}
	} else {
		if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
			dev_dbg(hsotg->dev, "a_peripheral->a_host\n");

			/* Change to L2 (suspend) state */
			hsotg->lx_state = DWC2_L2;
			/* Clear the a_peripheral flag, back to a_host */
			spin_unlock(&hsotg->lock);
			dwc2_hcd_start(hsotg);
			spin_lock(&hsotg->lock);
			hsotg->op_state = OTG_STATE_A_HOST;
		}
	}

clear_int:
	/* Clear interrupt */
	dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
}

#define GINTMSK_COMMON	(GINTSTS_WKUPINT | GINTSTS_SESSREQINT |		\
			 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT |	\
			 GINTSTS_MODEMIS | GINTSTS_DISCONNINT |		\
			 GINTSTS_USBSUSP | GINTSTS_PRTINT)

/*
 * This function returns the Core Interrupt register
 */
static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
{
	u32 gintsts;
	u32 gintmsk;
	u32 gahbcfg;
	u32 gintmsk_common = GINTMSK_COMMON;

	gintsts = dwc2_readl(hsotg->regs + GINTSTS);
	gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
	gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);

	/* If any common interrupts set */
	if (gintsts & gintmsk_common)
		dev_dbg(hsotg->dev, "gintsts=%08x  gintmsk=%08x\n",
			gintsts, gintmsk);

	if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
		return gintsts & gintmsk & gintmsk_common;
	else
		return 0;
}

/*
 * Common interrupt handler
 *
 * The common interrupts are those that occur in both Host and Device mode.
 * This handler handles the following interrupts:
 * - Mode Mismatch Interrupt
 * - OTG Interrupt
 * - Connector ID Status Change Interrupt
 * - Disconnect Interrupt
 * - Session Request Interrupt
 * - Resume / Remote Wakeup Detected Interrupt
 * - Suspend Interrupt
 */
irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
{
	struct dwc2_hsotg *hsotg = dev;
	u32 gintsts;
	irqreturn_t retval = IRQ_NONE;

	spin_lock(&hsotg->lock);

	if (!dwc2_is_controller_alive(hsotg)) {
		dev_warn(hsotg->dev, "Controller is dead\n");
		goto out;
	}

	gintsts = dwc2_read_common_intr(hsotg);
	if (gintsts & ~GINTSTS_PRTINT)
		retval = IRQ_HANDLED;

	if (gintsts & GINTSTS_MODEMIS)
		dwc2_handle_mode_mismatch_intr(hsotg);
	if (gintsts & GINTSTS_OTGINT)
		dwc2_handle_otg_intr(hsotg);
	if (gintsts & GINTSTS_CONIDSTSCHNG)
		dwc2_handle_conn_id_status_change_intr(hsotg);
	if (gintsts & GINTSTS_DISCONNINT)
		dwc2_handle_disconnect_intr(hsotg);
	if (gintsts & GINTSTS_SESSREQINT)
		dwc2_handle_session_req_intr(hsotg);
	if (gintsts & GINTSTS_WKUPINT)
		dwc2_handle_wakeup_detected_intr(hsotg);
	if (gintsts & GINTSTS_USBSUSP)
		dwc2_handle_usb_suspend_intr(hsotg);

	if (gintsts & GINTSTS_PRTINT) {
		/*
		 * The port interrupt occurs while in device mode with HPRT0
		 * Port Enable/Disable
		 */
		if (dwc2_is_device_mode(hsotg)) {
			dev_dbg(hsotg->dev,
				" --Port interrupt received in Device mode--\n");
			dwc2_handle_usb_port_intr(hsotg);
			retval = IRQ_HANDLED;
		}
	}

out:
	spin_unlock(&hsotg->lock);
	return retval;
}
Commit	Line	Data
56f5b1cf PZ	1	/*
	2	* core_intr.c - DesignWare HS OTG Controller common interrupt handling
	3	*
	4	* Copyright (C) 2004-2013 Synopsys, Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	* 1. Redistributions of source code must retain the above copyright
	10	* notice, this list of conditions, and the following disclaimer,
	11	* without modification.
	12	* 2. Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in the
	14	* documentation and/or other materials provided with the distribution.
	15	* 3. The names of the above-listed copyright holders may not be used
	16	* to endorse or promote products derived from this software without
	17	* specific prior written permission.
	18	*
	19	* ALTERNATIVELY, this software may be distributed under the terms of the
	20	* GNU General Public License ("GPL") as published by the Free Software
	21	* Foundation; either version 2 of the License, or (at your option) any
	22	* later version.
	23	*
	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	25	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	26	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	27	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	28	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	29	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	30	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	31	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	32	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	33	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	34	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	35	*/
	36
	37	/*
	38	* This file contains the common interrupt handlers
	39	*/
	40	#include <linux/kernel.h>
	41	#include <linux/module.h>
	42	#include <linux/moduleparam.h>
	43	#include <linux/spinlock.h>
	44	#include <linux/interrupt.h>
	45	#include <linux/dma-mapping.h>
	46	#include <linux/io.h>
	47	#include <linux/slab.h>
	48	#include <linux/usb.h>
	49
	50	#include <linux/usb/hcd.h>
	51	#include <linux/usb/ch11.h>
	52
	53	#include "core.h"
	54	#include "hcd.h"
	55
	56	static const char dwc2_op_state_str(struct dwc2_hsotg hsotg)
	57	{
56f5b1cf PZ	58	switch (hsotg->op_state) {
	59	case OTG_STATE_A_HOST:
	60	return "a_host";
	61	case OTG_STATE_A_SUSPEND:
	62	return "a_suspend";
	63	case OTG_STATE_A_PERIPHERAL:
	64	return "a_peripheral";
	65	case OTG_STATE_B_PERIPHERAL:
	66	return "b_peripheral";
	67	case OTG_STATE_B_HOST:
	68	return "b_host";
	69	default:
	70	return "unknown";
	71	}
56f5b1cf PZ	72	}
56f5b1cf PZ	73
93571adb DN	74	/**
	75	* dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
	76	* When the PRTINT interrupt fires, there are certain status bits in the Host
	77	* Port that needs to get cleared.
	78	*
	79	* @hsotg: Programming view of DWC_otg controller
	80	*/
	81	static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
	82	{
95c8bc36	83	u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
93571adb DN	84
	85	if (hprt0 & HPRT0_ENACHG) {
	86	hprt0 &= ~HPRT0_ENA;
95c8bc36	87	dwc2_writel(hprt0, hsotg->regs + HPRT0);
93571adb DN	88	}
	89
	90	/* Clear interrupt */
95c8bc36	91	dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
93571adb DN	92	}
93571adb DN	93
56f5b1cf PZ	94	/**
	95	* dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
	96	*
	97	* @hsotg: Programming view of DWC_otg controller
	98	*/
	99	static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
	100	{
	101	dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
	102	dwc2_is_host_mode(hsotg) ? "Host" : "Device");
	103
	104	/* Clear interrupt */
95c8bc36	105	dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
56f5b1cf PZ	106	}
	107
	108	/**
	109	* dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
	110	* Interrupt Register (GOTGINT) to determine what interrupt has occurred.
	111	*
	112	* @hsotg: Programming view of DWC_otg controller
	113	*/
	114	static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
	115	{
	116	u32 gotgint;
	117	u32 gotgctl;
	118	u32 gintmsk;
	119
95c8bc36 AS	120	gotgint = dwc2_readl(hsotg->regs + GOTGINT);
95c8bc36 AS	121	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
56f5b1cf PZ	122	dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
	123	dwc2_op_state_str(hsotg));
	124
	125	if (gotgint & GOTGINT_SES_END_DET) {
	126	dev_dbg(hsotg->dev,
	127	" ++OTG Interrupt: Session End Detected++ (%s)\n",
	128	dwc2_op_state_str(hsotg));
95c8bc36	129	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
56f5b1cf	130
4ace06e8	131	if (dwc2_is_device_mode(hsotg))
1f91b4cc	132	dwc2_hsotg_disconnect(hsotg);
4ace06e8	133
56f5b1cf PZ	134	if (hsotg->op_state == OTG_STATE_B_HOST) {
	135	hsotg->op_state = OTG_STATE_B_PERIPHERAL;
	136	} else {
	137	/*
	138	* If not B_HOST and Device HNP still set, HNP did
	139	* not succeed!
	140	*/
	141	if (gotgctl & GOTGCTL_DEVHNPEN) {
	142	dev_dbg(hsotg->dev, "Session End Detected\n");
	143	dev_err(hsotg->dev,
	144	"Device Not Connected/Responding!\n");
	145	}
	146
	147	/*
	148	* If Session End Detected the B-Cable has been
	149	* disconnected
	150	*/
	151	/* Reset to a clean state */
	152	hsotg->lx_state = DWC2_L0;
	153	}
	154
95c8bc36	155	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
56f5b1cf	156	gotgctl &= ~GOTGCTL_DEVHNPEN;
95c8bc36	157	dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
56f5b1cf PZ	158	}
	159
	160	if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
	161	dev_dbg(hsotg->dev,
	162	" ++OTG Interrupt: Session Request Success Status Change++\n");
95c8bc36	163	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
56f5b1cf PZ	164	if (gotgctl & GOTGCTL_SESREQSCS) {
	165	if (hsotg->core_params->phy_type ==
	166	DWC2_PHY_TYPE_PARAM_FS
	167	&& hsotg->core_params->i2c_enable > 0) {
	168	hsotg->srp_success = 1;
	169	} else {
	170	/* Clear Session Request */
95c8bc36	171	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
56f5b1cf	172	gotgctl &= ~GOTGCTL_SESREQ;
95c8bc36	173	dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
56f5b1cf PZ	174	}
	175	}
	176	}
	177
	178	if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
	179	/*
	180	* Print statements during the HNP interrupt handling
	181	* can cause it to fail
	182	*/
95c8bc36	183	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
56f5b1cf PZ	184	/*
	185	* WA for 3.00a- HW is not setting cur_mode, even sometimes
	186	* this does not help
	187	*/
9badec2f	188	if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
56f5b1cf PZ	189	udelay(100);
	190	if (gotgctl & GOTGCTL_HSTNEGSCS) {
	191	if (dwc2_is_host_mode(hsotg)) {
	192	hsotg->op_state = OTG_STATE_B_HOST;
	193	/*
	194	* Need to disable SOF interrupt immediately.
	195	* When switching from device to host, the PCD
	196	* interrupt handler won't handle the interrupt
	197	* if host mode is already set. The HCD
	198	* interrupt handler won't get called if the
	199	* HCD state is HALT. This means that the
	200	* interrupt does not get handled and Linux
	201	* complains loudly.
	202	*/
95c8bc36	203	gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
56f5b1cf	204	gintmsk &= ~GINTSTS_SOF;
95c8bc36	205	dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
56f5b1cf PZ	206
	207	/*
	208	* Call callback function with spin lock
	209	* released
	210	*/
	211	spin_unlock(&hsotg->lock);
	212
	213	/* Initialize the Core for Host mode */
	214	dwc2_hcd_start(hsotg);
	215	spin_lock(&hsotg->lock);
	216	hsotg->op_state = OTG_STATE_B_HOST;
	217	}
	218	} else {
95c8bc36	219	gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
56f5b1cf	220	gotgctl &= ~(GOTGCTL_HNPREQ \| GOTGCTL_DEVHNPEN);
95c8bc36	221	dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
56f5b1cf PZ	222	dev_dbg(hsotg->dev, "HNP Failed\n");
	223	dev_err(hsotg->dev,
	224	"Device Not Connected/Responding\n");
	225	}
	226	}
	227
	228	if (gotgint & GOTGINT_HST_NEG_DET) {
	229	/*
	230	* The disconnect interrupt is set at the same time as
	231	* Host Negotiation Detected. During the mode switch all
	232	* interrupts are cleared so the disconnect interrupt
	233	* handler will not get executed.
	234	*/
	235	dev_dbg(hsotg->dev,
	236	" ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
	237	(dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
	238	if (dwc2_is_device_mode(hsotg)) {
	239	dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
	240	hsotg->op_state);
	241	spin_unlock(&hsotg->lock);
	242	dwc2_hcd_disconnect(hsotg);
	243	spin_lock(&hsotg->lock);
	244	hsotg->op_state = OTG_STATE_A_PERIPHERAL;
	245	} else {
	246	/* Need to disable SOF interrupt immediately */
95c8bc36	247	gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
56f5b1cf	248	gintmsk &= ~GINTSTS_SOF;
95c8bc36	249	dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
56f5b1cf PZ	250	spin_unlock(&hsotg->lock);
	251	dwc2_hcd_start(hsotg);
	252	spin_lock(&hsotg->lock);
	253	hsotg->op_state = OTG_STATE_A_HOST;
	254	}
	255	}
	256
	257	if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
	258	dev_dbg(hsotg->dev,
	259	" ++OTG Interrupt: A-Device Timeout Change++\n");
	260	if (gotgint & GOTGINT_DBNCE_DONE)
	261	dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
	262
	263	/* Clear GOTGINT */
95c8bc36	264	dwc2_writel(gotgint, hsotg->regs + GOTGINT);
56f5b1cf PZ	265	}
	266
	267	/**
	268	* dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
	269	* Change Interrupt
	270	*
	271	* @hsotg: Programming view of DWC_otg controller
	272	*
	273	* Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
	274	* Device to Host Mode transition or a Host to Device Mode transition. This only
	275	* occurs when the cable is connected/removed from the PHY connector.
	276	*/
	277	static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
	278	{
95c8bc36	279	u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
56f5b1cf PZ	280
	281	/* Need to disable SOF interrupt immediately */
	282	gintmsk &= ~GINTSTS_SOF;
95c8bc36	283	dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
56f5b1cf PZ	284
	285	dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
	286	dwc2_is_host_mode(hsotg) ? "Host" : "Device");
	287
	288	/*
	289	* Need to schedule a work, as there are possible DELAY function calls.
	290	* Release lock before scheduling workq as it holds spinlock during
	291	* scheduling.
	292	*/
117777b2 DN	293	if (hsotg->wq_otg) {
	294	spin_unlock(&hsotg->lock);
	295	queue_work(hsotg->wq_otg, &hsotg->wf_otg);
	296	spin_lock(&hsotg->lock);
	297	}
56f5b1cf PZ	298
56f5b1cf PZ	299	/* Clear interrupt */
95c8bc36	300	dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
56f5b1cf PZ	301	}
	302
	303	/**
	304	* dwc2_handle_session_req_intr() - This interrupt indicates that a device is
	305	* initiating the Session Request Protocol to request the host to turn on bus
	306	* power so a new session can begin
	307	*
	308	* @hsotg: Programming view of DWC_otg controller
	309	*
	310	* This handler responds by turning on bus power. If the DWC_otg controller is
	311	* in low power mode, this handler brings the controller out of low power mode
	312	* before turning on bus power.
	313	*/
	314	static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
	315	{
21795c82 MYK	316	int ret;
	317
	318	dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
	319	hsotg->lx_state);
56f5b1cf PZ	320
56f5b1cf PZ	321	/* Clear interrupt */
95c8bc36	322	dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
4ace06e8	323
21795c82 MYK	324	if (dwc2_is_device_mode(hsotg)) {
	325	if (hsotg->lx_state == DWC2_L2) {
	326	ret = dwc2_exit_hibernation(hsotg, true);
	327	if (ret && (ret != -ENOTSUPP))
	328	dev_err(hsotg->dev,
	329	"exit hibernation failed\n");
	330	}
	331
	332	/*
	333	* Report disconnect if there is any previous session
	334	* established
	335	*/
1f91b4cc	336	dwc2_hsotg_disconnect(hsotg);
21795c82	337	}
56f5b1cf PZ	338	}
	339
	340	/*
	341	* This interrupt indicates that the DWC_otg controller has detected a
	342	* resume or remote wakeup sequence. If the DWC_otg controller is in
	343	* low power mode, the handler must brings the controller out of low
	344	* power mode. The controller automatically begins resume signaling.
	345	* The handler schedules a time to stop resume signaling.
	346	*/
	347	static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
	348	{
f81f46e1	349	int ret;
56f5b1cf PZ	350	dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
	351	dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
	352
	353	if (dwc2_is_device_mode(hsotg)) {
95c8bc36 AS	354	dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
95c8bc36 AS	355	dwc2_readl(hsotg->regs + DSTS));
56f5b1cf	356	if (hsotg->lx_state == DWC2_L2) {
95c8bc36	357	u32 dctl = dwc2_readl(hsotg->regs + DCTL);
56f5b1cf PZ	358
	359	/* Clear Remote Wakeup Signaling */
	360	dctl &= ~DCTL_RMTWKUPSIG;
95c8bc36	361	dwc2_writel(dctl, hsotg->regs + DCTL);
f81f46e1	362	ret = dwc2_exit_hibernation(hsotg, true);
285046aa	363	if (ret && (ret != -ENOTSUPP))
f81f46e1 GH	364	dev_err(hsotg->dev, "exit hibernation failed\n");
	365
	366	call_gadget(hsotg, resume);
56f5b1cf PZ	367	}
	368	/* Change to L0 state */
	369	hsotg->lx_state = DWC2_L0;
	370	} else {
6e74162f GH	371	if (hsotg->core_params->hibernation) {
	372	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
	373	return;
	374	}
56f5b1cf	375	if (hsotg->lx_state != DWC2_L1) {
95c8bc36	376	u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
56f5b1cf PZ	377
	378	/* Restart the Phy Clock */
	379	pcgcctl &= ~PCGCTL_STOPPCLK;
95c8bc36	380	dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
56f5b1cf PZ	381	mod_timer(&hsotg->wkp_timer,
	382	jiffies + msecs_to_jiffies(71));
	383	} else {
	384	/* Change to L0 state */
	385	hsotg->lx_state = DWC2_L0;
	386	}
	387	}
	388
	389	/* Clear interrupt */
95c8bc36	390	dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
56f5b1cf PZ	391	}
	392
	393	/*
	394	* This interrupt indicates that a device has been disconnected from the
	395	* root port
	396	*/
	397	static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
	398	{
	399	dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
	400	dwc2_is_host_mode(hsotg) ? "Host" : "Device",
	401	dwc2_op_state_str(hsotg));
	402
509d612b YL	403	if (hsotg->op_state == OTG_STATE_A_HOST)
	404	dwc2_hcd_disconnect(hsotg);
	405
95c8bc36	406	dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
56f5b1cf PZ	407	}
	408
	409	/*
	410	* This interrupt indicates that SUSPEND state has been detected on the USB.
	411	*
	412	* For HNP the USB Suspend interrupt signals the change from "a_peripheral"
	413	* to "a_host".
	414	*
	415	* When power management is enabled the core will be put in low power mode.
	416	*/
	417	static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
	418	{
	419	u32 dsts;
f81f46e1	420	int ret;
56f5b1cf PZ	421
	422	dev_dbg(hsotg->dev, "USB SUSPEND\n");
	423
	424	if (dwc2_is_device_mode(hsotg)) {
	425	/*
	426	* Check the Device status register to determine if the Suspend
	427	* state is active
	428	*/
95c8bc36	429	dsts = dwc2_readl(hsotg->regs + DSTS);
56f5b1cf PZ	430	dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
	431	dev_dbg(hsotg->dev,
	432	"DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
	433	!!(dsts & DSTS_SUSPSTS),
9badec2f	434	hsotg->hw_params.power_optimized);
f81f46e1 GH	435	if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) {
	436	/* Ignore suspend request before enumeration */
	437	if (!dwc2_is_device_connected(hsotg)) {
	438	dev_dbg(hsotg->dev,
	439	"ignore suspend request before enumeration\n");
	440	goto clear_int;
	441	}
	442
	443	ret = dwc2_enter_hibernation(hsotg);
	444	if (ret) {
285046aa GH	445	if (ret != -ENOTSUPP)
	446	dev_err(hsotg->dev,
	447	"enter hibernation failed\n");
f81f46e1 GH	448	goto skip_power_saving;
	449	}
	450
	451	udelay(100);
	452
	453	/* Ask phy to be suspended */
	454	if (!IS_ERR_OR_NULL(hsotg->uphy))
	455	usb_phy_set_suspend(hsotg->uphy, true);
	456	skip_power_saving:
3eb42df3 GH	457	/*
	458	* Change to L2 (suspend) state before releasing
	459	* spinlock
	460	*/
	461	hsotg->lx_state = DWC2_L2;
	462
f81f46e1 GH	463	/* Call gadget suspend callback */
	464	call_gadget(hsotg, suspend);
	465	}
56f5b1cf PZ	466	} else {
	467	if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
	468	dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
	469
3eb42df3 GH	470	/* Change to L2 (suspend) state */
3eb42df3 GH	471	hsotg->lx_state = DWC2_L2;
56f5b1cf PZ	472	/* Clear the a_peripheral flag, back to a_host */
	473	spin_unlock(&hsotg->lock);
	474	dwc2_hcd_start(hsotg);
	475	spin_lock(&hsotg->lock);
	476	hsotg->op_state = OTG_STATE_A_HOST;
	477	}
	478	}
	479
f81f46e1	480	clear_int:
56f5b1cf	481	/* Clear interrupt */
95c8bc36	482	dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
56f5b1cf PZ	483	}
	484
	485	#define GINTMSK_COMMON (GINTSTS_WKUPINT \| GINTSTS_SESSREQINT \| \
	486	GINTSTS_CONIDSTSCHNG \| GINTSTS_OTGINT \| \
	487	GINTSTS_MODEMIS \| GINTSTS_DISCONNINT \| \
438492ab	488	GINTSTS_USBSUSP \| GINTSTS_PRTINT)
56f5b1cf PZ	489
	490	/*
	491	* This function returns the Core Interrupt register
	492	*/
	493	static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
	494	{
	495	u32 gintsts;
	496	u32 gintmsk;
	497	u32 gahbcfg;
	498	u32 gintmsk_common = GINTMSK_COMMON;
	499
95c8bc36 AS	500	gintsts = dwc2_readl(hsotg->regs + GINTSTS);
	501	gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
	502	gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
56f5b1cf	503
56f5b1cf PZ	504	/* If any common interrupts set */
	505	if (gintsts & gintmsk_common)
	506	dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
	507	gintsts, gintmsk);
56f5b1cf PZ	508
	509	if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
	510	return gintsts & gintmsk & gintmsk_common;
	511	else
	512	return 0;
	513	}
	514
	515	/*
	516	* Common interrupt handler
	517	*
	518	* The common interrupts are those that occur in both Host and Device mode.
	519	* This handler handles the following interrupts:
	520	* - Mode Mismatch Interrupt
	521	* - OTG Interrupt
	522	* - Connector ID Status Change Interrupt
	523	* - Disconnect Interrupt
	524	* - Session Request Interrupt
	525	* - Resume / Remote Wakeup Detected Interrupt
	526	* - Suspend Interrupt
	527	*/
	528	irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
	529	{
	530	struct dwc2_hsotg *hsotg = dev;
	531	u32 gintsts;
6aafb003	532	irqreturn_t retval = IRQ_NONE;
56f5b1cf	533
cf54772b RB	534	spin_lock(&hsotg->lock);
cf54772b RB	535
057715f2 PZ	536	if (!dwc2_is_controller_alive(hsotg)) {
057715f2 PZ	537	dev_warn(hsotg->dev, "Controller is dead\n");
56f5b1cf PZ	538	goto out;
	539	}
	540
56f5b1cf PZ	541	gintsts = dwc2_read_common_intr(hsotg);
56f5b1cf PZ	542	if (gintsts & ~GINTSTS_PRTINT)
6aafb003	543	retval = IRQ_HANDLED;
56f5b1cf PZ	544
	545	if (gintsts & GINTSTS_MODEMIS)
	546	dwc2_handle_mode_mismatch_intr(hsotg);
	547	if (gintsts & GINTSTS_OTGINT)
	548	dwc2_handle_otg_intr(hsotg);
	549	if (gintsts & GINTSTS_CONIDSTSCHNG)
	550	dwc2_handle_conn_id_status_change_intr(hsotg);
	551	if (gintsts & GINTSTS_DISCONNINT)
	552	dwc2_handle_disconnect_intr(hsotg);
	553	if (gintsts & GINTSTS_SESSREQINT)
	554	dwc2_handle_session_req_intr(hsotg);
	555	if (gintsts & GINTSTS_WKUPINT)
	556	dwc2_handle_wakeup_detected_intr(hsotg);
	557	if (gintsts & GINTSTS_USBSUSP)
	558	dwc2_handle_usb_suspend_intr(hsotg);
	559
56f5b1cf PZ	560	if (gintsts & GINTSTS_PRTINT) {
	561	/*
	562	* The port interrupt occurs while in device mode with HPRT0
	563	* Port Enable/Disable
	564	*/
	565	if (dwc2_is_device_mode(hsotg)) {
	566	dev_dbg(hsotg->dev,
	567	" --Port interrupt received in Device mode--\n");
93571adb DN	568	dwc2_handle_usb_port_intr(hsotg);
93571adb DN	569	retval = IRQ_HANDLED;
56f5b1cf PZ	570	}
	571	}
	572
56f5b1cf	573	out:
cf54772b	574	spin_unlock(&hsotg->lock);
6aafb003	575	return retval;
56f5b1cf	576	}