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usb: dwc2: host: don't use dma_alloc_coherent with irqs disabled
[deliverable/linux.git] / drivers / usb / dwc2 / hcd.c
CommitLineData
7359d482
PZ		 1/*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/spinlock.h>
44#include <linux/interrupt.h>
45#include <linux/dma-mapping.h>
46#include <linux/delay.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57/**
58 * dwc2_dump_channel_info() - Prints the state of a host channel
59 *
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
62 *
63 * Must be called with interrupt disabled and spinlock held
64 *
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
67 */
68static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
70{
71#ifdef VERBOSE_DEBUG
72 int num_channels = hsotg->core_params->host_channels;
73 struct dwc2_qh *qh;
74 u32 hcchar;
75 u32 hcsplt;
76 u32 hctsiz;
77 u32 hc_dma;
78 int i;
79
80 if (chan == NULL)
81 return;
82
83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
87
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
90 hcchar, hcsplt);
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
92 hctsiz, hc_dma);
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
107 qh_list_entry)
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
111 qh_list_entry)
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
116
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
118 }
119#endif /* VERBOSE_DEBUG */
120}
121
122/*
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
125 *
126 * Must be called with interrupt disabled and spinlock held
127 */
128static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
130{
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
133
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
136 qtd_list_entry) {
0d012b98
PZ		 137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
7359d482
PZ		 139 }
140 }
141}
142
143static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
145{
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
148 unsigned long flags;
149
150 if (!qh_list->next)
151 /* The list hasn't been initialized yet */
152 return;
153
154 spin_lock_irqsave(&hsotg->lock, flags);
155
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
158
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
161
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
164 qtd_list_entry)
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
166
167 spin_unlock_irqrestore(&hsotg->lock, flags);
168 dwc2_hcd_qh_free(hsotg, qh);
169 spin_lock_irqsave(&hsotg->lock, flags);
170 }
171
172 spin_unlock_irqrestore(&hsotg->lock, flags);
173}
174
175/*
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
180 *
181 * Must be called with interrupt disabled and spinlock held
182 */
183static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
184{
185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
191}
192
193/**
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
195 *
196 * @hsotg: Pointer to struct dwc2_hsotg
197 */
198void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
199{
200 u32 hprt0;
201
202 if (hsotg->op_state == OTG_STATE_B_HOST) {
203 /*
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
206 * least 50ms.
207 */
208 hprt0 = dwc2_read_hprt0(hsotg);
209 hprt0 |= HPRT0_RST;
210 writel(hprt0, hsotg->regs + HPRT0);
211 }
212
213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 msecs_to_jiffies(50));
215}
216
217/* Must be called with interrupt disabled and spinlock held */
218static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
219{
220 int num_channels = hsotg->core_params->host_channels;
221 struct dwc2_host_chan *channel;
222 u32 hcchar;
223 int i;
224
225 if (hsotg->core_params->dma_enable <= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i = 0; i < num_channels; i++) {
228 channel = hsotg->hc_ptr_array[i];
229 if (!list_empty(&channel->hc_list_entry))
230 continue;
231 hcchar = readl(hsotg->regs + HCCHAR(i));
232 if (hcchar & HCCHAR_CHENA) {
233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 hcchar |= HCCHAR_CHDIS;
235 writel(hcchar, hsotg->regs + HCCHAR(i));
236 }
237 }
238 }
239
240 for (i = 0; i < num_channels; i++) {
241 channel = hsotg->hc_ptr_array[i];
242 if (!list_empty(&channel->hc_list_entry))
243 continue;
244 hcchar = readl(hsotg->regs + HCCHAR(i));
245 if (hcchar & HCCHAR_CHENA) {
246 /* Halt the channel */
247 hcchar |= HCCHAR_CHDIS;
248 writel(hcchar, hsotg->regs + HCCHAR(i));
249 }
250
251 dwc2_hc_cleanup(hsotg, channel);
252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
253 /*
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
256 * device disconnects
257 */
258 channel->qh = NULL;
259 }
7252f1bf
VP		 260 /* All channels have been freed, mark them available */
261 if (hsotg->core_params->uframe_sched > 0) {
262 hsotg->available_host_channels =
263 hsotg->core_params->host_channels;
264 } else {
265 hsotg->non_periodic_channels = 0;
266 hsotg->periodic_channels = 0;
267 }
7359d482
PZ		 268}
269
270/**
271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
272 *
273 * @hsotg: Pointer to struct dwc2_hsotg
274 *
275 * Must be called with interrupt disabled and spinlock held
276 */
277void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
278{
279 u32 intr;
280
281 /* Set status flags for the hub driver */
282 hsotg->flags.b.port_connect_status_change = 1;
283 hsotg->flags.b.port_connect_status = 0;
284
285 /*
286 * Shutdown any transfers in process by clearing the Tx FIFO Empty
287 * interrupt mask and status bits and disabling subsequent host
288 * channel interrupts.
289 */
290 intr = readl(hsotg->regs + GINTMSK);
291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
292 writel(intr, hsotg->regs + GINTMSK);
293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
294 writel(intr, hsotg->regs + GINTSTS);
295
296 /*
297 * Turn off the vbus power only if the core has transitioned to device
298 * mode. If still in host mode, need to keep power on to detect a
299 * reconnection.
300 */
301 if (dwc2_is_device_mode(hsotg)) {
302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
304 writel(0, hsotg->regs + HPRT0);
305 }
306
307 dwc2_disable_host_interrupts(hsotg);
308 }
309
310 /* Respond with an error status to all URBs in the schedule */
311 dwc2_kill_all_urbs(hsotg);
312
313 if (dwc2_is_host_mode(hsotg))
314 /* Clean up any host channels that were in use */
315 dwc2_hcd_cleanup_channels(hsotg);
316
317 dwc2_host_disconnect(hsotg);
318}
319
320/**
321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
322 *
323 * @hsotg: Pointer to struct dwc2_hsotg
324 */
325static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
326{
b46146d5 327 if (hsotg->lx_state == DWC2_L2) {
7359d482 328 hsotg->flags.b.port_suspend_change = 1;
b46146d5
GH		 329 usb_hcd_resume_root_hub(hsotg->priv);
330 } else {
7359d482 331 hsotg->flags.b.port_l1_change = 1;
b46146d5 332 }
7359d482
PZ		 333}
334
335/**
336 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
337 *
338 * @hsotg: Pointer to struct dwc2_hsotg
339 *
340 * Must be called with interrupt disabled and spinlock held
341 */
342void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
343{
344 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
345
346 /*
347 * The root hub should be disconnected before this function is called.
348 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
349 * and the QH lists (via ..._hcd_endpoint_disable).
350 */
351
352 /* Turn off all host-specific interrupts */
353 dwc2_disable_host_interrupts(hsotg);
354
355 /* Turn off the vbus power */
356 dev_dbg(hsotg->dev, "PortPower off\n");
357 writel(0, hsotg->regs + HPRT0);
358}
359
33ad261a 360/* Caller must hold driver lock */
7359d482
PZ		 361static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
362 struct dwc2_hcd_urb *urb, void **ep_handle,
363 gfp_t mem_flags)
364{
365 struct dwc2_qtd *qtd;
7359d482
PZ		 366 u32 intr_mask;
367 int retval;
9f8144c6 368 int dev_speed;
7359d482
PZ		 369
370 if (!hsotg->flags.b.port_connect_status) {
371 /* No longer connected */
372 dev_err(hsotg->dev, "Not connected\n");
373 return -ENODEV;
374 }
375
9f8144c6
NH		 376 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
377
378 /* Some configurations cannot support LS traffic on a FS root port */
379 if ((dev_speed == USB_SPEED_LOW) &&
380 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
381 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
382 u32 hprt0 = readl(hsotg->regs + HPRT0);
383 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
384
385 if (prtspd == HPRT0_SPD_FULL_SPEED)
386 return -ENODEV;
387 }
388
7359d482
PZ		 389 qtd = kzalloc(sizeof(*qtd), mem_flags);
390 if (!qtd)
391 return -ENOMEM;
392
393 dwc2_hcd_qtd_init(qtd, urb);
394 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
395 mem_flags);
9bda1aac 396 if (retval) {
7359d482
PZ		 397 dev_err(hsotg->dev,
398 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
399 retval);
400 kfree(qtd);
401 return retval;
402 }
403
404 intr_mask = readl(hsotg->regs + GINTMSK);
9bda1aac 405 if (!(intr_mask & GINTSTS_SOF)) {
7359d482
PZ		 406 enum dwc2_transaction_type tr_type;
407
408 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
409 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
410 /*
411 * Do not schedule SG transactions until qtd has
412 * URB_GIVEBACK_ASAP set
413 */
414 return 0;
415
7359d482
PZ		 416 tr_type = dwc2_hcd_select_transactions(hsotg);
417 if (tr_type != DWC2_TRANSACTION_NONE)
418 dwc2_hcd_queue_transactions(hsotg, tr_type);
7359d482
PZ		 419 }
420
9bda1aac 421 return 0;
7359d482
PZ		 422}
423
424/* Must be called with interrupt disabled and spinlock held */
425static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
426 struct dwc2_hcd_urb *urb)
427{
428 struct dwc2_qh *qh;
429 struct dwc2_qtd *urb_qtd;
430
431 urb_qtd = urb->qtd;
432 if (!urb_qtd) {
433 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
434 return -EINVAL;
435 }
436
437 qh = urb_qtd->qh;
438 if (!qh) {
439 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
440 return -EINVAL;
441 }
442
0d012b98
PZ		 443 urb->priv = NULL;
444
7359d482
PZ		 445 if (urb_qtd->in_process && qh->channel) {
446 dwc2_dump_channel_info(hsotg, qh->channel);
447
448 /* The QTD is in process (it has been assigned to a channel) */
449 if (hsotg->flags.b.port_connect_status)
450 /*
451 * If still connected (i.e. in host mode), halt the
452 * channel so it can be used for other transfers. If
453 * no longer connected, the host registers can't be
454 * written to halt the channel since the core is in
455 * device mode.
456 */
457 dwc2_hc_halt(hsotg, qh->channel,
458 DWC2_HC_XFER_URB_DEQUEUE);
459 }
460
461 /*
462 * Free the QTD and clean up the associated QH. Leave the QH in the
463 * schedule if it has any remaining QTDs.
464 */
465 if (hsotg->core_params->dma_desc_enable <= 0) {
466 u8 in_process = urb_qtd->in_process;
467
468 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
469 if (in_process) {
470 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
471 qh->channel = NULL;
472 } else if (list_empty(&qh->qtd_list)) {
473 dwc2_hcd_qh_unlink(hsotg, qh);
474 }
475 } else {
476 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
477 }
478
479 return 0;
480}
481
482/* Must NOT be called with interrupt disabled or spinlock held */
483static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
484 struct usb_host_endpoint *ep, int retry)
485{
486 struct dwc2_qtd *qtd, *qtd_tmp;
487 struct dwc2_qh *qh;
488 unsigned long flags;
489 int rc;
490
491 spin_lock_irqsave(&hsotg->lock, flags);
492
493 qh = ep->hcpriv;
494 if (!qh) {
495 rc = -EINVAL;
496 goto err;
497 }
498
499 while (!list_empty(&qh->qtd_list) && retry--) {
500 if (retry == 0) {
501 dev_err(hsotg->dev,
502 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
503 rc = -EBUSY;
504 goto err;
505 }
506
507 spin_unlock_irqrestore(&hsotg->lock, flags);
508 usleep_range(20000, 40000);
509 spin_lock_irqsave(&hsotg->lock, flags);
510 qh = ep->hcpriv;
511 if (!qh) {
512 rc = -EINVAL;
513 goto err;
514 }
515 }
516
517 dwc2_hcd_qh_unlink(hsotg, qh);
518
519 /* Free each QTD in the QH's QTD list */
520 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
521 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
522
523 ep->hcpriv = NULL;
524 spin_unlock_irqrestore(&hsotg->lock, flags);
525 dwc2_hcd_qh_free(hsotg, qh);
526
527 return 0;
528
529err:
530 ep->hcpriv = NULL;
531 spin_unlock_irqrestore(&hsotg->lock, flags);
532
533 return rc;
534}
535
536/* Must be called with interrupt disabled and spinlock held */
537static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
538 struct usb_host_endpoint *ep)
539{
540 struct dwc2_qh *qh = ep->hcpriv;
541
542 if (!qh)
543 return -EINVAL;
544
545 qh->data_toggle = DWC2_HC_PID_DATA0;
546
547 return 0;
548}
549
550/*
551 * Initializes dynamic portions of the DWC_otg HCD state
552 *
553 * Must be called with interrupt disabled and spinlock held
554 */
555static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
556{
557 struct dwc2_host_chan *chan, *chan_tmp;
558 int num_channels;
559 int i;
560
561 hsotg->flags.d32 = 0;
7359d482 562 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
20f2eb9c
DC		 563
564 if (hsotg->core_params->uframe_sched > 0) {
565 hsotg->available_host_channels =
566 hsotg->core_params->host_channels;
567 } else {
568 hsotg->non_periodic_channels = 0;
569 hsotg->periodic_channels = 0;
570 }
7359d482
PZ		 571
572 /*
573 * Put all channels in the free channel list and clean up channel
574 * states
575 */
576 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
577 hc_list_entry)
578 list_del_init(&chan->hc_list_entry);
579
580 num_channels = hsotg->core_params->host_channels;
581 for (i = 0; i < num_channels; i++) {
582 chan = hsotg->hc_ptr_array[i];
583 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
584 dwc2_hc_cleanup(hsotg, chan);
585 }
586
587 /* Initialize the DWC core for host mode operation */
588 dwc2_core_host_init(hsotg);
589}
590
591static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
592 struct dwc2_host_chan *chan,
593 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
594{
595 int hub_addr, hub_port;
596
597 chan->do_split = 1;
598 chan->xact_pos = qtd->isoc_split_pos;
599 chan->complete_split = qtd->complete_split;
600 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
601 chan->hub_addr = (u8)hub_addr;
602 chan->hub_port = (u8)hub_port;
603}
604
605static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
606 struct dwc2_host_chan *chan,
607 struct dwc2_qtd *qtd, void *bufptr)
608{
609 struct dwc2_hcd_urb *urb = qtd->urb;
610 struct dwc2_hcd_iso_packet_desc *frame_desc;
611
612 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
613 case USB_ENDPOINT_XFER_CONTROL:
614 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
615
616 switch (qtd->control_phase) {
617 case DWC2_CONTROL_SETUP:
618 dev_vdbg(hsotg->dev, " Control setup transaction\n");
619 chan->do_ping = 0;
620 chan->ep_is_in = 0;
621 chan->data_pid_start = DWC2_HC_PID_SETUP;
622 if (hsotg->core_params->dma_enable > 0)
623 chan->xfer_dma = urb->setup_dma;
624 else
625 chan->xfer_buf = urb->setup_packet;
626 chan->xfer_len = 8;
627 bufptr = NULL;
628 break;
629
630 case DWC2_CONTROL_DATA:
631 dev_vdbg(hsotg->dev, " Control data transaction\n");
632 chan->data_pid_start = qtd->data_toggle;
633 break;
634
635 case DWC2_CONTROL_STATUS:
636 /*
637 * Direction is opposite of data direction or IN if no
638 * data
639 */
640 dev_vdbg(hsotg->dev, " Control status transaction\n");
641 if (urb->length == 0)
642 chan->ep_is_in = 1;
643 else
644 chan->ep_is_in =
645 dwc2_hcd_is_pipe_out(&urb->pipe_info);
646 if (chan->ep_is_in)
647 chan->do_ping = 0;
648 chan->data_pid_start = DWC2_HC_PID_DATA1;
649 chan->xfer_len = 0;
650 if (hsotg->core_params->dma_enable > 0)
651 chan->xfer_dma = hsotg->status_buf_dma;
652 else
653 chan->xfer_buf = hsotg->status_buf;
654 bufptr = NULL;
655 break;
656 }
657 break;
658
659 case USB_ENDPOINT_XFER_BULK:
660 chan->ep_type = USB_ENDPOINT_XFER_BULK;
661 break;
662
663 case USB_ENDPOINT_XFER_INT:
664 chan->ep_type = USB_ENDPOINT_XFER_INT;
665 break;
666
667 case USB_ENDPOINT_XFER_ISOC:
668 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
669 if (hsotg->core_params->dma_desc_enable > 0)
670 break;
671
672 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
673 frame_desc->status = 0;
674
675 if (hsotg->core_params->dma_enable > 0) {
676 chan->xfer_dma = urb->dma;
677 chan->xfer_dma += frame_desc->offset +
678 qtd->isoc_split_offset;
679 } else {
680 chan->xfer_buf = urb->buf;
681 chan->xfer_buf += frame_desc->offset +
682 qtd->isoc_split_offset;
683 }
684
685 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
686
687 /* For non-dword aligned buffers */
688 if (hsotg->core_params->dma_enable > 0 &&
689 (chan->xfer_dma & 0x3))
690 bufptr = (u8 *)urb->buf + frame_desc->offset +
691 qtd->isoc_split_offset;
692 else
693 bufptr = NULL;
694
695 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
696 if (chan->xfer_len <= 188)
697 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
698 else
699 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
700 }
701 break;
702 }
703
704 return bufptr;
705}
706
707static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
5dce9555
PZ		 708 struct dwc2_host_chan *chan,
709 struct dwc2_hcd_urb *urb, void *bufptr)
7359d482
PZ		 710{
711 u32 buf_size;
5dce9555
PZ		 712 struct urb *usb_urb;
713 struct usb_hcd *hcd;
7359d482
PZ		 714
715 if (!qh->dw_align_buf) {
5dce9555
PZ		 716 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
717 buf_size = hsotg->core_params->max_transfer_size;
718 else
719 /* 3072 = 3 max-size Isoc packets */
720 buf_size = 3072;
721
db62b9a8 722 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
7359d482
PZ		 723 if (!qh->dw_align_buf)
724 return -ENOMEM;
5dce9555 725 qh->dw_align_buf_size = buf_size;
7359d482
PZ		 726 }
727
5dce9555
PZ		 728 if (chan->xfer_len) {
729 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
730 usb_urb = urb->priv;
731
732 if (usb_urb) {
733 if (usb_urb->transfer_flags &
734 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
735 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
736 hcd = dwc2_hsotg_to_hcd(hsotg);
737 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
738 }
739 if (!chan->ep_is_in)
740 memcpy(qh->dw_align_buf, bufptr,
741 chan->xfer_len);
742 } else {
743 dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
744 }
7359d482
PZ		 745 }
746
db62b9a8
GH		 747 qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
748 qh->dw_align_buf, qh->dw_align_buf_size,
749 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
750 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
751 dev_err(hsotg->dev, "can't map align_buf\n");
752 chan->align_buf = (dma_addr_t)NULL;
753 return -EINVAL;
754 }
755
7359d482
PZ		 756 chan->align_buf = qh->dw_align_buf_dma;
757 return 0;
758}
759
760/**
761 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
762 * channel and initializes the host channel to perform the transactions. The
763 * host channel is removed from the free list.
764 *
765 * @hsotg: The HCD state structure
766 * @qh: Transactions from the first QTD for this QH are selected and assigned
767 * to a free host channel
768 */
20f2eb9c 769static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
7359d482
PZ		 770{
771 struct dwc2_host_chan *chan;
772 struct dwc2_hcd_urb *urb;
773 struct dwc2_qtd *qtd;
774 void *bufptr = NULL;
775
b49977a6
MK		 776 if (dbg_qh(qh))
777 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
7359d482
PZ		 778
779 if (list_empty(&qh->qtd_list)) {
780 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
20f2eb9c 781 return -ENOMEM;
7359d482
PZ		 782 }
783
784 if (list_empty(&hsotg->free_hc_list)) {
785 dev_dbg(hsotg->dev, "No free channel to assign\n");
20f2eb9c 786 return -ENOMEM;
7359d482
PZ		 787 }
788
789 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
790 hc_list_entry);
791
20f2eb9c 792 /* Remove host channel from free list */
7359d482
PZ		 793 list_del_init(&chan->hc_list_entry);
794
795 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
796 urb = qtd->urb;
797 qh->channel = chan;
798 qtd->in_process = 1;
799
800 /*
801 * Use usb_pipedevice to determine device address. This address is
802 * 0 before the SET_ADDRESS command and the correct address afterward.
803 */
804 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
805 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
806 chan->speed = qh->dev_speed;
807 chan->max_packet = dwc2_max_packet(qh->maxp);
808
809 chan->xfer_started = 0;
810 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
811 chan->error_state = (qtd->error_count > 0);
812 chan->halt_on_queue = 0;
813 chan->halt_pending = 0;
814 chan->requests = 0;
815
816 /*
817 * The following values may be modified in the transfer type section
818 * below. The xfer_len value may be reduced when the transfer is
819 * started to accommodate the max widths of the XferSize and PktCnt
820 * fields in the HCTSIZn register.
821 */
822
823 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
824 if (chan->ep_is_in)
825 chan->do_ping = 0;
826 else
827 chan->do_ping = qh->ping_state;
828
829 chan->data_pid_start = qh->data_toggle;
830 chan->multi_count = 1;
831
bb6c3422
RK		 832 if (urb->actual_length > urb->length &&
833 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
84181086
PZ		 834 urb->actual_length = urb->length;
835
7359d482
PZ		 836 if (hsotg->core_params->dma_enable > 0) {
837 chan->xfer_dma = urb->dma + urb->actual_length;
838
839 /* For non-dword aligned case */
840 if (hsotg->core_params->dma_desc_enable <= 0 &&
841 (chan->xfer_dma & 0x3))
842 bufptr = (u8 *)urb->buf + urb->actual_length;
843 } else {
844 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
845 }
846
847 chan->xfer_len = urb->length - urb->actual_length;
848 chan->xfer_count = 0;
849
850 /* Set the split attributes if required */
851 if (qh->do_split)
852 dwc2_hc_init_split(hsotg, chan, qtd, urb);
853 else
854 chan->do_split = 0;
855
856 /* Set the transfer attributes */
857 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
858
859 /* Non DWORD-aligned buffer case */
860 if (bufptr) {
861 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
5dce9555 862 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
7359d482
PZ		 863 dev_err(hsotg->dev,
864 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
865 __func__);
866 /* Add channel back to free list */
867 chan->align_buf = 0;
868 chan->multi_count = 0;
869 list_add_tail(&chan->hc_list_entry,
870 &hsotg->free_hc_list);
871 qtd->in_process = 0;
872 qh->channel = NULL;
20f2eb9c 873 return -ENOMEM;
7359d482
PZ		 874 }
875 } else {
876 chan->align_buf = 0;
877 }
878
879 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
880 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
881 /*
882 * This value may be modified when the transfer is started
883 * to reflect the actual transfer length
884 */
885 chan->multi_count = dwc2_hb_mult(qh->maxp);
886
887 if (hsotg->core_params->dma_desc_enable > 0)
888 chan->desc_list_addr = qh->desc_list_dma;
889
890 dwc2_hc_init(hsotg, chan);
891 chan->qh = qh;
20f2eb9c
DC		 892
893 return 0;
7359d482
PZ		 894}
895
896/**
897 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
898 * schedule and assigns them to available host channels. Called from the HCD
899 * interrupt handler functions.
900 *
901 * @hsotg: The HCD state structure
902 *
903 * Return: The types of new transactions that were assigned to host channels
904 */
905enum dwc2_transaction_type dwc2_hcd_select_transactions(
906 struct dwc2_hsotg *hsotg)
907{
908 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
909 struct list_head *qh_ptr;
910 struct dwc2_qh *qh;
911 int num_channels;
912
913#ifdef DWC2_DEBUG_SOF
914 dev_vdbg(hsotg->dev, " Select Transactions\n");
915#endif
916
917 /* Process entries in the periodic ready list */
918 qh_ptr = hsotg->periodic_sched_ready.next;
919 while (qh_ptr != &hsotg->periodic_sched_ready) {
920 if (list_empty(&hsotg->free_hc_list))
921 break;
20f2eb9c
DC		 922 if (hsotg->core_params->uframe_sched > 0) {
923 if (hsotg->available_host_channels <= 1)
924 break;
925 hsotg->available_host_channels--;
926 }
7359d482 927 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 928 if (dwc2_assign_and_init_hc(hsotg, qh))
929 break;
7359d482
PZ		 930
931 /*
932 * Move the QH from the periodic ready schedule to the
933 * periodic assigned schedule
934 */
935 qh_ptr = qh_ptr->next;
936 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
937 ret_val = DWC2_TRANSACTION_PERIODIC;
938 }
939
940 /*
941 * Process entries in the inactive portion of the non-periodic
942 * schedule. Some free host channels may not be used if they are
943 * reserved for periodic transfers.
944 */
945 num_channels = hsotg->core_params->host_channels;
946 qh_ptr = hsotg->non_periodic_sched_inactive.next;
947 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
20f2eb9c
DC		 948 if (hsotg->core_params->uframe_sched <= 0 &&
949 hsotg->non_periodic_channels >= num_channels -
7359d482
PZ		 950 hsotg->periodic_channels)
951 break;
952 if (list_empty(&hsotg->free_hc_list))
953 break;
954 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 955 if (hsotg->core_params->uframe_sched > 0) {
956 if (hsotg->available_host_channels < 1)
957 break;
958 hsotg->available_host_channels--;
959 }
960
961 if (dwc2_assign_and_init_hc(hsotg, qh))
962 break;
7359d482
PZ		 963
964 /*
965 * Move the QH from the non-periodic inactive schedule to the
966 * non-periodic active schedule
967 */
968 qh_ptr = qh_ptr->next;
969 list_move(&qh->qh_list_entry,
970 &hsotg->non_periodic_sched_active);
971
972 if (ret_val == DWC2_TRANSACTION_NONE)
973 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
974 else
975 ret_val = DWC2_TRANSACTION_ALL;
976
20f2eb9c
DC		 977 if (hsotg->core_params->uframe_sched <= 0)
978 hsotg->non_periodic_channels++;
7359d482
PZ		 979 }
980
981 return ret_val;
982}
983
984/**
985 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
986 * a host channel associated with either a periodic or non-periodic transfer
987 *
988 * @hsotg: The HCD state structure
989 * @chan: Host channel descriptor associated with either a periodic or
990 * non-periodic transfer
991 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
992 * for periodic transfers or the non-periodic Tx FIFO
993 * for non-periodic transfers
994 *
995 * Return: 1 if a request is queued and more requests may be needed to
996 * complete the transfer, 0 if no more requests are required for this
997 * transfer, -1 if there is insufficient space in the Tx FIFO
998 *
999 * This function assumes that there is space available in the appropriate
1000 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
1001 * it checks whether space is available in the appropriate Tx FIFO.
1002 *
1003 * Must be called with interrupt disabled and spinlock held
1004 */
1005static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1006 struct dwc2_host_chan *chan,
1007 u16 fifo_dwords_avail)
1008{
1009 int retval = 0;
1010
1011 if (hsotg->core_params->dma_enable > 0) {
1012 if (hsotg->core_params->dma_desc_enable > 0) {
1013 if (!chan->xfer_started ||
1014 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1015 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1016 chan->qh->ping_state = 0;
1017 }
1018 } else if (!chan->xfer_started) {
1019 dwc2_hc_start_transfer(hsotg, chan);
1020 chan->qh->ping_state = 0;
1021 }
1022 } else if (chan->halt_pending) {
1023 /* Don't queue a request if the channel has been halted */
1024 } else if (chan->halt_on_queue) {
1025 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1026 } else if (chan->do_ping) {
1027 if (!chan->xfer_started)
1028 dwc2_hc_start_transfer(hsotg, chan);
1029 } else if (!chan->ep_is_in ||
1030 chan->data_pid_start == DWC2_HC_PID_SETUP) {
1031 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1032 if (!chan->xfer_started) {
1033 dwc2_hc_start_transfer(hsotg, chan);
1034 retval = 1;
1035 } else {
1036 retval = dwc2_hc_continue_transfer(hsotg, chan);
1037 }
1038 } else {
1039 retval = -1;
1040 }
1041 } else {
1042 if (!chan->xfer_started) {
1043 dwc2_hc_start_transfer(hsotg, chan);
1044 retval = 1;
1045 } else {
1046 retval = dwc2_hc_continue_transfer(hsotg, chan);
1047 }
1048 }
1049
1050 return retval;
1051}
1052
1053/*
1054 * Processes periodic channels for the next frame and queues transactions for
1055 * these channels to the DWC_otg controller. After queueing transactions, the
1056 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1057 * to queue as Periodic Tx FIFO or request queue space becomes available.
1058 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1059 *
1060 * Must be called with interrupt disabled and spinlock held
1061 */
1062static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1063{
1064 struct list_head *qh_ptr;
1065 struct dwc2_qh *qh;
1066 u32 tx_status;
1067 u32 fspcavail;
1068 u32 gintmsk;
1069 int status;
1070 int no_queue_space = 0;
1071 int no_fifo_space = 0;
1072 u32 qspcavail;
1073
b49977a6
MK		 1074 if (dbg_perio())
1075 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
7359d482
PZ		 1076
1077 tx_status = readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1079 TXSTS_QSPCAVAIL_SHIFT;
1080 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1081 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1082
1083 if (dbg_perio()) {
1084 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1085 qspcavail);
1086 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1087 fspcavail);
1088 }
7359d482
PZ		 1089
1090 qh_ptr = hsotg->periodic_sched_assigned.next;
1091 while (qh_ptr != &hsotg->periodic_sched_assigned) {
1092 tx_status = readl(hsotg->regs + HPTXSTS);
acdb9046
MK		 1093 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1094 TXSTS_QSPCAVAIL_SHIFT;
1095 if (qspcavail == 0) {
7359d482
PZ		 1096 no_queue_space = 1;
1097 break;
1098 }
1099
1100 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1101 if (!qh->channel) {
1102 qh_ptr = qh_ptr->next;
1103 continue;
1104 }
1105
1106 /* Make sure EP's TT buffer is clean before queueing qtds */
1107 if (qh->tt_buffer_dirty) {
1108 qh_ptr = qh_ptr->next;
1109 continue;
1110 }
1111
1112 /*
1113 * Set a flag if we're queuing high-bandwidth in slave mode.
1114 * The flag prevents any halts to get into the request queue in
1115 * the middle of multiple high-bandwidth packets getting queued.
1116 */
1117 if (hsotg->core_params->dma_enable <= 0 &&
1118 qh->channel->multi_count > 1)
1119 hsotg->queuing_high_bandwidth = 1;
1120
d6ec53e0
MK		 1121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1122 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1124 if (status < 0) {
1125 no_fifo_space = 1;
1126 break;
1127 }
1128
1129 /*
1130 * In Slave mode, stay on the current transfer until there is
1131 * nothing more to do or the high-bandwidth request count is
1132 * reached. In DMA mode, only need to queue one request. The
1133 * controller automatically handles multiple packets for
1134 * high-bandwidth transfers.
1135 */
1136 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1137 qh->channel->requests == qh->channel->multi_count) {
1138 qh_ptr = qh_ptr->next;
1139 /*
1140 * Move the QH from the periodic assigned schedule to
1141 * the periodic queued schedule
1142 */
1143 list_move(&qh->qh_list_entry,
1144 &hsotg->periodic_sched_queued);
1145
1146 /* done queuing high bandwidth */
1147 hsotg->queuing_high_bandwidth = 0;
1148 }
1149 }
1150
1151 if (hsotg->core_params->dma_enable <= 0) {
1152 tx_status = readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1153 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1154 TXSTS_QSPCAVAIL_SHIFT;
1155 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1156 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1157 if (dbg_perio()) {
1158 dev_vdbg(hsotg->dev,
1159 " P Tx Req Queue Space Avail (after queue): %d\n",
1160 qspcavail);
1161 dev_vdbg(hsotg->dev,
1162 " P Tx FIFO Space Avail (after queue): %d\n",
1163 fspcavail);
1164 }
7359d482
PZ		 1165
1166 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1167 no_queue_space || no_fifo_space) {
1168 /*
1169 * May need to queue more transactions as the request
1170 * queue or Tx FIFO empties. Enable the periodic Tx
1171 * FIFO empty interrupt. (Always use the half-empty
1172 * level to ensure that new requests are loaded as
1173 * soon as possible.)
1174 */
1175 gintmsk = readl(hsotg->regs + GINTMSK);
1176 gintmsk |= GINTSTS_PTXFEMP;
1177 writel(gintmsk, hsotg->regs + GINTMSK);
1178 } else {
1179 /*
1180 * Disable the Tx FIFO empty interrupt since there are
1181 * no more transactions that need to be queued right
1182 * now. This function is called from interrupt
1183 * handlers to queue more transactions as transfer
1184 * states change.
1185 */
1186 gintmsk = readl(hsotg->regs + GINTMSK);
1187 gintmsk &= ~GINTSTS_PTXFEMP;
1188 writel(gintmsk, hsotg->regs + GINTMSK);
1189 }
1190 }
1191}
1192
1193/*
1194 * Processes active non-periodic channels and queues transactions for these
1195 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1196 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1197 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1198 * FIFO Empty interrupt is disabled.
1199 *
1200 * Must be called with interrupt disabled and spinlock held
1201 */
1202static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1203{
1204 struct list_head *orig_qh_ptr;
1205 struct dwc2_qh *qh;
1206 u32 tx_status;
1207 u32 qspcavail;
1208 u32 fspcavail;
1209 u32 gintmsk;
1210 int status;
1211 int no_queue_space = 0;
1212 int no_fifo_space = 0;
1213 int more_to_do = 0;
1214
1215 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1216
1217 tx_status = readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1218 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1219 TXSTS_QSPCAVAIL_SHIFT;
1220 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1221 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1222 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1223 qspcavail);
1224 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1225 fspcavail);
1226
1227 /*
1228 * Keep track of the starting point. Skip over the start-of-list
1229 * entry.
1230 */
1231 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1232 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1233 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1234
1235 /*
1236 * Process once through the active list or until no more space is
1237 * available in the request queue or the Tx FIFO
1238 */
1239 do {
1240 tx_status = readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1241 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1242 TXSTS_QSPCAVAIL_SHIFT;
7359d482
PZ		 1243 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1244 no_queue_space = 1;
1245 break;
1246 }
1247
1248 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1249 qh_list_entry);
1250 if (!qh->channel)
1251 goto next;
1252
1253 /* Make sure EP's TT buffer is clean before queueing qtds */
1254 if (qh->tt_buffer_dirty)
1255 goto next;
1256
d6ec53e0
MK		 1257 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1258 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1259 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1260
1261 if (status > 0) {
1262 more_to_do = 1;
1263 } else if (status < 0) {
1264 no_fifo_space = 1;
1265 break;
1266 }
1267next:
1268 /* Advance to next QH, skipping start-of-list entry */
1269 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1270 if (hsotg->non_periodic_qh_ptr ==
1271 &hsotg->non_periodic_sched_active)
1272 hsotg->non_periodic_qh_ptr =
1273 hsotg->non_periodic_qh_ptr->next;
1274 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1275
1276 if (hsotg->core_params->dma_enable <= 0) {
1277 tx_status = readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1278 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1279 TXSTS_QSPCAVAIL_SHIFT;
1280 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1281 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1282 dev_vdbg(hsotg->dev,
1283 " NP Tx Req Queue Space Avail (after queue): %d\n",
1284 qspcavail);
1285 dev_vdbg(hsotg->dev,
1286 " NP Tx FIFO Space Avail (after queue): %d\n",
1287 fspcavail);
1288
1289 if (more_to_do || no_queue_space || no_fifo_space) {
1290 /*
1291 * May need to queue more transactions as the request
1292 * queue or Tx FIFO empties. Enable the non-periodic
1293 * Tx FIFO empty interrupt. (Always use the half-empty
1294 * level to ensure that new requests are loaded as
1295 * soon as possible.)
1296 */
1297 gintmsk = readl(hsotg->regs + GINTMSK);
1298 gintmsk |= GINTSTS_NPTXFEMP;
1299 writel(gintmsk, hsotg->regs + GINTMSK);
1300 } else {
1301 /*
1302 * Disable the Tx FIFO empty interrupt since there are
1303 * no more transactions that need to be queued right
1304 * now. This function is called from interrupt
1305 * handlers to queue more transactions as transfer
1306 * states change.
1307 */
1308 gintmsk = readl(hsotg->regs + GINTMSK);
1309 gintmsk &= ~GINTSTS_NPTXFEMP;
1310 writel(gintmsk, hsotg->regs + GINTMSK);
1311 }
1312 }
1313}
1314
1315/**
1316 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1317 * and queues transactions for these channels to the DWC_otg controller. Called
1318 * from the HCD interrupt handler functions.
1319 *
1320 * @hsotg: The HCD state structure
1321 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1322 * or both)
1323 *
1324 * Must be called with interrupt disabled and spinlock held
1325 */
1326void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1327 enum dwc2_transaction_type tr_type)
1328{
1329#ifdef DWC2_DEBUG_SOF
1330 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1331#endif
1332 /* Process host channels associated with periodic transfers */
1333 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1334 tr_type == DWC2_TRANSACTION_ALL) &&
1335 !list_empty(&hsotg->periodic_sched_assigned))
1336 dwc2_process_periodic_channels(hsotg);
1337
1338 /* Process host channels associated with non-periodic transfers */
1339 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1340 tr_type == DWC2_TRANSACTION_ALL) {
1341 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1342 dwc2_process_non_periodic_channels(hsotg);
1343 } else {
1344 /*
1345 * Ensure NP Tx FIFO empty interrupt is disabled when
1346 * there are no non-periodic transfers to process
1347 */
1348 u32 gintmsk = readl(hsotg->regs + GINTMSK);
1349
1350 gintmsk &= ~GINTSTS_NPTXFEMP;
1351 writel(gintmsk, hsotg->regs + GINTMSK);
1352 }
1353 }
1354}
1355
1356static void dwc2_conn_id_status_change(struct work_struct *work)
1357{
1358 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1359 wf_otg);
1360 u32 count = 0;
1361 u32 gotgctl;
1362
1363 dev_dbg(hsotg->dev, "%s()\n", __func__);
1364
1365 gotgctl = readl(hsotg->regs + GOTGCTL);
1366 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1367 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1368 !!(gotgctl & GOTGCTL_CONID_B));
1369
1370 /* B-Device connector (Device Mode) */
1371 if (gotgctl & GOTGCTL_CONID_B) {
1372 /* Wait for switch to device mode */
1373 dev_dbg(hsotg->dev, "connId B\n");
1374 while (!dwc2_is_device_mode(hsotg)) {
1375 dev_info(hsotg->dev,
1376 "Waiting for Peripheral Mode, Mode=%s\n",
1377 dwc2_is_host_mode(hsotg) ? "Host" :
1378 "Peripheral");
1379 usleep_range(20000, 40000);
1380 if (++count > 250)
1381 break;
1382 }
1383 if (count > 250)
1384 dev_err(hsotg->dev,
de9169a1 1385 "Connection id status change timed out\n");
7359d482 1386 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
6706c721 1387 dwc2_core_init(hsotg, false, -1);
7359d482 1388 dwc2_enable_global_interrupts(hsotg);
643cc4de 1389 s3c_hsotg_core_init_disconnected(hsotg, false);
510ffaa4 1390 s3c_hsotg_core_connect(hsotg);
7359d482
PZ		 1391 } else {
1392 /* A-Device connector (Host Mode) */
1393 dev_dbg(hsotg->dev, "connId A\n");
1394 while (!dwc2_is_host_mode(hsotg)) {
1395 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1396 dwc2_is_host_mode(hsotg) ?
1397 "Host" : "Peripheral");
1398 usleep_range(20000, 40000);
1399 if (++count > 250)
1400 break;
1401 }
1402 if (count > 250)
1403 dev_err(hsotg->dev,
de9169a1 1404 "Connection id status change timed out\n");
7359d482
PZ		 1405 hsotg->op_state = OTG_STATE_A_HOST;
1406
1407 /* Initialize the Core for Host mode */
6706c721 1408 dwc2_core_init(hsotg, false, -1);
7359d482
PZ		 1409 dwc2_enable_global_interrupts(hsotg);
1410 dwc2_hcd_start(hsotg);
1411 }
1412}
1413
1414static void dwc2_wakeup_detected(unsigned long data)
1415{
1416 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1417 u32 hprt0;
1418
1419 dev_dbg(hsotg->dev, "%s()\n", __func__);
1420
1421 /*
1422 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1423 * so that OPT tests pass with all PHYs.)
1424 */
1425 hprt0 = dwc2_read_hprt0(hsotg);
1426 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1427 hprt0 &= ~HPRT0_RES;
1428 writel(hprt0, hsotg->regs + HPRT0);
1429 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1430 readl(hsotg->regs + HPRT0));
1431
1432 dwc2_hcd_rem_wakeup(hsotg);
1433
1434 /* Change to L0 state */
1435 hsotg->lx_state = DWC2_L0;
1436}
1437
1438static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1439{
1440 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1441
1442 return hcd->self.b_hnp_enable;
1443}
1444
1445/* Must NOT be called with interrupt disabled or spinlock held */
1446static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1447{
1448 unsigned long flags;
1449 u32 hprt0;
1450 u32 pcgctl;
1451 u32 gotgctl;
1452
1453 dev_dbg(hsotg->dev, "%s()\n", __func__);
1454
1455 spin_lock_irqsave(&hsotg->lock, flags);
1456
1457 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1458 gotgctl = readl(hsotg->regs + GOTGCTL);
1459 gotgctl |= GOTGCTL_HSTSETHNPEN;
1460 writel(gotgctl, hsotg->regs + GOTGCTL);
1461 hsotg->op_state = OTG_STATE_A_SUSPEND;
1462 }
1463
1464 hprt0 = dwc2_read_hprt0(hsotg);
1465 hprt0 |= HPRT0_SUSP;
1466 writel(hprt0, hsotg->regs + HPRT0);
1467
1468 /* Update lx_state */
1469 hsotg->lx_state = DWC2_L2;
1470
1471 /* Suspend the Phy Clock */
1472 pcgctl = readl(hsotg->regs + PCGCTL);
1473 pcgctl |= PCGCTL_STOPPCLK;
1474 writel(pcgctl, hsotg->regs + PCGCTL);
1475 udelay(10);
1476
1477 /* For HNP the bus must be suspended for at least 200ms */
1478 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1479 pcgctl = readl(hsotg->regs + PCGCTL);
1480 pcgctl &= ~PCGCTL_STOPPCLK;
1481 writel(pcgctl, hsotg->regs + PCGCTL);
1482
1483 spin_unlock_irqrestore(&hsotg->lock, flags);
1484
1485 usleep_range(200000, 250000);
1486 } else {
1487 spin_unlock_irqrestore(&hsotg->lock, flags);
1488 }
1489}
1490
1491/* Handles hub class-specific requests */
1492static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1493 u16 wvalue, u16 windex, char *buf, u16 wlength)
1494{
1495 struct usb_hub_descriptor *hub_desc;
1496 int retval = 0;
1497 u32 hprt0;
1498 u32 port_status;
1499 u32 speed;
1500 u32 pcgctl;
1501
1502 switch (typereq) {
1503 case ClearHubFeature:
1504 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1505
1506 switch (wvalue) {
1507 case C_HUB_LOCAL_POWER:
1508 case C_HUB_OVER_CURRENT:
1509 /* Nothing required here */
1510 break;
1511
1512 default:
1513 retval = -EINVAL;
1514 dev_err(hsotg->dev,
1515 "ClearHubFeature request %1xh unknown\n",
1516 wvalue);
1517 }
1518 break;
1519
1520 case ClearPortFeature:
1521 if (wvalue != USB_PORT_FEAT_L1)
1522 if (!windex || windex > 1)
1523 goto error;
1524 switch (wvalue) {
1525 case USB_PORT_FEAT_ENABLE:
1526 dev_dbg(hsotg->dev,
1527 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1528 hprt0 = dwc2_read_hprt0(hsotg);
1529 hprt0 |= HPRT0_ENA;
1530 writel(hprt0, hsotg->regs + HPRT0);
1531 break;
1532
1533 case USB_PORT_FEAT_SUSPEND:
1534 dev_dbg(hsotg->dev,
1535 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
b0bb9bb6 1536 writel(0, hsotg->regs + PCGCTL);
42a6630a 1537 usleep_range(20000, 40000);
b0bb9bb6
PZ		 1538
1539 hprt0 = dwc2_read_hprt0(hsotg);
1540 hprt0 |= HPRT0_RES;
1541 writel(hprt0, hsotg->regs + HPRT0);
1542 hprt0 &= ~HPRT0_SUSP;
42a6630a 1543 msleep(USB_RESUME_TIMEOUT);
b0bb9bb6
PZ		 1544
1545 hprt0 &= ~HPRT0_RES;
1546 writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1547 break;
1548
1549 case USB_PORT_FEAT_POWER:
1550 dev_dbg(hsotg->dev,
1551 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1552 hprt0 = dwc2_read_hprt0(hsotg);
1553 hprt0 &= ~HPRT0_PWR;
1554 writel(hprt0, hsotg->regs + HPRT0);
1555 break;
1556
1557 case USB_PORT_FEAT_INDICATOR:
1558 dev_dbg(hsotg->dev,
1559 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1560 /* Port indicator not supported */
1561 break;
1562
1563 case USB_PORT_FEAT_C_CONNECTION:
1564 /*
1565 * Clears driver's internal Connect Status Change flag
1566 */
1567 dev_dbg(hsotg->dev,
1568 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1569 hsotg->flags.b.port_connect_status_change = 0;
1570 break;
1571
1572 case USB_PORT_FEAT_C_RESET:
1573 /* Clears driver's internal Port Reset Change flag */
1574 dev_dbg(hsotg->dev,
1575 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1576 hsotg->flags.b.port_reset_change = 0;
1577 break;
1578
1579 case USB_PORT_FEAT_C_ENABLE:
1580 /*
1581 * Clears the driver's internal Port Enable/Disable
1582 * Change flag
1583 */
1584 dev_dbg(hsotg->dev,
1585 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1586 hsotg->flags.b.port_enable_change = 0;
1587 break;
1588
1589 case USB_PORT_FEAT_C_SUSPEND:
1590 /*
1591 * Clears the driver's internal Port Suspend Change
1592 * flag, which is set when resume signaling on the host
1593 * port is complete
1594 */
1595 dev_dbg(hsotg->dev,
1596 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1597 hsotg->flags.b.port_suspend_change = 0;
1598 break;
1599
1600 case USB_PORT_FEAT_C_PORT_L1:
1601 dev_dbg(hsotg->dev,
1602 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1603 hsotg->flags.b.port_l1_change = 0;
1604 break;
1605
1606 case USB_PORT_FEAT_C_OVER_CURRENT:
1607 dev_dbg(hsotg->dev,
1608 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1609 hsotg->flags.b.port_over_current_change = 0;
1610 break;
1611
1612 default:
1613 retval = -EINVAL;
1614 dev_err(hsotg->dev,
1615 "ClearPortFeature request %1xh unknown or unsupported\n",
1616 wvalue);
1617 }
1618 break;
1619
1620 case GetHubDescriptor:
1621 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1622 hub_desc = (struct usb_hub_descriptor *)buf;
1623 hub_desc->bDescLength = 9;
a5dd0395 1624 hub_desc->bDescriptorType = USB_DT_HUB;
7359d482 1625 hub_desc->bNbrPorts = 1;
3d040de8
SS		 1626 hub_desc->wHubCharacteristics =
1627 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1628 HUB_CHAR_INDV_PORT_OCPM);
7359d482
PZ		 1629 hub_desc->bPwrOn2PwrGood = 1;
1630 hub_desc->bHubContrCurrent = 0;
1631 hub_desc->u.hs.DeviceRemovable[0] = 0;
1632 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1633 break;
1634
1635 case GetHubStatus:
1636 dev_dbg(hsotg->dev, "GetHubStatus\n");
1637 memset(buf, 0, 4);
1638 break;
1639
1640 case GetPortStatus:
b8313417
PZ		 1641 dev_vdbg(hsotg->dev,
1642 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1643 hsotg->flags.d32);
7359d482
PZ		 1644 if (!windex || windex > 1)
1645 goto error;
1646
1647 port_status = 0;
1648 if (hsotg->flags.b.port_connect_status_change)
1649 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1650 if (hsotg->flags.b.port_enable_change)
1651 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1652 if (hsotg->flags.b.port_suspend_change)
1653 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1654 if (hsotg->flags.b.port_l1_change)
1655 port_status |= USB_PORT_STAT_C_L1 << 16;
1656 if (hsotg->flags.b.port_reset_change)
1657 port_status |= USB_PORT_STAT_C_RESET << 16;
1658 if (hsotg->flags.b.port_over_current_change) {
1659 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1660 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1661 }
1662
1663 if (!hsotg->flags.b.port_connect_status) {
1664 /*
1665 * The port is disconnected, which means the core is
1666 * either in device mode or it soon will be. Just
1667 * return 0's for the remainder of the port status
1668 * since the port register can't be read if the core
1669 * is in device mode.
1670 */
1671 *(__le32 *)buf = cpu_to_le32(port_status);
1672 break;
1673 }
1674
1675 hprt0 = readl(hsotg->regs + HPRT0);
b8313417 1676 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
7359d482
PZ		 1677
1678 if (hprt0 & HPRT0_CONNSTS)
1679 port_status |= USB_PORT_STAT_CONNECTION;
1680 if (hprt0 & HPRT0_ENA)
1681 port_status |= USB_PORT_STAT_ENABLE;
1682 if (hprt0 & HPRT0_SUSP)
1683 port_status |= USB_PORT_STAT_SUSPEND;
1684 if (hprt0 & HPRT0_OVRCURRACT)
1685 port_status |= USB_PORT_STAT_OVERCURRENT;
1686 if (hprt0 & HPRT0_RST)
1687 port_status |= USB_PORT_STAT_RESET;
1688 if (hprt0 & HPRT0_PWR)
1689 port_status |= USB_PORT_STAT_POWER;
1690
f9234633 1691 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
7359d482
PZ		 1692 if (speed == HPRT0_SPD_HIGH_SPEED)
1693 port_status |= USB_PORT_STAT_HIGH_SPEED;
1694 else if (speed == HPRT0_SPD_LOW_SPEED)
1695 port_status |= USB_PORT_STAT_LOW_SPEED;
1696
1697 if (hprt0 & HPRT0_TSTCTL_MASK)
1698 port_status |= USB_PORT_STAT_TEST;
1699 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1700
b8313417 1701 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
7359d482
PZ		 1702 *(__le32 *)buf = cpu_to_le32(port_status);
1703 break;
1704
1705 case SetHubFeature:
1706 dev_dbg(hsotg->dev, "SetHubFeature\n");
1707 /* No HUB features supported */
1708 break;
1709
1710 case SetPortFeature:
1711 dev_dbg(hsotg->dev, "SetPortFeature\n");
1712 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1713 goto error;
1714
1715 if (!hsotg->flags.b.port_connect_status) {
1716 /*
1717 * The port is disconnected, which means the core is
1718 * either in device mode or it soon will be. Just
1719 * return without doing anything since the port
1720 * register can't be written if the core is in device
1721 * mode.
1722 */
1723 break;
1724 }
1725
1726 switch (wvalue) {
1727 case USB_PORT_FEAT_SUSPEND:
1728 dev_dbg(hsotg->dev,
1729 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1730 if (windex != hsotg->otg_port)
1731 goto error;
1732 dwc2_port_suspend(hsotg, windex);
1733 break;
1734
1735 case USB_PORT_FEAT_POWER:
1736 dev_dbg(hsotg->dev,
1737 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1738 hprt0 = dwc2_read_hprt0(hsotg);
1739 hprt0 |= HPRT0_PWR;
1740 writel(hprt0, hsotg->regs + HPRT0);
1741 break;
1742
1743 case USB_PORT_FEAT_RESET:
1744 hprt0 = dwc2_read_hprt0(hsotg);
1745 dev_dbg(hsotg->dev,
1746 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1747 pcgctl = readl(hsotg->regs + PCGCTL);
1748 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1749 writel(pcgctl, hsotg->regs + PCGCTL);
1750 /* ??? Original driver does this */
1751 writel(0, hsotg->regs + PCGCTL);
1752
1753 hprt0 = dwc2_read_hprt0(hsotg);
1754 /* Clear suspend bit if resetting from suspend state */
1755 hprt0 &= ~HPRT0_SUSP;
1756
1757 /*
1758 * When B-Host the Port reset bit is set in the Start
1759 * HCD Callback function, so that the reset is started
1760 * within 1ms of the HNP success interrupt
1761 */
1762 if (!dwc2_hcd_is_b_host(hsotg)) {
1763 hprt0 |= HPRT0_PWR | HPRT0_RST;
1764 dev_dbg(hsotg->dev,
1765 "In host mode, hprt0=%08x\n", hprt0);
1766 writel(hprt0, hsotg->regs + HPRT0);
1767 }
1768
1769 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1770 usleep_range(50000, 70000);
1771 hprt0 &= ~HPRT0_RST;
1772 writel(hprt0, hsotg->regs + HPRT0);
1773 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1774 break;
1775
1776 case USB_PORT_FEAT_INDICATOR:
1777 dev_dbg(hsotg->dev,
1778 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1779 /* Not supported */
1780 break;
1781
1782 default:
1783 retval = -EINVAL;
1784 dev_err(hsotg->dev,
1785 "SetPortFeature %1xh unknown or unsupported\n",
1786 wvalue);
1787 break;
1788 }
1789 break;
1790
1791 default:
1792error:
1793 retval = -EINVAL;
1794 dev_dbg(hsotg->dev,
1795 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1796 typereq, windex, wvalue);
1797 break;
1798 }
1799
1800 return retval;
1801}
1802
1803static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1804{
1805 int retval;
1806
7359d482
PZ		 1807 if (port != 1)
1808 return -EINVAL;
1809
1810 retval = (hsotg->flags.b.port_connect_status_change ||
1811 hsotg->flags.b.port_reset_change ||
1812 hsotg->flags.b.port_enable_change ||
1813 hsotg->flags.b.port_suspend_change ||
1814 hsotg->flags.b.port_over_current_change);
1815
1816 if (retval) {
1817 dev_dbg(hsotg->dev,
1818 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1819 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1820 hsotg->flags.b.port_connect_status_change);
1821 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1822 hsotg->flags.b.port_reset_change);
1823 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1824 hsotg->flags.b.port_enable_change);
1825 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1826 hsotg->flags.b.port_suspend_change);
1827 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1828 hsotg->flags.b.port_over_current_change);
1829 }
1830
1831 return retval;
1832}
1833
1834int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1835{
1836 u32 hfnum = readl(hsotg->regs + HFNUM);
1837
1838#ifdef DWC2_DEBUG_SOF
1839 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
d6ec53e0 1840 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
7359d482 1841#endif
d6ec53e0 1842 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
7359d482
PZ		 1843}
1844
1845int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1846{
6bf2e2a5 1847 return hsotg->op_state == OTG_STATE_B_HOST;
7359d482
PZ		 1848}
1849
1850static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1851 int iso_desc_count,
1852 gfp_t mem_flags)
1853{
1854 struct dwc2_hcd_urb *urb;
1855 u32 size = sizeof(*urb) + iso_desc_count *
1856 sizeof(struct dwc2_hcd_iso_packet_desc);
1857
1858 urb = kzalloc(size, mem_flags);
1859 if (urb)
1860 urb->packet_count = iso_desc_count;
1861 return urb;
1862}
1863
1864static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1865 struct dwc2_hcd_urb *urb, u8 dev_addr,
1866 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1867{
b49977a6
MK		 1868 if (dbg_perio() ||
1869 ep_type == USB_ENDPOINT_XFER_BULK ||
1870 ep_type == USB_ENDPOINT_XFER_CONTROL)
1871 dev_vdbg(hsotg->dev,
1872 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1873 dev_addr, ep_num, ep_dir, ep_type, mps);
7359d482
PZ		 1874 urb->pipe_info.dev_addr = dev_addr;
1875 urb->pipe_info.ep_num = ep_num;
1876 urb->pipe_info.pipe_type = ep_type;
1877 urb->pipe_info.pipe_dir = ep_dir;
1878 urb->pipe_info.mps = mps;
1879}
1880
1881/*
1882 * NOTE: This function will be removed once the peripheral controller code
1883 * is integrated and the driver is stable
1884 */
1885void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1886{
1887#ifdef DEBUG
1888 struct dwc2_host_chan *chan;
1889 struct dwc2_hcd_urb *urb;
1890 struct dwc2_qtd *qtd;
1891 int num_channels;
1892 u32 np_tx_status;
1893 u32 p_tx_status;
1894 int i;
1895
1896 num_channels = hsotg->core_params->host_channels;
1897 dev_dbg(hsotg->dev, "\n");
1898 dev_dbg(hsotg->dev,
1899 "************************************************************\n");
1900 dev_dbg(hsotg->dev, "HCD State:\n");
1901 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1902
1903 for (i = 0; i < num_channels; i++) {
1904 chan = hsotg->hc_ptr_array[i];
1905 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1906 dev_dbg(hsotg->dev,
1907 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1908 chan->dev_addr, chan->ep_num, chan->ep_is_in);
1909 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1910 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1911 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1912 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1913 chan->data_pid_start);
1914 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1915 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1916 chan->xfer_started);
1917 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1918 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1919 (unsigned long)chan->xfer_dma);
1920 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1921 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1922 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1923 chan->halt_on_queue);
1924 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1925 chan->halt_pending);
1926 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1927 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1928 dev_dbg(hsotg->dev, " complete_split: %d\n",
1929 chan->complete_split);
1930 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
1931 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
1932 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
1933 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
1934 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
1935
1936 if (chan->xfer_started) {
1937 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1938
1939 hfnum = readl(hsotg->regs + HFNUM);
1940 hcchar = readl(hsotg->regs + HCCHAR(i));
1941 hctsiz = readl(hsotg->regs + HCTSIZ(i));
1942 hcint = readl(hsotg->regs + HCINT(i));
1943 hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1944 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
1945 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
1946 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
1947 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
1948 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
1949 }
1950
1951 if (!(chan->xfer_started && chan->qh))
1952 continue;
1953
1954 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1955 if (!qtd->in_process)
1956 break;
1957 urb = qtd->urb;
1958 dev_dbg(hsotg->dev, " URB Info:\n");
1959 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
1960 qtd, urb);
1961 if (urb) {
1962 dev_dbg(hsotg->dev,
1963 " Dev: %d, EP: %d %s\n",
1964 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1965 dwc2_hcd_get_ep_num(&urb->pipe_info),
1966 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1967 "IN" : "OUT");
1968 dev_dbg(hsotg->dev,
1969 " Max packet size: %d\n",
1970 dwc2_hcd_get_mps(&urb->pipe_info));
1971 dev_dbg(hsotg->dev,
1972 " transfer_buffer: %p\n",
1973 urb->buf);
157dfaac
PZ		 1974 dev_dbg(hsotg->dev,
1975 " transfer_dma: %08lx\n",
1976 (unsigned long)urb->dma);
7359d482
PZ		 1977 dev_dbg(hsotg->dev,
1978 " transfer_buffer_length: %d\n",
1979 urb->length);
1980 dev_dbg(hsotg->dev, " actual_length: %d\n",
1981 urb->actual_length);
1982 }
1983 }
1984 }
1985
1986 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
1987 hsotg->non_periodic_channels);
1988 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
1989 hsotg->periodic_channels);
1990 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
1991 np_tx_status = readl(hsotg->regs + GNPTXSTS);
1992 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
d6ec53e0 1993 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 1994 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
d6ec53e0 1995 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
7359d482
PZ		 1996 p_tx_status = readl(hsotg->regs + HPTXSTS);
1997 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
d6ec53e0 1998 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 1999 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
d6ec53e0 2000 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
7359d482
PZ		 2001 dwc2_hcd_dump_frrem(hsotg);
2002 dwc2_dump_global_registers(hsotg);
2003 dwc2_dump_host_registers(hsotg);
2004 dev_dbg(hsotg->dev,
2005 "************************************************************\n");
2006 dev_dbg(hsotg->dev, "\n");
2007#endif
2008}
2009
2010/*
2011 * NOTE: This function will be removed once the peripheral controller code
2012 * is integrated and the driver is stable
2013 */
2014void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2015{
2016#ifdef DWC2_DUMP_FRREM
2017 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2018 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2019 hsotg->frrem_samples, hsotg->frrem_accum,
2020 hsotg->frrem_samples > 0 ?
2021 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2022 dev_dbg(hsotg->dev, "\n");
2023 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2024 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2025 hsotg->hfnum_7_samples,
2026 hsotg->hfnum_7_frrem_accum,
2027 hsotg->hfnum_7_samples > 0 ?
2028 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2029 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2030 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2031 hsotg->hfnum_0_samples,
2032 hsotg->hfnum_0_frrem_accum,
2033 hsotg->hfnum_0_samples > 0 ?
2034 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2035 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2036 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2037 hsotg->hfnum_other_samples,
2038 hsotg->hfnum_other_frrem_accum,
2039 hsotg->hfnum_other_samples > 0 ?
2040 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2041 0);
2042 dev_dbg(hsotg->dev, "\n");
2043 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2044 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2045 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2046 hsotg->hfnum_7_samples_a > 0 ?
2047 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2048 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2049 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2050 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2051 hsotg->hfnum_0_samples_a > 0 ?
2052 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2053 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2054 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2055 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2056 hsotg->hfnum_other_samples_a > 0 ?
2057 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2058 : 0);
2059 dev_dbg(hsotg->dev, "\n");
2060 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2061 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2062 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2063 hsotg->hfnum_7_samples_b > 0 ?
2064 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2065 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2066 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2067 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2068 (hsotg->hfnum_0_samples_b > 0) ?
2069 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2070 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2071 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2072 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2073 (hsotg->hfnum_other_samples_b > 0) ?
2074 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2075 : 0);
2076#endif
2077}
2078
2079struct wrapper_priv_data {
2080 struct dwc2_hsotg *hsotg;
2081};
2082
2083/* Gets the dwc2_hsotg from a usb_hcd */
2084static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2085{
2086 struct wrapper_priv_data *p;
2087
2088 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2089 return p->hsotg;
2090}
2091
2092static int _dwc2_hcd_start(struct usb_hcd *hcd);
2093
2094void dwc2_host_start(struct dwc2_hsotg *hsotg)
2095{
2096 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2097
2098 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2099 _dwc2_hcd_start(hcd);
2100}
2101
2102void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2103{
2104 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2105
2106 hcd->self.is_b_host = 0;
2107}
2108
2109void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2110 int *hub_port)
2111{
2112 struct urb *urb = context;
2113
2114 if (urb->dev->tt)
2115 *hub_addr = urb->dev->tt->hub->devnum;
2116 else
2117 *hub_addr = 0;
2118 *hub_port = urb->dev->ttport;
2119}
2120
2121int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2122{
2123 struct urb *urb = context;
2124
2125 return urb->dev->speed;
2126}
2127
2128static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2129 struct urb *urb)
2130{
2131 struct usb_bus *bus = hcd_to_bus(hcd);
2132
2133 if (urb->interval)
2134 bus->bandwidth_allocated += bw / urb->interval;
2135 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2136 bus->bandwidth_isoc_reqs++;
2137 else
2138 bus->bandwidth_int_reqs++;
2139}
2140
2141static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2142 struct urb *urb)
2143{
2144 struct usb_bus *bus = hcd_to_bus(hcd);
2145
2146 if (urb->interval)
2147 bus->bandwidth_allocated -= bw / urb->interval;
2148 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2149 bus->bandwidth_isoc_reqs--;
2150 else
2151 bus->bandwidth_int_reqs--;
2152}
2153
2154/*
2155 * Sets the final status of an URB and returns it to the upper layer. Any
2156 * required cleanup of the URB is performed.
2157 *
2158 * Must be called with interrupt disabled and spinlock held
2159 */
0d012b98
PZ		 2160void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2161 int status)
7359d482 2162{
0d012b98 2163 struct urb *urb;
7359d482
PZ		 2164 int i;
2165
0d012b98
PZ		 2166 if (!qtd) {
2167 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
7359d482
PZ		 2168 return;
2169 }
2170
0d012b98
PZ		 2171 if (!qtd->urb) {
2172 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
7359d482
PZ		 2173 return;
2174 }
2175
0d012b98
PZ		 2176 urb = qtd->urb->priv;
2177 if (!urb) {
2178 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2179 return;
2180 }
2181
2182 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
7359d482 2183
b49977a6
MK		 2184 if (dbg_urb(urb))
2185 dev_vdbg(hsotg->dev,
2186 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2187 __func__, urb, usb_pipedevice(urb->pipe),
2188 usb_pipeendpoint(urb->pipe),
2189 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2190 urb->actual_length);
7359d482 2191
b49977a6 2192 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
7359d482
PZ		 2193 for (i = 0; i < urb->number_of_packets; i++)
2194 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2195 i, urb->iso_frame_desc[i].status);
2196 }
2197
2198 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
0d012b98 2199 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
7359d482
PZ		 2200 for (i = 0; i < urb->number_of_packets; ++i) {
2201 urb->iso_frame_desc[i].actual_length =
2202 dwc2_hcd_urb_get_iso_desc_actual_length(
0d012b98 2203 qtd->urb, i);
7359d482 2204 urb->iso_frame_desc[i].status =
0d012b98 2205 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
7359d482
PZ		 2206 }
2207 }
2208
2209 urb->status = status;
7359d482
PZ		 2210 if (!status) {
2211 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2212 urb->actual_length < urb->transfer_buffer_length)
2213 urb->status = -EREMOTEIO;
2214 }
2215
2216 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2217 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2218 struct usb_host_endpoint *ep = urb->ep;
2219
2220 if (ep)
2221 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2222 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2223 urb);
2224 }
2225
c9e1c907 2226 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
0d012b98
PZ		 2227 urb->hcpriv = NULL;
2228 kfree(qtd->urb);
2229 qtd->urb = NULL;
7359d482
PZ		 2230
2231 spin_unlock(&hsotg->lock);
2232 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2233 spin_lock(&hsotg->lock);
2234}
2235
2236/*
2237 * Work queue function for starting the HCD when A-Cable is connected
2238 */
2239static void dwc2_hcd_start_func(struct work_struct *work)
2240{
2241 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2242 start_work.work);
2243
2244 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2245 dwc2_host_start(hsotg);
2246}
2247
2248/*
2249 * Reset work queue function
2250 */
2251static void dwc2_hcd_reset_func(struct work_struct *work)
2252{
2253 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2254 reset_work.work);
2255 u32 hprt0;
2256
2257 dev_dbg(hsotg->dev, "USB RESET function called\n");
2258 hprt0 = dwc2_read_hprt0(hsotg);
2259 hprt0 &= ~HPRT0_RST;
2260 writel(hprt0, hsotg->regs + HPRT0);
2261 hsotg->flags.b.port_reset_change = 1;
2262}
2263
2264/*
2265 * =========================================================================
2266 * Linux HC Driver Functions
2267 * =========================================================================
2268 */
2269
2270/*
2271 * Initializes the DWC_otg controller and its root hub and prepares it for host
2272 * mode operation. Activates the root port. Returns 0 on success and a negative
2273 * error code on failure.
2274 */
2275static int _dwc2_hcd_start(struct usb_hcd *hcd)
2276{
2277 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2278 struct usb_bus *bus = hcd_to_bus(hcd);
2279 unsigned long flags;
2280
2281 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2282
2283 spin_lock_irqsave(&hsotg->lock, flags);
2284
2285 hcd->state = HC_STATE_RUNNING;
2286
2287 if (dwc2_is_device_mode(hsotg)) {
2288 spin_unlock_irqrestore(&hsotg->lock, flags);
2289 return 0; /* why 0 ?? */
2290 }
2291
2292 dwc2_hcd_reinit(hsotg);
2293
2294 /* Initialize and connect root hub if one is not already attached */
2295 if (bus->root_hub) {
2296 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2297 /* Inform the HUB driver to resume */
2298 usb_hcd_resume_root_hub(hcd);
2299 }
2300
2301 spin_unlock_irqrestore(&hsotg->lock, flags);
2302 return 0;
2303}
2304
2305/*
2306 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2307 * stopped.
2308 */
2309static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2310{
2311 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2312 unsigned long flags;
2313
2314 spin_lock_irqsave(&hsotg->lock, flags);
2315 dwc2_hcd_stop(hsotg);
2316 spin_unlock_irqrestore(&hsotg->lock, flags);
2317
2318 usleep_range(1000, 3000);
2319}
2320
99a65798
GH		 2321static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2322{
2323 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2324
2325 hsotg->lx_state = DWC2_L2;
2326 return 0;
2327}
2328
2329static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2330{
2331 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2332
2333 hsotg->lx_state = DWC2_L0;
2334 return 0;
2335}
2336
7359d482
PZ		 2337/* Returns the current frame number */
2338static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2339{
2340 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2341
2342 return dwc2_hcd_get_frame_number(hsotg);
2343}
2344
2345static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2346 char *fn_name)
2347{
2348#ifdef VERBOSE_DEBUG
2349 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2350 char *pipetype;
2351 char *speed;
2352
2353 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2354 dev_vdbg(hsotg->dev, " Device address: %d\n",
2355 usb_pipedevice(urb->pipe));
2356 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2357 usb_pipeendpoint(urb->pipe),
2358 usb_pipein(urb->pipe) ? "IN" : "OUT");
2359
2360 switch (usb_pipetype(urb->pipe)) {
2361 case PIPE_CONTROL:
2362 pipetype = "CONTROL";
2363 break;
2364 case PIPE_BULK:
2365 pipetype = "BULK";
2366 break;
2367 case PIPE_INTERRUPT:
2368 pipetype = "INTERRUPT";
2369 break;
2370 case PIPE_ISOCHRONOUS:
2371 pipetype = "ISOCHRONOUS";
2372 break;
2373 default:
2374 pipetype = "UNKNOWN";
2375 break;
2376 }
2377
2378 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2379 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2380 "IN" : "OUT");
2381
2382 switch (urb->dev->speed) {
2383 case USB_SPEED_HIGH:
2384 speed = "HIGH";
2385 break;
2386 case USB_SPEED_FULL:
2387 speed = "FULL";
2388 break;
2389 case USB_SPEED_LOW:
2390 speed = "LOW";
2391 break;
2392 default:
2393 speed = "UNKNOWN";
2394 break;
2395 }
2396
2397 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2398 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2399 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2400 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2401 urb->transfer_buffer_length);
157dfaac
PZ		 2402 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2403 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2404 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2405 urb->setup_packet, (unsigned long)urb->setup_dma);
7359d482
PZ		 2406 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2407
2408 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2409 int i;
2410
2411 for (i = 0; i < urb->number_of_packets; i++) {
2412 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2413 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2414 urb->iso_frame_desc[i].offset,
2415 urb->iso_frame_desc[i].length);
2416 }
2417 }
2418#endif
2419}
2420
2421/*
2422 * Starts processing a USB transfer request specified by a USB Request Block
2423 * (URB). mem_flags indicates the type of memory allocation to use while
2424 * processing this URB.
2425 */
2426static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2427 gfp_t mem_flags)
2428{
2429 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2430 struct usb_host_endpoint *ep = urb->ep;
2431 struct dwc2_hcd_urb *dwc2_urb;
2432 int i;
c9e1c907 2433 int retval;
7359d482 2434 int alloc_bandwidth = 0;
7359d482
PZ		 2435 u8 ep_type = 0;
2436 u32 tflags = 0;
2437 void *buf;
2438 unsigned long flags;
2439
b49977a6
MK		 2440 if (dbg_urb(urb)) {
2441 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2442 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2443 }
7359d482
PZ		 2444
2445 if (ep == NULL)
2446 return -EINVAL;
2447
2448 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2449 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2450 spin_lock_irqsave(&hsotg->lock, flags);
2451 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2452 alloc_bandwidth = 1;
2453 spin_unlock_irqrestore(&hsotg->lock, flags);
2454 }
2455
2456 switch (usb_pipetype(urb->pipe)) {
2457 case PIPE_CONTROL:
2458 ep_type = USB_ENDPOINT_XFER_CONTROL;
2459 break;
2460 case PIPE_ISOCHRONOUS:
2461 ep_type = USB_ENDPOINT_XFER_ISOC;
2462 break;
2463 case PIPE_BULK:
2464 ep_type = USB_ENDPOINT_XFER_BULK;
2465 break;
2466 case PIPE_INTERRUPT:
2467 ep_type = USB_ENDPOINT_XFER_INT;
2468 break;
2469 default:
2470 dev_warn(hsotg->dev, "Wrong ep type\n");
2471 }
2472
2473 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2474 mem_flags);
2475 if (!dwc2_urb)
2476 return -ENOMEM;
2477
2478 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2479 usb_pipeendpoint(urb->pipe), ep_type,
2480 usb_pipein(urb->pipe),
2481 usb_maxpacket(urb->dev, urb->pipe,
2482 !(usb_pipein(urb->pipe))));
2483
2484 buf = urb->transfer_buffer;
25a49445 2485
7359d482 2486 if (hcd->self.uses_dma) {
25a49445
PZ		 2487 if (!buf && (urb->transfer_dma & 3)) {
2488 dev_err(hsotg->dev,
2489 "%s: unaligned transfer with no transfer_buffer",
2490 __func__);
2491 retval = -EINVAL;
33ad261a 2492 goto fail0;
25a49445 2493 }
7359d482
PZ		 2494 }
2495
2496 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2497 tflags |= URB_GIVEBACK_ASAP;
2498 if (urb->transfer_flags & URB_ZERO_PACKET)
2499 tflags |= URB_SEND_ZERO_PACKET;
2500
2501 dwc2_urb->priv = urb;
2502 dwc2_urb->buf = buf;
2503 dwc2_urb->dma = urb->transfer_dma;
2504 dwc2_urb->length = urb->transfer_buffer_length;
2505 dwc2_urb->setup_packet = urb->setup_packet;
2506 dwc2_urb->setup_dma = urb->setup_dma;
2507 dwc2_urb->flags = tflags;
2508 dwc2_urb->interval = urb->interval;
2509 dwc2_urb->status = -EINPROGRESS;
2510
2511 for (i = 0; i < urb->number_of_packets; ++i)
2512 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2513 urb->iso_frame_desc[i].offset,
2514 urb->iso_frame_desc[i].length);
2515
2516 urb->hcpriv = dwc2_urb;
c9e1c907
PZ		 2517
2518 spin_lock_irqsave(&hsotg->lock, flags);
2519 retval = usb_hcd_link_urb_to_ep(hcd, urb);
c9e1c907
PZ		 2520 if (retval)
2521 goto fail1;
2522
2523 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags);
2524 if (retval)
2525 goto fail2;
2526
2527 if (alloc_bandwidth) {
c9e1c907
PZ		 2528 dwc2_allocate_bus_bandwidth(hcd,
2529 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2530 urb);
7359d482
PZ		 2531 }
2532
33ad261a
GH		 2533 spin_unlock_irqrestore(&hsotg->lock, flags);
2534
c9e1c907
PZ		 2535 return 0;
2536
2537fail2:
c9e1c907
PZ		 2538 dwc2_urb->priv = NULL;
2539 usb_hcd_unlink_urb_from_ep(hcd, urb);
c9e1c907 2540fail1:
33ad261a 2541 spin_unlock_irqrestore(&hsotg->lock, flags);
c9e1c907 2542 urb->hcpriv = NULL;
33ad261a 2543fail0:
c9e1c907
PZ		 2544 kfree(dwc2_urb);
2545
7359d482
PZ		 2546 return retval;
2547}
2548
2549/*
2550 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2551 */
2552static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2553 int status)
2554{
2555 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
c9e1c907 2556 int rc;
7359d482
PZ		 2557 unsigned long flags;
2558
2559 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2560 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2561
2562 spin_lock_irqsave(&hsotg->lock, flags);
2563
c9e1c907
PZ		 2564 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2565 if (rc)
2566 goto out;
2567
7359d482
PZ		 2568 if (!urb->hcpriv) {
2569 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2570 goto out;
2571 }
2572
2573 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2574
c9e1c907
PZ		 2575 usb_hcd_unlink_urb_from_ep(hcd, urb);
2576
7359d482
PZ		 2577 kfree(urb->hcpriv);
2578 urb->hcpriv = NULL;
2579
2580 /* Higher layer software sets URB status */
2581 spin_unlock(&hsotg->lock);
2582 usb_hcd_giveback_urb(hcd, urb, status);
2583 spin_lock(&hsotg->lock);
2584
2585 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2586 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2587out:
2588 spin_unlock_irqrestore(&hsotg->lock, flags);
2589
2590 return rc;
2591}
2592
2593/*
2594 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2595 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2596 * must already be dequeued.
2597 */
2598static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2599 struct usb_host_endpoint *ep)
2600{
2601 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2602
2603 dev_dbg(hsotg->dev,
2604 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2605 ep->desc.bEndpointAddress, ep->hcpriv);
2606 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2607}
2608
2609/*
2610 * Resets endpoint specific parameter values, in current version used to reset
2611 * the data toggle (as a WA). This function can be called from usb_clear_halt
2612 * routine.
2613 */
2614static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2615 struct usb_host_endpoint *ep)
2616{
2617 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482
PZ		 2618 unsigned long flags;
2619
2620 dev_dbg(hsotg->dev,
2621 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2622 ep->desc.bEndpointAddress);
2623
7359d482 2624 spin_lock_irqsave(&hsotg->lock, flags);
7359d482 2625 dwc2_hcd_endpoint_reset(hsotg, ep);
7359d482
PZ		 2626 spin_unlock_irqrestore(&hsotg->lock, flags);
2627}
2628
2629/*
2630 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2631 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2632 * interrupt.
2633 *
2634 * This function is called by the USB core when an interrupt occurs
2635 */
2636static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2637{
2638 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482 2639
ca18f4a6 2640 return dwc2_handle_hcd_intr(hsotg);
7359d482
PZ		 2641}
2642
2643/*
2644 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2645 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2646 * is the status change indicator for the single root port. Returns 1 if either
2647 * change indicator is 1, otherwise returns 0.
2648 */
2649static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2650{
2651 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2652
2653 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2654 return buf[0] != 0;
2655}
2656
2657/* Handles hub class-specific requests */
2658static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2659 u16 windex, char *buf, u16 wlength)
2660{
2661 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2662 wvalue, windex, buf, wlength);
2663 return retval;
2664}
2665
2666/* Handles hub TT buffer clear completions */
2667static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2668 struct usb_host_endpoint *ep)
2669{
2670 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2671 struct dwc2_qh *qh;
2672 unsigned long flags;
2673
2674 qh = ep->hcpriv;
2675 if (!qh)
2676 return;
2677
2678 spin_lock_irqsave(&hsotg->lock, flags);
2679 qh->tt_buffer_dirty = 0;
2680
2681 if (hsotg->flags.b.port_connect_status)
2682 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2683
2684 spin_unlock_irqrestore(&hsotg->lock, flags);
2685}
2686
2687static struct hc_driver dwc2_hc_driver = {
2688 .description = "dwc2_hsotg",
2689 .product_desc = "DWC OTG Controller",
2690 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2691
2692 .irq = _dwc2_hcd_irq,
2693 .flags = HCD_MEMORY | HCD_USB2,
2694
2695 .start = _dwc2_hcd_start,
2696 .stop = _dwc2_hcd_stop,
2697 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2698 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2699 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2700 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2701 .get_frame_number = _dwc2_hcd_get_frame_number,
2702
2703 .hub_status_data = _dwc2_hcd_hub_status_data,
2704 .hub_control = _dwc2_hcd_hub_control,
2705 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
99a65798
GH		 2706
2707 .bus_suspend = _dwc2_hcd_suspend,
2708 .bus_resume = _dwc2_hcd_resume,
7359d482
PZ		 2709};
2710
2711/*
2712 * Frees secondary storage associated with the dwc2_hsotg structure contained
2713 * in the struct usb_hcd field
2714 */
2715static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2716{
2717 u32 ahbcfg;
2718 u32 dctl;
2719 int i;
2720
2721 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2722
2723 /* Free memory for QH/QTD lists */
2724 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2725 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2726 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2727 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2728 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2729 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2730
2731 /* Free memory for the host channels */
2732 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2733 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2734
2735 if (chan != NULL) {
2736 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2737 i, chan);
2738 hsotg->hc_ptr_array[i] = NULL;
2739 kfree(chan);
2740 }
2741 }
2742
2743 if (hsotg->core_params->dma_enable > 0) {
2744 if (hsotg->status_buf) {
2745 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2746 hsotg->status_buf,
2747 hsotg->status_buf_dma);
2748 hsotg->status_buf = NULL;
2749 }
2750 } else {
2751 kfree(hsotg->status_buf);
2752 hsotg->status_buf = NULL;
2753 }
2754
2755 ahbcfg = readl(hsotg->regs + GAHBCFG);
2756
2757 /* Disable all interrupts */
2758 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2759 writel(ahbcfg, hsotg->regs + GAHBCFG);
2760 writel(0, hsotg->regs + GINTMSK);
2761
9badec2f 2762 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
7359d482
PZ		 2763 dctl = readl(hsotg->regs + DCTL);
2764 dctl |= DCTL_SFTDISCON;
2765 writel(dctl, hsotg->regs + DCTL);
2766 }
2767
2768 if (hsotg->wq_otg) {
2769 if (!cancel_work_sync(&hsotg->wf_otg))
2770 flush_workqueue(hsotg->wq_otg);
2771 destroy_workqueue(hsotg->wq_otg);
2772 }
2773
7359d482
PZ		 2774 del_timer(&hsotg->wkp_timer);
2775}
2776
2777static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2778{
2779 /* Turn off all host-specific interrupts */
2780 dwc2_disable_host_interrupts(hsotg);
2781
2782 dwc2_hcd_free(hsotg);
2783}
2784
7359d482
PZ		 2785/*
2786 * Initializes the HCD. This function allocates memory for and initializes the
2787 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2788 * USB bus with the core and calls the hc_driver->start() function. It returns
2789 * a negative error on failure.
2790 */
ecb176c6 2791int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
7359d482
PZ		 2792{
2793 struct usb_hcd *hcd;
2794 struct dwc2_host_chan *channel;
9badec2f 2795 u32 hcfg;
7359d482 2796 int i, num_channels;
9badec2f 2797 int retval;
7359d482 2798
f5500ecc
DN		 2799 if (usb_disabled())
2800 return -ENODEV;
2801
e62662c7 2802 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
7359d482 2803
9badec2f 2804 retval = -ENOMEM;
7359d482
PZ		 2805
2806 hcfg = readl(hsotg->regs + HCFG);
2807 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
7359d482
PZ		 2808
2809#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2810 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2811 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2812 if (!hsotg->frame_num_array)
ba0e60d1 2813 goto error1;
7359d482
PZ		 2814 hsotg->last_frame_num_array = kzalloc(
2815 sizeof(*hsotg->last_frame_num_array) *
2816 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2817 if (!hsotg->last_frame_num_array)
ba0e60d1 2818 goto error1;
7359d482
PZ		 2819 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2820#endif
2821
a0112f48
MK		 2822 /* Check if the bus driver or platform code has setup a dma_mask */
2823 if (hsotg->core_params->dma_enable > 0 &&
2824 hsotg->dev->dma_mask == NULL) {
2825 dev_warn(hsotg->dev,
2826 "dma_mask not set, disabling DMA\n");
2827 hsotg->core_params->dma_enable = 0;
2828 hsotg->core_params->dma_desc_enable = 0;
2829 }
2830
ba0e60d1
PZ		 2831 /* Set device flags indicating whether the HCD supports DMA */
2832 if (hsotg->core_params->dma_enable > 0) {
30885313
PZ		 2833 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2834 dev_warn(hsotg->dev, "can't set DMA mask\n");
25a49445
PZ		 2835 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2836 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
ba0e60d1
PZ		 2837 }
2838
2839 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2840 if (!hcd)
2841 goto error1;
2842
7de76ee1
MK		 2843 if (hsotg->core_params->dma_enable <= 0)
2844 hcd->self.uses_dma = 0;
2845
ba0e60d1
PZ		 2846 hcd->has_tt = 1;
2847
ba0e60d1
PZ		 2848 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2849 hsotg->priv = hcd;
2850
7359d482
PZ		 2851 /*
2852 * Disable the global interrupt until all the interrupt handlers are
2853 * installed
2854 */
2855 dwc2_disable_global_interrupts(hsotg);
2856
6706c721
MK		 2857 /* Initialize the DWC_otg core, and select the Phy type */
2858 retval = dwc2_core_init(hsotg, true, irq);
2859 if (retval)
2860 goto error2;
2861
7359d482 2862 /* Create new workqueue and init work */
53510352 2863 retval = -ENOMEM;
050232a7 2864 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
7359d482
PZ		 2865 if (!hsotg->wq_otg) {
2866 dev_err(hsotg->dev, "Failed to create workqueue\n");
2867 goto error2;
2868 }
2869 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2870
7359d482
PZ		 2871 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2872 (unsigned long)hsotg);
2873
2874 /* Initialize the non-periodic schedule */
2875 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2876 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2877
2878 /* Initialize the periodic schedule */
2879 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2880 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2881 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2882 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2883
2884 /*
2885 * Create a host channel descriptor for each host channel implemented
2886 * in the controller. Initialize the channel descriptor array.
2887 */
2888 INIT_LIST_HEAD(&hsotg->free_hc_list);
2889 num_channels = hsotg->core_params->host_channels;
2890 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2891
2892 for (i = 0; i < num_channels; i++) {
2893 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2894 if (channel == NULL)
2895 goto error3;
2896 channel->hc_num = i;
2897 hsotg->hc_ptr_array[i] = channel;
2898 }
2899
20f2eb9c
DC		 2900 if (hsotg->core_params->uframe_sched > 0)
2901 dwc2_hcd_init_usecs(hsotg);
2902
7359d482
PZ		 2903 /* Initialize hsotg start work */
2904 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2905
2906 /* Initialize port reset work */
2907 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2908
2909 /*
2910 * Allocate space for storing data on status transactions. Normally no
2911 * data is sent, but this space acts as a bit bucket. This must be
2912 * done after usb_add_hcd since that function allocates the DMA buffer
2913 * pool.
2914 */
2915 if (hsotg->core_params->dma_enable > 0)
2916 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2917 DWC2_HCD_STATUS_BUF_SIZE,
2918 &hsotg->status_buf_dma, GFP_KERNEL);
2919 else
2920 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2921 GFP_KERNEL);
2922
2923 if (!hsotg->status_buf)
2924 goto error3;
2925
2926 hsotg->otg_port = 1;
2927 hsotg->frame_list = NULL;
2928 hsotg->frame_list_dma = 0;
2929 hsotg->periodic_qh_count = 0;
2930
2931 /* Initiate lx_state to L3 disconnected state */
2932 hsotg->lx_state = DWC2_L3;
2933
2934 hcd->self.otg_port = hsotg->otg_port;
2935
2936 /* Don't support SG list at this point */
2937 hcd->self.sg_tablesize = 0;
2938
9df4ceac
MYK		 2939 if (!IS_ERR_OR_NULL(hsotg->uphy))
2940 otg_set_host(hsotg->uphy->otg, &hcd->self);
2941
7359d482
PZ		 2942 /*
2943 * Finish generic HCD initialization and start the HCD. This function
2944 * allocates the DMA buffer pool, registers the USB bus, requests the
2945 * IRQ line, and calls hcd_start method.
2946 */
66513f49 2947 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
7359d482
PZ		 2948 if (retval < 0)
2949 goto error3;
2950
3c9740a1
PC		 2951 device_wakeup_enable(hcd->self.controller);
2952
7359d482
PZ		 2953 dwc2_hcd_dump_state(hsotg);
2954
2955 dwc2_enable_global_interrupts(hsotg);
2956
2957 return 0;
2958
2959error3:
2960 dwc2_hcd_release(hsotg);
2961error2:
ba0e60d1
PZ		 2962 usb_put_hcd(hcd);
2963error1:
7359d482
PZ		 2964 kfree(hsotg->core_params);
2965
2966#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2967 kfree(hsotg->last_frame_num_array);
2968 kfree(hsotg->frame_num_array);
2969#endif
2970
e62662c7 2971 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
7359d482
PZ		 2972 return retval;
2973}
2974EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2975
2976/*
2977 * Removes the HCD.
2978 * Frees memory and resources associated with the HCD and deregisters the bus.
2979 */
e62662c7 2980void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
7359d482
PZ		 2981{
2982 struct usb_hcd *hcd;
2983
e62662c7 2984 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
7359d482
PZ		 2985
2986 hcd = dwc2_hsotg_to_hcd(hsotg);
e62662c7 2987 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
7359d482
PZ		 2988
2989 if (!hcd) {
e62662c7 2990 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
7359d482
PZ		 2991 __func__);
2992 return;
2993 }
2994
9df4ceac
MYK		 2995 if (!IS_ERR_OR_NULL(hsotg->uphy))
2996 otg_set_host(hsotg->uphy->otg, NULL);
2997
7359d482
PZ		 2998 usb_remove_hcd(hcd);
2999 hsotg->priv = NULL;
3000 dwc2_hcd_release(hsotg);
ba0e60d1 3001 usb_put_hcd(hcd);
7359d482
PZ		 3002
3003#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3004 kfree(hsotg->last_frame_num_array);
3005 kfree(hsotg->frame_num_array);
3006#endif
7359d482
PZ		 3007}
3008EXPORT_SYMBOL_GPL(dwc2_hcd_remove);
Linux kernel - Deliverables
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