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usb: dwc2: host: fix descriptor list address masking
[deliverable/linux.git] / drivers / usb / dwc2 / hcd.c
CommitLineData
7359d482
PZ		 1/*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/spinlock.h>
44#include <linux/interrupt.h>
45#include <linux/dma-mapping.h>
46#include <linux/delay.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57/**
58 * dwc2_dump_channel_info() - Prints the state of a host channel
59 *
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
62 *
63 * Must be called with interrupt disabled and spinlock held
64 *
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
67 */
68static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
70{
71#ifdef VERBOSE_DEBUG
72 int num_channels = hsotg->core_params->host_channels;
73 struct dwc2_qh *qh;
74 u32 hcchar;
75 u32 hcsplt;
76 u32 hctsiz;
77 u32 hc_dma;
78 int i;
79
80 if (chan == NULL)
81 return;
82
95c8bc36
AS		 83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
7359d482
PZ		 87
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
90 hcchar, hcsplt);
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
92 hctsiz, hc_dma);
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
107 qh_list_entry)
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
111 qh_list_entry)
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
116
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
118 }
119#endif /* VERBOSE_DEBUG */
120}
121
122/*
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
125 *
126 * Must be called with interrupt disabled and spinlock held
127 */
128static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
130{
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
133
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
136 qtd_list_entry) {
2e84da6e 137 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
0d012b98 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
7359d482
PZ		 139 }
140 }
141}
142
143static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
145{
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
148 unsigned long flags;
149
150 if (!qh_list->next)
151 /* The list hasn't been initialized yet */
152 return;
153
154 spin_lock_irqsave(&hsotg->lock, flags);
155
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
158
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
161
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
164 qtd_list_entry)
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
166
167 spin_unlock_irqrestore(&hsotg->lock, flags);
168 dwc2_hcd_qh_free(hsotg, qh);
169 spin_lock_irqsave(&hsotg->lock, flags);
170 }
171
172 spin_unlock_irqrestore(&hsotg->lock, flags);
173}
174
175/*
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
180 *
181 * Must be called with interrupt disabled and spinlock held
182 */
183static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
184{
185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
191}
192
193/**
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
195 *
196 * @hsotg: Pointer to struct dwc2_hsotg
197 */
198void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
199{
200 u32 hprt0;
201
202 if (hsotg->op_state == OTG_STATE_B_HOST) {
203 /*
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
206 * least 50ms.
207 */
208 hprt0 = dwc2_read_hprt0(hsotg);
209 hprt0 |= HPRT0_RST;
95c8bc36 210 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 211 }
212
213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 msecs_to_jiffies(50));
215}
216
217/* Must be called with interrupt disabled and spinlock held */
218static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
219{
220 int num_channels = hsotg->core_params->host_channels;
221 struct dwc2_host_chan *channel;
222 u32 hcchar;
223 int i;
224
225 if (hsotg->core_params->dma_enable <= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i = 0; i < num_channels; i++) {
228 channel = hsotg->hc_ptr_array[i];
229 if (!list_empty(&channel->hc_list_entry))
230 continue;
95c8bc36 231 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
7359d482
PZ		 232 if (hcchar & HCCHAR_CHENA) {
233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 hcchar |= HCCHAR_CHDIS;
95c8bc36 235 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
7359d482
PZ		 236 }
237 }
238 }
239
240 for (i = 0; i < num_channels; i++) {
241 channel = hsotg->hc_ptr_array[i];
242 if (!list_empty(&channel->hc_list_entry))
243 continue;
95c8bc36 244 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
7359d482
PZ		 245 if (hcchar & HCCHAR_CHENA) {
246 /* Halt the channel */
247 hcchar |= HCCHAR_CHDIS;
95c8bc36 248 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
7359d482
PZ		 249 }
250
251 dwc2_hc_cleanup(hsotg, channel);
252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
253 /*
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
256 * device disconnects
257 */
258 channel->qh = NULL;
259 }
7252f1bf
VP		 260 /* All channels have been freed, mark them available */
261 if (hsotg->core_params->uframe_sched > 0) {
262 hsotg->available_host_channels =
263 hsotg->core_params->host_channels;
264 } else {
265 hsotg->non_periodic_channels = 0;
266 hsotg->periodic_channels = 0;
267 }
7359d482
PZ		 268}
269
270/**
271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
272 *
273 * @hsotg: Pointer to struct dwc2_hsotg
274 *
275 * Must be called with interrupt disabled and spinlock held
276 */
277void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
278{
279 u32 intr;
280
281 /* Set status flags for the hub driver */
282 hsotg->flags.b.port_connect_status_change = 1;
283 hsotg->flags.b.port_connect_status = 0;
284
285 /*
286 * Shutdown any transfers in process by clearing the Tx FIFO Empty
287 * interrupt mask and status bits and disabling subsequent host
288 * channel interrupts.
289 */
95c8bc36 290 intr = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
95c8bc36 292 dwc2_writel(intr, hsotg->regs + GINTMSK);
7359d482 293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
95c8bc36 294 dwc2_writel(intr, hsotg->regs + GINTSTS);
7359d482
PZ		 295
296 /*
297 * Turn off the vbus power only if the core has transitioned to device
298 * mode. If still in host mode, need to keep power on to detect a
299 * reconnection.
300 */
301 if (dwc2_is_device_mode(hsotg)) {
302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
95c8bc36 304 dwc2_writel(0, hsotg->regs + HPRT0);
7359d482
PZ		 305 }
306
307 dwc2_disable_host_interrupts(hsotg);
308 }
309
310 /* Respond with an error status to all URBs in the schedule */
311 dwc2_kill_all_urbs(hsotg);
312
313 if (dwc2_is_host_mode(hsotg))
314 /* Clean up any host channels that were in use */
315 dwc2_hcd_cleanup_channels(hsotg);
316
317 dwc2_host_disconnect(hsotg);
318}
319
320/**
321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
322 *
323 * @hsotg: Pointer to struct dwc2_hsotg
324 */
325static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
326{
1fb7f12d 327 if (hsotg->bus_suspended) {
7359d482 328 hsotg->flags.b.port_suspend_change = 1;
b46146d5 329 usb_hcd_resume_root_hub(hsotg->priv);
b46146d5 330 }
1fb7f12d
DA		 331
332 if (hsotg->lx_state == DWC2_L1)
333 hsotg->flags.b.port_l1_change = 1;
7359d482
PZ		 334}
335
336/**
337 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
338 *
339 * @hsotg: Pointer to struct dwc2_hsotg
340 *
341 * Must be called with interrupt disabled and spinlock held
342 */
343void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
344{
345 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
346
347 /*
348 * The root hub should be disconnected before this function is called.
349 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
350 * and the QH lists (via ..._hcd_endpoint_disable).
351 */
352
353 /* Turn off all host-specific interrupts */
354 dwc2_disable_host_interrupts(hsotg);
355
356 /* Turn off the vbus power */
357 dev_dbg(hsotg->dev, "PortPower off\n");
95c8bc36 358 dwc2_writel(0, hsotg->regs + HPRT0);
7359d482
PZ		 359}
360
33ad261a 361/* Caller must hold driver lock */
7359d482 362static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
b58e6cee 363 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
b5a468a6 364 struct dwc2_qtd *qtd)
7359d482 365{
7359d482
PZ		 366 u32 intr_mask;
367 int retval;
9f8144c6 368 int dev_speed;
7359d482
PZ		 369
370 if (!hsotg->flags.b.port_connect_status) {
371 /* No longer connected */
372 dev_err(hsotg->dev, "Not connected\n");
373 return -ENODEV;
374 }
375
9f8144c6
NH		 376 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
377
378 /* Some configurations cannot support LS traffic on a FS root port */
379 if ((dev_speed == USB_SPEED_LOW) &&
380 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
381 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
95c8bc36 382 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
9f8144c6
NH		 383 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
384
385 if (prtspd == HPRT0_SPD_FULL_SPEED)
386 return -ENODEV;
387 }
388
7359d482 389 if (!qtd)
b5a468a6 390 return -EINVAL;
7359d482
PZ		 391
392 dwc2_hcd_qtd_init(qtd, urb);
b58e6cee 393 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
9bda1aac 394 if (retval) {
7359d482
PZ		 395 dev_err(hsotg->dev,
396 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
397 retval);
7359d482
PZ		 398 return retval;
399 }
400
95c8bc36 401 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
9bda1aac 402 if (!(intr_mask & GINTSTS_SOF)) {
7359d482
PZ		 403 enum dwc2_transaction_type tr_type;
404
405 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
406 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
407 /*
408 * Do not schedule SG transactions until qtd has
409 * URB_GIVEBACK_ASAP set
410 */
411 return 0;
412
7359d482
PZ		 413 tr_type = dwc2_hcd_select_transactions(hsotg);
414 if (tr_type != DWC2_TRANSACTION_NONE)
415 dwc2_hcd_queue_transactions(hsotg, tr_type);
7359d482
PZ		 416 }
417
9bda1aac 418 return 0;
7359d482
PZ		 419}
420
421/* Must be called with interrupt disabled and spinlock held */
422static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
423 struct dwc2_hcd_urb *urb)
424{
425 struct dwc2_qh *qh;
426 struct dwc2_qtd *urb_qtd;
427
428 urb_qtd = urb->qtd;
429 if (!urb_qtd) {
430 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
431 return -EINVAL;
432 }
433
434 qh = urb_qtd->qh;
435 if (!qh) {
436 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
437 return -EINVAL;
438 }
439
0d012b98
PZ		 440 urb->priv = NULL;
441
7359d482
PZ		 442 if (urb_qtd->in_process && qh->channel) {
443 dwc2_dump_channel_info(hsotg, qh->channel);
444
445 /* The QTD is in process (it has been assigned to a channel) */
446 if (hsotg->flags.b.port_connect_status)
447 /*
448 * If still connected (i.e. in host mode), halt the
449 * channel so it can be used for other transfers. If
450 * no longer connected, the host registers can't be
451 * written to halt the channel since the core is in
452 * device mode.
453 */
454 dwc2_hc_halt(hsotg, qh->channel,
455 DWC2_HC_XFER_URB_DEQUEUE);
456 }
457
458 /*
459 * Free the QTD and clean up the associated QH. Leave the QH in the
460 * schedule if it has any remaining QTDs.
461 */
462 if (hsotg->core_params->dma_desc_enable <= 0) {
463 u8 in_process = urb_qtd->in_process;
464
465 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
466 if (in_process) {
467 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
468 qh->channel = NULL;
469 } else if (list_empty(&qh->qtd_list)) {
470 dwc2_hcd_qh_unlink(hsotg, qh);
471 }
472 } else {
473 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
474 }
475
476 return 0;
477}
478
479/* Must NOT be called with interrupt disabled or spinlock held */
480static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
481 struct usb_host_endpoint *ep, int retry)
482{
483 struct dwc2_qtd *qtd, *qtd_tmp;
484 struct dwc2_qh *qh;
485 unsigned long flags;
486 int rc;
487
488 spin_lock_irqsave(&hsotg->lock, flags);
489
490 qh = ep->hcpriv;
491 if (!qh) {
492 rc = -EINVAL;
493 goto err;
494 }
495
496 while (!list_empty(&qh->qtd_list) && retry--) {
497 if (retry == 0) {
498 dev_err(hsotg->dev,
499 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
500 rc = -EBUSY;
501 goto err;
502 }
503
504 spin_unlock_irqrestore(&hsotg->lock, flags);
505 usleep_range(20000, 40000);
506 spin_lock_irqsave(&hsotg->lock, flags);
507 qh = ep->hcpriv;
508 if (!qh) {
509 rc = -EINVAL;
510 goto err;
511 }
512 }
513
514 dwc2_hcd_qh_unlink(hsotg, qh);
515
516 /* Free each QTD in the QH's QTD list */
517 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
518 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
519
520 ep->hcpriv = NULL;
521 spin_unlock_irqrestore(&hsotg->lock, flags);
522 dwc2_hcd_qh_free(hsotg, qh);
523
524 return 0;
525
526err:
527 ep->hcpriv = NULL;
528 spin_unlock_irqrestore(&hsotg->lock, flags);
529
530 return rc;
531}
532
533/* Must be called with interrupt disabled and spinlock held */
534static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
535 struct usb_host_endpoint *ep)
536{
537 struct dwc2_qh *qh = ep->hcpriv;
538
539 if (!qh)
540 return -EINVAL;
541
542 qh->data_toggle = DWC2_HC_PID_DATA0;
543
544 return 0;
545}
546
547/*
548 * Initializes dynamic portions of the DWC_otg HCD state
549 *
550 * Must be called with interrupt disabled and spinlock held
551 */
552static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
553{
554 struct dwc2_host_chan *chan, *chan_tmp;
555 int num_channels;
556 int i;
557
558 hsotg->flags.d32 = 0;
7359d482 559 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
20f2eb9c
DC		 560
561 if (hsotg->core_params->uframe_sched > 0) {
562 hsotg->available_host_channels =
563 hsotg->core_params->host_channels;
564 } else {
565 hsotg->non_periodic_channels = 0;
566 hsotg->periodic_channels = 0;
567 }
7359d482
PZ		 568
569 /*
570 * Put all channels in the free channel list and clean up channel
571 * states
572 */
573 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
574 hc_list_entry)
575 list_del_init(&chan->hc_list_entry);
576
577 num_channels = hsotg->core_params->host_channels;
578 for (i = 0; i < num_channels; i++) {
579 chan = hsotg->hc_ptr_array[i];
580 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
581 dwc2_hc_cleanup(hsotg, chan);
582 }
583
584 /* Initialize the DWC core for host mode operation */
585 dwc2_core_host_init(hsotg);
586}
587
588static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
589 struct dwc2_host_chan *chan,
590 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
591{
592 int hub_addr, hub_port;
593
594 chan->do_split = 1;
595 chan->xact_pos = qtd->isoc_split_pos;
596 chan->complete_split = qtd->complete_split;
597 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
598 chan->hub_addr = (u8)hub_addr;
599 chan->hub_port = (u8)hub_port;
600}
601
602static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
603 struct dwc2_host_chan *chan,
604 struct dwc2_qtd *qtd, void *bufptr)
605{
606 struct dwc2_hcd_urb *urb = qtd->urb;
607 struct dwc2_hcd_iso_packet_desc *frame_desc;
608
609 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
610 case USB_ENDPOINT_XFER_CONTROL:
611 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
612
613 switch (qtd->control_phase) {
614 case DWC2_CONTROL_SETUP:
615 dev_vdbg(hsotg->dev, " Control setup transaction\n");
616 chan->do_ping = 0;
617 chan->ep_is_in = 0;
618 chan->data_pid_start = DWC2_HC_PID_SETUP;
619 if (hsotg->core_params->dma_enable > 0)
620 chan->xfer_dma = urb->setup_dma;
621 else
622 chan->xfer_buf = urb->setup_packet;
623 chan->xfer_len = 8;
624 bufptr = NULL;
625 break;
626
627 case DWC2_CONTROL_DATA:
628 dev_vdbg(hsotg->dev, " Control data transaction\n");
629 chan->data_pid_start = qtd->data_toggle;
630 break;
631
632 case DWC2_CONTROL_STATUS:
633 /*
634 * Direction is opposite of data direction or IN if no
635 * data
636 */
637 dev_vdbg(hsotg->dev, " Control status transaction\n");
638 if (urb->length == 0)
639 chan->ep_is_in = 1;
640 else
641 chan->ep_is_in =
642 dwc2_hcd_is_pipe_out(&urb->pipe_info);
643 if (chan->ep_is_in)
644 chan->do_ping = 0;
645 chan->data_pid_start = DWC2_HC_PID_DATA1;
646 chan->xfer_len = 0;
647 if (hsotg->core_params->dma_enable > 0)
648 chan->xfer_dma = hsotg->status_buf_dma;
649 else
650 chan->xfer_buf = hsotg->status_buf;
651 bufptr = NULL;
652 break;
653 }
654 break;
655
656 case USB_ENDPOINT_XFER_BULK:
657 chan->ep_type = USB_ENDPOINT_XFER_BULK;
658 break;
659
660 case USB_ENDPOINT_XFER_INT:
661 chan->ep_type = USB_ENDPOINT_XFER_INT;
662 break;
663
664 case USB_ENDPOINT_XFER_ISOC:
665 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
666 if (hsotg->core_params->dma_desc_enable > 0)
667 break;
668
669 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
670 frame_desc->status = 0;
671
672 if (hsotg->core_params->dma_enable > 0) {
673 chan->xfer_dma = urb->dma;
674 chan->xfer_dma += frame_desc->offset +
675 qtd->isoc_split_offset;
676 } else {
677 chan->xfer_buf = urb->buf;
678 chan->xfer_buf += frame_desc->offset +
679 qtd->isoc_split_offset;
680 }
681
682 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
683
684 /* For non-dword aligned buffers */
685 if (hsotg->core_params->dma_enable > 0 &&
686 (chan->xfer_dma & 0x3))
687 bufptr = (u8 *)urb->buf + frame_desc->offset +
688 qtd->isoc_split_offset;
689 else
690 bufptr = NULL;
691
692 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
693 if (chan->xfer_len <= 188)
694 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
695 else
696 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
697 }
698 break;
699 }
700
701 return bufptr;
702}
703
704static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
5dce9555
PZ		 705 struct dwc2_host_chan *chan,
706 struct dwc2_hcd_urb *urb, void *bufptr)
7359d482
PZ		 707{
708 u32 buf_size;
5dce9555
PZ		 709 struct urb *usb_urb;
710 struct usb_hcd *hcd;
7359d482
PZ		 711
712 if (!qh->dw_align_buf) {
5dce9555
PZ		 713 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
714 buf_size = hsotg->core_params->max_transfer_size;
715 else
716 /* 3072 = 3 max-size Isoc packets */
717 buf_size = 3072;
718
db62b9a8 719 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
7359d482
PZ		 720 if (!qh->dw_align_buf)
721 return -ENOMEM;
5dce9555 722 qh->dw_align_buf_size = buf_size;
7359d482
PZ		 723 }
724
5dce9555
PZ		 725 if (chan->xfer_len) {
726 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
727 usb_urb = urb->priv;
728
729 if (usb_urb) {
730 if (usb_urb->transfer_flags &
731 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
732 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
733 hcd = dwc2_hsotg_to_hcd(hsotg);
734 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
735 }
736 if (!chan->ep_is_in)
737 memcpy(qh->dw_align_buf, bufptr,
738 chan->xfer_len);
739 } else {
740 dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
741 }
7359d482
PZ		 742 }
743
db62b9a8
GH		 744 qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
745 qh->dw_align_buf, qh->dw_align_buf_size,
746 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
747 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
748 dev_err(hsotg->dev, "can't map align_buf\n");
3521a399 749 chan->align_buf = 0;
db62b9a8
GH		 750 return -EINVAL;
751 }
752
7359d482
PZ		 753 chan->align_buf = qh->dw_align_buf_dma;
754 return 0;
755}
756
757/**
758 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
759 * channel and initializes the host channel to perform the transactions. The
760 * host channel is removed from the free list.
761 *
762 * @hsotg: The HCD state structure
763 * @qh: Transactions from the first QTD for this QH are selected and assigned
764 * to a free host channel
765 */
20f2eb9c 766static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
7359d482
PZ		 767{
768 struct dwc2_host_chan *chan;
769 struct dwc2_hcd_urb *urb;
770 struct dwc2_qtd *qtd;
771 void *bufptr = NULL;
772
b49977a6
MK		 773 if (dbg_qh(qh))
774 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
7359d482
PZ		 775
776 if (list_empty(&qh->qtd_list)) {
777 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
20f2eb9c 778 return -ENOMEM;
7359d482
PZ		 779 }
780
781 if (list_empty(&hsotg->free_hc_list)) {
782 dev_dbg(hsotg->dev, "No free channel to assign\n");
20f2eb9c 783 return -ENOMEM;
7359d482
PZ		 784 }
785
786 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
787 hc_list_entry);
788
20f2eb9c 789 /* Remove host channel from free list */
7359d482
PZ		 790 list_del_init(&chan->hc_list_entry);
791
792 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
793 urb = qtd->urb;
794 qh->channel = chan;
795 qtd->in_process = 1;
796
797 /*
798 * Use usb_pipedevice to determine device address. This address is
799 * 0 before the SET_ADDRESS command and the correct address afterward.
800 */
801 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
802 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
803 chan->speed = qh->dev_speed;
804 chan->max_packet = dwc2_max_packet(qh->maxp);
805
806 chan->xfer_started = 0;
807 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
808 chan->error_state = (qtd->error_count > 0);
809 chan->halt_on_queue = 0;
810 chan->halt_pending = 0;
811 chan->requests = 0;
812
813 /*
814 * The following values may be modified in the transfer type section
815 * below. The xfer_len value may be reduced when the transfer is
816 * started to accommodate the max widths of the XferSize and PktCnt
817 * fields in the HCTSIZn register.
818 */
819
820 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
821 if (chan->ep_is_in)
822 chan->do_ping = 0;
823 else
824 chan->do_ping = qh->ping_state;
825
826 chan->data_pid_start = qh->data_toggle;
827 chan->multi_count = 1;
828
bb6c3422
RK		 829 if (urb->actual_length > urb->length &&
830 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
84181086
PZ		 831 urb->actual_length = urb->length;
832
7359d482
PZ		 833 if (hsotg->core_params->dma_enable > 0) {
834 chan->xfer_dma = urb->dma + urb->actual_length;
835
836 /* For non-dword aligned case */
837 if (hsotg->core_params->dma_desc_enable <= 0 &&
838 (chan->xfer_dma & 0x3))
839 bufptr = (u8 *)urb->buf + urb->actual_length;
840 } else {
841 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
842 }
843
844 chan->xfer_len = urb->length - urb->actual_length;
845 chan->xfer_count = 0;
846
847 /* Set the split attributes if required */
848 if (qh->do_split)
849 dwc2_hc_init_split(hsotg, chan, qtd, urb);
850 else
851 chan->do_split = 0;
852
853 /* Set the transfer attributes */
854 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
855
856 /* Non DWORD-aligned buffer case */
857 if (bufptr) {
858 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
5dce9555 859 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
7359d482
PZ		 860 dev_err(hsotg->dev,
861 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
862 __func__);
863 /* Add channel back to free list */
864 chan->align_buf = 0;
865 chan->multi_count = 0;
866 list_add_tail(&chan->hc_list_entry,
867 &hsotg->free_hc_list);
868 qtd->in_process = 0;
869 qh->channel = NULL;
20f2eb9c 870 return -ENOMEM;
7359d482
PZ		 871 }
872 } else {
873 chan->align_buf = 0;
874 }
875
876 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
877 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
878 /*
879 * This value may be modified when the transfer is started
880 * to reflect the actual transfer length
881 */
882 chan->multi_count = dwc2_hb_mult(qh->maxp);
883
95105a99 884 if (hsotg->core_params->dma_desc_enable > 0) {
7359d482 885 chan->desc_list_addr = qh->desc_list_dma;
95105a99
GH		 886 chan->desc_list_sz = qh->desc_list_sz;
887 }
7359d482
PZ		 888
889 dwc2_hc_init(hsotg, chan);
890 chan->qh = qh;
20f2eb9c
DC		 891
892 return 0;
7359d482
PZ		 893}
894
895/**
896 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
897 * schedule and assigns them to available host channels. Called from the HCD
898 * interrupt handler functions.
899 *
900 * @hsotg: The HCD state structure
901 *
902 * Return: The types of new transactions that were assigned to host channels
903 */
904enum dwc2_transaction_type dwc2_hcd_select_transactions(
905 struct dwc2_hsotg *hsotg)
906{
907 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
908 struct list_head *qh_ptr;
909 struct dwc2_qh *qh;
910 int num_channels;
911
912#ifdef DWC2_DEBUG_SOF
913 dev_vdbg(hsotg->dev, " Select Transactions\n");
914#endif
915
916 /* Process entries in the periodic ready list */
917 qh_ptr = hsotg->periodic_sched_ready.next;
918 while (qh_ptr != &hsotg->periodic_sched_ready) {
919 if (list_empty(&hsotg->free_hc_list))
920 break;
20f2eb9c
DC		 921 if (hsotg->core_params->uframe_sched > 0) {
922 if (hsotg->available_host_channels <= 1)
923 break;
924 hsotg->available_host_channels--;
925 }
7359d482 926 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 927 if (dwc2_assign_and_init_hc(hsotg, qh))
928 break;
7359d482
PZ		 929
930 /*
931 * Move the QH from the periodic ready schedule to the
932 * periodic assigned schedule
933 */
934 qh_ptr = qh_ptr->next;
935 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
936 ret_val = DWC2_TRANSACTION_PERIODIC;
937 }
938
939 /*
940 * Process entries in the inactive portion of the non-periodic
941 * schedule. Some free host channels may not be used if they are
942 * reserved for periodic transfers.
943 */
944 num_channels = hsotg->core_params->host_channels;
945 qh_ptr = hsotg->non_periodic_sched_inactive.next;
946 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
20f2eb9c
DC		 947 if (hsotg->core_params->uframe_sched <= 0 &&
948 hsotg->non_periodic_channels >= num_channels -
7359d482
PZ		 949 hsotg->periodic_channels)
950 break;
951 if (list_empty(&hsotg->free_hc_list))
952 break;
953 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 954 if (hsotg->core_params->uframe_sched > 0) {
955 if (hsotg->available_host_channels < 1)
956 break;
957 hsotg->available_host_channels--;
958 }
959
960 if (dwc2_assign_and_init_hc(hsotg, qh))
961 break;
7359d482
PZ		 962
963 /*
964 * Move the QH from the non-periodic inactive schedule to the
965 * non-periodic active schedule
966 */
967 qh_ptr = qh_ptr->next;
968 list_move(&qh->qh_list_entry,
969 &hsotg->non_periodic_sched_active);
970
971 if (ret_val == DWC2_TRANSACTION_NONE)
972 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
973 else
974 ret_val = DWC2_TRANSACTION_ALL;
975
20f2eb9c
DC		 976 if (hsotg->core_params->uframe_sched <= 0)
977 hsotg->non_periodic_channels++;
7359d482
PZ		 978 }
979
980 return ret_val;
981}
982
983/**
984 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
985 * a host channel associated with either a periodic or non-periodic transfer
986 *
987 * @hsotg: The HCD state structure
988 * @chan: Host channel descriptor associated with either a periodic or
989 * non-periodic transfer
990 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
991 * for periodic transfers or the non-periodic Tx FIFO
992 * for non-periodic transfers
993 *
994 * Return: 1 if a request is queued and more requests may be needed to
995 * complete the transfer, 0 if no more requests are required for this
996 * transfer, -1 if there is insufficient space in the Tx FIFO
997 *
998 * This function assumes that there is space available in the appropriate
999 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
1000 * it checks whether space is available in the appropriate Tx FIFO.
1001 *
1002 * Must be called with interrupt disabled and spinlock held
1003 */
1004static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1005 struct dwc2_host_chan *chan,
1006 u16 fifo_dwords_avail)
1007{
1008 int retval = 0;
1009
1010 if (hsotg->core_params->dma_enable > 0) {
1011 if (hsotg->core_params->dma_desc_enable > 0) {
1012 if (!chan->xfer_started ||
1013 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1014 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1015 chan->qh->ping_state = 0;
1016 }
1017 } else if (!chan->xfer_started) {
1018 dwc2_hc_start_transfer(hsotg, chan);
1019 chan->qh->ping_state = 0;
1020 }
1021 } else if (chan->halt_pending) {
1022 /* Don't queue a request if the channel has been halted */
1023 } else if (chan->halt_on_queue) {
1024 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1025 } else if (chan->do_ping) {
1026 if (!chan->xfer_started)
1027 dwc2_hc_start_transfer(hsotg, chan);
1028 } else if (!chan->ep_is_in ||
1029 chan->data_pid_start == DWC2_HC_PID_SETUP) {
1030 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1031 if (!chan->xfer_started) {
1032 dwc2_hc_start_transfer(hsotg, chan);
1033 retval = 1;
1034 } else {
1035 retval = dwc2_hc_continue_transfer(hsotg, chan);
1036 }
1037 } else {
1038 retval = -1;
1039 }
1040 } else {
1041 if (!chan->xfer_started) {
1042 dwc2_hc_start_transfer(hsotg, chan);
1043 retval = 1;
1044 } else {
1045 retval = dwc2_hc_continue_transfer(hsotg, chan);
1046 }
1047 }
1048
1049 return retval;
1050}
1051
1052/*
1053 * Processes periodic channels for the next frame and queues transactions for
1054 * these channels to the DWC_otg controller. After queueing transactions, the
1055 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1056 * to queue as Periodic Tx FIFO or request queue space becomes available.
1057 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1058 *
1059 * Must be called with interrupt disabled and spinlock held
1060 */
1061static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1062{
1063 struct list_head *qh_ptr;
1064 struct dwc2_qh *qh;
1065 u32 tx_status;
1066 u32 fspcavail;
1067 u32 gintmsk;
1068 int status;
1069 int no_queue_space = 0;
1070 int no_fifo_space = 0;
1071 u32 qspcavail;
1072
b49977a6
MK		 1073 if (dbg_perio())
1074 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
7359d482 1075
95c8bc36 1076 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1077 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1078 TXSTS_QSPCAVAIL_SHIFT;
1079 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1080 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1081
1082 if (dbg_perio()) {
1083 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1084 qspcavail);
1085 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1086 fspcavail);
1087 }
7359d482
PZ		 1088
1089 qh_ptr = hsotg->periodic_sched_assigned.next;
1090 while (qh_ptr != &hsotg->periodic_sched_assigned) {
95c8bc36 1091 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
acdb9046
MK		 1092 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1093 TXSTS_QSPCAVAIL_SHIFT;
1094 if (qspcavail == 0) {
7359d482
PZ		 1095 no_queue_space = 1;
1096 break;
1097 }
1098
1099 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1100 if (!qh->channel) {
1101 qh_ptr = qh_ptr->next;
1102 continue;
1103 }
1104
1105 /* Make sure EP's TT buffer is clean before queueing qtds */
1106 if (qh->tt_buffer_dirty) {
1107 qh_ptr = qh_ptr->next;
1108 continue;
1109 }
1110
1111 /*
1112 * Set a flag if we're queuing high-bandwidth in slave mode.
1113 * The flag prevents any halts to get into the request queue in
1114 * the middle of multiple high-bandwidth packets getting queued.
1115 */
1116 if (hsotg->core_params->dma_enable <= 0 &&
1117 qh->channel->multi_count > 1)
1118 hsotg->queuing_high_bandwidth = 1;
1119
d6ec53e0
MK		 1120 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1121 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1122 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1123 if (status < 0) {
1124 no_fifo_space = 1;
1125 break;
1126 }
1127
1128 /*
1129 * In Slave mode, stay on the current transfer until there is
1130 * nothing more to do or the high-bandwidth request count is
1131 * reached. In DMA mode, only need to queue one request. The
1132 * controller automatically handles multiple packets for
1133 * high-bandwidth transfers.
1134 */
1135 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1136 qh->channel->requests == qh->channel->multi_count) {
1137 qh_ptr = qh_ptr->next;
1138 /*
1139 * Move the QH from the periodic assigned schedule to
1140 * the periodic queued schedule
1141 */
1142 list_move(&qh->qh_list_entry,
1143 &hsotg->periodic_sched_queued);
1144
1145 /* done queuing high bandwidth */
1146 hsotg->queuing_high_bandwidth = 0;
1147 }
1148 }
1149
1150 if (hsotg->core_params->dma_enable <= 0) {
95c8bc36 1151 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1152 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1153 TXSTS_QSPCAVAIL_SHIFT;
1154 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1155 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1156 if (dbg_perio()) {
1157 dev_vdbg(hsotg->dev,
1158 " P Tx Req Queue Space Avail (after queue): %d\n",
1159 qspcavail);
1160 dev_vdbg(hsotg->dev,
1161 " P Tx FIFO Space Avail (after queue): %d\n",
1162 fspcavail);
1163 }
7359d482
PZ		 1164
1165 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1166 no_queue_space || no_fifo_space) {
1167 /*
1168 * May need to queue more transactions as the request
1169 * queue or Tx FIFO empties. Enable the periodic Tx
1170 * FIFO empty interrupt. (Always use the half-empty
1171 * level to ensure that new requests are loaded as
1172 * soon as possible.)
1173 */
95c8bc36 1174 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1175 gintmsk |= GINTSTS_PTXFEMP;
95c8bc36 1176 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1177 } else {
1178 /*
1179 * Disable the Tx FIFO empty interrupt since there are
1180 * no more transactions that need to be queued right
1181 * now. This function is called from interrupt
1182 * handlers to queue more transactions as transfer
1183 * states change.
1184 */
95c8bc36 1185 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1186 gintmsk &= ~GINTSTS_PTXFEMP;
95c8bc36 1187 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1188 }
1189 }
1190}
1191
1192/*
1193 * Processes active non-periodic channels and queues transactions for these
1194 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1195 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1196 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1197 * FIFO Empty interrupt is disabled.
1198 *
1199 * Must be called with interrupt disabled and spinlock held
1200 */
1201static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1202{
1203 struct list_head *orig_qh_ptr;
1204 struct dwc2_qh *qh;
1205 u32 tx_status;
1206 u32 qspcavail;
1207 u32 fspcavail;
1208 u32 gintmsk;
1209 int status;
1210 int no_queue_space = 0;
1211 int no_fifo_space = 0;
1212 int more_to_do = 0;
1213
1214 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1215
95c8bc36 1216 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1217 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1218 TXSTS_QSPCAVAIL_SHIFT;
1219 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1220 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1221 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1222 qspcavail);
1223 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1224 fspcavail);
1225
1226 /*
1227 * Keep track of the starting point. Skip over the start-of-list
1228 * entry.
1229 */
1230 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1231 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1232 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1233
1234 /*
1235 * Process once through the active list or until no more space is
1236 * available in the request queue or the Tx FIFO
1237 */
1238 do {
95c8bc36 1239 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1240 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1241 TXSTS_QSPCAVAIL_SHIFT;
7359d482
PZ		 1242 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1243 no_queue_space = 1;
1244 break;
1245 }
1246
1247 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1248 qh_list_entry);
1249 if (!qh->channel)
1250 goto next;
1251
1252 /* Make sure EP's TT buffer is clean before queueing qtds */
1253 if (qh->tt_buffer_dirty)
1254 goto next;
1255
d6ec53e0
MK		 1256 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1257 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1258 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1259
1260 if (status > 0) {
1261 more_to_do = 1;
1262 } else if (status < 0) {
1263 no_fifo_space = 1;
1264 break;
1265 }
1266next:
1267 /* Advance to next QH, skipping start-of-list entry */
1268 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1269 if (hsotg->non_periodic_qh_ptr ==
1270 &hsotg->non_periodic_sched_active)
1271 hsotg->non_periodic_qh_ptr =
1272 hsotg->non_periodic_qh_ptr->next;
1273 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1274
1275 if (hsotg->core_params->dma_enable <= 0) {
95c8bc36 1276 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1277 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1278 TXSTS_QSPCAVAIL_SHIFT;
1279 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1280 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1281 dev_vdbg(hsotg->dev,
1282 " NP Tx Req Queue Space Avail (after queue): %d\n",
1283 qspcavail);
1284 dev_vdbg(hsotg->dev,
1285 " NP Tx FIFO Space Avail (after queue): %d\n",
1286 fspcavail);
1287
1288 if (more_to_do || no_queue_space || no_fifo_space) {
1289 /*
1290 * May need to queue more transactions as the request
1291 * queue or Tx FIFO empties. Enable the non-periodic
1292 * Tx FIFO empty interrupt. (Always use the half-empty
1293 * level to ensure that new requests are loaded as
1294 * soon as possible.)
1295 */
95c8bc36 1296 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1297 gintmsk |= GINTSTS_NPTXFEMP;
95c8bc36 1298 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1299 } else {
1300 /*
1301 * Disable the Tx FIFO empty interrupt since there are
1302 * no more transactions that need to be queued right
1303 * now. This function is called from interrupt
1304 * handlers to queue more transactions as transfer
1305 * states change.
1306 */
95c8bc36 1307 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482 1308 gintmsk &= ~GINTSTS_NPTXFEMP;
95c8bc36 1309 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1310 }
1311 }
1312}
1313
1314/**
1315 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1316 * and queues transactions for these channels to the DWC_otg controller. Called
1317 * from the HCD interrupt handler functions.
1318 *
1319 * @hsotg: The HCD state structure
1320 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1321 * or both)
1322 *
1323 * Must be called with interrupt disabled and spinlock held
1324 */
1325void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1326 enum dwc2_transaction_type tr_type)
1327{
1328#ifdef DWC2_DEBUG_SOF
1329 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1330#endif
1331 /* Process host channels associated with periodic transfers */
1332 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1333 tr_type == DWC2_TRANSACTION_ALL) &&
1334 !list_empty(&hsotg->periodic_sched_assigned))
1335 dwc2_process_periodic_channels(hsotg);
1336
1337 /* Process host channels associated with non-periodic transfers */
1338 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1339 tr_type == DWC2_TRANSACTION_ALL) {
1340 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1341 dwc2_process_non_periodic_channels(hsotg);
1342 } else {
1343 /*
1344 * Ensure NP Tx FIFO empty interrupt is disabled when
1345 * there are no non-periodic transfers to process
1346 */
95c8bc36 1347 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
7359d482
PZ		 1348
1349 gintmsk &= ~GINTSTS_NPTXFEMP;
95c8bc36 1350 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
7359d482
PZ		 1351 }
1352 }
1353}
1354
1355static void dwc2_conn_id_status_change(struct work_struct *work)
1356{
1357 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1358 wf_otg);
1359 u32 count = 0;
1360 u32 gotgctl;
5390d438 1361 unsigned long flags;
7359d482
PZ		 1362
1363 dev_dbg(hsotg->dev, "%s()\n", __func__);
1364
95c8bc36 1365 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
7359d482
PZ		 1366 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1367 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1368 !!(gotgctl & GOTGCTL_CONID_B));
1369
1370 /* B-Device connector (Device Mode) */
1371 if (gotgctl & GOTGCTL_CONID_B) {
1372 /* Wait for switch to device mode */
1373 dev_dbg(hsotg->dev, "connId B\n");
1374 while (!dwc2_is_device_mode(hsotg)) {
1375 dev_info(hsotg->dev,
1376 "Waiting for Peripheral Mode, Mode=%s\n",
1377 dwc2_is_host_mode(hsotg) ? "Host" :
1378 "Peripheral");
1379 usleep_range(20000, 40000);
1380 if (++count > 250)
1381 break;
1382 }
1383 if (count > 250)
1384 dev_err(hsotg->dev,
de9169a1 1385 "Connection id status change timed out\n");
7359d482 1386 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
6706c721 1387 dwc2_core_init(hsotg, false, -1);
7359d482 1388 dwc2_enable_global_interrupts(hsotg);
5390d438 1389 spin_lock_irqsave(&hsotg->lock, flags);
1f91b4cc 1390 dwc2_hsotg_core_init_disconnected(hsotg, false);
5390d438 1391 spin_unlock_irqrestore(&hsotg->lock, flags);
1f91b4cc 1392 dwc2_hsotg_core_connect(hsotg);
7359d482
PZ		 1393 } else {
1394 /* A-Device connector (Host Mode) */
1395 dev_dbg(hsotg->dev, "connId A\n");
1396 while (!dwc2_is_host_mode(hsotg)) {
1397 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1398 dwc2_is_host_mode(hsotg) ?
1399 "Host" : "Peripheral");
1400 usleep_range(20000, 40000);
1401 if (++count > 250)
1402 break;
1403 }
1404 if (count > 250)
1405 dev_err(hsotg->dev,
de9169a1 1406 "Connection id status change timed out\n");
7359d482
PZ		 1407 hsotg->op_state = OTG_STATE_A_HOST;
1408
1409 /* Initialize the Core for Host mode */
6706c721 1410 dwc2_core_init(hsotg, false, -1);
7359d482
PZ		 1411 dwc2_enable_global_interrupts(hsotg);
1412 dwc2_hcd_start(hsotg);
1413 }
1414}
1415
1416static void dwc2_wakeup_detected(unsigned long data)
1417{
1418 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1419 u32 hprt0;
1420
1421 dev_dbg(hsotg->dev, "%s()\n", __func__);
1422
1423 /*
1424 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1425 * so that OPT tests pass with all PHYs.)
1426 */
1427 hprt0 = dwc2_read_hprt0(hsotg);
1428 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1429 hprt0 &= ~HPRT0_RES;
95c8bc36 1430 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482 1431 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
95c8bc36 1432 dwc2_readl(hsotg->regs + HPRT0));
7359d482
PZ		 1433
1434 dwc2_hcd_rem_wakeup(hsotg);
1fb7f12d 1435 hsotg->bus_suspended = 0;
7359d482
PZ		 1436
1437 /* Change to L0 state */
1438 hsotg->lx_state = DWC2_L0;
1439}
1440
1441static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1442{
1443 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1444
1445 return hcd->self.b_hnp_enable;
1446}
1447
1448/* Must NOT be called with interrupt disabled or spinlock held */
1449static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1450{
1451 unsigned long flags;
1452 u32 hprt0;
1453 u32 pcgctl;
1454 u32 gotgctl;
1455
1456 dev_dbg(hsotg->dev, "%s()\n", __func__);
1457
1458 spin_lock_irqsave(&hsotg->lock, flags);
1459
1460 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
95c8bc36 1461 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
7359d482 1462 gotgctl |= GOTGCTL_HSTSETHNPEN;
95c8bc36 1463 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
7359d482
PZ		 1464 hsotg->op_state = OTG_STATE_A_SUSPEND;
1465 }
1466
1467 hprt0 = dwc2_read_hprt0(hsotg);
1468 hprt0 |= HPRT0_SUSP;
95c8bc36 1469 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482 1470
734643df 1471 hsotg->bus_suspended = 1;
7359d482 1472
a2a23d3f
GH		 1473 /*
1474 * If hibernation is supported, Phy clock will be suspended
1475 * after registers are backuped.
1476 */
1477 if (!hsotg->core_params->hibernation) {
1478 /* Suspend the Phy Clock */
1479 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1480 pcgctl |= PCGCTL_STOPPCLK;
1481 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1482 udelay(10);
1483 }
7359d482
PZ		 1484
1485 /* For HNP the bus must be suspended for at least 200ms */
1486 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
95c8bc36 1487 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
7359d482 1488 pcgctl &= ~PCGCTL_STOPPCLK;
95c8bc36 1489 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
7359d482
PZ		 1490
1491 spin_unlock_irqrestore(&hsotg->lock, flags);
1492
1493 usleep_range(200000, 250000);
1494 } else {
1495 spin_unlock_irqrestore(&hsotg->lock, flags);
1496 }
1497}
1498
30db103c
GH		 1499/* Must NOT be called with interrupt disabled or spinlock held */
1500static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
1501{
1502 unsigned long flags;
1503 u32 hprt0;
1504 u32 pcgctl;
1505
4d273c2a
DA		 1506 spin_lock_irqsave(&hsotg->lock, flags);
1507
a2a23d3f
GH		 1508 /*
1509 * If hibernation is supported, Phy clock is already resumed
1510 * after registers restore.
1511 */
1512 if (!hsotg->core_params->hibernation) {
1513 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1514 pcgctl &= ~PCGCTL_STOPPCLK;
1515 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
4d273c2a 1516 spin_unlock_irqrestore(&hsotg->lock, flags);
a2a23d3f 1517 usleep_range(20000, 40000);
4d273c2a 1518 spin_lock_irqsave(&hsotg->lock, flags);
a2a23d3f 1519 }
30db103c 1520
30db103c
GH		 1521 hprt0 = dwc2_read_hprt0(hsotg);
1522 hprt0 |= HPRT0_RES;
1523 hprt0 &= ~HPRT0_SUSP;
1524 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1525 spin_unlock_irqrestore(&hsotg->lock, flags);
1526
1527 msleep(USB_RESUME_TIMEOUT);
1528
1529 spin_lock_irqsave(&hsotg->lock, flags);
1530 hprt0 = dwc2_read_hprt0(hsotg);
1531 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
1532 dwc2_writel(hprt0, hsotg->regs + HPRT0);
734643df 1533 hsotg->bus_suspended = 0;
30db103c
GH		 1534 spin_unlock_irqrestore(&hsotg->lock, flags);
1535}
1536
7359d482
PZ		 1537/* Handles hub class-specific requests */
1538static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1539 u16 wvalue, u16 windex, char *buf, u16 wlength)
1540{
1541 struct usb_hub_descriptor *hub_desc;
1542 int retval = 0;
1543 u32 hprt0;
1544 u32 port_status;
1545 u32 speed;
1546 u32 pcgctl;
1547
1548 switch (typereq) {
1549 case ClearHubFeature:
1550 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1551
1552 switch (wvalue) {
1553 case C_HUB_LOCAL_POWER:
1554 case C_HUB_OVER_CURRENT:
1555 /* Nothing required here */
1556 break;
1557
1558 default:
1559 retval = -EINVAL;
1560 dev_err(hsotg->dev,
1561 "ClearHubFeature request %1xh unknown\n",
1562 wvalue);
1563 }
1564 break;
1565
1566 case ClearPortFeature:
1567 if (wvalue != USB_PORT_FEAT_L1)
1568 if (!windex || windex > 1)
1569 goto error;
1570 switch (wvalue) {
1571 case USB_PORT_FEAT_ENABLE:
1572 dev_dbg(hsotg->dev,
1573 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1574 hprt0 = dwc2_read_hprt0(hsotg);
1575 hprt0 |= HPRT0_ENA;
95c8bc36 1576 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1577 break;
1578
1579 case USB_PORT_FEAT_SUSPEND:
1580 dev_dbg(hsotg->dev,
1581 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
b0bb9bb6 1582
bea78555
GH		 1583 if (hsotg->bus_suspended)
1584 dwc2_port_resume(hsotg);
7359d482
PZ		 1585 break;
1586
1587 case USB_PORT_FEAT_POWER:
1588 dev_dbg(hsotg->dev,
1589 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1590 hprt0 = dwc2_read_hprt0(hsotg);
1591 hprt0 &= ~HPRT0_PWR;
95c8bc36 1592 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1593 break;
1594
1595 case USB_PORT_FEAT_INDICATOR:
1596 dev_dbg(hsotg->dev,
1597 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1598 /* Port indicator not supported */
1599 break;
1600
1601 case USB_PORT_FEAT_C_CONNECTION:
1602 /*
1603 * Clears driver's internal Connect Status Change flag
1604 */
1605 dev_dbg(hsotg->dev,
1606 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1607 hsotg->flags.b.port_connect_status_change = 0;
1608 break;
1609
1610 case USB_PORT_FEAT_C_RESET:
1611 /* Clears driver's internal Port Reset Change flag */
1612 dev_dbg(hsotg->dev,
1613 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1614 hsotg->flags.b.port_reset_change = 0;
1615 break;
1616
1617 case USB_PORT_FEAT_C_ENABLE:
1618 /*
1619 * Clears the driver's internal Port Enable/Disable
1620 * Change flag
1621 */
1622 dev_dbg(hsotg->dev,
1623 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1624 hsotg->flags.b.port_enable_change = 0;
1625 break;
1626
1627 case USB_PORT_FEAT_C_SUSPEND:
1628 /*
1629 * Clears the driver's internal Port Suspend Change
1630 * flag, which is set when resume signaling on the host
1631 * port is complete
1632 */
1633 dev_dbg(hsotg->dev,
1634 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1635 hsotg->flags.b.port_suspend_change = 0;
1636 break;
1637
1638 case USB_PORT_FEAT_C_PORT_L1:
1639 dev_dbg(hsotg->dev,
1640 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1641 hsotg->flags.b.port_l1_change = 0;
1642 break;
1643
1644 case USB_PORT_FEAT_C_OVER_CURRENT:
1645 dev_dbg(hsotg->dev,
1646 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1647 hsotg->flags.b.port_over_current_change = 0;
1648 break;
1649
1650 default:
1651 retval = -EINVAL;
1652 dev_err(hsotg->dev,
1653 "ClearPortFeature request %1xh unknown or unsupported\n",
1654 wvalue);
1655 }
1656 break;
1657
1658 case GetHubDescriptor:
1659 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1660 hub_desc = (struct usb_hub_descriptor *)buf;
1661 hub_desc->bDescLength = 9;
a5dd0395 1662 hub_desc->bDescriptorType = USB_DT_HUB;
7359d482 1663 hub_desc->bNbrPorts = 1;
3d040de8
SS		 1664 hub_desc->wHubCharacteristics =
1665 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1666 HUB_CHAR_INDV_PORT_OCPM);
7359d482
PZ		 1667 hub_desc->bPwrOn2PwrGood = 1;
1668 hub_desc->bHubContrCurrent = 0;
1669 hub_desc->u.hs.DeviceRemovable[0] = 0;
1670 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1671 break;
1672
1673 case GetHubStatus:
1674 dev_dbg(hsotg->dev, "GetHubStatus\n");
1675 memset(buf, 0, 4);
1676 break;
1677
1678 case GetPortStatus:
b8313417
PZ		 1679 dev_vdbg(hsotg->dev,
1680 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1681 hsotg->flags.d32);
7359d482
PZ		 1682 if (!windex || windex > 1)
1683 goto error;
1684
1685 port_status = 0;
1686 if (hsotg->flags.b.port_connect_status_change)
1687 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1688 if (hsotg->flags.b.port_enable_change)
1689 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1690 if (hsotg->flags.b.port_suspend_change)
1691 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1692 if (hsotg->flags.b.port_l1_change)
1693 port_status |= USB_PORT_STAT_C_L1 << 16;
1694 if (hsotg->flags.b.port_reset_change)
1695 port_status |= USB_PORT_STAT_C_RESET << 16;
1696 if (hsotg->flags.b.port_over_current_change) {
1697 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1698 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1699 }
1700
1701 if (!hsotg->flags.b.port_connect_status) {
1702 /*
1703 * The port is disconnected, which means the core is
1704 * either in device mode or it soon will be. Just
1705 * return 0's for the remainder of the port status
1706 * since the port register can't be read if the core
1707 * is in device mode.
1708 */
1709 *(__le32 *)buf = cpu_to_le32(port_status);
1710 break;
1711 }
1712
95c8bc36 1713 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
b8313417 1714 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
7359d482
PZ		 1715
1716 if (hprt0 & HPRT0_CONNSTS)
1717 port_status |= USB_PORT_STAT_CONNECTION;
1718 if (hprt0 & HPRT0_ENA)
1719 port_status |= USB_PORT_STAT_ENABLE;
1720 if (hprt0 & HPRT0_SUSP)
1721 port_status |= USB_PORT_STAT_SUSPEND;
1722 if (hprt0 & HPRT0_OVRCURRACT)
1723 port_status |= USB_PORT_STAT_OVERCURRENT;
1724 if (hprt0 & HPRT0_RST)
1725 port_status |= USB_PORT_STAT_RESET;
1726 if (hprt0 & HPRT0_PWR)
1727 port_status |= USB_PORT_STAT_POWER;
1728
f9234633 1729 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
7359d482
PZ		 1730 if (speed == HPRT0_SPD_HIGH_SPEED)
1731 port_status |= USB_PORT_STAT_HIGH_SPEED;
1732 else if (speed == HPRT0_SPD_LOW_SPEED)
1733 port_status |= USB_PORT_STAT_LOW_SPEED;
1734
1735 if (hprt0 & HPRT0_TSTCTL_MASK)
1736 port_status |= USB_PORT_STAT_TEST;
1737 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1738
fbb9e22b
MYK		 1739 if (hsotg->core_params->dma_desc_fs_enable) {
1740 /*
1741 * Enable descriptor DMA only if a full speed
1742 * device is connected.
1743 */
1744 if (hsotg->new_connection &&
1745 ((port_status &
1746 (USB_PORT_STAT_CONNECTION |
1747 USB_PORT_STAT_HIGH_SPEED |
1748 USB_PORT_STAT_LOW_SPEED)) ==
1749 USB_PORT_STAT_CONNECTION)) {
1750 u32 hcfg;
1751
1752 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
1753 hsotg->core_params->dma_desc_enable = 1;
1754 hcfg = dwc2_readl(hsotg->regs + HCFG);
1755 hcfg |= HCFG_DESCDMA;
1756 dwc2_writel(hcfg, hsotg->regs + HCFG);
1757 hsotg->new_connection = false;
1758 }
1759 }
1760
b8313417 1761 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
7359d482
PZ		 1762 *(__le32 *)buf = cpu_to_le32(port_status);
1763 break;
1764
1765 case SetHubFeature:
1766 dev_dbg(hsotg->dev, "SetHubFeature\n");
1767 /* No HUB features supported */
1768 break;
1769
1770 case SetPortFeature:
1771 dev_dbg(hsotg->dev, "SetPortFeature\n");
1772 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1773 goto error;
1774
1775 if (!hsotg->flags.b.port_connect_status) {
1776 /*
1777 * The port is disconnected, which means the core is
1778 * either in device mode or it soon will be. Just
1779 * return without doing anything since the port
1780 * register can't be written if the core is in device
1781 * mode.
1782 */
1783 break;
1784 }
1785
1786 switch (wvalue) {
1787 case USB_PORT_FEAT_SUSPEND:
1788 dev_dbg(hsotg->dev,
1789 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1790 if (windex != hsotg->otg_port)
1791 goto error;
1792 dwc2_port_suspend(hsotg, windex);
1793 break;
1794
1795 case USB_PORT_FEAT_POWER:
1796 dev_dbg(hsotg->dev,
1797 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1798 hprt0 = dwc2_read_hprt0(hsotg);
1799 hprt0 |= HPRT0_PWR;
95c8bc36 1800 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1801 break;
1802
1803 case USB_PORT_FEAT_RESET:
1804 hprt0 = dwc2_read_hprt0(hsotg);
1805 dev_dbg(hsotg->dev,
1806 "SetPortFeature - USB_PORT_FEAT_RESET\n");
95c8bc36 1807 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
7359d482 1808 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
95c8bc36 1809 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
7359d482 1810 /* ??? Original driver does this */
95c8bc36 1811 dwc2_writel(0, hsotg->regs + PCGCTL);
7359d482
PZ		 1812
1813 hprt0 = dwc2_read_hprt0(hsotg);
1814 /* Clear suspend bit if resetting from suspend state */
1815 hprt0 &= ~HPRT0_SUSP;
1816
1817 /*
1818 * When B-Host the Port reset bit is set in the Start
1819 * HCD Callback function, so that the reset is started
1820 * within 1ms of the HNP success interrupt
1821 */
1822 if (!dwc2_hcd_is_b_host(hsotg)) {
1823 hprt0 |= HPRT0_PWR | HPRT0_RST;
1824 dev_dbg(hsotg->dev,
1825 "In host mode, hprt0=%08x\n", hprt0);
95c8bc36 1826 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1827 }
1828
1829 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1830 usleep_range(50000, 70000);
1831 hprt0 &= ~HPRT0_RST;
95c8bc36 1832 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1833 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1834 break;
1835
1836 case USB_PORT_FEAT_INDICATOR:
1837 dev_dbg(hsotg->dev,
1838 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1839 /* Not supported */
1840 break;
1841
96d480e6
JL		 1842 case USB_PORT_FEAT_TEST:
1843 hprt0 = dwc2_read_hprt0(hsotg);
1844 dev_dbg(hsotg->dev,
1845 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1846 hprt0 &= ~HPRT0_TSTCTL_MASK;
1847 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
95c8bc36 1848 dwc2_writel(hprt0, hsotg->regs + HPRT0);
96d480e6
JL		 1849 break;
1850
7359d482
PZ		 1851 default:
1852 retval = -EINVAL;
1853 dev_err(hsotg->dev,
1854 "SetPortFeature %1xh unknown or unsupported\n",
1855 wvalue);
1856 break;
1857 }
1858 break;
1859
1860 default:
1861error:
1862 retval = -EINVAL;
1863 dev_dbg(hsotg->dev,
1864 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1865 typereq, windex, wvalue);
1866 break;
1867 }
1868
1869 return retval;
1870}
1871
1872static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1873{
1874 int retval;
1875
7359d482
PZ		 1876 if (port != 1)
1877 return -EINVAL;
1878
1879 retval = (hsotg->flags.b.port_connect_status_change ||
1880 hsotg->flags.b.port_reset_change ||
1881 hsotg->flags.b.port_enable_change ||
1882 hsotg->flags.b.port_suspend_change ||
1883 hsotg->flags.b.port_over_current_change);
1884
1885 if (retval) {
1886 dev_dbg(hsotg->dev,
1887 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1888 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1889 hsotg->flags.b.port_connect_status_change);
1890 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1891 hsotg->flags.b.port_reset_change);
1892 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1893 hsotg->flags.b.port_enable_change);
1894 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1895 hsotg->flags.b.port_suspend_change);
1896 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1897 hsotg->flags.b.port_over_current_change);
1898 }
1899
1900 return retval;
1901}
1902
1903int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1904{
95c8bc36 1905 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
7359d482
PZ		 1906
1907#ifdef DWC2_DEBUG_SOF
1908 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
d6ec53e0 1909 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
7359d482 1910#endif
d6ec53e0 1911 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
7359d482
PZ		 1912}
1913
1914int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1915{
6bf2e2a5 1916 return hsotg->op_state == OTG_STATE_B_HOST;
7359d482
PZ		 1917}
1918
1919static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1920 int iso_desc_count,
1921 gfp_t mem_flags)
1922{
1923 struct dwc2_hcd_urb *urb;
1924 u32 size = sizeof(*urb) + iso_desc_count *
1925 sizeof(struct dwc2_hcd_iso_packet_desc);
1926
1927 urb = kzalloc(size, mem_flags);
1928 if (urb)
1929 urb->packet_count = iso_desc_count;
1930 return urb;
1931}
1932
1933static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1934 struct dwc2_hcd_urb *urb, u8 dev_addr,
1935 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1936{
b49977a6
MK		 1937 if (dbg_perio() ||
1938 ep_type == USB_ENDPOINT_XFER_BULK ||
1939 ep_type == USB_ENDPOINT_XFER_CONTROL)
1940 dev_vdbg(hsotg->dev,
1941 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1942 dev_addr, ep_num, ep_dir, ep_type, mps);
7359d482
PZ		 1943 urb->pipe_info.dev_addr = dev_addr;
1944 urb->pipe_info.ep_num = ep_num;
1945 urb->pipe_info.pipe_type = ep_type;
1946 urb->pipe_info.pipe_dir = ep_dir;
1947 urb->pipe_info.mps = mps;
1948}
1949
1950/*
1951 * NOTE: This function will be removed once the peripheral controller code
1952 * is integrated and the driver is stable
1953 */
1954void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1955{
1956#ifdef DEBUG
1957 struct dwc2_host_chan *chan;
1958 struct dwc2_hcd_urb *urb;
1959 struct dwc2_qtd *qtd;
1960 int num_channels;
1961 u32 np_tx_status;
1962 u32 p_tx_status;
1963 int i;
1964
1965 num_channels = hsotg->core_params->host_channels;
1966 dev_dbg(hsotg->dev, "\n");
1967 dev_dbg(hsotg->dev,
1968 "************************************************************\n");
1969 dev_dbg(hsotg->dev, "HCD State:\n");
1970 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1971
1972 for (i = 0; i < num_channels; i++) {
1973 chan = hsotg->hc_ptr_array[i];
1974 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1975 dev_dbg(hsotg->dev,
1976 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1977 chan->dev_addr, chan->ep_num, chan->ep_is_in);
1978 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1979 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1980 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1981 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1982 chan->data_pid_start);
1983 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1984 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1985 chan->xfer_started);
1986 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1987 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1988 (unsigned long)chan->xfer_dma);
1989 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1990 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1991 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1992 chan->halt_on_queue);
1993 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1994 chan->halt_pending);
1995 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1996 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1997 dev_dbg(hsotg->dev, " complete_split: %d\n",
1998 chan->complete_split);
1999 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
2000 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
2001 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
2002 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
2003 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
2004
2005 if (chan->xfer_started) {
2006 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
2007
95c8bc36
AS		 2008 hfnum = dwc2_readl(hsotg->regs + HFNUM);
2009 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2010 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
2011 hcint = dwc2_readl(hsotg->regs + HCINT(i));
2012 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
7359d482
PZ		 2013 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
2014 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
2015 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
2016 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
2017 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
2018 }
2019
2020 if (!(chan->xfer_started && chan->qh))
2021 continue;
2022
2023 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
2024 if (!qtd->in_process)
2025 break;
2026 urb = qtd->urb;
2027 dev_dbg(hsotg->dev, " URB Info:\n");
2028 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
2029 qtd, urb);
2030 if (urb) {
2031 dev_dbg(hsotg->dev,
2032 " Dev: %d, EP: %d %s\n",
2033 dwc2_hcd_get_dev_addr(&urb->pipe_info),
2034 dwc2_hcd_get_ep_num(&urb->pipe_info),
2035 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
2036 "IN" : "OUT");
2037 dev_dbg(hsotg->dev,
2038 " Max packet size: %d\n",
2039 dwc2_hcd_get_mps(&urb->pipe_info));
2040 dev_dbg(hsotg->dev,
2041 " transfer_buffer: %p\n",
2042 urb->buf);
157dfaac
PZ		 2043 dev_dbg(hsotg->dev,
2044 " transfer_dma: %08lx\n",
2045 (unsigned long)urb->dma);
7359d482
PZ		 2046 dev_dbg(hsotg->dev,
2047 " transfer_buffer_length: %d\n",
2048 urb->length);
2049 dev_dbg(hsotg->dev, " actual_length: %d\n",
2050 urb->actual_length);
2051 }
2052 }
2053 }
2054
2055 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
2056 hsotg->non_periodic_channels);
2057 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
2058 hsotg->periodic_channels);
2059 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
95c8bc36 2060 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
7359d482 2061 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
d6ec53e0 2062 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 2063 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
d6ec53e0 2064 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
95c8bc36 2065 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
7359d482 2066 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
d6ec53e0 2067 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 2068 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
d6ec53e0 2069 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
7359d482
PZ		 2070 dwc2_hcd_dump_frrem(hsotg);
2071 dwc2_dump_global_registers(hsotg);
2072 dwc2_dump_host_registers(hsotg);
2073 dev_dbg(hsotg->dev,
2074 "************************************************************\n");
2075 dev_dbg(hsotg->dev, "\n");
2076#endif
2077}
2078
2079/*
2080 * NOTE: This function will be removed once the peripheral controller code
2081 * is integrated and the driver is stable
2082 */
2083void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2084{
2085#ifdef DWC2_DUMP_FRREM
2086 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2087 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2088 hsotg->frrem_samples, hsotg->frrem_accum,
2089 hsotg->frrem_samples > 0 ?
2090 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2091 dev_dbg(hsotg->dev, "\n");
2092 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2093 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2094 hsotg->hfnum_7_samples,
2095 hsotg->hfnum_7_frrem_accum,
2096 hsotg->hfnum_7_samples > 0 ?
2097 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2098 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2099 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2100 hsotg->hfnum_0_samples,
2101 hsotg->hfnum_0_frrem_accum,
2102 hsotg->hfnum_0_samples > 0 ?
2103 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2104 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2105 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2106 hsotg->hfnum_other_samples,
2107 hsotg->hfnum_other_frrem_accum,
2108 hsotg->hfnum_other_samples > 0 ?
2109 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2110 0);
2111 dev_dbg(hsotg->dev, "\n");
2112 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2113 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2114 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2115 hsotg->hfnum_7_samples_a > 0 ?
2116 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2117 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2118 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2119 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2120 hsotg->hfnum_0_samples_a > 0 ?
2121 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2122 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2123 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2124 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2125 hsotg->hfnum_other_samples_a > 0 ?
2126 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2127 : 0);
2128 dev_dbg(hsotg->dev, "\n");
2129 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2130 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2131 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2132 hsotg->hfnum_7_samples_b > 0 ?
2133 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2134 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2135 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2136 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2137 (hsotg->hfnum_0_samples_b > 0) ?
2138 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2139 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2140 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2141 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2142 (hsotg->hfnum_other_samples_b > 0) ?
2143 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2144 : 0);
2145#endif
2146}
2147
2148struct wrapper_priv_data {
2149 struct dwc2_hsotg *hsotg;
2150};
2151
2152/* Gets the dwc2_hsotg from a usb_hcd */
2153static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2154{
2155 struct wrapper_priv_data *p;
2156
2157 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2158 return p->hsotg;
2159}
2160
2161static int _dwc2_hcd_start(struct usb_hcd *hcd);
2162
2163void dwc2_host_start(struct dwc2_hsotg *hsotg)
2164{
2165 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2166
2167 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2168 _dwc2_hcd_start(hcd);
2169}
2170
2171void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2172{
2173 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2174
2175 hcd->self.is_b_host = 0;
2176}
2177
2178void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2179 int *hub_port)
2180{
2181 struct urb *urb = context;
2182
2183 if (urb->dev->tt)
2184 *hub_addr = urb->dev->tt->hub->devnum;
2185 else
2186 *hub_addr = 0;
2187 *hub_port = urb->dev->ttport;
2188}
2189
2190int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2191{
2192 struct urb *urb = context;
2193
2194 return urb->dev->speed;
2195}
2196
2197static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2198 struct urb *urb)
2199{
2200 struct usb_bus *bus = hcd_to_bus(hcd);
2201
2202 if (urb->interval)
2203 bus->bandwidth_allocated += bw / urb->interval;
2204 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2205 bus->bandwidth_isoc_reqs++;
2206 else
2207 bus->bandwidth_int_reqs++;
2208}
2209
2210static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2211 struct urb *urb)
2212{
2213 struct usb_bus *bus = hcd_to_bus(hcd);
2214
2215 if (urb->interval)
2216 bus->bandwidth_allocated -= bw / urb->interval;
2217 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2218 bus->bandwidth_isoc_reqs--;
2219 else
2220 bus->bandwidth_int_reqs--;
2221}
2222
2223/*
2224 * Sets the final status of an URB and returns it to the upper layer. Any
2225 * required cleanup of the URB is performed.
2226 *
2227 * Must be called with interrupt disabled and spinlock held
2228 */
0d012b98
PZ		 2229void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2230 int status)
7359d482 2231{
0d012b98 2232 struct urb *urb;
7359d482
PZ		 2233 int i;
2234
0d012b98
PZ		 2235 if (!qtd) {
2236 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
7359d482
PZ		 2237 return;
2238 }
2239
0d012b98
PZ		 2240 if (!qtd->urb) {
2241 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
7359d482
PZ		 2242 return;
2243 }
2244
0d012b98
PZ		 2245 urb = qtd->urb->priv;
2246 if (!urb) {
2247 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2248 return;
2249 }
2250
2251 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
7359d482 2252
b49977a6
MK		 2253 if (dbg_urb(urb))
2254 dev_vdbg(hsotg->dev,
2255 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2256 __func__, urb, usb_pipedevice(urb->pipe),
2257 usb_pipeendpoint(urb->pipe),
2258 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2259 urb->actual_length);
7359d482 2260
7359d482
PZ		 2261
2262 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
0d012b98 2263 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
7359d482
PZ		 2264 for (i = 0; i < urb->number_of_packets; ++i) {
2265 urb->iso_frame_desc[i].actual_length =
2266 dwc2_hcd_urb_get_iso_desc_actual_length(
0d012b98 2267 qtd->urb, i);
7359d482 2268 urb->iso_frame_desc[i].status =
0d012b98 2269 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
7359d482
PZ		 2270 }
2271 }
2272
fe9b1773
GH		 2273 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2274 for (i = 0; i < urb->number_of_packets; i++)
2275 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2276 i, urb->iso_frame_desc[i].status);
2277 }
2278
7359d482 2279 urb->status = status;
7359d482
PZ		 2280 if (!status) {
2281 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2282 urb->actual_length < urb->transfer_buffer_length)
2283 urb->status = -EREMOTEIO;
2284 }
2285
2286 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2287 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2288 struct usb_host_endpoint *ep = urb->ep;
2289
2290 if (ep)
2291 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2292 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2293 urb);
2294 }
2295
c9e1c907 2296 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
0d012b98
PZ		 2297 urb->hcpriv = NULL;
2298 kfree(qtd->urb);
2299 qtd->urb = NULL;
7359d482
PZ		 2300
2301 spin_unlock(&hsotg->lock);
2302 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2303 spin_lock(&hsotg->lock);
2304}
2305
2306/*
2307 * Work queue function for starting the HCD when A-Cable is connected
2308 */
2309static void dwc2_hcd_start_func(struct work_struct *work)
2310{
2311 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2312 start_work.work);
2313
2314 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2315 dwc2_host_start(hsotg);
2316}
2317
2318/*
2319 * Reset work queue function
2320 */
2321static void dwc2_hcd_reset_func(struct work_struct *work)
2322{
2323 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2324 reset_work.work);
2325 u32 hprt0;
2326
2327 dev_dbg(hsotg->dev, "USB RESET function called\n");
2328 hprt0 = dwc2_read_hprt0(hsotg);
2329 hprt0 &= ~HPRT0_RST;
95c8bc36 2330 dwc2_writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 2331 hsotg->flags.b.port_reset_change = 1;
2332}
2333
2334/*
2335 * =========================================================================
2336 * Linux HC Driver Functions
2337 * =========================================================================
2338 */
2339
2340/*
2341 * Initializes the DWC_otg controller and its root hub and prepares it for host
2342 * mode operation. Activates the root port. Returns 0 on success and a negative
2343 * error code on failure.
2344 */
2345static int _dwc2_hcd_start(struct usb_hcd *hcd)
2346{
2347 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2348 struct usb_bus *bus = hcd_to_bus(hcd);
2349 unsigned long flags;
2350
2351 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2352
2353 spin_lock_irqsave(&hsotg->lock, flags);
31927b6b 2354 hsotg->lx_state = DWC2_L0;
7359d482 2355 hcd->state = HC_STATE_RUNNING;
31927b6b 2356 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
7359d482
PZ		 2357
2358 if (dwc2_is_device_mode(hsotg)) {
2359 spin_unlock_irqrestore(&hsotg->lock, flags);
2360 return 0; /* why 0 ?? */
2361 }
2362
2363 dwc2_hcd_reinit(hsotg);
2364
2365 /* Initialize and connect root hub if one is not already attached */
2366 if (bus->root_hub) {
2367 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2368 /* Inform the HUB driver to resume */
2369 usb_hcd_resume_root_hub(hcd);
2370 }
2371
2372 spin_unlock_irqrestore(&hsotg->lock, flags);
2373 return 0;
2374}
2375
2376/*
2377 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2378 * stopped.
2379 */
2380static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2381{
2382 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2383 unsigned long flags;
2384
5bbf6ce0
GH		 2385 /* Turn off all host-specific interrupts */
2386 dwc2_disable_host_interrupts(hsotg);
2387
091473ad
GH		 2388 /* Wait for interrupt processing to finish */
2389 synchronize_irq(hcd->irq);
2390
7359d482 2391 spin_lock_irqsave(&hsotg->lock, flags);
091473ad
GH		 2392 /* Ensure hcd is disconnected */
2393 dwc2_hcd_disconnect(hsotg);
7359d482 2394 dwc2_hcd_stop(hsotg);
31927b6b
GH		 2395 hsotg->lx_state = DWC2_L3;
2396 hcd->state = HC_STATE_HALT;
2397 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
7359d482
PZ		 2398 spin_unlock_irqrestore(&hsotg->lock, flags);
2399
2400 usleep_range(1000, 3000);
2401}
2402
99a65798
GH		 2403static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2404{
2405 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
a2a23d3f
GH		 2406 unsigned long flags;
2407 int ret = 0;
2408 u32 hprt0;
2409
2410 spin_lock_irqsave(&hsotg->lock, flags);
2411
2412 if (hsotg->lx_state != DWC2_L0)
2413 goto unlock;
2414
2415 if (!HCD_HW_ACCESSIBLE(hcd))
2416 goto unlock;
2417
2418 if (!hsotg->core_params->hibernation)
2419 goto skip_power_saving;
2420
2421 /*
2422 * Drive USB suspend and disable port Power
2423 * if usb bus is not suspended.
2424 */
2425 if (!hsotg->bus_suspended) {
2426 hprt0 = dwc2_read_hprt0(hsotg);
2427 hprt0 |= HPRT0_SUSP;
2428 hprt0 &= ~HPRT0_PWR;
2429 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2430 }
2431
2432 /* Enter hibernation */
2433 ret = dwc2_enter_hibernation(hsotg);
2434 if (ret) {
2435 if (ret != -ENOTSUPP)
2436 dev_err(hsotg->dev,
2437 "enter hibernation failed\n");
2438 goto skip_power_saving;
2439 }
2440
2441 /* Ask phy to be suspended */
2442 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2443 spin_unlock_irqrestore(&hsotg->lock, flags);
2444 usb_phy_set_suspend(hsotg->uphy, true);
2445 spin_lock_irqsave(&hsotg->lock, flags);
2446 }
2447
2448 /* After entering hibernation, hardware is no more accessible */
2449 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
99a65798 2450
a2a23d3f 2451skip_power_saving:
99a65798 2452 hsotg->lx_state = DWC2_L2;
a2a23d3f
GH		 2453unlock:
2454 spin_unlock_irqrestore(&hsotg->lock, flags);
2455
2456 return ret;
99a65798
GH		 2457}
2458
2459static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2460{
2461 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
a2a23d3f
GH		 2462 unsigned long flags;
2463 int ret = 0;
2464
2465 spin_lock_irqsave(&hsotg->lock, flags);
2466
2467 if (hsotg->lx_state != DWC2_L2)
2468 goto unlock;
2469
2470 if (!hsotg->core_params->hibernation) {
2471 hsotg->lx_state = DWC2_L0;
2472 goto unlock;
2473 }
2474
2475 /*
2476 * Set HW accessible bit before powering on the controller
2477 * since an interrupt may rise.
2478 */
2479 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2480
2481 /*
2482 * Enable power if not already done.
2483 * This must not be spinlocked since duration
2484 * of this call is unknown.
2485 */
2486 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2487 spin_unlock_irqrestore(&hsotg->lock, flags);
2488 usb_phy_set_suspend(hsotg->uphy, false);
2489 spin_lock_irqsave(&hsotg->lock, flags);
2490 }
2491
2492 /* Exit hibernation */
2493 ret = dwc2_exit_hibernation(hsotg, true);
2494 if (ret && (ret != -ENOTSUPP))
2495 dev_err(hsotg->dev, "exit hibernation failed\n");
99a65798
GH		 2496
2497 hsotg->lx_state = DWC2_L0;
a2a23d3f
GH		 2498
2499 spin_unlock_irqrestore(&hsotg->lock, flags);
2500
2501 if (hsotg->bus_suspended) {
2502 spin_lock_irqsave(&hsotg->lock, flags);
2503 hsotg->flags.b.port_suspend_change = 1;
2504 spin_unlock_irqrestore(&hsotg->lock, flags);
2505 dwc2_port_resume(hsotg);
2506 } else {
5634e016
GH		 2507 /* Wait for controller to correctly update D+/D- level */
2508 usleep_range(3000, 5000);
2509
a2a23d3f
GH		 2510 /*
2511 * Clear Port Enable and Port Status changes.
2512 * Enable Port Power.
2513 */
2514 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
2515 HPRT0_ENACHG, hsotg->regs + HPRT0);
2516 /* Wait for controller to detect Port Connect */
5634e016 2517 usleep_range(5000, 7000);
a2a23d3f
GH		 2518 }
2519
2520 return ret;
2521unlock:
2522 spin_unlock_irqrestore(&hsotg->lock, flags);
2523
2524 return ret;
99a65798
GH		 2525}
2526
7359d482
PZ		 2527/* Returns the current frame number */
2528static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2529{
2530 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2531
2532 return dwc2_hcd_get_frame_number(hsotg);
2533}
2534
2535static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2536 char *fn_name)
2537{
2538#ifdef VERBOSE_DEBUG
2539 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2540 char *pipetype;
2541 char *speed;
2542
2543 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2544 dev_vdbg(hsotg->dev, " Device address: %d\n",
2545 usb_pipedevice(urb->pipe));
2546 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2547 usb_pipeendpoint(urb->pipe),
2548 usb_pipein(urb->pipe) ? "IN" : "OUT");
2549
2550 switch (usb_pipetype(urb->pipe)) {
2551 case PIPE_CONTROL:
2552 pipetype = "CONTROL";
2553 break;
2554 case PIPE_BULK:
2555 pipetype = "BULK";
2556 break;
2557 case PIPE_INTERRUPT:
2558 pipetype = "INTERRUPT";
2559 break;
2560 case PIPE_ISOCHRONOUS:
2561 pipetype = "ISOCHRONOUS";
2562 break;
2563 default:
2564 pipetype = "UNKNOWN";
2565 break;
2566 }
2567
2568 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2569 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2570 "IN" : "OUT");
2571
2572 switch (urb->dev->speed) {
2573 case USB_SPEED_HIGH:
2574 speed = "HIGH";
2575 break;
2576 case USB_SPEED_FULL:
2577 speed = "FULL";
2578 break;
2579 case USB_SPEED_LOW:
2580 speed = "LOW";
2581 break;
2582 default:
2583 speed = "UNKNOWN";
2584 break;
2585 }
2586
2587 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2588 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2589 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2590 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2591 urb->transfer_buffer_length);
157dfaac
PZ		 2592 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2593 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2594 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2595 urb->setup_packet, (unsigned long)urb->setup_dma);
7359d482
PZ		 2596 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2597
2598 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2599 int i;
2600
2601 for (i = 0; i < urb->number_of_packets; i++) {
2602 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2603 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2604 urb->iso_frame_desc[i].offset,
2605 urb->iso_frame_desc[i].length);
2606 }
2607 }
2608#endif
2609}
2610
2611/*
2612 * Starts processing a USB transfer request specified by a USB Request Block
2613 * (URB). mem_flags indicates the type of memory allocation to use while
2614 * processing this URB.
2615 */
2616static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2617 gfp_t mem_flags)
2618{
2619 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2620 struct usb_host_endpoint *ep = urb->ep;
2621 struct dwc2_hcd_urb *dwc2_urb;
2622 int i;
c9e1c907 2623 int retval;
7359d482 2624 int alloc_bandwidth = 0;
7359d482
PZ		 2625 u8 ep_type = 0;
2626 u32 tflags = 0;
2627 void *buf;
2628 unsigned long flags;
b58e6cee
MYK		 2629 struct dwc2_qh *qh;
2630 bool qh_allocated = false;
b5a468a6 2631 struct dwc2_qtd *qtd;
7359d482 2632
b49977a6
MK		 2633 if (dbg_urb(urb)) {
2634 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2635 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2636 }
7359d482
PZ		 2637
2638 if (ep == NULL)
2639 return -EINVAL;
2640
2641 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2642 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2643 spin_lock_irqsave(&hsotg->lock, flags);
2644 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2645 alloc_bandwidth = 1;
2646 spin_unlock_irqrestore(&hsotg->lock, flags);
2647 }
2648
2649 switch (usb_pipetype(urb->pipe)) {
2650 case PIPE_CONTROL:
2651 ep_type = USB_ENDPOINT_XFER_CONTROL;
2652 break;
2653 case PIPE_ISOCHRONOUS:
2654 ep_type = USB_ENDPOINT_XFER_ISOC;
2655 break;
2656 case PIPE_BULK:
2657 ep_type = USB_ENDPOINT_XFER_BULK;
2658 break;
2659 case PIPE_INTERRUPT:
2660 ep_type = USB_ENDPOINT_XFER_INT;
2661 break;
2662 default:
2663 dev_warn(hsotg->dev, "Wrong ep type\n");
2664 }
2665
2666 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2667 mem_flags);
2668 if (!dwc2_urb)
2669 return -ENOMEM;
2670
2671 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2672 usb_pipeendpoint(urb->pipe), ep_type,
2673 usb_pipein(urb->pipe),
2674 usb_maxpacket(urb->dev, urb->pipe,
2675 !(usb_pipein(urb->pipe))));
2676
2677 buf = urb->transfer_buffer;
25a49445 2678
7359d482 2679 if (hcd->self.uses_dma) {
25a49445
PZ		 2680 if (!buf && (urb->transfer_dma & 3)) {
2681 dev_err(hsotg->dev,
2682 "%s: unaligned transfer with no transfer_buffer",
2683 __func__);
2684 retval = -EINVAL;
33ad261a 2685 goto fail0;
25a49445 2686 }
7359d482
PZ		 2687 }
2688
2689 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2690 tflags |= URB_GIVEBACK_ASAP;
2691 if (urb->transfer_flags & URB_ZERO_PACKET)
2692 tflags |= URB_SEND_ZERO_PACKET;
2693
2694 dwc2_urb->priv = urb;
2695 dwc2_urb->buf = buf;
2696 dwc2_urb->dma = urb->transfer_dma;
2697 dwc2_urb->length = urb->transfer_buffer_length;
2698 dwc2_urb->setup_packet = urb->setup_packet;
2699 dwc2_urb->setup_dma = urb->setup_dma;
2700 dwc2_urb->flags = tflags;
2701 dwc2_urb->interval = urb->interval;
2702 dwc2_urb->status = -EINPROGRESS;
2703
2704 for (i = 0; i < urb->number_of_packets; ++i)
2705 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2706 urb->iso_frame_desc[i].offset,
2707 urb->iso_frame_desc[i].length);
2708
2709 urb->hcpriv = dwc2_urb;
b58e6cee
MYK		 2710 qh = (struct dwc2_qh *) ep->hcpriv;
2711 /* Create QH for the endpoint if it doesn't exist */
2712 if (!qh) {
2713 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
2714 if (!qh) {
2715 retval = -ENOMEM;
2716 goto fail0;
2717 }
2718 ep->hcpriv = qh;
2719 qh_allocated = true;
2720 }
c9e1c907 2721
b5a468a6
MYK		 2722 qtd = kzalloc(sizeof(*qtd), mem_flags);
2723 if (!qtd) {
2724 retval = -ENOMEM;
2725 goto fail1;
2726 }
2727
c9e1c907
PZ		 2728 spin_lock_irqsave(&hsotg->lock, flags);
2729 retval = usb_hcd_link_urb_to_ep(hcd, urb);
c9e1c907 2730 if (retval)
b5a468a6 2731 goto fail2;
c9e1c907 2732
b5a468a6 2733 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
c9e1c907 2734 if (retval)
b5a468a6 2735 goto fail3;
c9e1c907
PZ		 2736
2737 if (alloc_bandwidth) {
c9e1c907
PZ		 2738 dwc2_allocate_bus_bandwidth(hcd,
2739 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2740 urb);
7359d482
PZ		 2741 }
2742
33ad261a
GH		 2743 spin_unlock_irqrestore(&hsotg->lock, flags);
2744
c9e1c907
PZ		 2745 return 0;
2746
b5a468a6 2747fail3:
c9e1c907
PZ		 2748 dwc2_urb->priv = NULL;
2749 usb_hcd_unlink_urb_from_ep(hcd, urb);
b5a468a6 2750fail2:
33ad261a 2751 spin_unlock_irqrestore(&hsotg->lock, flags);
c9e1c907 2752 urb->hcpriv = NULL;
b5a468a6
MYK		 2753 kfree(qtd);
2754fail1:
b58e6cee
MYK		 2755 if (qh_allocated) {
2756 struct dwc2_qtd *qtd2, *qtd2_tmp;
2757
2758 ep->hcpriv = NULL;
2759 dwc2_hcd_qh_unlink(hsotg, qh);
2760 /* Free each QTD in the QH's QTD list */
2761 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
2762 qtd_list_entry)
2763 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
2764 dwc2_hcd_qh_free(hsotg, qh);
2765 }
33ad261a 2766fail0:
c9e1c907
PZ		 2767 kfree(dwc2_urb);
2768
7359d482
PZ		 2769 return retval;
2770}
2771
2772/*
2773 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2774 */
2775static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2776 int status)
2777{
2778 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
c9e1c907 2779 int rc;
7359d482
PZ		 2780 unsigned long flags;
2781
2782 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2783 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2784
2785 spin_lock_irqsave(&hsotg->lock, flags);
2786
c9e1c907
PZ		 2787 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2788 if (rc)
2789 goto out;
2790
7359d482
PZ		 2791 if (!urb->hcpriv) {
2792 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2793 goto out;
2794 }
2795
2796 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2797
c9e1c907
PZ		 2798 usb_hcd_unlink_urb_from_ep(hcd, urb);
2799
7359d482
PZ		 2800 kfree(urb->hcpriv);
2801 urb->hcpriv = NULL;
2802
2803 /* Higher layer software sets URB status */
2804 spin_unlock(&hsotg->lock);
2805 usb_hcd_giveback_urb(hcd, urb, status);
2806 spin_lock(&hsotg->lock);
2807
2808 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2809 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2810out:
2811 spin_unlock_irqrestore(&hsotg->lock, flags);
2812
2813 return rc;
2814}
2815
2816/*
2817 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2818 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2819 * must already be dequeued.
2820 */
2821static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2822 struct usb_host_endpoint *ep)
2823{
2824 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2825
2826 dev_dbg(hsotg->dev,
2827 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2828 ep->desc.bEndpointAddress, ep->hcpriv);
2829 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2830}
2831
2832/*
2833 * Resets endpoint specific parameter values, in current version used to reset
2834 * the data toggle (as a WA). This function can be called from usb_clear_halt
2835 * routine.
2836 */
2837static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2838 struct usb_host_endpoint *ep)
2839{
2840 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482
PZ		 2841 unsigned long flags;
2842
2843 dev_dbg(hsotg->dev,
2844 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2845 ep->desc.bEndpointAddress);
2846
7359d482 2847 spin_lock_irqsave(&hsotg->lock, flags);
7359d482 2848 dwc2_hcd_endpoint_reset(hsotg, ep);
7359d482
PZ		 2849 spin_unlock_irqrestore(&hsotg->lock, flags);
2850}
2851
2852/*
2853 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2854 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2855 * interrupt.
2856 *
2857 * This function is called by the USB core when an interrupt occurs
2858 */
2859static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2860{
2861 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482 2862
ca18f4a6 2863 return dwc2_handle_hcd_intr(hsotg);
7359d482
PZ		 2864}
2865
2866/*
2867 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2868 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2869 * is the status change indicator for the single root port. Returns 1 if either
2870 * change indicator is 1, otherwise returns 0.
2871 */
2872static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2873{
2874 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2875
2876 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2877 return buf[0] != 0;
2878}
2879
2880/* Handles hub class-specific requests */
2881static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2882 u16 windex, char *buf, u16 wlength)
2883{
2884 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2885 wvalue, windex, buf, wlength);
2886 return retval;
2887}
2888
2889/* Handles hub TT buffer clear completions */
2890static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2891 struct usb_host_endpoint *ep)
2892{
2893 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2894 struct dwc2_qh *qh;
2895 unsigned long flags;
2896
2897 qh = ep->hcpriv;
2898 if (!qh)
2899 return;
2900
2901 spin_lock_irqsave(&hsotg->lock, flags);
2902 qh->tt_buffer_dirty = 0;
2903
2904 if (hsotg->flags.b.port_connect_status)
2905 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2906
2907 spin_unlock_irqrestore(&hsotg->lock, flags);
2908}
2909
2910static struct hc_driver dwc2_hc_driver = {
2911 .description = "dwc2_hsotg",
2912 .product_desc = "DWC OTG Controller",
2913 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2914
2915 .irq = _dwc2_hcd_irq,
2916 .flags = HCD_MEMORY | HCD_USB2,
2917
2918 .start = _dwc2_hcd_start,
2919 .stop = _dwc2_hcd_stop,
2920 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2921 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2922 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2923 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2924 .get_frame_number = _dwc2_hcd_get_frame_number,
2925
2926 .hub_status_data = _dwc2_hcd_hub_status_data,
2927 .hub_control = _dwc2_hcd_hub_control,
2928 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
99a65798
GH		 2929
2930 .bus_suspend = _dwc2_hcd_suspend,
2931 .bus_resume = _dwc2_hcd_resume,
7359d482
PZ		 2932};
2933
2934/*
2935 * Frees secondary storage associated with the dwc2_hsotg structure contained
2936 * in the struct usb_hcd field
2937 */
2938static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2939{
2940 u32 ahbcfg;
2941 u32 dctl;
2942 int i;
2943
2944 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2945
2946 /* Free memory for QH/QTD lists */
2947 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2948 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2949 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2950 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2951 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2952 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2953
2954 /* Free memory for the host channels */
2955 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2956 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2957
2958 if (chan != NULL) {
2959 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2960 i, chan);
2961 hsotg->hc_ptr_array[i] = NULL;
2962 kfree(chan);
2963 }
2964 }
2965
2966 if (hsotg->core_params->dma_enable > 0) {
2967 if (hsotg->status_buf) {
2968 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2969 hsotg->status_buf,
2970 hsotg->status_buf_dma);
2971 hsotg->status_buf = NULL;
2972 }
2973 } else {
2974 kfree(hsotg->status_buf);
2975 hsotg->status_buf = NULL;
2976 }
2977
95c8bc36 2978 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
7359d482
PZ		 2979
2980 /* Disable all interrupts */
2981 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
95c8bc36
AS		 2982 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
2983 dwc2_writel(0, hsotg->regs + GINTMSK);
7359d482 2984
9badec2f 2985 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
95c8bc36 2986 dctl = dwc2_readl(hsotg->regs + DCTL);
7359d482 2987 dctl |= DCTL_SFTDISCON;
95c8bc36 2988 dwc2_writel(dctl, hsotg->regs + DCTL);
7359d482
PZ		 2989 }
2990
2991 if (hsotg->wq_otg) {
2992 if (!cancel_work_sync(&hsotg->wf_otg))
2993 flush_workqueue(hsotg->wq_otg);
2994 destroy_workqueue(hsotg->wq_otg);
2995 }
2996
7359d482
PZ		 2997 del_timer(&hsotg->wkp_timer);
2998}
2999
3000static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
3001{
3002 /* Turn off all host-specific interrupts */
3003 dwc2_disable_host_interrupts(hsotg);
3004
3005 dwc2_hcd_free(hsotg);
3006}
3007
7359d482
PZ		 3008/*
3009 * Initializes the HCD. This function allocates memory for and initializes the
3010 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
3011 * USB bus with the core and calls the hc_driver->start() function. It returns
3012 * a negative error on failure.
3013 */
ecb176c6 3014int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
7359d482
PZ		 3015{
3016 struct usb_hcd *hcd;
3017 struct dwc2_host_chan *channel;
9badec2f 3018 u32 hcfg;
7359d482 3019 int i, num_channels;
9badec2f 3020 int retval;
7359d482 3021
f5500ecc
DN		 3022 if (usb_disabled())
3023 return -ENODEV;
3024
e62662c7 3025 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
7359d482 3026
9badec2f 3027 retval = -ENOMEM;
7359d482 3028
95c8bc36 3029 hcfg = dwc2_readl(hsotg->regs + HCFG);
7359d482 3030 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
7359d482
PZ		 3031
3032#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3033 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
3034 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3035 if (!hsotg->frame_num_array)
ba0e60d1 3036 goto error1;
7359d482
PZ		 3037 hsotg->last_frame_num_array = kzalloc(
3038 sizeof(*hsotg->last_frame_num_array) *
3039 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3040 if (!hsotg->last_frame_num_array)
ba0e60d1 3041 goto error1;
7359d482
PZ		 3042 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
3043#endif
3044
a0112f48
MK		 3045 /* Check if the bus driver or platform code has setup a dma_mask */
3046 if (hsotg->core_params->dma_enable > 0 &&
3047 hsotg->dev->dma_mask == NULL) {
3048 dev_warn(hsotg->dev,
3049 "dma_mask not set, disabling DMA\n");
3050 hsotg->core_params->dma_enable = 0;
3051 hsotg->core_params->dma_desc_enable = 0;
3052 }
3053
ba0e60d1
PZ		 3054 /* Set device flags indicating whether the HCD supports DMA */
3055 if (hsotg->core_params->dma_enable > 0) {
30885313
PZ		 3056 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3057 dev_warn(hsotg->dev, "can't set DMA mask\n");
25a49445
PZ		 3058 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3059 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
ba0e60d1
PZ		 3060 }
3061
3062 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
3063 if (!hcd)
3064 goto error1;
3065
7de76ee1
MK		 3066 if (hsotg->core_params->dma_enable <= 0)
3067 hcd->self.uses_dma = 0;
3068
ba0e60d1
PZ		 3069 hcd->has_tt = 1;
3070
ba0e60d1
PZ		 3071 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
3072 hsotg->priv = hcd;
3073
7359d482
PZ		 3074 /*
3075 * Disable the global interrupt until all the interrupt handlers are
3076 * installed
3077 */
3078 dwc2_disable_global_interrupts(hsotg);
3079
6706c721
MK		 3080 /* Initialize the DWC_otg core, and select the Phy type */
3081 retval = dwc2_core_init(hsotg, true, irq);
3082 if (retval)
3083 goto error2;
3084
7359d482 3085 /* Create new workqueue and init work */
53510352 3086 retval = -ENOMEM;
050232a7 3087 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
7359d482
PZ		 3088 if (!hsotg->wq_otg) {
3089 dev_err(hsotg->dev, "Failed to create workqueue\n");
3090 goto error2;
3091 }
3092 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
3093
7359d482
PZ		 3094 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
3095 (unsigned long)hsotg);
3096
3097 /* Initialize the non-periodic schedule */
3098 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
3099 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
3100
3101 /* Initialize the periodic schedule */
3102 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
3103 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
3104 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
3105 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
3106
3107 /*
3108 * Create a host channel descriptor for each host channel implemented
3109 * in the controller. Initialize the channel descriptor array.
3110 */
3111 INIT_LIST_HEAD(&hsotg->free_hc_list);
3112 num_channels = hsotg->core_params->host_channels;
3113 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
3114
3115 for (i = 0; i < num_channels; i++) {
3116 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3117 if (channel == NULL)
3118 goto error3;
3119 channel->hc_num = i;
3120 hsotg->hc_ptr_array[i] = channel;
3121 }
3122
20f2eb9c
DC		 3123 if (hsotg->core_params->uframe_sched > 0)
3124 dwc2_hcd_init_usecs(hsotg);
3125
7359d482
PZ		 3126 /* Initialize hsotg start work */
3127 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
3128
3129 /* Initialize port reset work */
3130 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
3131
3132 /*
3133 * Allocate space for storing data on status transactions. Normally no
3134 * data is sent, but this space acts as a bit bucket. This must be
3135 * done after usb_add_hcd since that function allocates the DMA buffer
3136 * pool.
3137 */
3138 if (hsotg->core_params->dma_enable > 0)
3139 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
3140 DWC2_HCD_STATUS_BUF_SIZE,
3141 &hsotg->status_buf_dma, GFP_KERNEL);
3142 else
3143 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
3144 GFP_KERNEL);
3145
3146 if (!hsotg->status_buf)
3147 goto error3;
3148
3149 hsotg->otg_port = 1;
3150 hsotg->frame_list = NULL;
3151 hsotg->frame_list_dma = 0;
3152 hsotg->periodic_qh_count = 0;
3153
3154 /* Initiate lx_state to L3 disconnected state */
3155 hsotg->lx_state = DWC2_L3;
3156
3157 hcd->self.otg_port = hsotg->otg_port;
3158
3159 /* Don't support SG list at this point */
3160 hcd->self.sg_tablesize = 0;
3161
9df4ceac
MYK		 3162 if (!IS_ERR_OR_NULL(hsotg->uphy))
3163 otg_set_host(hsotg->uphy->otg, &hcd->self);
3164
7359d482
PZ		 3165 /*
3166 * Finish generic HCD initialization and start the HCD. This function
3167 * allocates the DMA buffer pool, registers the USB bus, requests the
3168 * IRQ line, and calls hcd_start method.
3169 */
66513f49 3170 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
7359d482
PZ		 3171 if (retval < 0)
3172 goto error3;
3173
3c9740a1
PC		 3174 device_wakeup_enable(hcd->self.controller);
3175
7359d482
PZ		 3176 dwc2_hcd_dump_state(hsotg);
3177
3178 dwc2_enable_global_interrupts(hsotg);
3179
3180 return 0;
3181
3182error3:
3183 dwc2_hcd_release(hsotg);
3184error2:
ba0e60d1
PZ		 3185 usb_put_hcd(hcd);
3186error1:
7359d482
PZ		 3187 kfree(hsotg->core_params);
3188
3189#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3190 kfree(hsotg->last_frame_num_array);
3191 kfree(hsotg->frame_num_array);
3192#endif
3193
e62662c7 3194 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
7359d482
PZ		 3195 return retval;
3196}
7359d482
PZ		 3197
3198/*
3199 * Removes the HCD.
3200 * Frees memory and resources associated with the HCD and deregisters the bus.
3201 */
e62662c7 3202void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
7359d482
PZ		 3203{
3204 struct usb_hcd *hcd;
3205
e62662c7 3206 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
7359d482
PZ		 3207
3208 hcd = dwc2_hsotg_to_hcd(hsotg);
e62662c7 3209 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
7359d482
PZ		 3210
3211 if (!hcd) {
e62662c7 3212 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
7359d482
PZ		 3213 __func__);
3214 return;
3215 }
3216
9df4ceac
MYK		 3217 if (!IS_ERR_OR_NULL(hsotg->uphy))
3218 otg_set_host(hsotg->uphy->otg, NULL);
3219
7359d482
PZ		 3220 usb_remove_hcd(hcd);
3221 hsotg->priv = NULL;
3222 dwc2_hcd_release(hsotg);
ba0e60d1 3223 usb_put_hcd(hcd);
7359d482
PZ		 3224
3225#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3226 kfree(hsotg->last_frame_num_array);
3227 kfree(hsotg->frame_num_array);
3228#endif
7359d482 3229}
Linux kernel - Deliverables
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