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usb: musb: add omap-control dependency
[deliverable/linux.git] / drivers / usb / dwc2 / hcd.c
CommitLineData
7359d482
PZ		 1/*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/spinlock.h>
44#include <linux/interrupt.h>
45#include <linux/dma-mapping.h>
46#include <linux/delay.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57/**
58 * dwc2_dump_channel_info() - Prints the state of a host channel
59 *
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
62 *
63 * Must be called with interrupt disabled and spinlock held
64 *
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
67 */
68static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
70{
71#ifdef VERBOSE_DEBUG
72 int num_channels = hsotg->core_params->host_channels;
73 struct dwc2_qh *qh;
74 u32 hcchar;
75 u32 hcsplt;
76 u32 hctsiz;
77 u32 hc_dma;
78 int i;
79
80 if (chan == NULL)
81 return;
82
83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
87
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
90 hcchar, hcsplt);
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
92 hctsiz, hc_dma);
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
107 qh_list_entry)
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
111 qh_list_entry)
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
116
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
118 }
119#endif /* VERBOSE_DEBUG */
120}
121
122/*
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
125 *
126 * Must be called with interrupt disabled and spinlock held
127 */
128static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
130{
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
133
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
136 qtd_list_entry) {
0d012b98
PZ		 137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
7359d482
PZ		 139 }
140 }
141}
142
143static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
145{
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
148 unsigned long flags;
149
150 if (!qh_list->next)
151 /* The list hasn't been initialized yet */
152 return;
153
154 spin_lock_irqsave(&hsotg->lock, flags);
155
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
158
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
161
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
164 qtd_list_entry)
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
166
167 spin_unlock_irqrestore(&hsotg->lock, flags);
168 dwc2_hcd_qh_free(hsotg, qh);
169 spin_lock_irqsave(&hsotg->lock, flags);
170 }
171
172 spin_unlock_irqrestore(&hsotg->lock, flags);
173}
174
175/*
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
180 *
181 * Must be called with interrupt disabled and spinlock held
182 */
183static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
184{
185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
191}
192
193/**
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
195 *
196 * @hsotg: Pointer to struct dwc2_hsotg
197 */
198void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
199{
200 u32 hprt0;
201
202 if (hsotg->op_state == OTG_STATE_B_HOST) {
203 /*
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
206 * least 50ms.
207 */
208 hprt0 = dwc2_read_hprt0(hsotg);
209 hprt0 |= HPRT0_RST;
210 writel(hprt0, hsotg->regs + HPRT0);
211 }
212
213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 msecs_to_jiffies(50));
215}
216
217/* Must be called with interrupt disabled and spinlock held */
218static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
219{
220 int num_channels = hsotg->core_params->host_channels;
221 struct dwc2_host_chan *channel;
222 u32 hcchar;
223 int i;
224
225 if (hsotg->core_params->dma_enable <= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i = 0; i < num_channels; i++) {
228 channel = hsotg->hc_ptr_array[i];
229 if (!list_empty(&channel->hc_list_entry))
230 continue;
231 hcchar = readl(hsotg->regs + HCCHAR(i));
232 if (hcchar & HCCHAR_CHENA) {
233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 hcchar |= HCCHAR_CHDIS;
235 writel(hcchar, hsotg->regs + HCCHAR(i));
236 }
237 }
238 }
239
240 for (i = 0; i < num_channels; i++) {
241 channel = hsotg->hc_ptr_array[i];
242 if (!list_empty(&channel->hc_list_entry))
243 continue;
244 hcchar = readl(hsotg->regs + HCCHAR(i));
245 if (hcchar & HCCHAR_CHENA) {
246 /* Halt the channel */
247 hcchar |= HCCHAR_CHDIS;
248 writel(hcchar, hsotg->regs + HCCHAR(i));
249 }
250
251 dwc2_hc_cleanup(hsotg, channel);
252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
253 /*
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
256 * device disconnects
257 */
258 channel->qh = NULL;
259 }
260}
261
262/**
263 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
264 *
265 * @hsotg: Pointer to struct dwc2_hsotg
266 *
267 * Must be called with interrupt disabled and spinlock held
268 */
269void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
270{
271 u32 intr;
272
273 /* Set status flags for the hub driver */
274 hsotg->flags.b.port_connect_status_change = 1;
275 hsotg->flags.b.port_connect_status = 0;
276
277 /*
278 * Shutdown any transfers in process by clearing the Tx FIFO Empty
279 * interrupt mask and status bits and disabling subsequent host
280 * channel interrupts.
281 */
282 intr = readl(hsotg->regs + GINTMSK);
283 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
284 writel(intr, hsotg->regs + GINTMSK);
285 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
286 writel(intr, hsotg->regs + GINTSTS);
287
288 /*
289 * Turn off the vbus power only if the core has transitioned to device
290 * mode. If still in host mode, need to keep power on to detect a
291 * reconnection.
292 */
293 if (dwc2_is_device_mode(hsotg)) {
294 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
295 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
296 writel(0, hsotg->regs + HPRT0);
297 }
298
299 dwc2_disable_host_interrupts(hsotg);
300 }
301
302 /* Respond with an error status to all URBs in the schedule */
303 dwc2_kill_all_urbs(hsotg);
304
305 if (dwc2_is_host_mode(hsotg))
306 /* Clean up any host channels that were in use */
307 dwc2_hcd_cleanup_channels(hsotg);
308
309 dwc2_host_disconnect(hsotg);
310}
311
312/**
313 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
314 *
315 * @hsotg: Pointer to struct dwc2_hsotg
316 */
317static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
318{
319 if (hsotg->lx_state == DWC2_L2)
320 hsotg->flags.b.port_suspend_change = 1;
321 else
322 hsotg->flags.b.port_l1_change = 1;
323}
324
325/**
326 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
327 *
328 * @hsotg: Pointer to struct dwc2_hsotg
329 *
330 * Must be called with interrupt disabled and spinlock held
331 */
332void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
333{
334 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
335
336 /*
337 * The root hub should be disconnected before this function is called.
338 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
339 * and the QH lists (via ..._hcd_endpoint_disable).
340 */
341
342 /* Turn off all host-specific interrupts */
343 dwc2_disable_host_interrupts(hsotg);
344
345 /* Turn off the vbus power */
346 dev_dbg(hsotg->dev, "PortPower off\n");
347 writel(0, hsotg->regs + HPRT0);
348}
349
350static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
351 struct dwc2_hcd_urb *urb, void **ep_handle,
352 gfp_t mem_flags)
353{
354 struct dwc2_qtd *qtd;
355 unsigned long flags;
356 u32 intr_mask;
357 int retval;
9f8144c6 358 int dev_speed;
7359d482
PZ		 359
360 if (!hsotg->flags.b.port_connect_status) {
361 /* No longer connected */
362 dev_err(hsotg->dev, "Not connected\n");
363 return -ENODEV;
364 }
365
9f8144c6
NH		 366 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
367
368 /* Some configurations cannot support LS traffic on a FS root port */
369 if ((dev_speed == USB_SPEED_LOW) &&
370 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
371 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
372 u32 hprt0 = readl(hsotg->regs + HPRT0);
373 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
374
375 if (prtspd == HPRT0_SPD_FULL_SPEED)
376 return -ENODEV;
377 }
378
7359d482
PZ		 379 qtd = kzalloc(sizeof(*qtd), mem_flags);
380 if (!qtd)
381 return -ENOMEM;
382
383 dwc2_hcd_qtd_init(qtd, urb);
384 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
385 mem_flags);
9bda1aac 386 if (retval) {
7359d482
PZ		 387 dev_err(hsotg->dev,
388 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
389 retval);
390 kfree(qtd);
391 return retval;
392 }
393
394 intr_mask = readl(hsotg->regs + GINTMSK);
9bda1aac 395 if (!(intr_mask & GINTSTS_SOF)) {
7359d482
PZ		 396 enum dwc2_transaction_type tr_type;
397
398 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
399 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
400 /*
401 * Do not schedule SG transactions until qtd has
402 * URB_GIVEBACK_ASAP set
403 */
404 return 0;
405
406 spin_lock_irqsave(&hsotg->lock, flags);
407 tr_type = dwc2_hcd_select_transactions(hsotg);
408 if (tr_type != DWC2_TRANSACTION_NONE)
409 dwc2_hcd_queue_transactions(hsotg, tr_type);
410 spin_unlock_irqrestore(&hsotg->lock, flags);
411 }
412
9bda1aac 413 return 0;
7359d482
PZ		 414}
415
416/* Must be called with interrupt disabled and spinlock held */
417static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
418 struct dwc2_hcd_urb *urb)
419{
420 struct dwc2_qh *qh;
421 struct dwc2_qtd *urb_qtd;
422
423 urb_qtd = urb->qtd;
424 if (!urb_qtd) {
425 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
426 return -EINVAL;
427 }
428
429 qh = urb_qtd->qh;
430 if (!qh) {
431 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
432 return -EINVAL;
433 }
434
0d012b98
PZ		 435 urb->priv = NULL;
436
7359d482
PZ		 437 if (urb_qtd->in_process && qh->channel) {
438 dwc2_dump_channel_info(hsotg, qh->channel);
439
440 /* The QTD is in process (it has been assigned to a channel) */
441 if (hsotg->flags.b.port_connect_status)
442 /*
443 * If still connected (i.e. in host mode), halt the
444 * channel so it can be used for other transfers. If
445 * no longer connected, the host registers can't be
446 * written to halt the channel since the core is in
447 * device mode.
448 */
449 dwc2_hc_halt(hsotg, qh->channel,
450 DWC2_HC_XFER_URB_DEQUEUE);
451 }
452
453 /*
454 * Free the QTD and clean up the associated QH. Leave the QH in the
455 * schedule if it has any remaining QTDs.
456 */
457 if (hsotg->core_params->dma_desc_enable <= 0) {
458 u8 in_process = urb_qtd->in_process;
459
460 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
461 if (in_process) {
462 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
463 qh->channel = NULL;
464 } else if (list_empty(&qh->qtd_list)) {
465 dwc2_hcd_qh_unlink(hsotg, qh);
466 }
467 } else {
468 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
469 }
470
471 return 0;
472}
473
474/* Must NOT be called with interrupt disabled or spinlock held */
475static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
476 struct usb_host_endpoint *ep, int retry)
477{
478 struct dwc2_qtd *qtd, *qtd_tmp;
479 struct dwc2_qh *qh;
480 unsigned long flags;
481 int rc;
482
483 spin_lock_irqsave(&hsotg->lock, flags);
484
485 qh = ep->hcpriv;
486 if (!qh) {
487 rc = -EINVAL;
488 goto err;
489 }
490
491 while (!list_empty(&qh->qtd_list) && retry--) {
492 if (retry == 0) {
493 dev_err(hsotg->dev,
494 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
495 rc = -EBUSY;
496 goto err;
497 }
498
499 spin_unlock_irqrestore(&hsotg->lock, flags);
500 usleep_range(20000, 40000);
501 spin_lock_irqsave(&hsotg->lock, flags);
502 qh = ep->hcpriv;
503 if (!qh) {
504 rc = -EINVAL;
505 goto err;
506 }
507 }
508
509 dwc2_hcd_qh_unlink(hsotg, qh);
510
511 /* Free each QTD in the QH's QTD list */
512 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
513 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
514
515 ep->hcpriv = NULL;
516 spin_unlock_irqrestore(&hsotg->lock, flags);
517 dwc2_hcd_qh_free(hsotg, qh);
518
519 return 0;
520
521err:
522 ep->hcpriv = NULL;
523 spin_unlock_irqrestore(&hsotg->lock, flags);
524
525 return rc;
526}
527
528/* Must be called with interrupt disabled and spinlock held */
529static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
530 struct usb_host_endpoint *ep)
531{
532 struct dwc2_qh *qh = ep->hcpriv;
533
534 if (!qh)
535 return -EINVAL;
536
537 qh->data_toggle = DWC2_HC_PID_DATA0;
538
539 return 0;
540}
541
542/*
543 * Initializes dynamic portions of the DWC_otg HCD state
544 *
545 * Must be called with interrupt disabled and spinlock held
546 */
547static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
548{
549 struct dwc2_host_chan *chan, *chan_tmp;
550 int num_channels;
551 int i;
552
553 hsotg->flags.d32 = 0;
7359d482 554 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
20f2eb9c
DC		 555
556 if (hsotg->core_params->uframe_sched > 0) {
557 hsotg->available_host_channels =
558 hsotg->core_params->host_channels;
559 } else {
560 hsotg->non_periodic_channels = 0;
561 hsotg->periodic_channels = 0;
562 }
7359d482
PZ		 563
564 /*
565 * Put all channels in the free channel list and clean up channel
566 * states
567 */
568 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
569 hc_list_entry)
570 list_del_init(&chan->hc_list_entry);
571
572 num_channels = hsotg->core_params->host_channels;
573 for (i = 0; i < num_channels; i++) {
574 chan = hsotg->hc_ptr_array[i];
575 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
576 dwc2_hc_cleanup(hsotg, chan);
577 }
578
579 /* Initialize the DWC core for host mode operation */
580 dwc2_core_host_init(hsotg);
581}
582
583static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
584 struct dwc2_host_chan *chan,
585 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
586{
587 int hub_addr, hub_port;
588
589 chan->do_split = 1;
590 chan->xact_pos = qtd->isoc_split_pos;
591 chan->complete_split = qtd->complete_split;
592 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
593 chan->hub_addr = (u8)hub_addr;
594 chan->hub_port = (u8)hub_port;
595}
596
597static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
598 struct dwc2_host_chan *chan,
599 struct dwc2_qtd *qtd, void *bufptr)
600{
601 struct dwc2_hcd_urb *urb = qtd->urb;
602 struct dwc2_hcd_iso_packet_desc *frame_desc;
603
604 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
605 case USB_ENDPOINT_XFER_CONTROL:
606 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
607
608 switch (qtd->control_phase) {
609 case DWC2_CONTROL_SETUP:
610 dev_vdbg(hsotg->dev, " Control setup transaction\n");
611 chan->do_ping = 0;
612 chan->ep_is_in = 0;
613 chan->data_pid_start = DWC2_HC_PID_SETUP;
614 if (hsotg->core_params->dma_enable > 0)
615 chan->xfer_dma = urb->setup_dma;
616 else
617 chan->xfer_buf = urb->setup_packet;
618 chan->xfer_len = 8;
619 bufptr = NULL;
620 break;
621
622 case DWC2_CONTROL_DATA:
623 dev_vdbg(hsotg->dev, " Control data transaction\n");
624 chan->data_pid_start = qtd->data_toggle;
625 break;
626
627 case DWC2_CONTROL_STATUS:
628 /*
629 * Direction is opposite of data direction or IN if no
630 * data
631 */
632 dev_vdbg(hsotg->dev, " Control status transaction\n");
633 if (urb->length == 0)
634 chan->ep_is_in = 1;
635 else
636 chan->ep_is_in =
637 dwc2_hcd_is_pipe_out(&urb->pipe_info);
638 if (chan->ep_is_in)
639 chan->do_ping = 0;
640 chan->data_pid_start = DWC2_HC_PID_DATA1;
641 chan->xfer_len = 0;
642 if (hsotg->core_params->dma_enable > 0)
643 chan->xfer_dma = hsotg->status_buf_dma;
644 else
645 chan->xfer_buf = hsotg->status_buf;
646 bufptr = NULL;
647 break;
648 }
649 break;
650
651 case USB_ENDPOINT_XFER_BULK:
652 chan->ep_type = USB_ENDPOINT_XFER_BULK;
653 break;
654
655 case USB_ENDPOINT_XFER_INT:
656 chan->ep_type = USB_ENDPOINT_XFER_INT;
657 break;
658
659 case USB_ENDPOINT_XFER_ISOC:
660 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
661 if (hsotg->core_params->dma_desc_enable > 0)
662 break;
663
664 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
665 frame_desc->status = 0;
666
667 if (hsotg->core_params->dma_enable > 0) {
668 chan->xfer_dma = urb->dma;
669 chan->xfer_dma += frame_desc->offset +
670 qtd->isoc_split_offset;
671 } else {
672 chan->xfer_buf = urb->buf;
673 chan->xfer_buf += frame_desc->offset +
674 qtd->isoc_split_offset;
675 }
676
677 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
678
679 /* For non-dword aligned buffers */
680 if (hsotg->core_params->dma_enable > 0 &&
681 (chan->xfer_dma & 0x3))
682 bufptr = (u8 *)urb->buf + frame_desc->offset +
683 qtd->isoc_split_offset;
684 else
685 bufptr = NULL;
686
687 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
688 if (chan->xfer_len <= 188)
689 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
690 else
691 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
692 }
693 break;
694 }
695
696 return bufptr;
697}
698
699static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
5dce9555
PZ		 700 struct dwc2_host_chan *chan,
701 struct dwc2_hcd_urb *urb, void *bufptr)
7359d482
PZ		 702{
703 u32 buf_size;
5dce9555
PZ		 704 struct urb *usb_urb;
705 struct usb_hcd *hcd;
7359d482
PZ		 706
707 if (!qh->dw_align_buf) {
5dce9555
PZ		 708 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
709 buf_size = hsotg->core_params->max_transfer_size;
710 else
711 /* 3072 = 3 max-size Isoc packets */
712 buf_size = 3072;
713
7359d482
PZ		 714 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size,
715 &qh->dw_align_buf_dma,
716 GFP_ATOMIC);
717 if (!qh->dw_align_buf)
718 return -ENOMEM;
5dce9555 719 qh->dw_align_buf_size = buf_size;
7359d482
PZ		 720 }
721
5dce9555
PZ		 722 if (chan->xfer_len) {
723 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
724 usb_urb = urb->priv;
725
726 if (usb_urb) {
727 if (usb_urb->transfer_flags &
728 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
729 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
730 hcd = dwc2_hsotg_to_hcd(hsotg);
731 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
732 }
733 if (!chan->ep_is_in)
734 memcpy(qh->dw_align_buf, bufptr,
735 chan->xfer_len);
736 } else {
737 dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
738 }
7359d482
PZ		 739 }
740
741 chan->align_buf = qh->dw_align_buf_dma;
742 return 0;
743}
744
745/**
746 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
747 * channel and initializes the host channel to perform the transactions. The
748 * host channel is removed from the free list.
749 *
750 * @hsotg: The HCD state structure
751 * @qh: Transactions from the first QTD for this QH are selected and assigned
752 * to a free host channel
753 */
20f2eb9c 754static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
7359d482
PZ		 755{
756 struct dwc2_host_chan *chan;
757 struct dwc2_hcd_urb *urb;
758 struct dwc2_qtd *qtd;
759 void *bufptr = NULL;
760
b49977a6
MK		 761 if (dbg_qh(qh))
762 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
7359d482
PZ		 763
764 if (list_empty(&qh->qtd_list)) {
765 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
20f2eb9c 766 return -ENOMEM;
7359d482
PZ		 767 }
768
769 if (list_empty(&hsotg->free_hc_list)) {
770 dev_dbg(hsotg->dev, "No free channel to assign\n");
20f2eb9c 771 return -ENOMEM;
7359d482
PZ		 772 }
773
774 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
775 hc_list_entry);
776
20f2eb9c 777 /* Remove host channel from free list */
7359d482
PZ		 778 list_del_init(&chan->hc_list_entry);
779
780 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
781 urb = qtd->urb;
782 qh->channel = chan;
783 qtd->in_process = 1;
784
785 /*
786 * Use usb_pipedevice to determine device address. This address is
787 * 0 before the SET_ADDRESS command and the correct address afterward.
788 */
789 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
790 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
791 chan->speed = qh->dev_speed;
792 chan->max_packet = dwc2_max_packet(qh->maxp);
793
794 chan->xfer_started = 0;
795 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
796 chan->error_state = (qtd->error_count > 0);
797 chan->halt_on_queue = 0;
798 chan->halt_pending = 0;
799 chan->requests = 0;
800
801 /*
802 * The following values may be modified in the transfer type section
803 * below. The xfer_len value may be reduced when the transfer is
804 * started to accommodate the max widths of the XferSize and PktCnt
805 * fields in the HCTSIZn register.
806 */
807
808 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
809 if (chan->ep_is_in)
810 chan->do_ping = 0;
811 else
812 chan->do_ping = qh->ping_state;
813
814 chan->data_pid_start = qh->data_toggle;
815 chan->multi_count = 1;
816
bb6c3422
RK		 817 if (urb->actual_length > urb->length &&
818 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
84181086
PZ		 819 urb->actual_length = urb->length;
820
7359d482
PZ		 821 if (hsotg->core_params->dma_enable > 0) {
822 chan->xfer_dma = urb->dma + urb->actual_length;
823
824 /* For non-dword aligned case */
825 if (hsotg->core_params->dma_desc_enable <= 0 &&
826 (chan->xfer_dma & 0x3))
827 bufptr = (u8 *)urb->buf + urb->actual_length;
828 } else {
829 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
830 }
831
832 chan->xfer_len = urb->length - urb->actual_length;
833 chan->xfer_count = 0;
834
835 /* Set the split attributes if required */
836 if (qh->do_split)
837 dwc2_hc_init_split(hsotg, chan, qtd, urb);
838 else
839 chan->do_split = 0;
840
841 /* Set the transfer attributes */
842 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
843
844 /* Non DWORD-aligned buffer case */
845 if (bufptr) {
846 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
5dce9555 847 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
7359d482
PZ		 848 dev_err(hsotg->dev,
849 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
850 __func__);
851 /* Add channel back to free list */
852 chan->align_buf = 0;
853 chan->multi_count = 0;
854 list_add_tail(&chan->hc_list_entry,
855 &hsotg->free_hc_list);
856 qtd->in_process = 0;
857 qh->channel = NULL;
20f2eb9c 858 return -ENOMEM;
7359d482
PZ		 859 }
860 } else {
861 chan->align_buf = 0;
862 }
863
864 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
865 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
866 /*
867 * This value may be modified when the transfer is started
868 * to reflect the actual transfer length
869 */
870 chan->multi_count = dwc2_hb_mult(qh->maxp);
871
872 if (hsotg->core_params->dma_desc_enable > 0)
873 chan->desc_list_addr = qh->desc_list_dma;
874
875 dwc2_hc_init(hsotg, chan);
876 chan->qh = qh;
20f2eb9c
DC		 877
878 return 0;
7359d482
PZ		 879}
880
881/**
882 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
883 * schedule and assigns them to available host channels. Called from the HCD
884 * interrupt handler functions.
885 *
886 * @hsotg: The HCD state structure
887 *
888 * Return: The types of new transactions that were assigned to host channels
889 */
890enum dwc2_transaction_type dwc2_hcd_select_transactions(
891 struct dwc2_hsotg *hsotg)
892{
893 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
894 struct list_head *qh_ptr;
895 struct dwc2_qh *qh;
896 int num_channels;
897
898#ifdef DWC2_DEBUG_SOF
899 dev_vdbg(hsotg->dev, " Select Transactions\n");
900#endif
901
902 /* Process entries in the periodic ready list */
903 qh_ptr = hsotg->periodic_sched_ready.next;
904 while (qh_ptr != &hsotg->periodic_sched_ready) {
905 if (list_empty(&hsotg->free_hc_list))
906 break;
20f2eb9c
DC		 907 if (hsotg->core_params->uframe_sched > 0) {
908 if (hsotg->available_host_channels <= 1)
909 break;
910 hsotg->available_host_channels--;
911 }
7359d482 912 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 913 if (dwc2_assign_and_init_hc(hsotg, qh))
914 break;
7359d482
PZ		 915
916 /*
917 * Move the QH from the periodic ready schedule to the
918 * periodic assigned schedule
919 */
920 qh_ptr = qh_ptr->next;
921 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
922 ret_val = DWC2_TRANSACTION_PERIODIC;
923 }
924
925 /*
926 * Process entries in the inactive portion of the non-periodic
927 * schedule. Some free host channels may not be used if they are
928 * reserved for periodic transfers.
929 */
930 num_channels = hsotg->core_params->host_channels;
931 qh_ptr = hsotg->non_periodic_sched_inactive.next;
932 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
20f2eb9c
DC		 933 if (hsotg->core_params->uframe_sched <= 0 &&
934 hsotg->non_periodic_channels >= num_channels -
7359d482
PZ		 935 hsotg->periodic_channels)
936 break;
937 if (list_empty(&hsotg->free_hc_list))
938 break;
939 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
20f2eb9c
DC		 940 if (hsotg->core_params->uframe_sched > 0) {
941 if (hsotg->available_host_channels < 1)
942 break;
943 hsotg->available_host_channels--;
944 }
945
946 if (dwc2_assign_and_init_hc(hsotg, qh))
947 break;
7359d482
PZ		 948
949 /*
950 * Move the QH from the non-periodic inactive schedule to the
951 * non-periodic active schedule
952 */
953 qh_ptr = qh_ptr->next;
954 list_move(&qh->qh_list_entry,
955 &hsotg->non_periodic_sched_active);
956
957 if (ret_val == DWC2_TRANSACTION_NONE)
958 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
959 else
960 ret_val = DWC2_TRANSACTION_ALL;
961
20f2eb9c
DC		 962 if (hsotg->core_params->uframe_sched <= 0)
963 hsotg->non_periodic_channels++;
7359d482
PZ		 964 }
965
966 return ret_val;
967}
968
969/**
970 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
971 * a host channel associated with either a periodic or non-periodic transfer
972 *
973 * @hsotg: The HCD state structure
974 * @chan: Host channel descriptor associated with either a periodic or
975 * non-periodic transfer
976 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
977 * for periodic transfers or the non-periodic Tx FIFO
978 * for non-periodic transfers
979 *
980 * Return: 1 if a request is queued and more requests may be needed to
981 * complete the transfer, 0 if no more requests are required for this
982 * transfer, -1 if there is insufficient space in the Tx FIFO
983 *
984 * This function assumes that there is space available in the appropriate
985 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
986 * it checks whether space is available in the appropriate Tx FIFO.
987 *
988 * Must be called with interrupt disabled and spinlock held
989 */
990static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
991 struct dwc2_host_chan *chan,
992 u16 fifo_dwords_avail)
993{
994 int retval = 0;
995
996 if (hsotg->core_params->dma_enable > 0) {
997 if (hsotg->core_params->dma_desc_enable > 0) {
998 if (!chan->xfer_started ||
999 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1000 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1001 chan->qh->ping_state = 0;
1002 }
1003 } else if (!chan->xfer_started) {
1004 dwc2_hc_start_transfer(hsotg, chan);
1005 chan->qh->ping_state = 0;
1006 }
1007 } else if (chan->halt_pending) {
1008 /* Don't queue a request if the channel has been halted */
1009 } else if (chan->halt_on_queue) {
1010 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1011 } else if (chan->do_ping) {
1012 if (!chan->xfer_started)
1013 dwc2_hc_start_transfer(hsotg, chan);
1014 } else if (!chan->ep_is_in ||
1015 chan->data_pid_start == DWC2_HC_PID_SETUP) {
1016 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1017 if (!chan->xfer_started) {
1018 dwc2_hc_start_transfer(hsotg, chan);
1019 retval = 1;
1020 } else {
1021 retval = dwc2_hc_continue_transfer(hsotg, chan);
1022 }
1023 } else {
1024 retval = -1;
1025 }
1026 } else {
1027 if (!chan->xfer_started) {
1028 dwc2_hc_start_transfer(hsotg, chan);
1029 retval = 1;
1030 } else {
1031 retval = dwc2_hc_continue_transfer(hsotg, chan);
1032 }
1033 }
1034
1035 return retval;
1036}
1037
1038/*
1039 * Processes periodic channels for the next frame and queues transactions for
1040 * these channels to the DWC_otg controller. After queueing transactions, the
1041 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1042 * to queue as Periodic Tx FIFO or request queue space becomes available.
1043 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1044 *
1045 * Must be called with interrupt disabled and spinlock held
1046 */
1047static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1048{
1049 struct list_head *qh_ptr;
1050 struct dwc2_qh *qh;
1051 u32 tx_status;
1052 u32 fspcavail;
1053 u32 gintmsk;
1054 int status;
1055 int no_queue_space = 0;
1056 int no_fifo_space = 0;
1057 u32 qspcavail;
1058
b49977a6
MK		 1059 if (dbg_perio())
1060 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
7359d482
PZ		 1061
1062 tx_status = readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1063 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1064 TXSTS_QSPCAVAIL_SHIFT;
1065 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1066 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1067
1068 if (dbg_perio()) {
1069 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1070 qspcavail);
1071 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1072 fspcavail);
1073 }
7359d482
PZ		 1074
1075 qh_ptr = hsotg->periodic_sched_assigned.next;
1076 while (qh_ptr != &hsotg->periodic_sched_assigned) {
1077 tx_status = readl(hsotg->regs + HPTXSTS);
acdb9046
MK		 1078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1079 TXSTS_QSPCAVAIL_SHIFT;
1080 if (qspcavail == 0) {
7359d482
PZ		 1081 no_queue_space = 1;
1082 break;
1083 }
1084
1085 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1086 if (!qh->channel) {
1087 qh_ptr = qh_ptr->next;
1088 continue;
1089 }
1090
1091 /* Make sure EP's TT buffer is clean before queueing qtds */
1092 if (qh->tt_buffer_dirty) {
1093 qh_ptr = qh_ptr->next;
1094 continue;
1095 }
1096
1097 /*
1098 * Set a flag if we're queuing high-bandwidth in slave mode.
1099 * The flag prevents any halts to get into the request queue in
1100 * the middle of multiple high-bandwidth packets getting queued.
1101 */
1102 if (hsotg->core_params->dma_enable <= 0 &&
1103 qh->channel->multi_count > 1)
1104 hsotg->queuing_high_bandwidth = 1;
1105
d6ec53e0
MK		 1106 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1107 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1108 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1109 if (status < 0) {
1110 no_fifo_space = 1;
1111 break;
1112 }
1113
1114 /*
1115 * In Slave mode, stay on the current transfer until there is
1116 * nothing more to do or the high-bandwidth request count is
1117 * reached. In DMA mode, only need to queue one request. The
1118 * controller automatically handles multiple packets for
1119 * high-bandwidth transfers.
1120 */
1121 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1122 qh->channel->requests == qh->channel->multi_count) {
1123 qh_ptr = qh_ptr->next;
1124 /*
1125 * Move the QH from the periodic assigned schedule to
1126 * the periodic queued schedule
1127 */
1128 list_move(&qh->qh_list_entry,
1129 &hsotg->periodic_sched_queued);
1130
1131 /* done queuing high bandwidth */
1132 hsotg->queuing_high_bandwidth = 0;
1133 }
1134 }
1135
1136 if (hsotg->core_params->dma_enable <= 0) {
1137 tx_status = readl(hsotg->regs + HPTXSTS);
d6ec53e0
MK		 1138 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1139 TXSTS_QSPCAVAIL_SHIFT;
1140 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1141 TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1142 if (dbg_perio()) {
1143 dev_vdbg(hsotg->dev,
1144 " P Tx Req Queue Space Avail (after queue): %d\n",
1145 qspcavail);
1146 dev_vdbg(hsotg->dev,
1147 " P Tx FIFO Space Avail (after queue): %d\n",
1148 fspcavail);
1149 }
7359d482
PZ		 1150
1151 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1152 no_queue_space || no_fifo_space) {
1153 /*
1154 * May need to queue more transactions as the request
1155 * queue or Tx FIFO empties. Enable the periodic Tx
1156 * FIFO empty interrupt. (Always use the half-empty
1157 * level to ensure that new requests are loaded as
1158 * soon as possible.)
1159 */
1160 gintmsk = readl(hsotg->regs + GINTMSK);
1161 gintmsk |= GINTSTS_PTXFEMP;
1162 writel(gintmsk, hsotg->regs + GINTMSK);
1163 } else {
1164 /*
1165 * Disable the Tx FIFO empty interrupt since there are
1166 * no more transactions that need to be queued right
1167 * now. This function is called from interrupt
1168 * handlers to queue more transactions as transfer
1169 * states change.
1170 */
1171 gintmsk = readl(hsotg->regs + GINTMSK);
1172 gintmsk &= ~GINTSTS_PTXFEMP;
1173 writel(gintmsk, hsotg->regs + GINTMSK);
1174 }
1175 }
1176}
1177
1178/*
1179 * Processes active non-periodic channels and queues transactions for these
1180 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1181 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1182 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1183 * FIFO Empty interrupt is disabled.
1184 *
1185 * Must be called with interrupt disabled and spinlock held
1186 */
1187static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1188{
1189 struct list_head *orig_qh_ptr;
1190 struct dwc2_qh *qh;
1191 u32 tx_status;
1192 u32 qspcavail;
1193 u32 fspcavail;
1194 u32 gintmsk;
1195 int status;
1196 int no_queue_space = 0;
1197 int no_fifo_space = 0;
1198 int more_to_do = 0;
1199
1200 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1201
1202 tx_status = readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1203 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1204 TXSTS_QSPCAVAIL_SHIFT;
1205 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1206 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1207 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1208 qspcavail);
1209 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1210 fspcavail);
1211
1212 /*
1213 * Keep track of the starting point. Skip over the start-of-list
1214 * entry.
1215 */
1216 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1217 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1218 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1219
1220 /*
1221 * Process once through the active list or until no more space is
1222 * available in the request queue or the Tx FIFO
1223 */
1224 do {
1225 tx_status = readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1226 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1227 TXSTS_QSPCAVAIL_SHIFT;
7359d482
PZ		 1228 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1229 no_queue_space = 1;
1230 break;
1231 }
1232
1233 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1234 qh_list_entry);
1235 if (!qh->channel)
1236 goto next;
1237
1238 /* Make sure EP's TT buffer is clean before queueing qtds */
1239 if (qh->tt_buffer_dirty)
1240 goto next;
1241
d6ec53e0
MK		 1242 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1243 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1244 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1245
1246 if (status > 0) {
1247 more_to_do = 1;
1248 } else if (status < 0) {
1249 no_fifo_space = 1;
1250 break;
1251 }
1252next:
1253 /* Advance to next QH, skipping start-of-list entry */
1254 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1255 if (hsotg->non_periodic_qh_ptr ==
1256 &hsotg->non_periodic_sched_active)
1257 hsotg->non_periodic_qh_ptr =
1258 hsotg->non_periodic_qh_ptr->next;
1259 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1260
1261 if (hsotg->core_params->dma_enable <= 0) {
1262 tx_status = readl(hsotg->regs + GNPTXSTS);
d6ec53e0
MK		 1263 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1264 TXSTS_QSPCAVAIL_SHIFT;
1265 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1266 TXSTS_FSPCAVAIL_SHIFT;
7359d482
PZ		 1267 dev_vdbg(hsotg->dev,
1268 " NP Tx Req Queue Space Avail (after queue): %d\n",
1269 qspcavail);
1270 dev_vdbg(hsotg->dev,
1271 " NP Tx FIFO Space Avail (after queue): %d\n",
1272 fspcavail);
1273
1274 if (more_to_do || no_queue_space || no_fifo_space) {
1275 /*
1276 * May need to queue more transactions as the request
1277 * queue or Tx FIFO empties. Enable the non-periodic
1278 * Tx FIFO empty interrupt. (Always use the half-empty
1279 * level to ensure that new requests are loaded as
1280 * soon as possible.)
1281 */
1282 gintmsk = readl(hsotg->regs + GINTMSK);
1283 gintmsk |= GINTSTS_NPTXFEMP;
1284 writel(gintmsk, hsotg->regs + GINTMSK);
1285 } else {
1286 /*
1287 * Disable the Tx FIFO empty interrupt since there are
1288 * no more transactions that need to be queued right
1289 * now. This function is called from interrupt
1290 * handlers to queue more transactions as transfer
1291 * states change.
1292 */
1293 gintmsk = readl(hsotg->regs + GINTMSK);
1294 gintmsk &= ~GINTSTS_NPTXFEMP;
1295 writel(gintmsk, hsotg->regs + GINTMSK);
1296 }
1297 }
1298}
1299
1300/**
1301 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1302 * and queues transactions for these channels to the DWC_otg controller. Called
1303 * from the HCD interrupt handler functions.
1304 *
1305 * @hsotg: The HCD state structure
1306 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1307 * or both)
1308 *
1309 * Must be called with interrupt disabled and spinlock held
1310 */
1311void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1312 enum dwc2_transaction_type tr_type)
1313{
1314#ifdef DWC2_DEBUG_SOF
1315 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1316#endif
1317 /* Process host channels associated with periodic transfers */
1318 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1319 tr_type == DWC2_TRANSACTION_ALL) &&
1320 !list_empty(&hsotg->periodic_sched_assigned))
1321 dwc2_process_periodic_channels(hsotg);
1322
1323 /* Process host channels associated with non-periodic transfers */
1324 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1325 tr_type == DWC2_TRANSACTION_ALL) {
1326 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1327 dwc2_process_non_periodic_channels(hsotg);
1328 } else {
1329 /*
1330 * Ensure NP Tx FIFO empty interrupt is disabled when
1331 * there are no non-periodic transfers to process
1332 */
1333 u32 gintmsk = readl(hsotg->regs + GINTMSK);
1334
1335 gintmsk &= ~GINTSTS_NPTXFEMP;
1336 writel(gintmsk, hsotg->regs + GINTMSK);
1337 }
1338 }
1339}
1340
1341static void dwc2_conn_id_status_change(struct work_struct *work)
1342{
1343 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1344 wf_otg);
1345 u32 count = 0;
1346 u32 gotgctl;
1347
1348 dev_dbg(hsotg->dev, "%s()\n", __func__);
1349
1350 gotgctl = readl(hsotg->regs + GOTGCTL);
1351 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1352 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1353 !!(gotgctl & GOTGCTL_CONID_B));
1354
1355 /* B-Device connector (Device Mode) */
1356 if (gotgctl & GOTGCTL_CONID_B) {
1357 /* Wait for switch to device mode */
1358 dev_dbg(hsotg->dev, "connId B\n");
1359 while (!dwc2_is_device_mode(hsotg)) {
1360 dev_info(hsotg->dev,
1361 "Waiting for Peripheral Mode, Mode=%s\n",
1362 dwc2_is_host_mode(hsotg) ? "Host" :
1363 "Peripheral");
1364 usleep_range(20000, 40000);
1365 if (++count > 250)
1366 break;
1367 }
1368 if (count > 250)
1369 dev_err(hsotg->dev,
de9169a1 1370 "Connection id status change timed out\n");
7359d482 1371 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
6706c721 1372 dwc2_core_init(hsotg, false, -1);
7359d482 1373 dwc2_enable_global_interrupts(hsotg);
510ffaa4
DN		 1374 s3c_hsotg_core_init_disconnected(hsotg);
1375 s3c_hsotg_core_connect(hsotg);
7359d482
PZ		 1376 } else {
1377 /* A-Device connector (Host Mode) */
1378 dev_dbg(hsotg->dev, "connId A\n");
1379 while (!dwc2_is_host_mode(hsotg)) {
1380 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1381 dwc2_is_host_mode(hsotg) ?
1382 "Host" : "Peripheral");
1383 usleep_range(20000, 40000);
1384 if (++count > 250)
1385 break;
1386 }
1387 if (count > 250)
1388 dev_err(hsotg->dev,
de9169a1 1389 "Connection id status change timed out\n");
7359d482
PZ		 1390 hsotg->op_state = OTG_STATE_A_HOST;
1391
1392 /* Initialize the Core for Host mode */
6706c721 1393 dwc2_core_init(hsotg, false, -1);
7359d482
PZ		 1394 dwc2_enable_global_interrupts(hsotg);
1395 dwc2_hcd_start(hsotg);
1396 }
1397}
1398
1399static void dwc2_wakeup_detected(unsigned long data)
1400{
1401 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1402 u32 hprt0;
1403
1404 dev_dbg(hsotg->dev, "%s()\n", __func__);
1405
1406 /*
1407 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1408 * so that OPT tests pass with all PHYs.)
1409 */
1410 hprt0 = dwc2_read_hprt0(hsotg);
1411 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1412 hprt0 &= ~HPRT0_RES;
1413 writel(hprt0, hsotg->regs + HPRT0);
1414 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1415 readl(hsotg->regs + HPRT0));
1416
1417 dwc2_hcd_rem_wakeup(hsotg);
1418
1419 /* Change to L0 state */
1420 hsotg->lx_state = DWC2_L0;
1421}
1422
1423static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1424{
1425 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1426
1427 return hcd->self.b_hnp_enable;
1428}
1429
1430/* Must NOT be called with interrupt disabled or spinlock held */
1431static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1432{
1433 unsigned long flags;
1434 u32 hprt0;
1435 u32 pcgctl;
1436 u32 gotgctl;
1437
1438 dev_dbg(hsotg->dev, "%s()\n", __func__);
1439
1440 spin_lock_irqsave(&hsotg->lock, flags);
1441
1442 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1443 gotgctl = readl(hsotg->regs + GOTGCTL);
1444 gotgctl |= GOTGCTL_HSTSETHNPEN;
1445 writel(gotgctl, hsotg->regs + GOTGCTL);
1446 hsotg->op_state = OTG_STATE_A_SUSPEND;
1447 }
1448
1449 hprt0 = dwc2_read_hprt0(hsotg);
1450 hprt0 |= HPRT0_SUSP;
1451 writel(hprt0, hsotg->regs + HPRT0);
1452
1453 /* Update lx_state */
1454 hsotg->lx_state = DWC2_L2;
1455
1456 /* Suspend the Phy Clock */
1457 pcgctl = readl(hsotg->regs + PCGCTL);
1458 pcgctl |= PCGCTL_STOPPCLK;
1459 writel(pcgctl, hsotg->regs + PCGCTL);
1460 udelay(10);
1461
1462 /* For HNP the bus must be suspended for at least 200ms */
1463 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1464 pcgctl = readl(hsotg->regs + PCGCTL);
1465 pcgctl &= ~PCGCTL_STOPPCLK;
1466 writel(pcgctl, hsotg->regs + PCGCTL);
1467
1468 spin_unlock_irqrestore(&hsotg->lock, flags);
1469
1470 usleep_range(200000, 250000);
1471 } else {
1472 spin_unlock_irqrestore(&hsotg->lock, flags);
1473 }
1474}
1475
1476/* Handles hub class-specific requests */
1477static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1478 u16 wvalue, u16 windex, char *buf, u16 wlength)
1479{
1480 struct usb_hub_descriptor *hub_desc;
1481 int retval = 0;
1482 u32 hprt0;
1483 u32 port_status;
1484 u32 speed;
1485 u32 pcgctl;
1486
1487 switch (typereq) {
1488 case ClearHubFeature:
1489 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1490
1491 switch (wvalue) {
1492 case C_HUB_LOCAL_POWER:
1493 case C_HUB_OVER_CURRENT:
1494 /* Nothing required here */
1495 break;
1496
1497 default:
1498 retval = -EINVAL;
1499 dev_err(hsotg->dev,
1500 "ClearHubFeature request %1xh unknown\n",
1501 wvalue);
1502 }
1503 break;
1504
1505 case ClearPortFeature:
1506 if (wvalue != USB_PORT_FEAT_L1)
1507 if (!windex || windex > 1)
1508 goto error;
1509 switch (wvalue) {
1510 case USB_PORT_FEAT_ENABLE:
1511 dev_dbg(hsotg->dev,
1512 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1513 hprt0 = dwc2_read_hprt0(hsotg);
1514 hprt0 |= HPRT0_ENA;
1515 writel(hprt0, hsotg->regs + HPRT0);
1516 break;
1517
1518 case USB_PORT_FEAT_SUSPEND:
1519 dev_dbg(hsotg->dev,
1520 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
b0bb9bb6
PZ		 1521 writel(0, hsotg->regs + PCGCTL);
1522 usleep_range(20000, 40000);
1523
1524 hprt0 = dwc2_read_hprt0(hsotg);
1525 hprt0 |= HPRT0_RES;
1526 writel(hprt0, hsotg->regs + HPRT0);
1527 hprt0 &= ~HPRT0_SUSP;
1528 usleep_range(100000, 150000);
1529
1530 hprt0 &= ~HPRT0_RES;
1531 writel(hprt0, hsotg->regs + HPRT0);
7359d482
PZ		 1532 break;
1533
1534 case USB_PORT_FEAT_POWER:
1535 dev_dbg(hsotg->dev,
1536 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1537 hprt0 = dwc2_read_hprt0(hsotg);
1538 hprt0 &= ~HPRT0_PWR;
1539 writel(hprt0, hsotg->regs + HPRT0);
1540 break;
1541
1542 case USB_PORT_FEAT_INDICATOR:
1543 dev_dbg(hsotg->dev,
1544 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1545 /* Port indicator not supported */
1546 break;
1547
1548 case USB_PORT_FEAT_C_CONNECTION:
1549 /*
1550 * Clears driver's internal Connect Status Change flag
1551 */
1552 dev_dbg(hsotg->dev,
1553 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1554 hsotg->flags.b.port_connect_status_change = 0;
1555 break;
1556
1557 case USB_PORT_FEAT_C_RESET:
1558 /* Clears driver's internal Port Reset Change flag */
1559 dev_dbg(hsotg->dev,
1560 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1561 hsotg->flags.b.port_reset_change = 0;
1562 break;
1563
1564 case USB_PORT_FEAT_C_ENABLE:
1565 /*
1566 * Clears the driver's internal Port Enable/Disable
1567 * Change flag
1568 */
1569 dev_dbg(hsotg->dev,
1570 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1571 hsotg->flags.b.port_enable_change = 0;
1572 break;
1573
1574 case USB_PORT_FEAT_C_SUSPEND:
1575 /*
1576 * Clears the driver's internal Port Suspend Change
1577 * flag, which is set when resume signaling on the host
1578 * port is complete
1579 */
1580 dev_dbg(hsotg->dev,
1581 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1582 hsotg->flags.b.port_suspend_change = 0;
1583 break;
1584
1585 case USB_PORT_FEAT_C_PORT_L1:
1586 dev_dbg(hsotg->dev,
1587 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1588 hsotg->flags.b.port_l1_change = 0;
1589 break;
1590
1591 case USB_PORT_FEAT_C_OVER_CURRENT:
1592 dev_dbg(hsotg->dev,
1593 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1594 hsotg->flags.b.port_over_current_change = 0;
1595 break;
1596
1597 default:
1598 retval = -EINVAL;
1599 dev_err(hsotg->dev,
1600 "ClearPortFeature request %1xh unknown or unsupported\n",
1601 wvalue);
1602 }
1603 break;
1604
1605 case GetHubDescriptor:
1606 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1607 hub_desc = (struct usb_hub_descriptor *)buf;
1608 hub_desc->bDescLength = 9;
1609 hub_desc->bDescriptorType = 0x29;
1610 hub_desc->bNbrPorts = 1;
3d040de8
SS		 1611 hub_desc->wHubCharacteristics =
1612 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1613 HUB_CHAR_INDV_PORT_OCPM);
7359d482
PZ		 1614 hub_desc->bPwrOn2PwrGood = 1;
1615 hub_desc->bHubContrCurrent = 0;
1616 hub_desc->u.hs.DeviceRemovable[0] = 0;
1617 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1618 break;
1619
1620 case GetHubStatus:
1621 dev_dbg(hsotg->dev, "GetHubStatus\n");
1622 memset(buf, 0, 4);
1623 break;
1624
1625 case GetPortStatus:
b8313417
PZ		 1626 dev_vdbg(hsotg->dev,
1627 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1628 hsotg->flags.d32);
7359d482
PZ		 1629 if (!windex || windex > 1)
1630 goto error;
1631
1632 port_status = 0;
1633 if (hsotg->flags.b.port_connect_status_change)
1634 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1635 if (hsotg->flags.b.port_enable_change)
1636 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1637 if (hsotg->flags.b.port_suspend_change)
1638 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1639 if (hsotg->flags.b.port_l1_change)
1640 port_status |= USB_PORT_STAT_C_L1 << 16;
1641 if (hsotg->flags.b.port_reset_change)
1642 port_status |= USB_PORT_STAT_C_RESET << 16;
1643 if (hsotg->flags.b.port_over_current_change) {
1644 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1645 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1646 }
1647
1648 if (!hsotg->flags.b.port_connect_status) {
1649 /*
1650 * The port is disconnected, which means the core is
1651 * either in device mode or it soon will be. Just
1652 * return 0's for the remainder of the port status
1653 * since the port register can't be read if the core
1654 * is in device mode.
1655 */
1656 *(__le32 *)buf = cpu_to_le32(port_status);
1657 break;
1658 }
1659
1660 hprt0 = readl(hsotg->regs + HPRT0);
b8313417 1661 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
7359d482
PZ		 1662
1663 if (hprt0 & HPRT0_CONNSTS)
1664 port_status |= USB_PORT_STAT_CONNECTION;
1665 if (hprt0 & HPRT0_ENA)
1666 port_status |= USB_PORT_STAT_ENABLE;
1667 if (hprt0 & HPRT0_SUSP)
1668 port_status |= USB_PORT_STAT_SUSPEND;
1669 if (hprt0 & HPRT0_OVRCURRACT)
1670 port_status |= USB_PORT_STAT_OVERCURRENT;
1671 if (hprt0 & HPRT0_RST)
1672 port_status |= USB_PORT_STAT_RESET;
1673 if (hprt0 & HPRT0_PWR)
1674 port_status |= USB_PORT_STAT_POWER;
1675
f9234633 1676 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
7359d482
PZ		 1677 if (speed == HPRT0_SPD_HIGH_SPEED)
1678 port_status |= USB_PORT_STAT_HIGH_SPEED;
1679 else if (speed == HPRT0_SPD_LOW_SPEED)
1680 port_status |= USB_PORT_STAT_LOW_SPEED;
1681
1682 if (hprt0 & HPRT0_TSTCTL_MASK)
1683 port_status |= USB_PORT_STAT_TEST;
1684 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1685
b8313417 1686 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
7359d482
PZ		 1687 *(__le32 *)buf = cpu_to_le32(port_status);
1688 break;
1689
1690 case SetHubFeature:
1691 dev_dbg(hsotg->dev, "SetHubFeature\n");
1692 /* No HUB features supported */
1693 break;
1694
1695 case SetPortFeature:
1696 dev_dbg(hsotg->dev, "SetPortFeature\n");
1697 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1698 goto error;
1699
1700 if (!hsotg->flags.b.port_connect_status) {
1701 /*
1702 * The port is disconnected, which means the core is
1703 * either in device mode or it soon will be. Just
1704 * return without doing anything since the port
1705 * register can't be written if the core is in device
1706 * mode.
1707 */
1708 break;
1709 }
1710
1711 switch (wvalue) {
1712 case USB_PORT_FEAT_SUSPEND:
1713 dev_dbg(hsotg->dev,
1714 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1715 if (windex != hsotg->otg_port)
1716 goto error;
1717 dwc2_port_suspend(hsotg, windex);
1718 break;
1719
1720 case USB_PORT_FEAT_POWER:
1721 dev_dbg(hsotg->dev,
1722 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1723 hprt0 = dwc2_read_hprt0(hsotg);
1724 hprt0 |= HPRT0_PWR;
1725 writel(hprt0, hsotg->regs + HPRT0);
1726 break;
1727
1728 case USB_PORT_FEAT_RESET:
1729 hprt0 = dwc2_read_hprt0(hsotg);
1730 dev_dbg(hsotg->dev,
1731 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1732 pcgctl = readl(hsotg->regs + PCGCTL);
1733 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1734 writel(pcgctl, hsotg->regs + PCGCTL);
1735 /* ??? Original driver does this */
1736 writel(0, hsotg->regs + PCGCTL);
1737
1738 hprt0 = dwc2_read_hprt0(hsotg);
1739 /* Clear suspend bit if resetting from suspend state */
1740 hprt0 &= ~HPRT0_SUSP;
1741
1742 /*
1743 * When B-Host the Port reset bit is set in the Start
1744 * HCD Callback function, so that the reset is started
1745 * within 1ms of the HNP success interrupt
1746 */
1747 if (!dwc2_hcd_is_b_host(hsotg)) {
1748 hprt0 |= HPRT0_PWR | HPRT0_RST;
1749 dev_dbg(hsotg->dev,
1750 "In host mode, hprt0=%08x\n", hprt0);
1751 writel(hprt0, hsotg->regs + HPRT0);
1752 }
1753
1754 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1755 usleep_range(50000, 70000);
1756 hprt0 &= ~HPRT0_RST;
1757 writel(hprt0, hsotg->regs + HPRT0);
1758 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1759 break;
1760
1761 case USB_PORT_FEAT_INDICATOR:
1762 dev_dbg(hsotg->dev,
1763 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1764 /* Not supported */
1765 break;
1766
1767 default:
1768 retval = -EINVAL;
1769 dev_err(hsotg->dev,
1770 "SetPortFeature %1xh unknown or unsupported\n",
1771 wvalue);
1772 break;
1773 }
1774 break;
1775
1776 default:
1777error:
1778 retval = -EINVAL;
1779 dev_dbg(hsotg->dev,
1780 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1781 typereq, windex, wvalue);
1782 break;
1783 }
1784
1785 return retval;
1786}
1787
1788static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1789{
1790 int retval;
1791
7359d482
PZ		 1792 if (port != 1)
1793 return -EINVAL;
1794
1795 retval = (hsotg->flags.b.port_connect_status_change ||
1796 hsotg->flags.b.port_reset_change ||
1797 hsotg->flags.b.port_enable_change ||
1798 hsotg->flags.b.port_suspend_change ||
1799 hsotg->flags.b.port_over_current_change);
1800
1801 if (retval) {
1802 dev_dbg(hsotg->dev,
1803 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1804 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1805 hsotg->flags.b.port_connect_status_change);
1806 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1807 hsotg->flags.b.port_reset_change);
1808 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1809 hsotg->flags.b.port_enable_change);
1810 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1811 hsotg->flags.b.port_suspend_change);
1812 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1813 hsotg->flags.b.port_over_current_change);
1814 }
1815
1816 return retval;
1817}
1818
1819int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1820{
1821 u32 hfnum = readl(hsotg->regs + HFNUM);
1822
1823#ifdef DWC2_DEBUG_SOF
1824 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
d6ec53e0 1825 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
7359d482 1826#endif
d6ec53e0 1827 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
7359d482
PZ		 1828}
1829
1830int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1831{
6bf2e2a5 1832 return hsotg->op_state == OTG_STATE_B_HOST;
7359d482
PZ		 1833}
1834
1835static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1836 int iso_desc_count,
1837 gfp_t mem_flags)
1838{
1839 struct dwc2_hcd_urb *urb;
1840 u32 size = sizeof(*urb) + iso_desc_count *
1841 sizeof(struct dwc2_hcd_iso_packet_desc);
1842
1843 urb = kzalloc(size, mem_flags);
1844 if (urb)
1845 urb->packet_count = iso_desc_count;
1846 return urb;
1847}
1848
1849static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1850 struct dwc2_hcd_urb *urb, u8 dev_addr,
1851 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1852{
b49977a6
MK		 1853 if (dbg_perio() ||
1854 ep_type == USB_ENDPOINT_XFER_BULK ||
1855 ep_type == USB_ENDPOINT_XFER_CONTROL)
1856 dev_vdbg(hsotg->dev,
1857 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1858 dev_addr, ep_num, ep_dir, ep_type, mps);
7359d482
PZ		 1859 urb->pipe_info.dev_addr = dev_addr;
1860 urb->pipe_info.ep_num = ep_num;
1861 urb->pipe_info.pipe_type = ep_type;
1862 urb->pipe_info.pipe_dir = ep_dir;
1863 urb->pipe_info.mps = mps;
1864}
1865
1866/*
1867 * NOTE: This function will be removed once the peripheral controller code
1868 * is integrated and the driver is stable
1869 */
1870void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1871{
1872#ifdef DEBUG
1873 struct dwc2_host_chan *chan;
1874 struct dwc2_hcd_urb *urb;
1875 struct dwc2_qtd *qtd;
1876 int num_channels;
1877 u32 np_tx_status;
1878 u32 p_tx_status;
1879 int i;
1880
1881 num_channels = hsotg->core_params->host_channels;
1882 dev_dbg(hsotg->dev, "\n");
1883 dev_dbg(hsotg->dev,
1884 "************************************************************\n");
1885 dev_dbg(hsotg->dev, "HCD State:\n");
1886 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1887
1888 for (i = 0; i < num_channels; i++) {
1889 chan = hsotg->hc_ptr_array[i];
1890 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1891 dev_dbg(hsotg->dev,
1892 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1893 chan->dev_addr, chan->ep_num, chan->ep_is_in);
1894 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1895 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1896 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1897 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1898 chan->data_pid_start);
1899 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1900 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1901 chan->xfer_started);
1902 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1903 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1904 (unsigned long)chan->xfer_dma);
1905 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1906 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1907 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1908 chan->halt_on_queue);
1909 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1910 chan->halt_pending);
1911 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1912 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1913 dev_dbg(hsotg->dev, " complete_split: %d\n",
1914 chan->complete_split);
1915 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
1916 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
1917 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
1918 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
1919 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
1920
1921 if (chan->xfer_started) {
1922 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1923
1924 hfnum = readl(hsotg->regs + HFNUM);
1925 hcchar = readl(hsotg->regs + HCCHAR(i));
1926 hctsiz = readl(hsotg->regs + HCTSIZ(i));
1927 hcint = readl(hsotg->regs + HCINT(i));
1928 hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1929 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
1930 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
1931 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
1932 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
1933 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
1934 }
1935
1936 if (!(chan->xfer_started && chan->qh))
1937 continue;
1938
1939 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1940 if (!qtd->in_process)
1941 break;
1942 urb = qtd->urb;
1943 dev_dbg(hsotg->dev, " URB Info:\n");
1944 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
1945 qtd, urb);
1946 if (urb) {
1947 dev_dbg(hsotg->dev,
1948 " Dev: %d, EP: %d %s\n",
1949 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1950 dwc2_hcd_get_ep_num(&urb->pipe_info),
1951 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1952 "IN" : "OUT");
1953 dev_dbg(hsotg->dev,
1954 " Max packet size: %d\n",
1955 dwc2_hcd_get_mps(&urb->pipe_info));
1956 dev_dbg(hsotg->dev,
1957 " transfer_buffer: %p\n",
1958 urb->buf);
157dfaac
PZ		 1959 dev_dbg(hsotg->dev,
1960 " transfer_dma: %08lx\n",
1961 (unsigned long)urb->dma);
7359d482
PZ		 1962 dev_dbg(hsotg->dev,
1963 " transfer_buffer_length: %d\n",
1964 urb->length);
1965 dev_dbg(hsotg->dev, " actual_length: %d\n",
1966 urb->actual_length);
1967 }
1968 }
1969 }
1970
1971 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
1972 hsotg->non_periodic_channels);
1973 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
1974 hsotg->periodic_channels);
1975 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
1976 np_tx_status = readl(hsotg->regs + GNPTXSTS);
1977 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
d6ec53e0 1978 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 1979 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
d6ec53e0 1980 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
7359d482
PZ		 1981 p_tx_status = readl(hsotg->regs + HPTXSTS);
1982 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
d6ec53e0 1983 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
7359d482 1984 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
d6ec53e0 1985 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
7359d482
PZ		 1986 dwc2_hcd_dump_frrem(hsotg);
1987 dwc2_dump_global_registers(hsotg);
1988 dwc2_dump_host_registers(hsotg);
1989 dev_dbg(hsotg->dev,
1990 "************************************************************\n");
1991 dev_dbg(hsotg->dev, "\n");
1992#endif
1993}
1994
1995/*
1996 * NOTE: This function will be removed once the peripheral controller code
1997 * is integrated and the driver is stable
1998 */
1999void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2000{
2001#ifdef DWC2_DUMP_FRREM
2002 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2003 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2004 hsotg->frrem_samples, hsotg->frrem_accum,
2005 hsotg->frrem_samples > 0 ?
2006 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2007 dev_dbg(hsotg->dev, "\n");
2008 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2009 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2010 hsotg->hfnum_7_samples,
2011 hsotg->hfnum_7_frrem_accum,
2012 hsotg->hfnum_7_samples > 0 ?
2013 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2014 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2015 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2016 hsotg->hfnum_0_samples,
2017 hsotg->hfnum_0_frrem_accum,
2018 hsotg->hfnum_0_samples > 0 ?
2019 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2020 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2021 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2022 hsotg->hfnum_other_samples,
2023 hsotg->hfnum_other_frrem_accum,
2024 hsotg->hfnum_other_samples > 0 ?
2025 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2026 0);
2027 dev_dbg(hsotg->dev, "\n");
2028 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2029 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2030 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2031 hsotg->hfnum_7_samples_a > 0 ?
2032 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2033 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2034 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2035 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2036 hsotg->hfnum_0_samples_a > 0 ?
2037 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2038 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2039 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2040 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2041 hsotg->hfnum_other_samples_a > 0 ?
2042 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2043 : 0);
2044 dev_dbg(hsotg->dev, "\n");
2045 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2046 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2047 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2048 hsotg->hfnum_7_samples_b > 0 ?
2049 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2050 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2051 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2052 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2053 (hsotg->hfnum_0_samples_b > 0) ?
2054 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2055 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2056 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2057 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2058 (hsotg->hfnum_other_samples_b > 0) ?
2059 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2060 : 0);
2061#endif
2062}
2063
2064struct wrapper_priv_data {
2065 struct dwc2_hsotg *hsotg;
2066};
2067
2068/* Gets the dwc2_hsotg from a usb_hcd */
2069static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2070{
2071 struct wrapper_priv_data *p;
2072
2073 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2074 return p->hsotg;
2075}
2076
2077static int _dwc2_hcd_start(struct usb_hcd *hcd);
2078
2079void dwc2_host_start(struct dwc2_hsotg *hsotg)
2080{
2081 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2082
2083 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2084 _dwc2_hcd_start(hcd);
2085}
2086
2087void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2088{
2089 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2090
2091 hcd->self.is_b_host = 0;
2092}
2093
2094void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2095 int *hub_port)
2096{
2097 struct urb *urb = context;
2098
2099 if (urb->dev->tt)
2100 *hub_addr = urb->dev->tt->hub->devnum;
2101 else
2102 *hub_addr = 0;
2103 *hub_port = urb->dev->ttport;
2104}
2105
2106int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2107{
2108 struct urb *urb = context;
2109
2110 return urb->dev->speed;
2111}
2112
2113static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2114 struct urb *urb)
2115{
2116 struct usb_bus *bus = hcd_to_bus(hcd);
2117
2118 if (urb->interval)
2119 bus->bandwidth_allocated += bw / urb->interval;
2120 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2121 bus->bandwidth_isoc_reqs++;
2122 else
2123 bus->bandwidth_int_reqs++;
2124}
2125
2126static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2127 struct urb *urb)
2128{
2129 struct usb_bus *bus = hcd_to_bus(hcd);
2130
2131 if (urb->interval)
2132 bus->bandwidth_allocated -= bw / urb->interval;
2133 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2134 bus->bandwidth_isoc_reqs--;
2135 else
2136 bus->bandwidth_int_reqs--;
2137}
2138
2139/*
2140 * Sets the final status of an URB and returns it to the upper layer. Any
2141 * required cleanup of the URB is performed.
2142 *
2143 * Must be called with interrupt disabled and spinlock held
2144 */
0d012b98
PZ		 2145void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2146 int status)
7359d482 2147{
0d012b98 2148 struct urb *urb;
7359d482
PZ		 2149 int i;
2150
0d012b98
PZ		 2151 if (!qtd) {
2152 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
7359d482
PZ		 2153 return;
2154 }
2155
0d012b98
PZ		 2156 if (!qtd->urb) {
2157 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
7359d482
PZ		 2158 return;
2159 }
2160
0d012b98
PZ		 2161 urb = qtd->urb->priv;
2162 if (!urb) {
2163 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2164 return;
2165 }
2166
2167 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
7359d482 2168
b49977a6
MK		 2169 if (dbg_urb(urb))
2170 dev_vdbg(hsotg->dev,
2171 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2172 __func__, urb, usb_pipedevice(urb->pipe),
2173 usb_pipeendpoint(urb->pipe),
2174 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2175 urb->actual_length);
7359d482 2176
b49977a6 2177 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
7359d482
PZ		 2178 for (i = 0; i < urb->number_of_packets; i++)
2179 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2180 i, urb->iso_frame_desc[i].status);
2181 }
2182
2183 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
0d012b98 2184 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
7359d482
PZ		 2185 for (i = 0; i < urb->number_of_packets; ++i) {
2186 urb->iso_frame_desc[i].actual_length =
2187 dwc2_hcd_urb_get_iso_desc_actual_length(
0d012b98 2188 qtd->urb, i);
7359d482 2189 urb->iso_frame_desc[i].status =
0d012b98 2190 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
7359d482
PZ		 2191 }
2192 }
2193
2194 urb->status = status;
7359d482
PZ		 2195 if (!status) {
2196 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2197 urb->actual_length < urb->transfer_buffer_length)
2198 urb->status = -EREMOTEIO;
2199 }
2200
2201 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2202 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2203 struct usb_host_endpoint *ep = urb->ep;
2204
2205 if (ep)
2206 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2207 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2208 urb);
2209 }
2210
c9e1c907 2211 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
0d012b98
PZ		 2212 urb->hcpriv = NULL;
2213 kfree(qtd->urb);
2214 qtd->urb = NULL;
7359d482
PZ		 2215
2216 spin_unlock(&hsotg->lock);
2217 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2218 spin_lock(&hsotg->lock);
2219}
2220
2221/*
2222 * Work queue function for starting the HCD when A-Cable is connected
2223 */
2224static void dwc2_hcd_start_func(struct work_struct *work)
2225{
2226 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2227 start_work.work);
2228
2229 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2230 dwc2_host_start(hsotg);
2231}
2232
2233/*
2234 * Reset work queue function
2235 */
2236static void dwc2_hcd_reset_func(struct work_struct *work)
2237{
2238 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2239 reset_work.work);
2240 u32 hprt0;
2241
2242 dev_dbg(hsotg->dev, "USB RESET function called\n");
2243 hprt0 = dwc2_read_hprt0(hsotg);
2244 hprt0 &= ~HPRT0_RST;
2245 writel(hprt0, hsotg->regs + HPRT0);
2246 hsotg->flags.b.port_reset_change = 1;
2247}
2248
2249/*
2250 * =========================================================================
2251 * Linux HC Driver Functions
2252 * =========================================================================
2253 */
2254
2255/*
2256 * Initializes the DWC_otg controller and its root hub and prepares it for host
2257 * mode operation. Activates the root port. Returns 0 on success and a negative
2258 * error code on failure.
2259 */
2260static int _dwc2_hcd_start(struct usb_hcd *hcd)
2261{
2262 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2263 struct usb_bus *bus = hcd_to_bus(hcd);
2264 unsigned long flags;
2265
2266 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2267
2268 spin_lock_irqsave(&hsotg->lock, flags);
2269
2270 hcd->state = HC_STATE_RUNNING;
2271
2272 if (dwc2_is_device_mode(hsotg)) {
2273 spin_unlock_irqrestore(&hsotg->lock, flags);
2274 return 0; /* why 0 ?? */
2275 }
2276
2277 dwc2_hcd_reinit(hsotg);
2278
2279 /* Initialize and connect root hub if one is not already attached */
2280 if (bus->root_hub) {
2281 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2282 /* Inform the HUB driver to resume */
2283 usb_hcd_resume_root_hub(hcd);
2284 }
2285
2286 spin_unlock_irqrestore(&hsotg->lock, flags);
2287 return 0;
2288}
2289
2290/*
2291 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2292 * stopped.
2293 */
2294static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2295{
2296 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2297 unsigned long flags;
2298
2299 spin_lock_irqsave(&hsotg->lock, flags);
2300 dwc2_hcd_stop(hsotg);
2301 spin_unlock_irqrestore(&hsotg->lock, flags);
2302
2303 usleep_range(1000, 3000);
2304}
2305
2306/* Returns the current frame number */
2307static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2308{
2309 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2310
2311 return dwc2_hcd_get_frame_number(hsotg);
2312}
2313
2314static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2315 char *fn_name)
2316{
2317#ifdef VERBOSE_DEBUG
2318 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2319 char *pipetype;
2320 char *speed;
2321
2322 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2323 dev_vdbg(hsotg->dev, " Device address: %d\n",
2324 usb_pipedevice(urb->pipe));
2325 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2326 usb_pipeendpoint(urb->pipe),
2327 usb_pipein(urb->pipe) ? "IN" : "OUT");
2328
2329 switch (usb_pipetype(urb->pipe)) {
2330 case PIPE_CONTROL:
2331 pipetype = "CONTROL";
2332 break;
2333 case PIPE_BULK:
2334 pipetype = "BULK";
2335 break;
2336 case PIPE_INTERRUPT:
2337 pipetype = "INTERRUPT";
2338 break;
2339 case PIPE_ISOCHRONOUS:
2340 pipetype = "ISOCHRONOUS";
2341 break;
2342 default:
2343 pipetype = "UNKNOWN";
2344 break;
2345 }
2346
2347 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2348 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2349 "IN" : "OUT");
2350
2351 switch (urb->dev->speed) {
2352 case USB_SPEED_HIGH:
2353 speed = "HIGH";
2354 break;
2355 case USB_SPEED_FULL:
2356 speed = "FULL";
2357 break;
2358 case USB_SPEED_LOW:
2359 speed = "LOW";
2360 break;
2361 default:
2362 speed = "UNKNOWN";
2363 break;
2364 }
2365
2366 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2367 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2368 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2369 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2370 urb->transfer_buffer_length);
157dfaac
PZ		 2371 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2372 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2373 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2374 urb->setup_packet, (unsigned long)urb->setup_dma);
7359d482
PZ		 2375 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2376
2377 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2378 int i;
2379
2380 for (i = 0; i < urb->number_of_packets; i++) {
2381 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2382 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2383 urb->iso_frame_desc[i].offset,
2384 urb->iso_frame_desc[i].length);
2385 }
2386 }
2387#endif
2388}
2389
2390/*
2391 * Starts processing a USB transfer request specified by a USB Request Block
2392 * (URB). mem_flags indicates the type of memory allocation to use while
2393 * processing this URB.
2394 */
2395static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2396 gfp_t mem_flags)
2397{
2398 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2399 struct usb_host_endpoint *ep = urb->ep;
2400 struct dwc2_hcd_urb *dwc2_urb;
2401 int i;
c9e1c907 2402 int retval;
7359d482 2403 int alloc_bandwidth = 0;
7359d482
PZ		 2404 u8 ep_type = 0;
2405 u32 tflags = 0;
2406 void *buf;
2407 unsigned long flags;
2408
b49977a6
MK		 2409 if (dbg_urb(urb)) {
2410 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2411 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2412 }
7359d482
PZ		 2413
2414 if (ep == NULL)
2415 return -EINVAL;
2416
2417 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2418 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2419 spin_lock_irqsave(&hsotg->lock, flags);
2420 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2421 alloc_bandwidth = 1;
2422 spin_unlock_irqrestore(&hsotg->lock, flags);
2423 }
2424
2425 switch (usb_pipetype(urb->pipe)) {
2426 case PIPE_CONTROL:
2427 ep_type = USB_ENDPOINT_XFER_CONTROL;
2428 break;
2429 case PIPE_ISOCHRONOUS:
2430 ep_type = USB_ENDPOINT_XFER_ISOC;
2431 break;
2432 case PIPE_BULK:
2433 ep_type = USB_ENDPOINT_XFER_BULK;
2434 break;
2435 case PIPE_INTERRUPT:
2436 ep_type = USB_ENDPOINT_XFER_INT;
2437 break;
2438 default:
2439 dev_warn(hsotg->dev, "Wrong ep type\n");
2440 }
2441
2442 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2443 mem_flags);
2444 if (!dwc2_urb)
2445 return -ENOMEM;
2446
2447 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2448 usb_pipeendpoint(urb->pipe), ep_type,
2449 usb_pipein(urb->pipe),
2450 usb_maxpacket(urb->dev, urb->pipe,
2451 !(usb_pipein(urb->pipe))));
2452
2453 buf = urb->transfer_buffer;
25a49445 2454
7359d482 2455 if (hcd->self.uses_dma) {
25a49445
PZ		 2456 if (!buf && (urb->transfer_dma & 3)) {
2457 dev_err(hsotg->dev,
2458 "%s: unaligned transfer with no transfer_buffer",
2459 __func__);
2460 retval = -EINVAL;
2461 goto fail1;
2462 }
7359d482
PZ		 2463 }
2464
2465 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2466 tflags |= URB_GIVEBACK_ASAP;
2467 if (urb->transfer_flags & URB_ZERO_PACKET)
2468 tflags |= URB_SEND_ZERO_PACKET;
2469
2470 dwc2_urb->priv = urb;
2471 dwc2_urb->buf = buf;
2472 dwc2_urb->dma = urb->transfer_dma;
2473 dwc2_urb->length = urb->transfer_buffer_length;
2474 dwc2_urb->setup_packet = urb->setup_packet;
2475 dwc2_urb->setup_dma = urb->setup_dma;
2476 dwc2_urb->flags = tflags;
2477 dwc2_urb->interval = urb->interval;
2478 dwc2_urb->status = -EINPROGRESS;
2479
2480 for (i = 0; i < urb->number_of_packets; ++i)
2481 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2482 urb->iso_frame_desc[i].offset,
2483 urb->iso_frame_desc[i].length);
2484
2485 urb->hcpriv = dwc2_urb;
c9e1c907
PZ		 2486
2487 spin_lock_irqsave(&hsotg->lock, flags);
2488 retval = usb_hcd_link_urb_to_ep(hcd, urb);
2489 spin_unlock_irqrestore(&hsotg->lock, flags);
2490 if (retval)
2491 goto fail1;
2492
2493 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags);
2494 if (retval)
2495 goto fail2;
2496
2497 if (alloc_bandwidth) {
2498 spin_lock_irqsave(&hsotg->lock, flags);
2499 dwc2_allocate_bus_bandwidth(hcd,
2500 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2501 urb);
2502 spin_unlock_irqrestore(&hsotg->lock, flags);
7359d482
PZ		 2503 }
2504
c9e1c907
PZ		 2505 return 0;
2506
2507fail2:
2508 spin_lock_irqsave(&hsotg->lock, flags);
2509 dwc2_urb->priv = NULL;
2510 usb_hcd_unlink_urb_from_ep(hcd, urb);
2511 spin_unlock_irqrestore(&hsotg->lock, flags);
2512fail1:
2513 urb->hcpriv = NULL;
2514 kfree(dwc2_urb);
2515
7359d482
PZ		 2516 return retval;
2517}
2518
2519/*
2520 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2521 */
2522static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2523 int status)
2524{
2525 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
c9e1c907 2526 int rc;
7359d482
PZ		 2527 unsigned long flags;
2528
2529 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2530 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2531
2532 spin_lock_irqsave(&hsotg->lock, flags);
2533
c9e1c907
PZ		 2534 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2535 if (rc)
2536 goto out;
2537
7359d482
PZ		 2538 if (!urb->hcpriv) {
2539 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2540 goto out;
2541 }
2542
2543 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2544
c9e1c907
PZ		 2545 usb_hcd_unlink_urb_from_ep(hcd, urb);
2546
7359d482
PZ		 2547 kfree(urb->hcpriv);
2548 urb->hcpriv = NULL;
2549
2550 /* Higher layer software sets URB status */
2551 spin_unlock(&hsotg->lock);
2552 usb_hcd_giveback_urb(hcd, urb, status);
2553 spin_lock(&hsotg->lock);
2554
2555 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2556 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2557out:
2558 spin_unlock_irqrestore(&hsotg->lock, flags);
2559
2560 return rc;
2561}
2562
2563/*
2564 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2565 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2566 * must already be dequeued.
2567 */
2568static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2569 struct usb_host_endpoint *ep)
2570{
2571 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2572
2573 dev_dbg(hsotg->dev,
2574 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2575 ep->desc.bEndpointAddress, ep->hcpriv);
2576 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2577}
2578
2579/*
2580 * Resets endpoint specific parameter values, in current version used to reset
2581 * the data toggle (as a WA). This function can be called from usb_clear_halt
2582 * routine.
2583 */
2584static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2585 struct usb_host_endpoint *ep)
2586{
2587 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482
PZ		 2588 unsigned long flags;
2589
2590 dev_dbg(hsotg->dev,
2591 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2592 ep->desc.bEndpointAddress);
2593
7359d482 2594 spin_lock_irqsave(&hsotg->lock, flags);
7359d482 2595 dwc2_hcd_endpoint_reset(hsotg, ep);
7359d482
PZ		 2596 spin_unlock_irqrestore(&hsotg->lock, flags);
2597}
2598
2599/*
2600 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2601 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2602 * interrupt.
2603 *
2604 * This function is called by the USB core when an interrupt occurs
2605 */
2606static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2607{
2608 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482 2609
ca18f4a6 2610 return dwc2_handle_hcd_intr(hsotg);
7359d482
PZ		 2611}
2612
2613/*
2614 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2615 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2616 * is the status change indicator for the single root port. Returns 1 if either
2617 * change indicator is 1, otherwise returns 0.
2618 */
2619static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2620{
2621 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2622
2623 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2624 return buf[0] != 0;
2625}
2626
2627/* Handles hub class-specific requests */
2628static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2629 u16 windex, char *buf, u16 wlength)
2630{
2631 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2632 wvalue, windex, buf, wlength);
2633 return retval;
2634}
2635
2636/* Handles hub TT buffer clear completions */
2637static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2638 struct usb_host_endpoint *ep)
2639{
2640 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2641 struct dwc2_qh *qh;
2642 unsigned long flags;
2643
2644 qh = ep->hcpriv;
2645 if (!qh)
2646 return;
2647
2648 spin_lock_irqsave(&hsotg->lock, flags);
2649 qh->tt_buffer_dirty = 0;
2650
2651 if (hsotg->flags.b.port_connect_status)
2652 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2653
2654 spin_unlock_irqrestore(&hsotg->lock, flags);
2655}
2656
2657static struct hc_driver dwc2_hc_driver = {
2658 .description = "dwc2_hsotg",
2659 .product_desc = "DWC OTG Controller",
2660 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2661
2662 .irq = _dwc2_hcd_irq,
2663 .flags = HCD_MEMORY | HCD_USB2,
2664
2665 .start = _dwc2_hcd_start,
2666 .stop = _dwc2_hcd_stop,
2667 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2668 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2669 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2670 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2671 .get_frame_number = _dwc2_hcd_get_frame_number,
2672
2673 .hub_status_data = _dwc2_hcd_hub_status_data,
2674 .hub_control = _dwc2_hcd_hub_control,
2675 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2676};
2677
2678/*
2679 * Frees secondary storage associated with the dwc2_hsotg structure contained
2680 * in the struct usb_hcd field
2681 */
2682static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2683{
2684 u32 ahbcfg;
2685 u32 dctl;
2686 int i;
2687
2688 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2689
2690 /* Free memory for QH/QTD lists */
2691 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2692 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2693 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2694 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2695 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2696 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2697
2698 /* Free memory for the host channels */
2699 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2700 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2701
2702 if (chan != NULL) {
2703 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2704 i, chan);
2705 hsotg->hc_ptr_array[i] = NULL;
2706 kfree(chan);
2707 }
2708 }
2709
2710 if (hsotg->core_params->dma_enable > 0) {
2711 if (hsotg->status_buf) {
2712 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2713 hsotg->status_buf,
2714 hsotg->status_buf_dma);
2715 hsotg->status_buf = NULL;
2716 }
2717 } else {
2718 kfree(hsotg->status_buf);
2719 hsotg->status_buf = NULL;
2720 }
2721
2722 ahbcfg = readl(hsotg->regs + GAHBCFG);
2723
2724 /* Disable all interrupts */
2725 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2726 writel(ahbcfg, hsotg->regs + GAHBCFG);
2727 writel(0, hsotg->regs + GINTMSK);
2728
9badec2f 2729 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
7359d482
PZ		 2730 dctl = readl(hsotg->regs + DCTL);
2731 dctl |= DCTL_SFTDISCON;
2732 writel(dctl, hsotg->regs + DCTL);
2733 }
2734
2735 if (hsotg->wq_otg) {
2736 if (!cancel_work_sync(&hsotg->wf_otg))
2737 flush_workqueue(hsotg->wq_otg);
2738 destroy_workqueue(hsotg->wq_otg);
2739 }
2740
2741 kfree(hsotg->core_params);
2742 hsotg->core_params = NULL;
2743 del_timer(&hsotg->wkp_timer);
2744}
2745
2746static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2747{
2748 /* Turn off all host-specific interrupts */
2749 dwc2_disable_host_interrupts(hsotg);
2750
2751 dwc2_hcd_free(hsotg);
2752}
2753
8284f93b
MK		 2754/*
2755 * Sets all parameters to the given value.
2756 *
2757 * Assumes that the dwc2_core_params struct contains only integers.
2758 */
2759void dwc2_set_all_params(struct dwc2_core_params *params, int value)
7359d482 2760{
8284f93b
MK		 2761 int *p = (int *)params;
2762 size_t size = sizeof(*params) / sizeof(*p);
7359d482
PZ		 2763 int i;
2764
2765 for (i = 0; i < size; i++)
b39ed5c7 2766 p[i] = value;
7359d482 2767}
5b9974b1 2768EXPORT_SYMBOL_GPL(dwc2_set_all_params);
7359d482
PZ		 2769
2770/*
2771 * Initializes the HCD. This function allocates memory for and initializes the
2772 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2773 * USB bus with the core and calls the hc_driver->start() function. It returns
2774 * a negative error on failure.
2775 */
e62662c7 2776int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
90dbceaf 2777 const struct dwc2_core_params *params)
7359d482
PZ		 2778{
2779 struct usb_hcd *hcd;
2780 struct dwc2_host_chan *channel;
9badec2f 2781 u32 hcfg;
7359d482 2782 int i, num_channels;
9badec2f 2783 int retval;
7359d482 2784
f5500ecc
DN		 2785 if (usb_disabled())
2786 return -ENODEV;
2787
e62662c7 2788 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
7359d482 2789
9badec2f
MK		 2790 /* Detect config values from hardware */
2791 retval = dwc2_get_hwparams(hsotg);
7359d482 2792
9badec2f
MK		 2793 if (retval)
2794 return retval;
2795
2796 retval = -ENOMEM;
7359d482
PZ		 2797
2798 hcfg = readl(hsotg->regs + HCFG);
2799 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
7359d482
PZ		 2800
2801#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2802 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2803 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2804 if (!hsotg->frame_num_array)
ba0e60d1 2805 goto error1;
7359d482
PZ		 2806 hsotg->last_frame_num_array = kzalloc(
2807 sizeof(*hsotg->last_frame_num_array) *
2808 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2809 if (!hsotg->last_frame_num_array)
ba0e60d1 2810 goto error1;
7359d482
PZ		 2811 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2812#endif
2813
2814 hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL);
2815 if (!hsotg->core_params)
ba0e60d1 2816 goto error1;
7359d482 2817
8284f93b 2818 dwc2_set_all_params(hsotg->core_params, -1);
7359d482
PZ		 2819
2820 /* Validate parameter values */
2821 dwc2_set_parameters(hsotg, params);
2822
a0112f48
MK		 2823 /* Check if the bus driver or platform code has setup a dma_mask */
2824 if (hsotg->core_params->dma_enable > 0 &&
2825 hsotg->dev->dma_mask == NULL) {
2826 dev_warn(hsotg->dev,
2827 "dma_mask not set, disabling DMA\n");
2828 hsotg->core_params->dma_enable = 0;
2829 hsotg->core_params->dma_desc_enable = 0;
2830 }
2831
ba0e60d1
PZ		 2832 /* Set device flags indicating whether the HCD supports DMA */
2833 if (hsotg->core_params->dma_enable > 0) {
30885313
PZ		 2834 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2835 dev_warn(hsotg->dev, "can't set DMA mask\n");
25a49445
PZ		 2836 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2837 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
ba0e60d1
PZ		 2838 }
2839
2840 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2841 if (!hcd)
2842 goto error1;
2843
7de76ee1
MK		 2844 if (hsotg->core_params->dma_enable <= 0)
2845 hcd->self.uses_dma = 0;
2846
ba0e60d1
PZ		 2847 hcd->has_tt = 1;
2848
ba0e60d1
PZ		 2849 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2850 hsotg->priv = hcd;
2851
7359d482
PZ		 2852 /*
2853 * Disable the global interrupt until all the interrupt handlers are
2854 * installed
2855 */
2856 dwc2_disable_global_interrupts(hsotg);
2857
6706c721
MK		 2858 /* Initialize the DWC_otg core, and select the Phy type */
2859 retval = dwc2_core_init(hsotg, true, irq);
2860 if (retval)
2861 goto error2;
2862
7359d482 2863 /* Create new workqueue and init work */
53510352 2864 retval = -ENOMEM;
050232a7 2865 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
7359d482
PZ		 2866 if (!hsotg->wq_otg) {
2867 dev_err(hsotg->dev, "Failed to create workqueue\n");
2868 goto error2;
2869 }
2870 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2871
7359d482
PZ		 2872 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2873 (unsigned long)hsotg);
2874
2875 /* Initialize the non-periodic schedule */
2876 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2877 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2878
2879 /* Initialize the periodic schedule */
2880 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2881 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2882 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2883 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2884
2885 /*
2886 * Create a host channel descriptor for each host channel implemented
2887 * in the controller. Initialize the channel descriptor array.
2888 */
2889 INIT_LIST_HEAD(&hsotg->free_hc_list);
2890 num_channels = hsotg->core_params->host_channels;
2891 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2892
2893 for (i = 0; i < num_channels; i++) {
2894 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2895 if (channel == NULL)
2896 goto error3;
2897 channel->hc_num = i;
2898 hsotg->hc_ptr_array[i] = channel;
2899 }
2900
20f2eb9c
DC		 2901 if (hsotg->core_params->uframe_sched > 0)
2902 dwc2_hcd_init_usecs(hsotg);
2903
7359d482
PZ		 2904 /* Initialize hsotg start work */
2905 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2906
2907 /* Initialize port reset work */
2908 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2909
2910 /*
2911 * Allocate space for storing data on status transactions. Normally no
2912 * data is sent, but this space acts as a bit bucket. This must be
2913 * done after usb_add_hcd since that function allocates the DMA buffer
2914 * pool.
2915 */
2916 if (hsotg->core_params->dma_enable > 0)
2917 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2918 DWC2_HCD_STATUS_BUF_SIZE,
2919 &hsotg->status_buf_dma, GFP_KERNEL);
2920 else
2921 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2922 GFP_KERNEL);
2923
2924 if (!hsotg->status_buf)
2925 goto error3;
2926
2927 hsotg->otg_port = 1;
2928 hsotg->frame_list = NULL;
2929 hsotg->frame_list_dma = 0;
2930 hsotg->periodic_qh_count = 0;
2931
2932 /* Initiate lx_state to L3 disconnected state */
2933 hsotg->lx_state = DWC2_L3;
2934
2935 hcd->self.otg_port = hsotg->otg_port;
2936
2937 /* Don't support SG list at this point */
2938 hcd->self.sg_tablesize = 0;
2939
2940 /*
2941 * Finish generic HCD initialization and start the HCD. This function
2942 * allocates the DMA buffer pool, registers the USB bus, requests the
2943 * IRQ line, and calls hcd_start method.
2944 */
66513f49 2945 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
7359d482
PZ		 2946 if (retval < 0)
2947 goto error3;
2948
3c9740a1
PC		 2949 device_wakeup_enable(hcd->self.controller);
2950
7359d482
PZ		 2951 dwc2_hcd_dump_state(hsotg);
2952
2953 dwc2_enable_global_interrupts(hsotg);
2954
2955 return 0;
2956
2957error3:
2958 dwc2_hcd_release(hsotg);
2959error2:
ba0e60d1
PZ		 2960 usb_put_hcd(hcd);
2961error1:
7359d482
PZ		 2962 kfree(hsotg->core_params);
2963
2964#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2965 kfree(hsotg->last_frame_num_array);
2966 kfree(hsotg->frame_num_array);
2967#endif
2968
e62662c7 2969 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
7359d482
PZ		 2970 return retval;
2971}
2972EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2973
2974/*
2975 * Removes the HCD.
2976 * Frees memory and resources associated with the HCD and deregisters the bus.
2977 */
e62662c7 2978void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
7359d482
PZ		 2979{
2980 struct usb_hcd *hcd;
2981
e62662c7 2982 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
7359d482
PZ		 2983
2984 hcd = dwc2_hsotg_to_hcd(hsotg);
e62662c7 2985 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
7359d482
PZ		 2986
2987 if (!hcd) {
e62662c7 2988 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
7359d482
PZ		 2989 __func__);
2990 return;
2991 }
2992
2993 usb_remove_hcd(hcd);
2994 hsotg->priv = NULL;
2995 dwc2_hcd_release(hsotg);
ba0e60d1 2996 usb_put_hcd(hcd);
7359d482
PZ		 2997
2998#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2999 kfree(hsotg->last_frame_num_array);
3000 kfree(hsotg->frame_num_array);
3001#endif
7359d482
PZ		 3002}
3003EXPORT_SYMBOL_GPL(dwc2_hcd_remove);
Linux kernel - Deliverables
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