Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
a72e658b | 22 | #include <linux/module.h> |
72246da4 FB |
23 | #include <linux/kernel.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
457e84b6 | 34 | #include <linux/of.h> |
72246da4 FB |
35 | |
36 | #include <linux/usb/ch9.h> | |
37 | #include <linux/usb/gadget.h> | |
f7e846f0 | 38 | #include <linux/usb/of.h> |
a45c82b8 | 39 | #include <linux/usb/otg.h> |
72246da4 | 40 | |
6462cbd5 | 41 | #include "platform_data.h" |
72246da4 FB |
42 | #include "core.h" |
43 | #include "gadget.h" | |
44 | #include "io.h" | |
45 | ||
46 | #include "debug.h" | |
47 | ||
8300dd23 FB |
48 | /* -------------------------------------------------------------------------- */ |
49 | ||
3140e8cb SAS |
50 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
51 | { | |
52 | u32 reg; | |
53 | ||
54 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
55 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
56 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
57 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
58 | } | |
8300dd23 | 59 | |
72246da4 FB |
60 | /** |
61 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
62 | * @dwc: pointer to our context structure | |
63 | */ | |
64 | static void dwc3_core_soft_reset(struct dwc3 *dwc) | |
65 | { | |
66 | u32 reg; | |
67 | ||
68 | /* Before Resetting PHY, put Core in Reset */ | |
69 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
70 | reg |= DWC3_GCTL_CORESOFTRESET; | |
71 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
72 | ||
73 | /* Assert USB3 PHY reset */ | |
74 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
75 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
76 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
77 | ||
78 | /* Assert USB2 PHY reset */ | |
79 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
80 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
81 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
82 | ||
51e1e7bc FB |
83 | usb_phy_init(dwc->usb2_phy); |
84 | usb_phy_init(dwc->usb3_phy); | |
72246da4 FB |
85 | mdelay(100); |
86 | ||
87 | /* Clear USB3 PHY reset */ | |
88 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
89 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
90 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
91 | ||
92 | /* Clear USB2 PHY reset */ | |
93 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
94 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
95 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
96 | ||
45627ac6 PA |
97 | mdelay(100); |
98 | ||
72246da4 FB |
99 | /* After PHYs are stable we can take Core out of reset state */ |
100 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
101 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
102 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
103 | } | |
104 | ||
105 | /** | |
106 | * dwc3_free_one_event_buffer - Frees one event buffer | |
107 | * @dwc: Pointer to our controller context structure | |
108 | * @evt: Pointer to event buffer to be freed | |
109 | */ | |
110 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
111 | struct dwc3_event_buffer *evt) | |
112 | { | |
113 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
114 | } |
115 | ||
116 | /** | |
1d046793 | 117 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
118 | * @dwc: Pointer to our controller context structure |
119 | * @length: size of the event buffer | |
120 | * | |
1d046793 | 121 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
122 | * otherwise ERR_PTR(errno). |
123 | */ | |
67d0b500 FB |
124 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
125 | unsigned length) | |
72246da4 FB |
126 | { |
127 | struct dwc3_event_buffer *evt; | |
128 | ||
380f0d28 | 129 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
130 | if (!evt) |
131 | return ERR_PTR(-ENOMEM); | |
132 | ||
133 | evt->dwc = dwc; | |
134 | evt->length = length; | |
135 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
136 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 137 | if (!evt->buf) |
72246da4 | 138 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
139 | |
140 | return evt; | |
141 | } | |
142 | ||
143 | /** | |
144 | * dwc3_free_event_buffers - frees all allocated event buffers | |
145 | * @dwc: Pointer to our controller context structure | |
146 | */ | |
147 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
148 | { | |
149 | struct dwc3_event_buffer *evt; | |
150 | int i; | |
151 | ||
9f622b2a | 152 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 153 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 154 | if (evt) |
72246da4 | 155 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
156 | } |
157 | } | |
158 | ||
159 | /** | |
160 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 161 | * @dwc: pointer to our controller context structure |
72246da4 FB |
162 | * @length: size of event buffer |
163 | * | |
1d046793 | 164 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
165 | * may contain some buffers allocated but not all which were requested. |
166 | */ | |
41ac7b3a | 167 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 168 | { |
9f622b2a | 169 | int num; |
72246da4 FB |
170 | int i; |
171 | ||
9f622b2a FB |
172 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
173 | dwc->num_event_buffers = num; | |
174 | ||
380f0d28 FB |
175 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
176 | GFP_KERNEL); | |
457d3f21 FB |
177 | if (!dwc->ev_buffs) { |
178 | dev_err(dwc->dev, "can't allocate event buffers array\n"); | |
179 | return -ENOMEM; | |
180 | } | |
181 | ||
72246da4 FB |
182 | for (i = 0; i < num; i++) { |
183 | struct dwc3_event_buffer *evt; | |
184 | ||
185 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
186 | if (IS_ERR(evt)) { | |
187 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
188 | return PTR_ERR(evt); | |
189 | } | |
190 | dwc->ev_buffs[i] = evt; | |
191 | } | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | /** | |
197 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 198 | * @dwc: pointer to our controller context structure |
72246da4 FB |
199 | * |
200 | * Returns 0 on success otherwise negative errno. | |
201 | */ | |
7acd85e0 | 202 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
203 | { |
204 | struct dwc3_event_buffer *evt; | |
205 | int n; | |
206 | ||
9f622b2a | 207 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
208 | evt = dwc->ev_buffs[n]; |
209 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
210 | evt->buf, (unsigned long long) evt->dma, | |
211 | evt->length); | |
212 | ||
7acd85e0 PZ |
213 | evt->lpos = 0; |
214 | ||
72246da4 FB |
215 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
216 | lower_32_bits(evt->dma)); | |
217 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
218 | upper_32_bits(evt->dma)); | |
219 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
68d6a01b | 220 | DWC3_GEVNTSIZ_SIZE(evt->length)); |
72246da4 FB |
221 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
228 | { | |
229 | struct dwc3_event_buffer *evt; | |
230 | int n; | |
231 | ||
9f622b2a | 232 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 233 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
234 | |
235 | evt->lpos = 0; | |
236 | ||
72246da4 FB |
237 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
238 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
68d6a01b FB |
239 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK |
240 | | DWC3_GEVNTSIZ_SIZE(0)); | |
72246da4 FB |
241 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
242 | } | |
243 | } | |
244 | ||
789451f6 FB |
245 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
246 | { | |
247 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
248 | ||
249 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
250 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
251 | ||
252 | dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", | |
253 | dwc->num_in_eps, dwc->num_out_eps); | |
254 | } | |
255 | ||
41ac7b3a | 256 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
257 | { |
258 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
259 | ||
260 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
261 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
262 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
263 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
264 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
265 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
266 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
267 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
268 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
269 | } | |
270 | ||
72246da4 FB |
271 | /** |
272 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
273 | * @dwc: Pointer to our controller context structure | |
274 | * | |
275 | * Returns 0 on success otherwise negative errno. | |
276 | */ | |
41ac7b3a | 277 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 FB |
278 | { |
279 | unsigned long timeout; | |
280 | u32 reg; | |
281 | int ret; | |
282 | ||
7650bd74 SAS |
283 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
284 | /* This should read as U3 followed by revision number */ | |
285 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
286 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
287 | ret = -ENODEV; | |
288 | goto err0; | |
289 | } | |
248b122b | 290 | dwc->revision = reg; |
7650bd74 | 291 | |
72246da4 FB |
292 | /* issue device SoftReset too */ |
293 | timeout = jiffies + msecs_to_jiffies(500); | |
294 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
295 | do { | |
296 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
297 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
298 | break; | |
299 | ||
300 | if (time_after(jiffies, timeout)) { | |
301 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
302 | ret = -ETIMEDOUT; | |
303 | goto err0; | |
304 | } | |
305 | ||
306 | cpu_relax(); | |
307 | } while (true); | |
308 | ||
58a0f23f PA |
309 | dwc3_core_soft_reset(dwc); |
310 | ||
4878a028 | 311 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 312 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 SAS |
313 | reg &= ~DWC3_GCTL_DISSCRAMBLE; |
314 | ||
164d7731 | 315 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 SAS |
316 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
317 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
318 | break; | |
319 | default: | |
320 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
321 | } | |
322 | ||
323 | /* | |
324 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 325 | * where the device can fail to connect at SuperSpeed |
4878a028 | 326 | * and falls back to high-speed mode which causes |
1d046793 | 327 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
328 | */ |
329 | if (dwc->revision < DWC3_REVISION_190A) | |
330 | reg |= DWC3_GCTL_U2RSTECN; | |
331 | ||
789451f6 FB |
332 | dwc3_core_num_eps(dwc); |
333 | ||
4878a028 SAS |
334 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
335 | ||
72246da4 FB |
336 | return 0; |
337 | ||
72246da4 FB |
338 | err0: |
339 | return ret; | |
340 | } | |
341 | ||
342 | static void dwc3_core_exit(struct dwc3 *dwc) | |
343 | { | |
01b8daf7 VG |
344 | usb_phy_shutdown(dwc->usb2_phy); |
345 | usb_phy_shutdown(dwc->usb3_phy); | |
72246da4 FB |
346 | } |
347 | ||
348 | #define DWC3_ALIGN_MASK (16 - 1) | |
349 | ||
41ac7b3a | 350 | static int dwc3_probe(struct platform_device *pdev) |
72246da4 | 351 | { |
941ea361 FB |
352 | struct device *dev = &pdev->dev; |
353 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
354 | struct device_node *node = dev->of_node; | |
72246da4 FB |
355 | struct resource *res; |
356 | struct dwc3 *dwc; | |
0949e99b | 357 | |
72246da4 | 358 | int ret = -ENOMEM; |
0949e99b FB |
359 | |
360 | void __iomem *regs; | |
72246da4 FB |
361 | void *mem; |
362 | ||
802ca850 | 363 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); |
72246da4 | 364 | if (!mem) { |
802ca850 CP |
365 | dev_err(dev, "not enough memory\n"); |
366 | return -ENOMEM; | |
72246da4 FB |
367 | } |
368 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); | |
369 | dwc->mem = mem; | |
370 | ||
51249dca | 371 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
72246da4 | 372 | if (!res) { |
51249dca | 373 | dev_err(dev, "missing IRQ\n"); |
802ca850 | 374 | return -ENODEV; |
72246da4 | 375 | } |
066618bc KVA |
376 | dwc->xhci_resources[1].start = res->start; |
377 | dwc->xhci_resources[1].end = res->end; | |
378 | dwc->xhci_resources[1].flags = res->flags; | |
379 | dwc->xhci_resources[1].name = res->name; | |
72246da4 | 380 | |
51249dca IS |
381 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
382 | if (!res) { | |
383 | dev_err(dev, "missing memory resource\n"); | |
384 | return -ENODEV; | |
385 | } | |
72246da4 | 386 | |
5088b6f5 | 387 | if (node) { |
f7e846f0 FB |
388 | dwc->maximum_speed = of_usb_get_maximum_speed(node); |
389 | ||
5088b6f5 KVA |
390 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); |
391 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
6462cbd5 FB |
392 | |
393 | dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize"); | |
a45c82b8 | 394 | dwc->dr_mode = of_usb_get_dr_mode(node); |
bb674907 | 395 | } else if (pdata) { |
f7e846f0 FB |
396 | dwc->maximum_speed = pdata->maximum_speed; |
397 | ||
5088b6f5 KVA |
398 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); |
399 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
6462cbd5 FB |
400 | |
401 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
a45c82b8 | 402 | dwc->dr_mode = pdata->dr_mode; |
bb674907 FB |
403 | } else { |
404 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
405 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
406 | } |
407 | ||
f7e846f0 FB |
408 | /* default to superspeed if no maximum_speed passed */ |
409 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
410 | dwc->maximum_speed = USB_SPEED_SUPER; | |
411 | ||
d105e7f8 FB |
412 | if (IS_ERR(dwc->usb2_phy)) { |
413 | ret = PTR_ERR(dwc->usb2_phy); | |
414 | ||
415 | /* | |
416 | * if -ENXIO is returned, it means PHY layer wasn't | |
417 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
418 | * in that case, since no PHY driver will ever probe. | |
419 | */ | |
420 | if (ret == -ENXIO) | |
421 | return ret; | |
422 | ||
51e1e7bc FB |
423 | dev_err(dev, "no usb2 phy configured\n"); |
424 | return -EPROBE_DEFER; | |
425 | } | |
426 | ||
d105e7f8 | 427 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 428 | ret = PTR_ERR(dwc->usb3_phy); |
d105e7f8 FB |
429 | |
430 | /* | |
431 | * if -ENXIO is returned, it means PHY layer wasn't | |
432 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
433 | * in that case, since no PHY driver will ever probe. | |
434 | */ | |
435 | if (ret == -ENXIO) | |
436 | return ret; | |
437 | ||
51e1e7bc FB |
438 | dev_err(dev, "no usb3 phy configured\n"); |
439 | return -EPROBE_DEFER; | |
440 | } | |
441 | ||
2e112345 II |
442 | dwc->xhci_resources[0].start = res->start; |
443 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
444 | DWC3_XHCI_REGS_END; | |
445 | dwc->xhci_resources[0].flags = res->flags; | |
446 | dwc->xhci_resources[0].name = res->name; | |
447 | ||
448 | res->start += DWC3_GLOBALS_REGS_START; | |
449 | ||
450 | /* | |
451 | * Request memory region but exclude xHCI regs, | |
452 | * since it will be requested by the xhci-plat driver. | |
453 | */ | |
454 | regs = devm_ioremap_resource(dev, res); | |
455 | if (IS_ERR(regs)) | |
456 | return PTR_ERR(regs); | |
457 | ||
72246da4 FB |
458 | spin_lock_init(&dwc->lock); |
459 | platform_set_drvdata(pdev, dwc); | |
460 | ||
461 | dwc->regs = regs; | |
462 | dwc->regs_size = resource_size(res); | |
802ca850 | 463 | dwc->dev = dev; |
72246da4 | 464 | |
ddff14f1 KVA |
465 | dev->dma_mask = dev->parent->dma_mask; |
466 | dev->dma_parms = dev->parent->dma_parms; | |
467 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
468 | ||
802ca850 CP |
469 | pm_runtime_enable(dev); |
470 | pm_runtime_get_sync(dev); | |
471 | pm_runtime_forbid(dev); | |
72246da4 | 472 | |
4fd24483 KVA |
473 | dwc3_cache_hwparams(dwc); |
474 | ||
3921426b FB |
475 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
476 | if (ret) { | |
477 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
478 | ret = -ENOMEM; | |
479 | goto err0; | |
480 | } | |
481 | ||
72246da4 FB |
482 | ret = dwc3_core_init(dwc); |
483 | if (ret) { | |
802ca850 | 484 | dev_err(dev, "failed to initialize core\n"); |
3921426b | 485 | goto err0; |
72246da4 FB |
486 | } |
487 | ||
3088f108 KVA |
488 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
489 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
490 | ||
f122d33e FB |
491 | ret = dwc3_event_buffers_setup(dwc); |
492 | if (ret) { | |
493 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
494 | goto err1; | |
495 | } | |
496 | ||
cd051da2 | 497 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
a45c82b8 | 498 | dwc->dr_mode = USB_DR_MODE_HOST; |
cd051da2 | 499 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) |
a45c82b8 RK |
500 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; |
501 | ||
502 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
503 | dwc->dr_mode = USB_DR_MODE_OTG; | |
0949e99b | 504 | |
a45c82b8 RK |
505 | switch (dwc->dr_mode) { |
506 | case USB_DR_MODE_PERIPHERAL: | |
3140e8cb | 507 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
72246da4 FB |
508 | ret = dwc3_gadget_init(dwc); |
509 | if (ret) { | |
802ca850 | 510 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 511 | goto err2; |
72246da4 | 512 | } |
d07e8819 | 513 | break; |
a45c82b8 | 514 | case USB_DR_MODE_HOST: |
3140e8cb | 515 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); |
d07e8819 FB |
516 | ret = dwc3_host_init(dwc); |
517 | if (ret) { | |
802ca850 | 518 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 519 | goto err2; |
d07e8819 FB |
520 | } |
521 | break; | |
a45c82b8 | 522 | case USB_DR_MODE_OTG: |
3140e8cb | 523 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); |
d07e8819 FB |
524 | ret = dwc3_host_init(dwc); |
525 | if (ret) { | |
802ca850 | 526 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 527 | goto err2; |
d07e8819 FB |
528 | } |
529 | ||
72246da4 FB |
530 | ret = dwc3_gadget_init(dwc); |
531 | if (ret) { | |
802ca850 | 532 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 533 | goto err2; |
72246da4 | 534 | } |
0949e99b FB |
535 | break; |
536 | default: | |
a45c82b8 | 537 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); |
f122d33e | 538 | goto err2; |
72246da4 FB |
539 | } |
540 | ||
541 | ret = dwc3_debugfs_init(dwc); | |
542 | if (ret) { | |
802ca850 | 543 | dev_err(dev, "failed to initialize debugfs\n"); |
f122d33e | 544 | goto err3; |
72246da4 FB |
545 | } |
546 | ||
802ca850 | 547 | pm_runtime_allow(dev); |
72246da4 FB |
548 | |
549 | return 0; | |
550 | ||
f122d33e | 551 | err3: |
a45c82b8 RK |
552 | switch (dwc->dr_mode) { |
553 | case USB_DR_MODE_PERIPHERAL: | |
72246da4 | 554 | dwc3_gadget_exit(dwc); |
0949e99b | 555 | break; |
a45c82b8 | 556 | case USB_DR_MODE_HOST: |
d07e8819 FB |
557 | dwc3_host_exit(dwc); |
558 | break; | |
a45c82b8 | 559 | case USB_DR_MODE_OTG: |
d07e8819 | 560 | dwc3_host_exit(dwc); |
72246da4 | 561 | dwc3_gadget_exit(dwc); |
d07e8819 | 562 | break; |
0949e99b FB |
563 | default: |
564 | /* do nothing */ | |
565 | break; | |
566 | } | |
72246da4 | 567 | |
f122d33e FB |
568 | err2: |
569 | dwc3_event_buffers_cleanup(dwc); | |
570 | ||
72246da4 | 571 | err1: |
501fae51 KVA |
572 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
573 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802ca850 | 574 | dwc3_core_exit(dwc); |
72246da4 | 575 | |
3921426b FB |
576 | err0: |
577 | dwc3_free_event_buffers(dwc); | |
578 | ||
72246da4 FB |
579 | return ret; |
580 | } | |
581 | ||
fb4e98ab | 582 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 583 | { |
72246da4 | 584 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
72246da4 | 585 | |
8ba007a9 KVA |
586 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
587 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
588 | ||
16b972a5 | 589 | pm_runtime_put_sync(&pdev->dev); |
72246da4 FB |
590 | pm_runtime_disable(&pdev->dev); |
591 | ||
592 | dwc3_debugfs_exit(dwc); | |
593 | ||
a45c82b8 RK |
594 | switch (dwc->dr_mode) { |
595 | case USB_DR_MODE_PERIPHERAL: | |
72246da4 | 596 | dwc3_gadget_exit(dwc); |
0949e99b | 597 | break; |
a45c82b8 | 598 | case USB_DR_MODE_HOST: |
d07e8819 FB |
599 | dwc3_host_exit(dwc); |
600 | break; | |
a45c82b8 | 601 | case USB_DR_MODE_OTG: |
d07e8819 | 602 | dwc3_host_exit(dwc); |
72246da4 | 603 | dwc3_gadget_exit(dwc); |
d07e8819 | 604 | break; |
0949e99b FB |
605 | default: |
606 | /* do nothing */ | |
607 | break; | |
608 | } | |
72246da4 | 609 | |
f122d33e | 610 | dwc3_event_buffers_cleanup(dwc); |
d9b4330a | 611 | dwc3_free_event_buffers(dwc); |
72246da4 | 612 | dwc3_core_exit(dwc); |
72246da4 FB |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
19fda7cd | 617 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
618 | static int dwc3_prepare(struct device *dev) |
619 | { | |
620 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
621 | unsigned long flags; | |
622 | ||
623 | spin_lock_irqsave(&dwc->lock, flags); | |
624 | ||
a45c82b8 RK |
625 | switch (dwc->dr_mode) { |
626 | case USB_DR_MODE_PERIPHERAL: | |
627 | case USB_DR_MODE_OTG: | |
7415f17c FB |
628 | dwc3_gadget_prepare(dwc); |
629 | /* FALLTHROUGH */ | |
a45c82b8 | 630 | case USB_DR_MODE_HOST: |
7415f17c FB |
631 | default: |
632 | dwc3_event_buffers_cleanup(dwc); | |
633 | break; | |
634 | } | |
635 | ||
636 | spin_unlock_irqrestore(&dwc->lock, flags); | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
641 | static void dwc3_complete(struct device *dev) | |
642 | { | |
643 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
644 | unsigned long flags; | |
645 | ||
646 | spin_lock_irqsave(&dwc->lock, flags); | |
647 | ||
a45c82b8 RK |
648 | switch (dwc->dr_mode) { |
649 | case USB_DR_MODE_PERIPHERAL: | |
650 | case USB_DR_MODE_OTG: | |
7415f17c FB |
651 | dwc3_gadget_complete(dwc); |
652 | /* FALLTHROUGH */ | |
a45c82b8 | 653 | case USB_DR_MODE_HOST: |
7415f17c FB |
654 | default: |
655 | dwc3_event_buffers_setup(dwc); | |
656 | break; | |
657 | } | |
658 | ||
659 | spin_unlock_irqrestore(&dwc->lock, flags); | |
660 | } | |
661 | ||
662 | static int dwc3_suspend(struct device *dev) | |
663 | { | |
664 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
665 | unsigned long flags; | |
666 | ||
667 | spin_lock_irqsave(&dwc->lock, flags); | |
668 | ||
a45c82b8 RK |
669 | switch (dwc->dr_mode) { |
670 | case USB_DR_MODE_PERIPHERAL: | |
671 | case USB_DR_MODE_OTG: | |
7415f17c FB |
672 | dwc3_gadget_suspend(dwc); |
673 | /* FALLTHROUGH */ | |
a45c82b8 | 674 | case USB_DR_MODE_HOST: |
7415f17c FB |
675 | default: |
676 | /* do nothing */ | |
677 | break; | |
678 | } | |
679 | ||
680 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
681 | spin_unlock_irqrestore(&dwc->lock, flags); | |
682 | ||
683 | usb_phy_shutdown(dwc->usb3_phy); | |
684 | usb_phy_shutdown(dwc->usb2_phy); | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
689 | static int dwc3_resume(struct device *dev) | |
690 | { | |
691 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
692 | unsigned long flags; | |
693 | ||
694 | usb_phy_init(dwc->usb3_phy); | |
695 | usb_phy_init(dwc->usb2_phy); | |
7415f17c FB |
696 | |
697 | spin_lock_irqsave(&dwc->lock, flags); | |
698 | ||
699 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); | |
700 | ||
a45c82b8 RK |
701 | switch (dwc->dr_mode) { |
702 | case USB_DR_MODE_PERIPHERAL: | |
703 | case USB_DR_MODE_OTG: | |
7415f17c FB |
704 | dwc3_gadget_resume(dwc); |
705 | /* FALLTHROUGH */ | |
a45c82b8 | 706 | case USB_DR_MODE_HOST: |
7415f17c FB |
707 | default: |
708 | /* do nothing */ | |
709 | break; | |
710 | } | |
711 | ||
712 | spin_unlock_irqrestore(&dwc->lock, flags); | |
713 | ||
714 | pm_runtime_disable(dev); | |
715 | pm_runtime_set_active(dev); | |
716 | pm_runtime_enable(dev); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
722 | .prepare = dwc3_prepare, | |
723 | .complete = dwc3_complete, | |
724 | ||
725 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) | |
726 | }; | |
727 | ||
728 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
729 | #else | |
730 | #define DWC3_PM_OPS NULL | |
731 | #endif | |
732 | ||
5088b6f5 KVA |
733 | #ifdef CONFIG_OF |
734 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
735 | { |
736 | .compatible = "snps,dwc3" | |
737 | }, | |
5088b6f5 KVA |
738 | { |
739 | .compatible = "synopsys,dwc3" | |
740 | }, | |
741 | { }, | |
742 | }; | |
743 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
744 | #endif | |
745 | ||
72246da4 FB |
746 | static struct platform_driver dwc3_driver = { |
747 | .probe = dwc3_probe, | |
7690417d | 748 | .remove = dwc3_remove, |
72246da4 FB |
749 | .driver = { |
750 | .name = "dwc3", | |
5088b6f5 | 751 | .of_match_table = of_match_ptr(of_dwc3_match), |
7415f17c | 752 | .pm = DWC3_PM_OPS, |
72246da4 | 753 | }, |
72246da4 FB |
754 | }; |
755 | ||
b1116dcc TK |
756 | module_platform_driver(dwc3_driver); |
757 | ||
7ae4fc4d | 758 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 759 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 760 | MODULE_LICENSE("GPL v2"); |
72246da4 | 761 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |