[deliverable/linux.git] / drivers / usb / dwc3 / core.c

/**
 * core.c - DesignWare USB3 DRD Controller Core file
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

#include "debug.h"

static char *maximum_speed = "super";
module_param(maximum_speed, charp, 0);
MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");

/* -------------------------------------------------------------------------- */

#define DWC3_DEVS_POSSIBLE	32

static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);

int dwc3_get_device_id(void)
{
	int		id;

again:
	id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
	if (id < DWC3_DEVS_POSSIBLE) {
		int old;

		old = test_and_set_bit(id, dwc3_devs);
		if (old)
			goto again;
	} else {
		pr_err("dwc3: no space for new device\n");
		id = -ENOMEM;
	}

	return id;
}
EXPORT_SYMBOL_GPL(dwc3_get_device_id);

void dwc3_put_device_id(int id)
{
	int			ret;

	if (id < 0)
		return;

	ret = test_bit(id, dwc3_devs);
	WARN(!ret, "dwc3: ID %d not in use\n", id);
	clear_bit(id, dwc3_devs);
}
EXPORT_SYMBOL_GPL(dwc3_put_device_id);

void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
{
	u32 reg;

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	reg |= DWC3_GCTL_PRTCAPDIR(mode);
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 * @dwc: pointer to our context structure
 */
static void dwc3_core_soft_reset(struct dwc3 *dwc)
{
	u32		reg;

	/* Before Resetting PHY, put Core in Reset */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg |= DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	/* Assert USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Assert USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	mdelay(100);

	/* Clear USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Clear USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	/* After PHYs are stable we can take Core out of reset state */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_free_one_event_buffer - Frees one event buffer
 * @dwc: Pointer to our controller context structure
 * @evt: Pointer to event buffer to be freed
 */
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
		struct dwc3_event_buffer *evt)
{
	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	kfree(evt);
}

/**
 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 * @dwc: Pointer to our controller context structure
 * @length: size of the event buffer
 *
 * Returns a pointer to the allocated event buffer structure on success
 * otherwise ERR_PTR(errno).
 */
static struct dwc3_event_buffer *__devinit
dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
{
	struct dwc3_event_buffer	*evt;

	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
	if (!evt)
		return ERR_PTR(-ENOMEM);

	evt->dwc	= dwc;
	evt->length	= length;
	evt->buf	= dma_alloc_coherent(dwc->dev, length,
			&evt->dma, GFP_KERNEL);
	if (!evt->buf) {
		kfree(evt);
		return ERR_PTR(-ENOMEM);
	}

	return evt;
}

/**
 * dwc3_free_event_buffers - frees all allocated event buffers
 * @dwc: Pointer to our controller context structure
 */
static void dwc3_free_event_buffers(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int i;

	for (i = 0; i < dwc->num_event_buffers; i++) {
		evt = dwc->ev_buffs[i];
		if (evt)
			dwc3_free_one_event_buffer(dwc, evt);
	}

	kfree(dwc->ev_buffs);
}

/**
 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 * @dwc: pointer to our controller context structure
 * @length: size of event buffer
 *
 * Returns 0 on success otherwise negative errno. In the error case, dwc
 * may contain some buffers allocated but not all which were requested.
 */
static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
{
	int			num;
	int			i;

	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	dwc->num_event_buffers = num;

	dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
	if (!dwc->ev_buffs) {
		dev_err(dwc->dev, "can't allocate event buffers array\n");
		return -ENOMEM;
	}

	for (i = 0; i < num; i++) {
		struct dwc3_event_buffer	*evt;

		evt = dwc3_alloc_one_event_buffer(dwc, length);
		if (IS_ERR(evt)) {
			dev_err(dwc->dev, "can't allocate event buffer\n");
			return PTR_ERR(evt);
		}
		dwc->ev_buffs[i] = evt;
	}

	return 0;
}

/**
 * dwc3_event_buffers_setup - setup our allocated event buffers
 * @dwc: pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
				evt->buf, (unsigned long long) evt->dma,
				evt->length);

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
				lower_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
				upper_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
				evt->length & 0xffff);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}

	return 0;
}

static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}
}

static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
{
	struct dwc3_hwparams	*parms = &dwc->hwparams;

	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
}

/**
 * dwc3_core_init - Low-level initialization of DWC3 Core
 * @dwc: Pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_core_init(struct dwc3 *dwc)
{
	unsigned long		timeout;
	u32			reg;
	int			ret;

	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	/* This should read as U3 followed by revision number */
	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
		ret = -ENODEV;
		goto err0;
	}
	dwc->revision = reg;

	dwc3_core_soft_reset(dwc);

	/* issue device SoftReset too */
	timeout = jiffies + msecs_to_jiffies(500);
	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	do {
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		if (!(reg & DWC3_DCTL_CSFTRST))
			break;

		if (time_after(jiffies, timeout)) {
			dev_err(dwc->dev, "Reset Timed Out\n");
			ret = -ETIMEDOUT;
			goto err0;
		}

		cpu_relax();
	} while (true);

	dwc3_cache_hwparams(dwc);

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	reg &= ~DWC3_GCTL_DISSCRAMBLE;

	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
		break;
	default:
		dev_dbg(dwc->dev, "No power optimization available\n");
	}

	/*
	 * WORKAROUND: DWC3 revisions <1.90a have a bug
	 * where the device can fail to connect at SuperSpeed
	 * and falls back to high-speed mode which causes
	 * the device to enter a Connect/Disconnect loop
	 */
	if (dwc->revision < DWC3_REVISION_190A)
		reg |= DWC3_GCTL_U2RSTECN;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
	if (ret) {
		dev_err(dwc->dev, "failed to allocate event buffers\n");
		ret = -ENOMEM;
		goto err1;
	}

	ret = dwc3_event_buffers_setup(dwc);
	if (ret) {
		dev_err(dwc->dev, "failed to setup event buffers\n");
		goto err1;
	}

	return 0;

err1:
	dwc3_free_event_buffers(dwc);

err0:
	return ret;
}

static void dwc3_core_exit(struct dwc3 *dwc)
{
	dwc3_event_buffers_cleanup(dwc);
	dwc3_free_event_buffers(dwc);
}

#define DWC3_ALIGN_MASK		(16 - 1)

static int __devinit dwc3_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;
	struct resource		*res;
	struct dwc3		*dwc;
	struct device		*dev = &pdev->dev;

	int			ret = -ENOMEM;

	void __iomem		*regs;
	void			*mem;

	u8			mode;

	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	if (!mem) {
		dev_err(dev, "not enough memory\n");
		return -ENOMEM;
	}
	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	dwc->mem = mem;

	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}
	dwc->xhci_resources[1] = *res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "missing memory resource\n");
		return -ENODEV;
	}
	dwc->xhci_resources[0] = *res;
	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
					DWC3_XHCI_REGS_END;

	 /*
	  * Request memory region but exclude xHCI regs,
	  * since it will be requested by the xhci-plat driver.
	  */
	res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
			resource_size(res) - DWC3_GLOBALS_REGS_START,
			dev_name(dev));
	if (!res) {
		dev_err(dev, "can't request mem region\n");
		return -ENOMEM;
	}

	regs = devm_ioremap(dev, res->start, resource_size(res));
	if (!regs) {
		dev_err(dev, "ioremap failed\n");
		return -ENOMEM;
	}

	spin_lock_init(&dwc->lock);
	platform_set_drvdata(pdev, dwc);

	dwc->regs	= regs;
	dwc->regs_size	= resource_size(res);
	dwc->dev	= dev;

	if (!strncmp("super", maximum_speed, 5))
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	else if (!strncmp("high", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	else if (!strncmp("full", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	else if (!strncmp("low", maximum_speed, 3))
		dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	else
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;

	if (of_get_property(node, "tx-fifo-resize", NULL))
		dwc->needs_fifo_resize = true;

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	pm_runtime_forbid(dev);

	ret = dwc3_core_init(dwc);
	if (ret) {
		dev_err(dev, "failed to initialize core\n");
		return ret;
	}

	mode = DWC3_MODE(dwc->hwparams.hwparams0);

	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto err1;
		}
		break;
	case DWC3_MODE_HOST:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto err1;
		}
		break;
	case DWC3_MODE_DRD:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto err1;
		}

		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto err1;
		}
		break;
	default:
		dev_err(dev, "Unsupported mode of operation %d\n", mode);
		goto err1;
	}
	dwc->mode = mode;

	ret = dwc3_debugfs_init(dwc);
	if (ret) {
		dev_err(dev, "failed to initialize debugfs\n");
		goto err2;
	}

	pm_runtime_allow(dev);

	return 0;

err2:
	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

err1:
	dwc3_core_exit(dwc);

	return ret;
}

static int __devexit dwc3_remove(struct platform_device *pdev)
{
	struct dwc3	*dwc = platform_get_drvdata(pdev);
	struct resource	*res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	dwc3_debugfs_exit(dwc);

	switch (dwc->mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

	dwc3_core_exit(dwc);

	return 0;
}

static struct platform_driver dwc3_driver = {
	.probe		= dwc3_probe,
	.remove		= __devexit_p(dwc3_remove),
	.driver		= {
		.name	= "dwc3",
	},
};

module_platform_driver(dwc3_driver);

MODULE_ALIAS("platform:dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Commit	Line	Data
72246da4 FB	1	/**
	2	* core.c - DesignWare USB3 DRD Controller Core file
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/ioport.h>
	47	#include <linux/io.h>
	48	#include <linux/list.h>
	49	#include <linux/delay.h>
	50	#include <linux/dma-mapping.h>
457e84b6	51	#include <linux/of.h>
72246da4 FB	52
	53	#include <linux/usb/ch9.h>
	54	#include <linux/usb/gadget.h>
	55
	56	#include "core.h"
	57	#include "gadget.h"
	58	#include "io.h"
	59
	60	#include "debug.h"
	61
6c167fc9 FB	62	static char *maximum_speed = "super";
	63	module_param(maximum_speed, charp, 0);
	64	MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
	65
8300dd23 FB	66	/* -------------------------------------------------------------------------- */
	67
	68	#define DWC3_DEVS_POSSIBLE 32
	69
	70	static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
	71
	72	int dwc3_get_device_id(void)
	73	{
	74	int id;
	75
	76	again:
	77	id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
	78	if (id < DWC3_DEVS_POSSIBLE) {
	79	int old;
	80
	81	old = test_and_set_bit(id, dwc3_devs);
	82	if (old)
	83	goto again;
	84	} else {
	85	pr_err("dwc3: no space for new device\n");
	86	id = -ENOMEM;
	87	}
	88
075cd14d	89	return id;
8300dd23 FB	90	}
	91	EXPORT_SYMBOL_GPL(dwc3_get_device_id);
	92
	93	void dwc3_put_device_id(int id)
	94	{
	95	int ret;
	96
	97	if (id < 0)
	98	return;
	99
	100	ret = test_bit(id, dwc3_devs);
	101	WARN(!ret, "dwc3: ID %d not in use\n", id);
	102	clear_bit(id, dwc3_devs);
	103	}
	104	EXPORT_SYMBOL_GPL(dwc3_put_device_id);
	105
3140e8cb SAS	106	void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
	107	{
	108	u32 reg;
	109
	110	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	111	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	112	reg \|= DWC3_GCTL_PRTCAPDIR(mode);
	113	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	114	}
8300dd23	115
72246da4 FB	116	/**
	117	* dwc3_core_soft_reset - Issues core soft reset and PHY reset
	118	* @dwc: pointer to our context structure
	119	*/
	120	static void dwc3_core_soft_reset(struct dwc3 *dwc)
	121	{
	122	u32 reg;
	123
	124	/* Before Resetting PHY, put Core in Reset */
	125	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	126	reg \|= DWC3_GCTL_CORESOFTRESET;
	127	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	128
	129	/* Assert USB3 PHY reset */
	130	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	131	reg \|= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	132	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	133
	134	/* Assert USB2 PHY reset */
	135	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	136	reg \|= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	137	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	138
	139	mdelay(100);
	140
	141	/* Clear USB3 PHY reset */
	142	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	143	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	144	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	145
	146	/* Clear USB2 PHY reset */
	147	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	148	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	149	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	150
	151	/* After PHYs are stable we can take Core out of reset state */
	152	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	153	reg &= ~DWC3_GCTL_CORESOFTRESET;
	154	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	155	}
	156
	157	/**
	158	* dwc3_free_one_event_buffer - Frees one event buffer
	159	* @dwc: Pointer to our controller context structure
	160	* @evt: Pointer to event buffer to be freed
	161	*/
	162	static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
	163	struct dwc3_event_buffer *evt)
	164	{
	165	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	166	kfree(evt);
	167	}
	168
	169	/**
1d046793	170	* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4 FB	171	* @dwc: Pointer to our controller context structure
	172	* @length: size of the event buffer
	173	*
1d046793	174	* Returns a pointer to the allocated event buffer structure on success
72246da4 FB	175	* otherwise ERR_PTR(errno).
	176	*/
	177	static struct dwc3_event_buffer *__devinit
	178	dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
	179	{
	180	struct dwc3_event_buffer *evt;
	181
	182	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
	183	if (!evt)
	184	return ERR_PTR(-ENOMEM);
	185
	186	evt->dwc = dwc;
	187	evt->length = length;
	188	evt->buf = dma_alloc_coherent(dwc->dev, length,
	189	&evt->dma, GFP_KERNEL);
	190	if (!evt->buf) {
	191	kfree(evt);
	192	return ERR_PTR(-ENOMEM);
	193	}
	194
	195	return evt;
	196	}
	197
	198	/**
	199	* dwc3_free_event_buffers - frees all allocated event buffers
	200	* @dwc: Pointer to our controller context structure
	201	*/
	202	static void dwc3_free_event_buffers(struct dwc3 *dwc)
	203	{
	204	struct dwc3_event_buffer *evt;
	205	int i;
	206
9f622b2a	207	for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4	208	evt = dwc->ev_buffs[i];
64b6c8a7	209	if (evt)
72246da4	210	dwc3_free_one_event_buffer(dwc, evt);
72246da4	211	}
64b6c8a7 AT	212
64b6c8a7 AT	213	kfree(dwc->ev_buffs);
72246da4 FB	214	}
	215
	216	/**
	217	* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793	218	* @dwc: pointer to our controller context structure
72246da4 FB	219	* @length: size of event buffer
72246da4 FB	220	*
1d046793	221	* Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4 FB	222	* may contain some buffers allocated but not all which were requested.
72246da4 FB	223	*/
9f622b2a	224	static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4	225	{
9f622b2a	226	int num;
72246da4 FB	227	int i;
72246da4 FB	228
9f622b2a FB	229	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	230	dwc->num_event_buffers = num;
	231
457d3f21 FB	232	dwc->ev_buffs = kzalloc(sizeof(dwc->ev_buffs) num, GFP_KERNEL);
	233	if (!dwc->ev_buffs) {
	234	dev_err(dwc->dev, "can't allocate event buffers array\n");
	235	return -ENOMEM;
	236	}
	237
72246da4 FB	238	for (i = 0; i < num; i++) {
	239	struct dwc3_event_buffer *evt;
	240
	241	evt = dwc3_alloc_one_event_buffer(dwc, length);
	242	if (IS_ERR(evt)) {
	243	dev_err(dwc->dev, "can't allocate event buffer\n");
	244	return PTR_ERR(evt);
	245	}
	246	dwc->ev_buffs[i] = evt;
	247	}
	248
	249	return 0;
	250	}
	251
	252	/**
	253	* dwc3_event_buffers_setup - setup our allocated event buffers
1d046793	254	* @dwc: pointer to our controller context structure
72246da4 FB	255	*
	256	* Returns 0 on success otherwise negative errno.
	257	*/
	258	static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
	259	{
	260	struct dwc3_event_buffer *evt;
	261	int n;
	262
9f622b2a	263	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	264	evt = dwc->ev_buffs[n];
	265	dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
	266	evt->buf, (unsigned long long) evt->dma,
	267	evt->length);
	268
	269	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
	270	lower_32_bits(evt->dma));
	271	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
	272	upper_32_bits(evt->dma));
	273	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
	274	evt->length & 0xffff);
	275	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	276	}
	277
	278	return 0;
	279	}
	280
	281	static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
	282	{
	283	struct dwc3_event_buffer *evt;
	284	int n;
	285
9f622b2a	286	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	287	evt = dwc->ev_buffs[n];
	288	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
	289	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
	290	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
	291	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	292	}
	293	}
	294
26ceca97 FB	295	static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
	296	{
	297	struct dwc3_hwparams *parms = &dwc->hwparams;
	298
	299	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	300	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	301	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	302	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	303	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	304	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	305	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	306	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	307	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
	308	}
	309
72246da4 FB	310	/**
	311	* dwc3_core_init - Low-level initialization of DWC3 Core
	312	* @dwc: Pointer to our controller context structure
	313	*
	314	* Returns 0 on success otherwise negative errno.
	315	*/
	316	static int __devinit dwc3_core_init(struct dwc3 *dwc)
	317	{
	318	unsigned long timeout;
	319	u32 reg;
	320	int ret;
	321
7650bd74 SAS	322	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	323	/* This should read as U3 followed by revision number */
	324	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
	325	dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
	326	ret = -ENODEV;
	327	goto err0;
	328	}
248b122b	329	dwc->revision = reg;
7650bd74	330
72246da4 FB	331	dwc3_core_soft_reset(dwc);
	332
	333	/* issue device SoftReset too */
	334	timeout = jiffies + msecs_to_jiffies(500);
	335	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	336	do {
	337	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	338	if (!(reg & DWC3_DCTL_CSFTRST))
	339	break;
	340
	341	if (time_after(jiffies, timeout)) {
	342	dev_err(dwc->dev, "Reset Timed Out\n");
	343	ret = -ETIMEDOUT;
	344	goto err0;
	345	}
	346
	347	cpu_relax();
	348	} while (true);
	349
9f622b2a FB	350	dwc3_cache_hwparams(dwc);
9f622b2a FB	351
4878a028	352	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a	353	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 SAS	354	reg &= ~DWC3_GCTL_DISSCRAMBLE;
4878a028 SAS	355
164d7731	356	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 SAS	357	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
	358	reg &= ~DWC3_GCTL_DSBLCLKGTNG;
	359	break;
	360	default:
	361	dev_dbg(dwc->dev, "No power optimization available\n");
	362	}
	363
	364	/*
	365	* WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793	366	* where the device can fail to connect at SuperSpeed
4878a028	367	* and falls back to high-speed mode which causes
1d046793	368	* the device to enter a Connect/Disconnect loop
4878a028 SAS	369	*/
	370	if (dwc->revision < DWC3_REVISION_190A)
	371	reg \|= DWC3_GCTL_U2RSTECN;
	372
	373	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	374
9f622b2a	375	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
72246da4 FB	376	if (ret) {
	377	dev_err(dwc->dev, "failed to allocate event buffers\n");
	378	ret = -ENOMEM;
	379	goto err1;
	380	}
	381
	382	ret = dwc3_event_buffers_setup(dwc);
	383	if (ret) {
	384	dev_err(dwc->dev, "failed to setup event buffers\n");
	385	goto err1;
	386	}
	387
	388	return 0;
	389
	390	err1:
	391	dwc3_free_event_buffers(dwc);
	392
	393	err0:
	394	return ret;
	395	}
	396
	397	static void dwc3_core_exit(struct dwc3 *dwc)
	398	{
	399	dwc3_event_buffers_cleanup(dwc);
	400	dwc3_free_event_buffers(dwc);
	401	}
	402
	403	#define DWC3_ALIGN_MASK (16 - 1)
	404
	405	static int __devinit dwc3_probe(struct platform_device *pdev)
	406	{
457e84b6	407	struct device_node *node = pdev->dev.of_node;
72246da4 FB	408	struct resource *res;
72246da4 FB	409	struct dwc3 *dwc;
802ca850	410	struct device *dev = &pdev->dev;
0949e99b	411
72246da4	412	int ret = -ENOMEM;
0949e99b FB	413
0949e99b FB	414	void __iomem *regs;
72246da4 FB	415	void *mem;
72246da4 FB	416
0949e99b FB	417	u8 mode;
0949e99b FB	418
802ca850	419	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
72246da4	420	if (!mem) {
802ca850 CP	421	dev_err(dev, "not enough memory\n");
802ca850 CP	422	return -ENOMEM;
72246da4 FB	423	}
	424	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	425	dwc->mem = mem;
	426
51249dca	427	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
72246da4	428	if (!res) {
51249dca	429	dev_err(dev, "missing IRQ\n");
802ca850	430	return -ENODEV;
72246da4	431	}
51249dca	432	dwc->xhci_resources[1] = *res;
72246da4	433
51249dca IS	434	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	435	if (!res) {
	436	dev_err(dev, "missing memory resource\n");
	437	return -ENODEV;
	438	}
	439	dwc->xhci_resources[0] = *res;
	440	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
	441	DWC3_XHCI_REGS_END;
	442
	443	/*
	444	* Request memory region but exclude xHCI regs,
	445	* since it will be requested by the xhci-plat driver.
	446	*/
	447	res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
	448	resource_size(res) - DWC3_GLOBALS_REGS_START,
802ca850	449	dev_name(dev));
72246da4	450	if (!res) {
802ca850 CP	451	dev_err(dev, "can't request mem region\n");
802ca850 CP	452	return -ENOMEM;
72246da4 FB	453	}
72246da4 FB	454
802ca850	455	regs = devm_ioremap(dev, res->start, resource_size(res));
72246da4	456	if (!regs) {
802ca850 CP	457	dev_err(dev, "ioremap failed\n");
802ca850 CP	458	return -ENOMEM;
72246da4 FB	459	}
72246da4 FB	460
72246da4 FB	461	spin_lock_init(&dwc->lock);
	462	platform_set_drvdata(pdev, dwc);
	463
	464	dwc->regs = regs;
	465	dwc->regs_size = resource_size(res);
802ca850	466	dwc->dev = dev;
72246da4	467
6c167fc9 FB	468	if (!strncmp("super", maximum_speed, 5))
	469	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	470	else if (!strncmp("high", maximum_speed, 4))
	471	dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	472	else if (!strncmp("full", maximum_speed, 4))
	473	dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	474	else if (!strncmp("low", maximum_speed, 3))
	475	dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	476	else
	477	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	478
457e84b6 FB	479	if (of_get_property(node, "tx-fifo-resize", NULL))
	480	dwc->needs_fifo_resize = true;
	481
802ca850 CP	482	pm_runtime_enable(dev);
	483	pm_runtime_get_sync(dev);
	484	pm_runtime_forbid(dev);
72246da4 FB	485
	486	ret = dwc3_core_init(dwc);
	487	if (ret) {
802ca850 CP	488	dev_err(dev, "failed to initialize core\n");
802ca850 CP	489	return ret;
72246da4 FB	490	}
72246da4 FB	491
0949e99b FB	492	mode = DWC3_MODE(dwc->hwparams.hwparams0);
	493
	494	switch (mode) {
0949e99b	495	case DWC3_MODE_DEVICE:
3140e8cb	496	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
72246da4 FB	497	ret = dwc3_gadget_init(dwc);
72246da4 FB	498	if (ret) {
802ca850 CP	499	dev_err(dev, "failed to initialize gadget\n");
802ca850 CP	500	goto err1;
72246da4	501	}
d07e8819 FB	502	break;
d07e8819 FB	503	case DWC3_MODE_HOST:
3140e8cb	504	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
d07e8819 FB	505	ret = dwc3_host_init(dwc);
d07e8819 FB	506	if (ret) {
802ca850 CP	507	dev_err(dev, "failed to initialize host\n");
802ca850 CP	508	goto err1;
d07e8819 FB	509	}
	510	break;
	511	case DWC3_MODE_DRD:
3140e8cb	512	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
d07e8819 FB	513	ret = dwc3_host_init(dwc);
d07e8819 FB	514	if (ret) {
802ca850 CP	515	dev_err(dev, "failed to initialize host\n");
802ca850 CP	516	goto err1;
d07e8819 FB	517	}
d07e8819 FB	518
72246da4 FB	519	ret = dwc3_gadget_init(dwc);
72246da4 FB	520	if (ret) {
802ca850 CP	521	dev_err(dev, "failed to initialize gadget\n");
802ca850 CP	522	goto err1;
72246da4	523	}
0949e99b FB	524	break;
0949e99b FB	525	default:
802ca850 CP	526	dev_err(dev, "Unsupported mode of operation %d\n", mode);
802ca850 CP	527	goto err1;
72246da4	528	}
0949e99b	529	dwc->mode = mode;
72246da4 FB	530
	531	ret = dwc3_debugfs_init(dwc);
	532	if (ret) {
802ca850 CP	533	dev_err(dev, "failed to initialize debugfs\n");
802ca850 CP	534	goto err2;
72246da4 FB	535	}
72246da4 FB	536
802ca850	537	pm_runtime_allow(dev);
72246da4 FB	538
	539	return 0;
	540
802ca850	541	err2:
0949e99b	542	switch (mode) {
0949e99b	543	case DWC3_MODE_DEVICE:
72246da4	544	dwc3_gadget_exit(dwc);
0949e99b	545	break;
d07e8819 FB	546	case DWC3_MODE_HOST:
	547	dwc3_host_exit(dwc);
	548	break;
	549	case DWC3_MODE_DRD:
	550	dwc3_host_exit(dwc);
72246da4	551	dwc3_gadget_exit(dwc);
d07e8819	552	break;
0949e99b FB	553	default:
	554	/* do nothing */
	555	break;
	556	}
72246da4	557
72246da4	558	err1:
802ca850	559	dwc3_core_exit(dwc);
72246da4	560
72246da4 FB	561	return ret;
	562	}
	563
	564	static int __devexit dwc3_remove(struct platform_device *pdev)
	565	{
72246da4 FB	566	struct dwc3 *dwc = platform_get_drvdata(pdev);
72246da4 FB	567	struct resource *res;
72246da4 FB	568
	569	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	570
	571	pm_runtime_put(&pdev->dev);
	572	pm_runtime_disable(&pdev->dev);
	573
	574	dwc3_debugfs_exit(dwc);
	575
0949e99b	576	switch (dwc->mode) {
0949e99b	577	case DWC3_MODE_DEVICE:
72246da4	578	dwc3_gadget_exit(dwc);
0949e99b	579	break;
d07e8819 FB	580	case DWC3_MODE_HOST:
	581	dwc3_host_exit(dwc);
	582	break;
	583	case DWC3_MODE_DRD:
	584	dwc3_host_exit(dwc);
72246da4	585	dwc3_gadget_exit(dwc);
d07e8819	586	break;
0949e99b FB	587	default:
	588	/* do nothing */
	589	break;
	590	}
72246da4 FB	591
72246da4 FB	592	dwc3_core_exit(dwc);
72246da4 FB	593
	594	return 0;
	595	}
	596
72246da4 FB	597	static struct platform_driver dwc3_driver = {
	598	.probe = dwc3_probe,
	599	.remove = __devexit_p(dwc3_remove),
	600	.driver = {
	601	.name = "dwc3",
	602	},
72246da4 FB	603	};
72246da4 FB	604
b1116dcc TK	605	module_platform_driver(dwc3_driver);
b1116dcc TK	606
7ae4fc4d	607	MODULE_ALIAS("platform:dwc3");
72246da4 FB	608	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	609	MODULE_LICENSE("Dual BSD/GPL");
	610	MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");