Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
a72e658b | 22 | #include <linux/module.h> |
72246da4 FB |
23 | #include <linux/kernel.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
457e84b6 | 34 | #include <linux/of.h> |
72246da4 FB |
35 | |
36 | #include <linux/usb/ch9.h> | |
37 | #include <linux/usb/gadget.h> | |
f7e846f0 | 38 | #include <linux/usb/of.h> |
a45c82b8 | 39 | #include <linux/usb/otg.h> |
72246da4 | 40 | |
6462cbd5 | 41 | #include "platform_data.h" |
72246da4 FB |
42 | #include "core.h" |
43 | #include "gadget.h" | |
44 | #include "io.h" | |
45 | ||
46 | #include "debug.h" | |
47 | ||
8300dd23 FB |
48 | /* -------------------------------------------------------------------------- */ |
49 | ||
3140e8cb SAS |
50 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
51 | { | |
52 | u32 reg; | |
53 | ||
54 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
55 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
56 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
57 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
58 | } | |
8300dd23 | 59 | |
72246da4 FB |
60 | /** |
61 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
62 | * @dwc: pointer to our context structure | |
63 | */ | |
64 | static void dwc3_core_soft_reset(struct dwc3 *dwc) | |
65 | { | |
66 | u32 reg; | |
67 | ||
68 | /* Before Resetting PHY, put Core in Reset */ | |
69 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
70 | reg |= DWC3_GCTL_CORESOFTRESET; | |
71 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
72 | ||
73 | /* Assert USB3 PHY reset */ | |
74 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
75 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
76 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
77 | ||
78 | /* Assert USB2 PHY reset */ | |
79 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
80 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
81 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
82 | ||
51e1e7bc FB |
83 | usb_phy_init(dwc->usb2_phy); |
84 | usb_phy_init(dwc->usb3_phy); | |
72246da4 FB |
85 | mdelay(100); |
86 | ||
87 | /* Clear USB3 PHY reset */ | |
88 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
89 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
90 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
91 | ||
92 | /* Clear USB2 PHY reset */ | |
93 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
94 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
95 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
96 | ||
45627ac6 PA |
97 | mdelay(100); |
98 | ||
72246da4 FB |
99 | /* After PHYs are stable we can take Core out of reset state */ |
100 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
101 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
102 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
103 | } | |
104 | ||
105 | /** | |
106 | * dwc3_free_one_event_buffer - Frees one event buffer | |
107 | * @dwc: Pointer to our controller context structure | |
108 | * @evt: Pointer to event buffer to be freed | |
109 | */ | |
110 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
111 | struct dwc3_event_buffer *evt) | |
112 | { | |
113 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
114 | } |
115 | ||
116 | /** | |
1d046793 | 117 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
118 | * @dwc: Pointer to our controller context structure |
119 | * @length: size of the event buffer | |
120 | * | |
1d046793 | 121 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
122 | * otherwise ERR_PTR(errno). |
123 | */ | |
67d0b500 FB |
124 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
125 | unsigned length) | |
72246da4 FB |
126 | { |
127 | struct dwc3_event_buffer *evt; | |
128 | ||
380f0d28 | 129 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
130 | if (!evt) |
131 | return ERR_PTR(-ENOMEM); | |
132 | ||
133 | evt->dwc = dwc; | |
134 | evt->length = length; | |
135 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
136 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 137 | if (!evt->buf) |
72246da4 | 138 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
139 | |
140 | return evt; | |
141 | } | |
142 | ||
143 | /** | |
144 | * dwc3_free_event_buffers - frees all allocated event buffers | |
145 | * @dwc: Pointer to our controller context structure | |
146 | */ | |
147 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
148 | { | |
149 | struct dwc3_event_buffer *evt; | |
150 | int i; | |
151 | ||
9f622b2a | 152 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 153 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 154 | if (evt) |
72246da4 | 155 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
156 | } |
157 | } | |
158 | ||
159 | /** | |
160 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 161 | * @dwc: pointer to our controller context structure |
72246da4 FB |
162 | * @length: size of event buffer |
163 | * | |
1d046793 | 164 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
165 | * may contain some buffers allocated but not all which were requested. |
166 | */ | |
41ac7b3a | 167 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 168 | { |
9f622b2a | 169 | int num; |
72246da4 FB |
170 | int i; |
171 | ||
9f622b2a FB |
172 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
173 | dwc->num_event_buffers = num; | |
174 | ||
380f0d28 FB |
175 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
176 | GFP_KERNEL); | |
457d3f21 FB |
177 | if (!dwc->ev_buffs) { |
178 | dev_err(dwc->dev, "can't allocate event buffers array\n"); | |
179 | return -ENOMEM; | |
180 | } | |
181 | ||
72246da4 FB |
182 | for (i = 0; i < num; i++) { |
183 | struct dwc3_event_buffer *evt; | |
184 | ||
185 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
186 | if (IS_ERR(evt)) { | |
187 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
188 | return PTR_ERR(evt); | |
189 | } | |
190 | dwc->ev_buffs[i] = evt; | |
191 | } | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | /** | |
197 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 198 | * @dwc: pointer to our controller context structure |
72246da4 FB |
199 | * |
200 | * Returns 0 on success otherwise negative errno. | |
201 | */ | |
7acd85e0 | 202 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
203 | { |
204 | struct dwc3_event_buffer *evt; | |
205 | int n; | |
206 | ||
9f622b2a | 207 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
208 | evt = dwc->ev_buffs[n]; |
209 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
210 | evt->buf, (unsigned long long) evt->dma, | |
211 | evt->length); | |
212 | ||
7acd85e0 PZ |
213 | evt->lpos = 0; |
214 | ||
72246da4 FB |
215 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
216 | lower_32_bits(evt->dma)); | |
217 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
218 | upper_32_bits(evt->dma)); | |
219 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
68d6a01b | 220 | DWC3_GEVNTSIZ_SIZE(evt->length)); |
72246da4 FB |
221 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
228 | { | |
229 | struct dwc3_event_buffer *evt; | |
230 | int n; | |
231 | ||
9f622b2a | 232 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 233 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
234 | |
235 | evt->lpos = 0; | |
236 | ||
72246da4 FB |
237 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
238 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
68d6a01b FB |
239 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK |
240 | | DWC3_GEVNTSIZ_SIZE(0)); | |
72246da4 FB |
241 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
242 | } | |
243 | } | |
244 | ||
0ffcaf37 FB |
245 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
246 | { | |
247 | if (!dwc->has_hibernation) | |
248 | return 0; | |
249 | ||
250 | if (!dwc->nr_scratch) | |
251 | return 0; | |
252 | ||
253 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
254 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
255 | if (!dwc->scratchbuf) | |
256 | return -ENOMEM; | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
262 | { | |
263 | dma_addr_t scratch_addr; | |
264 | u32 param; | |
265 | int ret; | |
266 | ||
267 | if (!dwc->has_hibernation) | |
268 | return 0; | |
269 | ||
270 | if (!dwc->nr_scratch) | |
271 | return 0; | |
272 | ||
273 | /* should never fall here */ | |
274 | if (!WARN_ON(dwc->scratchbuf)) | |
275 | return 0; | |
276 | ||
277 | scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, | |
278 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
279 | DMA_BIDIRECTIONAL); | |
280 | if (dma_mapping_error(dwc->dev, scratch_addr)) { | |
281 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
282 | ret = -EFAULT; | |
283 | goto err0; | |
284 | } | |
285 | ||
286 | dwc->scratch_addr = scratch_addr; | |
287 | ||
288 | param = lower_32_bits(scratch_addr); | |
289 | ||
290 | ret = dwc3_send_gadget_generic_command(dwc, | |
291 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
292 | if (ret < 0) | |
293 | goto err1; | |
294 | ||
295 | param = upper_32_bits(scratch_addr); | |
296 | ||
297 | ret = dwc3_send_gadget_generic_command(dwc, | |
298 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
299 | if (ret < 0) | |
300 | goto err1; | |
301 | ||
302 | return 0; | |
303 | ||
304 | err1: | |
305 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
306 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
307 | ||
308 | err0: | |
309 | return ret; | |
310 | } | |
311 | ||
312 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
313 | { | |
314 | if (!dwc->has_hibernation) | |
315 | return; | |
316 | ||
317 | if (!dwc->nr_scratch) | |
318 | return; | |
319 | ||
320 | /* should never fall here */ | |
321 | if (!WARN_ON(dwc->scratchbuf)) | |
322 | return; | |
323 | ||
324 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
325 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
326 | kfree(dwc->scratchbuf); | |
327 | } | |
328 | ||
789451f6 FB |
329 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
330 | { | |
331 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
332 | ||
333 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
334 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
335 | ||
336 | dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", | |
337 | dwc->num_in_eps, dwc->num_out_eps); | |
338 | } | |
339 | ||
41ac7b3a | 340 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
341 | { |
342 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
343 | ||
344 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
345 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
346 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
347 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
348 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
349 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
350 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
351 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
352 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
353 | } | |
354 | ||
72246da4 FB |
355 | /** |
356 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
357 | * @dwc: Pointer to our controller context structure | |
358 | * | |
359 | * Returns 0 on success otherwise negative errno. | |
360 | */ | |
41ac7b3a | 361 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 FB |
362 | { |
363 | unsigned long timeout; | |
0ffcaf37 | 364 | u32 hwparams4 = dwc->hwparams.hwparams4; |
72246da4 FB |
365 | u32 reg; |
366 | int ret; | |
367 | ||
7650bd74 SAS |
368 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
369 | /* This should read as U3 followed by revision number */ | |
370 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
371 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
372 | ret = -ENODEV; | |
373 | goto err0; | |
374 | } | |
248b122b | 375 | dwc->revision = reg; |
7650bd74 | 376 | |
72246da4 FB |
377 | /* issue device SoftReset too */ |
378 | timeout = jiffies + msecs_to_jiffies(500); | |
379 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
380 | do { | |
381 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
382 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
383 | break; | |
384 | ||
385 | if (time_after(jiffies, timeout)) { | |
386 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
387 | ret = -ETIMEDOUT; | |
388 | goto err0; | |
389 | } | |
390 | ||
391 | cpu_relax(); | |
392 | } while (true); | |
393 | ||
58a0f23f PA |
394 | dwc3_core_soft_reset(dwc); |
395 | ||
4878a028 | 396 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 397 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 SAS |
398 | reg &= ~DWC3_GCTL_DISSCRAMBLE; |
399 | ||
164d7731 | 400 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 401 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
402 | /** |
403 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
404 | * issue which would cause xHCI compliance tests to fail. | |
405 | * | |
406 | * Because of that we cannot enable clock gating on such | |
407 | * configurations. | |
408 | * | |
409 | * Refers to: | |
410 | * | |
411 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
412 | * SOF/ITP Mode Used | |
413 | */ | |
414 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
415 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
416 | (dwc->revision >= DWC3_REVISION_210A && | |
417 | dwc->revision <= DWC3_REVISION_250A)) | |
418 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
419 | else | |
420 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 421 | break; |
0ffcaf37 FB |
422 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
423 | /* enable hibernation here */ | |
424 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
425 | break; | |
4878a028 SAS |
426 | default: |
427 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
428 | } | |
429 | ||
430 | /* | |
431 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 432 | * where the device can fail to connect at SuperSpeed |
4878a028 | 433 | * and falls back to high-speed mode which causes |
1d046793 | 434 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
435 | */ |
436 | if (dwc->revision < DWC3_REVISION_190A) | |
437 | reg |= DWC3_GCTL_U2RSTECN; | |
438 | ||
789451f6 FB |
439 | dwc3_core_num_eps(dwc); |
440 | ||
4878a028 SAS |
441 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
442 | ||
0ffcaf37 FB |
443 | ret = dwc3_alloc_scratch_buffers(dwc); |
444 | if (ret) | |
445 | goto err1; | |
446 | ||
447 | ret = dwc3_setup_scratch_buffers(dwc); | |
448 | if (ret) | |
449 | goto err2; | |
450 | ||
72246da4 FB |
451 | return 0; |
452 | ||
0ffcaf37 FB |
453 | err2: |
454 | dwc3_free_scratch_buffers(dwc); | |
455 | ||
456 | err1: | |
457 | usb_phy_shutdown(dwc->usb2_phy); | |
458 | usb_phy_shutdown(dwc->usb3_phy); | |
459 | ||
72246da4 FB |
460 | err0: |
461 | return ret; | |
462 | } | |
463 | ||
464 | static void dwc3_core_exit(struct dwc3 *dwc) | |
465 | { | |
0ffcaf37 | 466 | dwc3_free_scratch_buffers(dwc); |
01b8daf7 VG |
467 | usb_phy_shutdown(dwc->usb2_phy); |
468 | usb_phy_shutdown(dwc->usb3_phy); | |
72246da4 FB |
469 | } |
470 | ||
471 | #define DWC3_ALIGN_MASK (16 - 1) | |
472 | ||
41ac7b3a | 473 | static int dwc3_probe(struct platform_device *pdev) |
72246da4 | 474 | { |
941ea361 FB |
475 | struct device *dev = &pdev->dev; |
476 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
477 | struct device_node *node = dev->of_node; | |
72246da4 FB |
478 | struct resource *res; |
479 | struct dwc3 *dwc; | |
0949e99b | 480 | |
72246da4 | 481 | int ret = -ENOMEM; |
0949e99b FB |
482 | |
483 | void __iomem *regs; | |
72246da4 FB |
484 | void *mem; |
485 | ||
802ca850 | 486 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); |
72246da4 | 487 | if (!mem) { |
802ca850 CP |
488 | dev_err(dev, "not enough memory\n"); |
489 | return -ENOMEM; | |
72246da4 FB |
490 | } |
491 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); | |
492 | dwc->mem = mem; | |
493 | ||
51249dca | 494 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
72246da4 | 495 | if (!res) { |
51249dca | 496 | dev_err(dev, "missing IRQ\n"); |
802ca850 | 497 | return -ENODEV; |
72246da4 | 498 | } |
066618bc KVA |
499 | dwc->xhci_resources[1].start = res->start; |
500 | dwc->xhci_resources[1].end = res->end; | |
501 | dwc->xhci_resources[1].flags = res->flags; | |
502 | dwc->xhci_resources[1].name = res->name; | |
72246da4 | 503 | |
51249dca IS |
504 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
505 | if (!res) { | |
506 | dev_err(dev, "missing memory resource\n"); | |
507 | return -ENODEV; | |
508 | } | |
72246da4 | 509 | |
5088b6f5 | 510 | if (node) { |
f7e846f0 FB |
511 | dwc->maximum_speed = of_usb_get_maximum_speed(node); |
512 | ||
5088b6f5 KVA |
513 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); |
514 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
6462cbd5 FB |
515 | |
516 | dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize"); | |
a45c82b8 | 517 | dwc->dr_mode = of_usb_get_dr_mode(node); |
bb674907 | 518 | } else if (pdata) { |
f7e846f0 FB |
519 | dwc->maximum_speed = pdata->maximum_speed; |
520 | ||
5088b6f5 KVA |
521 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); |
522 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
6462cbd5 FB |
523 | |
524 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
a45c82b8 | 525 | dwc->dr_mode = pdata->dr_mode; |
bb674907 FB |
526 | } else { |
527 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
528 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
529 | } |
530 | ||
f7e846f0 FB |
531 | /* default to superspeed if no maximum_speed passed */ |
532 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
533 | dwc->maximum_speed = USB_SPEED_SUPER; | |
534 | ||
d105e7f8 FB |
535 | if (IS_ERR(dwc->usb2_phy)) { |
536 | ret = PTR_ERR(dwc->usb2_phy); | |
537 | ||
538 | /* | |
539 | * if -ENXIO is returned, it means PHY layer wasn't | |
540 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
541 | * in that case, since no PHY driver will ever probe. | |
542 | */ | |
543 | if (ret == -ENXIO) | |
544 | return ret; | |
545 | ||
51e1e7bc FB |
546 | dev_err(dev, "no usb2 phy configured\n"); |
547 | return -EPROBE_DEFER; | |
548 | } | |
549 | ||
d105e7f8 | 550 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 551 | ret = PTR_ERR(dwc->usb3_phy); |
d105e7f8 FB |
552 | |
553 | /* | |
554 | * if -ENXIO is returned, it means PHY layer wasn't | |
555 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
556 | * in that case, since no PHY driver will ever probe. | |
557 | */ | |
558 | if (ret == -ENXIO) | |
559 | return ret; | |
560 | ||
51e1e7bc FB |
561 | dev_err(dev, "no usb3 phy configured\n"); |
562 | return -EPROBE_DEFER; | |
563 | } | |
564 | ||
2e112345 II |
565 | dwc->xhci_resources[0].start = res->start; |
566 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
567 | DWC3_XHCI_REGS_END; | |
568 | dwc->xhci_resources[0].flags = res->flags; | |
569 | dwc->xhci_resources[0].name = res->name; | |
570 | ||
571 | res->start += DWC3_GLOBALS_REGS_START; | |
572 | ||
573 | /* | |
574 | * Request memory region but exclude xHCI regs, | |
575 | * since it will be requested by the xhci-plat driver. | |
576 | */ | |
577 | regs = devm_ioremap_resource(dev, res); | |
578 | if (IS_ERR(regs)) | |
579 | return PTR_ERR(regs); | |
580 | ||
72246da4 FB |
581 | spin_lock_init(&dwc->lock); |
582 | platform_set_drvdata(pdev, dwc); | |
583 | ||
584 | dwc->regs = regs; | |
585 | dwc->regs_size = resource_size(res); | |
802ca850 | 586 | dwc->dev = dev; |
72246da4 | 587 | |
ddff14f1 KVA |
588 | dev->dma_mask = dev->parent->dma_mask; |
589 | dev->dma_parms = dev->parent->dma_parms; | |
590 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
591 | ||
802ca850 CP |
592 | pm_runtime_enable(dev); |
593 | pm_runtime_get_sync(dev); | |
594 | pm_runtime_forbid(dev); | |
72246da4 | 595 | |
4fd24483 KVA |
596 | dwc3_cache_hwparams(dwc); |
597 | ||
3921426b FB |
598 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
599 | if (ret) { | |
600 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
601 | ret = -ENOMEM; | |
602 | goto err0; | |
603 | } | |
604 | ||
32a4a135 FB |
605 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
606 | dwc->dr_mode = USB_DR_MODE_HOST; | |
607 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
608 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; | |
609 | ||
610 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
611 | dwc->dr_mode = USB_DR_MODE_OTG; | |
612 | ||
72246da4 FB |
613 | ret = dwc3_core_init(dwc); |
614 | if (ret) { | |
802ca850 | 615 | dev_err(dev, "failed to initialize core\n"); |
3921426b | 616 | goto err0; |
72246da4 FB |
617 | } |
618 | ||
3088f108 KVA |
619 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
620 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
621 | ||
f122d33e FB |
622 | ret = dwc3_event_buffers_setup(dwc); |
623 | if (ret) { | |
624 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
625 | goto err1; | |
626 | } | |
627 | ||
a45c82b8 RK |
628 | switch (dwc->dr_mode) { |
629 | case USB_DR_MODE_PERIPHERAL: | |
3140e8cb | 630 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
72246da4 FB |
631 | ret = dwc3_gadget_init(dwc); |
632 | if (ret) { | |
802ca850 | 633 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 634 | goto err2; |
72246da4 | 635 | } |
d07e8819 | 636 | break; |
a45c82b8 | 637 | case USB_DR_MODE_HOST: |
3140e8cb | 638 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); |
d07e8819 FB |
639 | ret = dwc3_host_init(dwc); |
640 | if (ret) { | |
802ca850 | 641 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 642 | goto err2; |
d07e8819 FB |
643 | } |
644 | break; | |
a45c82b8 | 645 | case USB_DR_MODE_OTG: |
3140e8cb | 646 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); |
d07e8819 FB |
647 | ret = dwc3_host_init(dwc); |
648 | if (ret) { | |
802ca850 | 649 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 650 | goto err2; |
d07e8819 FB |
651 | } |
652 | ||
72246da4 FB |
653 | ret = dwc3_gadget_init(dwc); |
654 | if (ret) { | |
802ca850 | 655 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 656 | goto err2; |
72246da4 | 657 | } |
0949e99b FB |
658 | break; |
659 | default: | |
a45c82b8 | 660 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); |
f122d33e | 661 | goto err2; |
72246da4 FB |
662 | } |
663 | ||
664 | ret = dwc3_debugfs_init(dwc); | |
665 | if (ret) { | |
802ca850 | 666 | dev_err(dev, "failed to initialize debugfs\n"); |
f122d33e | 667 | goto err3; |
72246da4 FB |
668 | } |
669 | ||
802ca850 | 670 | pm_runtime_allow(dev); |
72246da4 FB |
671 | |
672 | return 0; | |
673 | ||
f122d33e | 674 | err3: |
a45c82b8 RK |
675 | switch (dwc->dr_mode) { |
676 | case USB_DR_MODE_PERIPHERAL: | |
72246da4 | 677 | dwc3_gadget_exit(dwc); |
0949e99b | 678 | break; |
a45c82b8 | 679 | case USB_DR_MODE_HOST: |
d07e8819 FB |
680 | dwc3_host_exit(dwc); |
681 | break; | |
a45c82b8 | 682 | case USB_DR_MODE_OTG: |
d07e8819 | 683 | dwc3_host_exit(dwc); |
72246da4 | 684 | dwc3_gadget_exit(dwc); |
d07e8819 | 685 | break; |
0949e99b FB |
686 | default: |
687 | /* do nothing */ | |
688 | break; | |
689 | } | |
72246da4 | 690 | |
f122d33e FB |
691 | err2: |
692 | dwc3_event_buffers_cleanup(dwc); | |
693 | ||
72246da4 | 694 | err1: |
501fae51 KVA |
695 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
696 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802ca850 | 697 | dwc3_core_exit(dwc); |
72246da4 | 698 | |
3921426b FB |
699 | err0: |
700 | dwc3_free_event_buffers(dwc); | |
701 | ||
72246da4 FB |
702 | return ret; |
703 | } | |
704 | ||
fb4e98ab | 705 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 706 | { |
72246da4 | 707 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
72246da4 | 708 | |
8ba007a9 KVA |
709 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
710 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
711 | ||
16b972a5 | 712 | pm_runtime_put_sync(&pdev->dev); |
72246da4 FB |
713 | pm_runtime_disable(&pdev->dev); |
714 | ||
715 | dwc3_debugfs_exit(dwc); | |
716 | ||
a45c82b8 RK |
717 | switch (dwc->dr_mode) { |
718 | case USB_DR_MODE_PERIPHERAL: | |
72246da4 | 719 | dwc3_gadget_exit(dwc); |
0949e99b | 720 | break; |
a45c82b8 | 721 | case USB_DR_MODE_HOST: |
d07e8819 FB |
722 | dwc3_host_exit(dwc); |
723 | break; | |
a45c82b8 | 724 | case USB_DR_MODE_OTG: |
d07e8819 | 725 | dwc3_host_exit(dwc); |
72246da4 | 726 | dwc3_gadget_exit(dwc); |
d07e8819 | 727 | break; |
0949e99b FB |
728 | default: |
729 | /* do nothing */ | |
730 | break; | |
731 | } | |
72246da4 | 732 | |
f122d33e | 733 | dwc3_event_buffers_cleanup(dwc); |
d9b4330a | 734 | dwc3_free_event_buffers(dwc); |
72246da4 | 735 | dwc3_core_exit(dwc); |
72246da4 FB |
736 | |
737 | return 0; | |
738 | } | |
739 | ||
19fda7cd | 740 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
741 | static int dwc3_prepare(struct device *dev) |
742 | { | |
743 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
744 | unsigned long flags; | |
745 | ||
746 | spin_lock_irqsave(&dwc->lock, flags); | |
747 | ||
a45c82b8 RK |
748 | switch (dwc->dr_mode) { |
749 | case USB_DR_MODE_PERIPHERAL: | |
750 | case USB_DR_MODE_OTG: | |
7415f17c FB |
751 | dwc3_gadget_prepare(dwc); |
752 | /* FALLTHROUGH */ | |
a45c82b8 | 753 | case USB_DR_MODE_HOST: |
7415f17c FB |
754 | default: |
755 | dwc3_event_buffers_cleanup(dwc); | |
756 | break; | |
757 | } | |
758 | ||
759 | spin_unlock_irqrestore(&dwc->lock, flags); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | static void dwc3_complete(struct device *dev) | |
765 | { | |
766 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
767 | unsigned long flags; | |
768 | ||
769 | spin_lock_irqsave(&dwc->lock, flags); | |
770 | ||
a45c82b8 RK |
771 | switch (dwc->dr_mode) { |
772 | case USB_DR_MODE_PERIPHERAL: | |
773 | case USB_DR_MODE_OTG: | |
7415f17c FB |
774 | dwc3_gadget_complete(dwc); |
775 | /* FALLTHROUGH */ | |
a45c82b8 | 776 | case USB_DR_MODE_HOST: |
7415f17c FB |
777 | default: |
778 | dwc3_event_buffers_setup(dwc); | |
779 | break; | |
780 | } | |
781 | ||
782 | spin_unlock_irqrestore(&dwc->lock, flags); | |
783 | } | |
784 | ||
785 | static int dwc3_suspend(struct device *dev) | |
786 | { | |
787 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
788 | unsigned long flags; | |
789 | ||
790 | spin_lock_irqsave(&dwc->lock, flags); | |
791 | ||
a45c82b8 RK |
792 | switch (dwc->dr_mode) { |
793 | case USB_DR_MODE_PERIPHERAL: | |
794 | case USB_DR_MODE_OTG: | |
7415f17c FB |
795 | dwc3_gadget_suspend(dwc); |
796 | /* FALLTHROUGH */ | |
a45c82b8 | 797 | case USB_DR_MODE_HOST: |
7415f17c FB |
798 | default: |
799 | /* do nothing */ | |
800 | break; | |
801 | } | |
802 | ||
803 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
804 | spin_unlock_irqrestore(&dwc->lock, flags); | |
805 | ||
806 | usb_phy_shutdown(dwc->usb3_phy); | |
807 | usb_phy_shutdown(dwc->usb2_phy); | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
812 | static int dwc3_resume(struct device *dev) | |
813 | { | |
814 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
815 | unsigned long flags; | |
816 | ||
817 | usb_phy_init(dwc->usb3_phy); | |
818 | usb_phy_init(dwc->usb2_phy); | |
7415f17c FB |
819 | |
820 | spin_lock_irqsave(&dwc->lock, flags); | |
821 | ||
822 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); | |
823 | ||
a45c82b8 RK |
824 | switch (dwc->dr_mode) { |
825 | case USB_DR_MODE_PERIPHERAL: | |
826 | case USB_DR_MODE_OTG: | |
7415f17c FB |
827 | dwc3_gadget_resume(dwc); |
828 | /* FALLTHROUGH */ | |
a45c82b8 | 829 | case USB_DR_MODE_HOST: |
7415f17c FB |
830 | default: |
831 | /* do nothing */ | |
832 | break; | |
833 | } | |
834 | ||
835 | spin_unlock_irqrestore(&dwc->lock, flags); | |
836 | ||
837 | pm_runtime_disable(dev); | |
838 | pm_runtime_set_active(dev); | |
839 | pm_runtime_enable(dev); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
845 | .prepare = dwc3_prepare, | |
846 | .complete = dwc3_complete, | |
847 | ||
848 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) | |
849 | }; | |
850 | ||
851 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
852 | #else | |
853 | #define DWC3_PM_OPS NULL | |
854 | #endif | |
855 | ||
5088b6f5 KVA |
856 | #ifdef CONFIG_OF |
857 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
858 | { |
859 | .compatible = "snps,dwc3" | |
860 | }, | |
5088b6f5 KVA |
861 | { |
862 | .compatible = "synopsys,dwc3" | |
863 | }, | |
864 | { }, | |
865 | }; | |
866 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
867 | #endif | |
868 | ||
72246da4 FB |
869 | static struct platform_driver dwc3_driver = { |
870 | .probe = dwc3_probe, | |
7690417d | 871 | .remove = dwc3_remove, |
72246da4 FB |
872 | .driver = { |
873 | .name = "dwc3", | |
5088b6f5 | 874 | .of_match_table = of_match_ptr(of_dwc3_match), |
7415f17c | 875 | .pm = DWC3_PM_OPS, |
72246da4 | 876 | }, |
72246da4 FB |
877 | }; |
878 | ||
b1116dcc TK |
879 | module_platform_driver(dwc3_driver); |
880 | ||
7ae4fc4d | 881 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 882 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 883 | MODULE_LICENSE("GPL v2"); |
72246da4 | 884 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |