[deliverable/linux.git] / drivers / usb / dwc3 / core.c

/**
 * core.c - DesignWare USB3 DRD Controller Core file
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/module.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

#include "debug.h"

static char *maximum_speed = "super";
module_param(maximum_speed, charp, 0);
MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");

/* -------------------------------------------------------------------------- */

#define DWC3_DEVS_POSSIBLE	32

static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);

int dwc3_get_device_id(void)
{
	int		id;

again:
	id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
	if (id < DWC3_DEVS_POSSIBLE) {
		int old;

		old = test_and_set_bit(id, dwc3_devs);
		if (old)
			goto again;
	} else {
		pr_err("dwc3: no space for new device\n");
		id = -ENOMEM;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(dwc3_get_device_id);

void dwc3_put_device_id(int id)
{
	int			ret;

	if (id < 0)
		return;

	ret = test_bit(id, dwc3_devs);
	WARN(!ret, "dwc3: ID %d not in use\n", id);
	clear_bit(id, dwc3_devs);
}
EXPORT_SYMBOL_GPL(dwc3_put_device_id);

void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
{
	u32 reg;

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	reg |= DWC3_GCTL_PRTCAPDIR(mode);
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 * @dwc: pointer to our context structure
 */
static void dwc3_core_soft_reset(struct dwc3 *dwc)
{
	u32		reg;

	/* Before Resetting PHY, put Core in Reset */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg |= DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	/* Assert USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Assert USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	mdelay(100);

	/* Clear USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Clear USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	/* After PHYs are stable we can take Core out of reset state */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_free_one_event_buffer - Frees one event buffer
 * @dwc: Pointer to our controller context structure
 * @evt: Pointer to event buffer to be freed
 */
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
		struct dwc3_event_buffer *evt)
{
	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	kfree(evt);
}

/**
 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
 * @dwc: Pointer to our controller context structure
 * @length: size of the event buffer
 *
 * Returns a pointer to the allocated event buffer structure on succes
 * otherwise ERR_PTR(errno).
 */
static struct dwc3_event_buffer *__devinit
dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
{
	struct dwc3_event_buffer	*evt;

	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
	if (!evt)
		return ERR_PTR(-ENOMEM);

	evt->dwc	= dwc;
	evt->length	= length;
	evt->buf	= dma_alloc_coherent(dwc->dev, length,
			&evt->dma, GFP_KERNEL);
	if (!evt->buf) {
		kfree(evt);
		return ERR_PTR(-ENOMEM);
	}

	return evt;
}

/**
 * dwc3_free_event_buffers - frees all allocated event buffers
 * @dwc: Pointer to our controller context structure
 */
static void dwc3_free_event_buffers(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int i;

	for (i = 0; i < dwc->num_event_buffers; i++) {
		evt = dwc->ev_buffs[i];
		if (evt) {
			dwc3_free_one_event_buffer(dwc, evt);
			dwc->ev_buffs[i] = NULL;
		}
	}
}

/**
 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 * @dwc: Pointer to out controller context structure
 * @length: size of event buffer
 *
 * Returns 0 on success otherwise negative errno. In error the case, dwc
 * may contain some buffers allocated but not all which were requested.
 */
static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
{
	int			num;
	int			i;

	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	dwc->num_event_buffers = num;

	dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);
	if (!dwc->ev_buffs) {
		dev_err(dwc->dev, "can't allocate event buffers array\n");
		return -ENOMEM;
	}

	for (i = 0; i < num; i++) {
		struct dwc3_event_buffer	*evt;

		evt = dwc3_alloc_one_event_buffer(dwc, length);
		if (IS_ERR(evt)) {
			dev_err(dwc->dev, "can't allocate event buffer\n");
			return PTR_ERR(evt);
		}
		dwc->ev_buffs[i] = evt;
	}

	return 0;
}

/**
 * dwc3_event_buffers_setup - setup our allocated event buffers
 * @dwc: Pointer to out controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
				evt->buf, (unsigned long long) evt->dma,
				evt->length);

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
				lower_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
				upper_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
				evt->length & 0xffff);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}

	return 0;
}

static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}
}

static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
{
	struct dwc3_hwparams	*parms = &dwc->hwparams;

	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
}

/**
 * dwc3_core_init - Low-level initialization of DWC3 Core
 * @dwc: Pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_core_init(struct dwc3 *dwc)
{
	unsigned long		timeout;
	u32			reg;
	int			ret;

	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	/* This should read as U3 followed by revision number */
	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
		ret = -ENODEV;
		goto err0;
	}
	dwc->revision = reg;

	dwc3_core_soft_reset(dwc);

	/* issue device SoftReset too */
	timeout = jiffies + msecs_to_jiffies(500);
	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	do {
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		if (!(reg & DWC3_DCTL_CSFTRST))
			break;

		if (time_after(jiffies, timeout)) {
			dev_err(dwc->dev, "Reset Timed Out\n");
			ret = -ETIMEDOUT;
			goto err0;
		}

		cpu_relax();
	} while (true);

	dwc3_cache_hwparams(dwc);

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_SCALEDOWN(3);
	reg &= ~DWC3_GCTL_DISSCRAMBLE;

	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
		break;
	default:
		dev_dbg(dwc->dev, "No power optimization available\n");
	}

	/*
	 * WORKAROUND: DWC3 revisions <1.90a have a bug
	 * when The device fails to connect at SuperSpeed
	 * and falls back to high-speed mode which causes
	 * the device to enter in a Connect/Disconnect loop
	 */
	if (dwc->revision < DWC3_REVISION_190A)
		reg |= DWC3_GCTL_U2RSTECN;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
	if (ret) {
		dev_err(dwc->dev, "failed to allocate event buffers\n");
		ret = -ENOMEM;
		goto err1;
	}

	ret = dwc3_event_buffers_setup(dwc);
	if (ret) {
		dev_err(dwc->dev, "failed to setup event buffers\n");
		goto err1;
	}

	return 0;

err1:
	dwc3_free_event_buffers(dwc);

err0:
	return ret;
}

static void dwc3_core_exit(struct dwc3 *dwc)
{
	dwc3_event_buffers_cleanup(dwc);
	dwc3_free_event_buffers(dwc);
}

#define DWC3_ALIGN_MASK		(16 - 1)

static int __devinit dwc3_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;
	struct resource		*res;
	struct dwc3		*dwc;

	int			ret = -ENOMEM;
	int			irq;

	void __iomem		*regs;
	void			*mem;

	u8			mode;

	mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	if (!mem) {
		dev_err(&pdev->dev, "not enough memory\n");
		goto err0;
	}
	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	dwc->mem = mem;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "missing resource\n");
		goto err1;
	}

	dwc->res = res;

	res = request_mem_region(res->start, resource_size(res),
			dev_name(&pdev->dev));
	if (!res) {
		dev_err(&pdev->dev, "can't request mem region\n");
		goto err1;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		goto err2;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "missing IRQ\n");
		goto err3;
	}

	spin_lock_init(&dwc->lock);
	platform_set_drvdata(pdev, dwc);

	dwc->regs	= regs;
	dwc->regs_size	= resource_size(res);
	dwc->dev	= &pdev->dev;
	dwc->irq	= irq;

	if (!strncmp("super", maximum_speed, 5))
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	else if (!strncmp("high", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	else if (!strncmp("full", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	else if (!strncmp("low", maximum_speed, 3))
		dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	else
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;

	if (of_get_property(node, "tx-fifo-resize", NULL))
		dwc->needs_fifo_resize = true;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_forbid(&pdev->dev);

	ret = dwc3_core_init(dwc);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize core\n");
		goto err3;
	}

	mode = DWC3_MODE(dwc->hwparams.hwparams0);

	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize gadget\n");
			goto err4;
		}
		break;
	case DWC3_MODE_HOST:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize host\n");
			goto err4;
		}
		break;
	case DWC3_MODE_DRD:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize host\n");
			goto err4;
		}

		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize gadget\n");
			goto err4;
		}
		break;
	default:
		dev_err(&pdev->dev, "Unsupported mode of operation %d\n", mode);
		goto err4;
	}
	dwc->mode = mode;

	ret = dwc3_debugfs_init(dwc);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize debugfs\n");
		goto err5;
	}

	pm_runtime_allow(&pdev->dev);

	return 0;

err5:
	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

err4:
	dwc3_core_exit(dwc);

err3:
	iounmap(regs);

err2:
	release_mem_region(res->start, resource_size(res));

err1:
	kfree(dwc->mem);

err0:
	return ret;
}

static int __devexit dwc3_remove(struct platform_device *pdev)
{
	struct dwc3	*dwc = platform_get_drvdata(pdev);
	struct resource	*res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	dwc3_debugfs_exit(dwc);

	switch (dwc->mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

	dwc3_core_exit(dwc);
	release_mem_region(res->start, resource_size(res));
	iounmap(dwc->regs);
	kfree(dwc->mem);

	return 0;
}

static struct platform_driver dwc3_driver = {
	.probe		= dwc3_probe,
	.remove		= __devexit_p(dwc3_remove),
	.driver		= {
		.name	= "dwc3",
	},
};

MODULE_ALIAS("platform:dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");

static int __devinit dwc3_init(void)
{
	return platform_driver_register(&dwc3_driver);
}
module_init(dwc3_init);

static void __exit dwc3_exit(void)
{
	platform_driver_unregister(&dwc3_driver);
}
module_exit(dwc3_exit);
Commit	Line	Data
72246da4 FB	1	/**
	2	* core.c - DesignWare USB3 DRD Controller Core file
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/ioport.h>
	47	#include <linux/io.h>
	48	#include <linux/list.h>
	49	#include <linux/delay.h>
	50	#include <linux/dma-mapping.h>
457e84b6	51	#include <linux/of.h>
72246da4 FB	52
	53	#include <linux/usb/ch9.h>
	54	#include <linux/usb/gadget.h>
2204fdee	55	#include <linux/module.h>
72246da4 FB	56
	57	#include "core.h"
	58	#include "gadget.h"
	59	#include "io.h"
	60
	61	#include "debug.h"
	62
6c167fc9 FB	63	static char *maximum_speed = "super";
	64	module_param(maximum_speed, charp, 0);
	65	MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
	66
8300dd23 FB	67	/* -------------------------------------------------------------------------- */
	68
	69	#define DWC3_DEVS_POSSIBLE 32
	70
	71	static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
	72
	73	int dwc3_get_device_id(void)
	74	{
	75	int id;
	76
	77	again:
	78	id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
	79	if (id < DWC3_DEVS_POSSIBLE) {
	80	int old;
	81
	82	old = test_and_set_bit(id, dwc3_devs);
	83	if (old)
	84	goto again;
	85	} else {
	86	pr_err("dwc3: no space for new device\n");
	87	id = -ENOMEM;
	88	}
	89
	90	return 0;
	91	}
	92	EXPORT_SYMBOL_GPL(dwc3_get_device_id);
	93
	94	void dwc3_put_device_id(int id)
	95	{
	96	int ret;
	97
	98	if (id < 0)
	99	return;
	100
	101	ret = test_bit(id, dwc3_devs);
	102	WARN(!ret, "dwc3: ID %d not in use\n", id);
	103	clear_bit(id, dwc3_devs);
	104	}
	105	EXPORT_SYMBOL_GPL(dwc3_put_device_id);
	106
3140e8cb SAS	107	void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
	108	{
	109	u32 reg;
	110
	111	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	112	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	113	reg \|= DWC3_GCTL_PRTCAPDIR(mode);
	114	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	115	}
8300dd23	116
72246da4 FB	117	/**
	118	* dwc3_core_soft_reset - Issues core soft reset and PHY reset
	119	* @dwc: pointer to our context structure
	120	*/
	121	static void dwc3_core_soft_reset(struct dwc3 *dwc)
	122	{
	123	u32 reg;
	124
	125	/* Before Resetting PHY, put Core in Reset */
	126	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	127	reg \|= DWC3_GCTL_CORESOFTRESET;
	128	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	129
	130	/* Assert USB3 PHY reset */
	131	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	132	reg \|= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	133	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	134
	135	/* Assert USB2 PHY reset */
	136	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	137	reg \|= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	138	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	139
	140	mdelay(100);
	141
	142	/* Clear USB3 PHY reset */
	143	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	144	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	145	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	146
	147	/* Clear USB2 PHY reset */
	148	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	149	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	150	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	151
	152	/* After PHYs are stable we can take Core out of reset state */
	153	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	154	reg &= ~DWC3_GCTL_CORESOFTRESET;
	155	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	156	}
	157
	158	/**
	159	* dwc3_free_one_event_buffer - Frees one event buffer
	160	* @dwc: Pointer to our controller context structure
	161	* @evt: Pointer to event buffer to be freed
	162	*/
	163	static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
	164	struct dwc3_event_buffer *evt)
	165	{
	166	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	167	kfree(evt);
	168	}
	169
	170	/**
	171	* dwc3_alloc_one_event_buffer - Allocated one event buffer structure
	172	* @dwc: Pointer to our controller context structure
	173	* @length: size of the event buffer
	174	*
	175	* Returns a pointer to the allocated event buffer structure on succes
	176	* otherwise ERR_PTR(errno).
	177	*/
	178	static struct dwc3_event_buffer *__devinit
	179	dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
	180	{
181	struct dwc3_event_buffer *evt;
182
183	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
184	if (!evt)
185	return ERR_PTR(-ENOMEM);
186
187	evt->dwc = dwc;
188	evt->length = length;
189	evt->buf = dma_alloc_coherent(dwc->dev, length,
190	&evt->dma, GFP_KERNEL);
191	if (!evt->buf) {
192	kfree(evt);
193	return ERR_PTR(-ENOMEM);
194	}
195
196	return evt;
197	}
198
199	/**
200	* dwc3_free_event_buffers - frees all allocated event buffers
201	* @dwc: Pointer to our controller context structure
202	*/
203	static void dwc3_free_event_buffers(struct dwc3 *dwc)
204	{
205	struct dwc3_event_buffer *evt;
206	int i;
207
9f622b2a	208	for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4 FB	209	evt = dwc->ev_buffs[i];
	210	if (evt) {
	211	dwc3_free_one_event_buffer(dwc, evt);
	212	dwc->ev_buffs[i] = NULL;
	213	}
	214	}
	215	}
	216
	217	/**
	218	* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
	219	* @dwc: Pointer to out controller context structure
72246da4 FB	220	* @length: size of event buffer
	221	*
	222	* Returns 0 on success otherwise negative errno. In error the case, dwc
	223	* may contain some buffers allocated but not all which were requested.
	224	*/
9f622b2a	225	static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4	226	{
9f622b2a	227	int num;
72246da4 FB	228	int i;
72246da4 FB	229
9f622b2a FB	230	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	231	dwc->num_event_buffers = num;
	232
457d3f21 FB	233	dwc->ev_buffs = kzalloc(sizeof(dwc->ev_buffs) num, GFP_KERNEL);
	234	if (!dwc->ev_buffs) {
	235	dev_err(dwc->dev, "can't allocate event buffers array\n");
	236	return -ENOMEM;
	237	}
	238
72246da4 FB	239	for (i = 0; i < num; i++) {
	240	struct dwc3_event_buffer *evt;
	241
	242	evt = dwc3_alloc_one_event_buffer(dwc, length);
	243	if (IS_ERR(evt)) {
	244	dev_err(dwc->dev, "can't allocate event buffer\n");
	245	return PTR_ERR(evt);
	246	}
	247	dwc->ev_buffs[i] = evt;
	248	}
	249
	250	return 0;
	251	}
	252
	253	/**
	254	* dwc3_event_buffers_setup - setup our allocated event buffers
	255	* @dwc: Pointer to out controller context structure
	256	*
	257	* Returns 0 on success otherwise negative errno.
	258	*/
	259	static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
	260	{
	261	struct dwc3_event_buffer *evt;
	262	int n;
	263
9f622b2a	264	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	265	evt = dwc->ev_buffs[n];
	266	dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
	267	evt->buf, (unsigned long long) evt->dma,
	268	evt->length);
	269
	270	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
	271	lower_32_bits(evt->dma));
	272	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
	273	upper_32_bits(evt->dma));
	274	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
	275	evt->length & 0xffff);
	276	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	277	}
	278
	279	return 0;
	280	}
	281
	282	static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
	283	{
	284	struct dwc3_event_buffer *evt;
	285	int n;
	286
9f622b2a	287	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	288	evt = dwc->ev_buffs[n];
	289	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
	290	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
	291	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
	292	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	293	}
	294	}
	295
26ceca97 FB	296	static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
	297	{
	298	struct dwc3_hwparams *parms = &dwc->hwparams;
	299
	300	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	301	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	302	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	303	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	304	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	305	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	306	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	307	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	308	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
	309	}
	310
72246da4 FB	311	/**
	312	* dwc3_core_init - Low-level initialization of DWC3 Core
	313	* @dwc: Pointer to our controller context structure
	314	*
	315	* Returns 0 on success otherwise negative errno.
	316	*/
	317	static int __devinit dwc3_core_init(struct dwc3 *dwc)
	318	{
	319	unsigned long timeout;
	320	u32 reg;
	321	int ret;
	322
7650bd74 SAS	323	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	324	/* This should read as U3 followed by revision number */
	325	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
	326	dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
	327	ret = -ENODEV;
	328	goto err0;
	329	}
248b122b	330	dwc->revision = reg;
7650bd74	331
72246da4 FB	332	dwc3_core_soft_reset(dwc);
	333
	334	/* issue device SoftReset too */
	335	timeout = jiffies + msecs_to_jiffies(500);
	336	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	337	do {
	338	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	339	if (!(reg & DWC3_DCTL_CSFTRST))
	340	break;
	341
	342	if (time_after(jiffies, timeout)) {
	343	dev_err(dwc->dev, "Reset Timed Out\n");
	344	ret = -ETIMEDOUT;
	345	goto err0;
	346	}
	347
	348	cpu_relax();
	349	} while (true);
	350
9f622b2a FB	351	dwc3_cache_hwparams(dwc);
9f622b2a FB	352
4878a028 SAS	353	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	354	reg &= ~DWC3_GCTL_SCALEDOWN(3);
	355	reg &= ~DWC3_GCTL_DISSCRAMBLE;
	356
164d7731	357	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 SAS	358	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
	359	reg &= ~DWC3_GCTL_DSBLCLKGTNG;
	360	break;
	361	default:
	362	dev_dbg(dwc->dev, "No power optimization available\n");
	363	}
	364
	365	/*
	366	* WORKAROUND: DWC3 revisions <1.90a have a bug
	367	* when The device fails to connect at SuperSpeed
	368	* and falls back to high-speed mode which causes
	369	* the device to enter in a Connect/Disconnect loop
	370	*/
	371	if (dwc->revision < DWC3_REVISION_190A)
	372	reg \|= DWC3_GCTL_U2RSTECN;
	373
	374	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	375
9f622b2a	376	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
72246da4 FB	377	if (ret) {
	378	dev_err(dwc->dev, "failed to allocate event buffers\n");
	379	ret = -ENOMEM;
	380	goto err1;
	381	}
	382
	383	ret = dwc3_event_buffers_setup(dwc);
	384	if (ret) {
	385	dev_err(dwc->dev, "failed to setup event buffers\n");
	386	goto err1;
	387	}
	388
	389	return 0;
	390
	391	err1:
	392	dwc3_free_event_buffers(dwc);
	393
	394	err0:
	395	return ret;
	396	}
	397
	398	static void dwc3_core_exit(struct dwc3 *dwc)
	399	{
	400	dwc3_event_buffers_cleanup(dwc);
	401	dwc3_free_event_buffers(dwc);
	402	}
	403
	404	#define DWC3_ALIGN_MASK (16 - 1)
	405
	406	static int __devinit dwc3_probe(struct platform_device *pdev)
	407	{
457e84b6	408	struct device_node *node = pdev->dev.of_node;
72246da4 FB	409	struct resource *res;
72246da4 FB	410	struct dwc3 *dwc;
0949e99b	411
72246da4 FB	412	int ret = -ENOMEM;
72246da4 FB	413	int irq;
0949e99b FB	414
0949e99b FB	415	void __iomem *regs;
72246da4 FB	416	void *mem;
72246da4 FB	417
0949e99b FB	418	u8 mode;
0949e99b FB	419
72246da4 FB	420	mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	421	if (!mem) {
	422	dev_err(&pdev->dev, "not enough memory\n");
	423	goto err0;
	424	}
	425	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	426	dwc->mem = mem;
	427
	428	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	429	if (!res) {
	430	dev_err(&pdev->dev, "missing resource\n");
	431	goto err1;
	432	}
	433
d07e8819 FB	434	dwc->res = res;
d07e8819 FB	435
72246da4 FB	436	res = request_mem_region(res->start, resource_size(res),
	437	dev_name(&pdev->dev));
	438	if (!res) {
	439	dev_err(&pdev->dev, "can't request mem region\n");
	440	goto err1;
	441	}
	442
	443	regs = ioremap(res->start, resource_size(res));
	444	if (!regs) {
	445	dev_err(&pdev->dev, "ioremap failed\n");
	446	goto err2;
	447	}
	448
	449	irq = platform_get_irq(pdev, 0);
	450	if (irq < 0) {
	451	dev_err(&pdev->dev, "missing IRQ\n");
	452	goto err3;
	453	}
	454
	455	spin_lock_init(&dwc->lock);
	456	platform_set_drvdata(pdev, dwc);
	457
	458	dwc->regs = regs;
	459	dwc->regs_size = resource_size(res);
	460	dwc->dev = &pdev->dev;
	461	dwc->irq = irq;
	462
6c167fc9 FB	463	if (!strncmp("super", maximum_speed, 5))
	464	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	465	else if (!strncmp("high", maximum_speed, 4))
	466	dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	467	else if (!strncmp("full", maximum_speed, 4))
	468	dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	469	else if (!strncmp("low", maximum_speed, 3))
	470	dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	471	else
	472	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	473
457e84b6 FB	474	if (of_get_property(node, "tx-fifo-resize", NULL))
	475	dwc->needs_fifo_resize = true;
	476
72246da4 FB	477	pm_runtime_enable(&pdev->dev);
	478	pm_runtime_get_sync(&pdev->dev);
	479	pm_runtime_forbid(&pdev->dev);
	480
	481	ret = dwc3_core_init(dwc);
	482	if (ret) {
	483	dev_err(&pdev->dev, "failed to initialize core\n");
	484	goto err3;
	485	}
	486
0949e99b FB	487	mode = DWC3_MODE(dwc->hwparams.hwparams0);
	488
	489	switch (mode) {
0949e99b	490	case DWC3_MODE_DEVICE:
3140e8cb	491	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
72246da4 FB	492	ret = dwc3_gadget_init(dwc);
72246da4 FB	493	if (ret) {
d07e8819	494	dev_err(&pdev->dev, "failed to initialize gadget\n");
72246da4 FB	495	goto err4;
72246da4 FB	496	}
d07e8819 FB	497	break;
d07e8819 FB	498	case DWC3_MODE_HOST:
3140e8cb	499	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
d07e8819 FB	500	ret = dwc3_host_init(dwc);
	501	if (ret) {
	502	dev_err(&pdev->dev, "failed to initialize host\n");
	503	goto err4;
	504	}
	505	break;
	506	case DWC3_MODE_DRD:
3140e8cb	507	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
d07e8819 FB	508	ret = dwc3_host_init(dwc);
	509	if (ret) {
	510	dev_err(&pdev->dev, "failed to initialize host\n");
	511	goto err4;
	512	}
	513
72246da4 FB	514	ret = dwc3_gadget_init(dwc);
72246da4 FB	515	if (ret) {
0949e99b	516	dev_err(&pdev->dev, "failed to initialize gadget\n");
72246da4 FB	517	goto err4;
72246da4 FB	518	}
0949e99b FB	519	break;
	520	default:
	521	dev_err(&pdev->dev, "Unsupported mode of operation %d\n", mode);
	522	goto err4;
72246da4	523	}
0949e99b	524	dwc->mode = mode;
72246da4 FB	525
	526	ret = dwc3_debugfs_init(dwc);
	527	if (ret) {
	528	dev_err(&pdev->dev, "failed to initialize debugfs\n");
	529	goto err5;
	530	}
	531
	532	pm_runtime_allow(&pdev->dev);
	533
	534	return 0;
	535
	536	err5:
0949e99b	537	switch (mode) {
0949e99b	538	case DWC3_MODE_DEVICE:
72246da4	539	dwc3_gadget_exit(dwc);
0949e99b	540	break;
d07e8819 FB	541	case DWC3_MODE_HOST:
	542	dwc3_host_exit(dwc);
	543	break;
	544	case DWC3_MODE_DRD:
	545	dwc3_host_exit(dwc);
72246da4	546	dwc3_gadget_exit(dwc);
d07e8819	547	break;
0949e99b FB	548	default:
	549	/* do nothing */
	550	break;
	551	}
72246da4 FB	552
	553	err4:
	554	dwc3_core_exit(dwc);
	555
	556	err3:
	557	iounmap(regs);
	558
	559	err2:
	560	release_mem_region(res->start, resource_size(res));
	561
	562	err1:
	563	kfree(dwc->mem);
	564
	565	err0:
	566	return ret;
	567	}
	568
	569	static int __devexit dwc3_remove(struct platform_device *pdev)
	570	{
72246da4 FB	571	struct dwc3 *dwc = platform_get_drvdata(pdev);
72246da4 FB	572	struct resource *res;
72246da4 FB	573
	574	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	575
	576	pm_runtime_put(&pdev->dev);
	577	pm_runtime_disable(&pdev->dev);
	578
	579	dwc3_debugfs_exit(dwc);
	580
0949e99b	581	switch (dwc->mode) {
0949e99b	582	case DWC3_MODE_DEVICE:
72246da4	583	dwc3_gadget_exit(dwc);
0949e99b	584	break;
d07e8819 FB	585	case DWC3_MODE_HOST:
	586	dwc3_host_exit(dwc);
	587	break;
	588	case DWC3_MODE_DRD:
	589	dwc3_host_exit(dwc);
72246da4	590	dwc3_gadget_exit(dwc);
d07e8819	591	break;
0949e99b FB	592	default:
	593	/* do nothing */
	594	break;
	595	}
72246da4 FB	596
	597	dwc3_core_exit(dwc);
	598	release_mem_region(res->start, resource_size(res));
	599	iounmap(dwc->regs);
	600	kfree(dwc->mem);
	601
	602	return 0;
	603	}
	604
72246da4 FB	605	static struct platform_driver dwc3_driver = {
	606	.probe = dwc3_probe,
	607	.remove = __devexit_p(dwc3_remove),
	608	.driver = {
	609	.name = "dwc3",
	610	},
72246da4 FB	611	};
72246da4 FB	612
7ae4fc4d	613	MODULE_ALIAS("platform:dwc3");
72246da4 FB	614	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	615	MODULE_LICENSE("Dual BSD/GPL");
	616	MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
	617
	618	static int __devinit dwc3_init(void)
	619	{
	620	return platform_driver_register(&dwc3_driver);
	621	}
	622	module_init(dwc3_init);
	623
	624	static void __exit dwc3_exit(void)
	625	{
	626	platform_driver_unregister(&dwc3_driver);
	627	}
	628	module_exit(dwc3_exit);