Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
fa0ea13e | 22 | #include <linux/version.h> |
a72e658b | 23 | #include <linux/module.h> |
72246da4 FB |
24 | #include <linux/kernel.h> |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/list.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
457e84b6 | 35 | #include <linux/of.h> |
404905a6 | 36 | #include <linux/acpi.h> |
72246da4 FB |
37 | |
38 | #include <linux/usb/ch9.h> | |
39 | #include <linux/usb/gadget.h> | |
f7e846f0 | 40 | #include <linux/usb/of.h> |
a45c82b8 | 41 | #include <linux/usb/otg.h> |
72246da4 | 42 | |
6462cbd5 | 43 | #include "platform_data.h" |
72246da4 FB |
44 | #include "core.h" |
45 | #include "gadget.h" | |
46 | #include "io.h" | |
47 | ||
48 | #include "debug.h" | |
49 | ||
8300dd23 FB |
50 | /* -------------------------------------------------------------------------- */ |
51 | ||
3140e8cb SAS |
52 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
53 | { | |
54 | u32 reg; | |
55 | ||
56 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
57 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
58 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
59 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
60 | } | |
8300dd23 | 61 | |
72246da4 FB |
62 | /** |
63 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
64 | * @dwc: pointer to our context structure | |
65 | */ | |
57303488 | 66 | static int dwc3_core_soft_reset(struct dwc3 *dwc) |
72246da4 FB |
67 | { |
68 | u32 reg; | |
57303488 | 69 | int ret; |
72246da4 FB |
70 | |
71 | /* Before Resetting PHY, put Core in Reset */ | |
72 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
73 | reg |= DWC3_GCTL_CORESOFTRESET; | |
74 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
75 | ||
76 | /* Assert USB3 PHY reset */ | |
77 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
78 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
79 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
80 | ||
81 | /* Assert USB2 PHY reset */ | |
82 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
83 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
84 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
85 | ||
51e1e7bc FB |
86 | usb_phy_init(dwc->usb2_phy); |
87 | usb_phy_init(dwc->usb3_phy); | |
57303488 KVA |
88 | ret = phy_init(dwc->usb2_generic_phy); |
89 | if (ret < 0) | |
90 | return ret; | |
91 | ||
92 | ret = phy_init(dwc->usb3_generic_phy); | |
93 | if (ret < 0) { | |
94 | phy_exit(dwc->usb2_generic_phy); | |
95 | return ret; | |
96 | } | |
72246da4 FB |
97 | mdelay(100); |
98 | ||
99 | /* Clear USB3 PHY reset */ | |
100 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
101 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
102 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
103 | ||
104 | /* Clear USB2 PHY reset */ | |
105 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
106 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
107 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
108 | ||
45627ac6 PA |
109 | mdelay(100); |
110 | ||
72246da4 FB |
111 | /* After PHYs are stable we can take Core out of reset state */ |
112 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
113 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
114 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
57303488 KVA |
115 | |
116 | return 0; | |
72246da4 FB |
117 | } |
118 | ||
119 | /** | |
120 | * dwc3_free_one_event_buffer - Frees one event buffer | |
121 | * @dwc: Pointer to our controller context structure | |
122 | * @evt: Pointer to event buffer to be freed | |
123 | */ | |
124 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
125 | struct dwc3_event_buffer *evt) | |
126 | { | |
127 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
128 | } |
129 | ||
130 | /** | |
1d046793 | 131 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
132 | * @dwc: Pointer to our controller context structure |
133 | * @length: size of the event buffer | |
134 | * | |
1d046793 | 135 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
136 | * otherwise ERR_PTR(errno). |
137 | */ | |
67d0b500 FB |
138 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
139 | unsigned length) | |
72246da4 FB |
140 | { |
141 | struct dwc3_event_buffer *evt; | |
142 | ||
380f0d28 | 143 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
144 | if (!evt) |
145 | return ERR_PTR(-ENOMEM); | |
146 | ||
147 | evt->dwc = dwc; | |
148 | evt->length = length; | |
149 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
150 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 151 | if (!evt->buf) |
72246da4 | 152 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
153 | |
154 | return evt; | |
155 | } | |
156 | ||
157 | /** | |
158 | * dwc3_free_event_buffers - frees all allocated event buffers | |
159 | * @dwc: Pointer to our controller context structure | |
160 | */ | |
161 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
162 | { | |
163 | struct dwc3_event_buffer *evt; | |
164 | int i; | |
165 | ||
9f622b2a | 166 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 167 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 168 | if (evt) |
72246da4 | 169 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
170 | } |
171 | } | |
172 | ||
173 | /** | |
174 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 175 | * @dwc: pointer to our controller context structure |
72246da4 FB |
176 | * @length: size of event buffer |
177 | * | |
1d046793 | 178 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
179 | * may contain some buffers allocated but not all which were requested. |
180 | */ | |
41ac7b3a | 181 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 182 | { |
9f622b2a | 183 | int num; |
72246da4 FB |
184 | int i; |
185 | ||
9f622b2a FB |
186 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
187 | dwc->num_event_buffers = num; | |
188 | ||
380f0d28 FB |
189 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
190 | GFP_KERNEL); | |
734d5a53 | 191 | if (!dwc->ev_buffs) |
457d3f21 | 192 | return -ENOMEM; |
457d3f21 | 193 | |
72246da4 FB |
194 | for (i = 0; i < num; i++) { |
195 | struct dwc3_event_buffer *evt; | |
196 | ||
197 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
198 | if (IS_ERR(evt)) { | |
199 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
200 | return PTR_ERR(evt); | |
201 | } | |
202 | dwc->ev_buffs[i] = evt; | |
203 | } | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
208 | /** | |
209 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 210 | * @dwc: pointer to our controller context structure |
72246da4 FB |
211 | * |
212 | * Returns 0 on success otherwise negative errno. | |
213 | */ | |
7acd85e0 | 214 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
215 | { |
216 | struct dwc3_event_buffer *evt; | |
217 | int n; | |
218 | ||
9f622b2a | 219 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
220 | evt = dwc->ev_buffs[n]; |
221 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
222 | evt->buf, (unsigned long long) evt->dma, | |
223 | evt->length); | |
224 | ||
7acd85e0 PZ |
225 | evt->lpos = 0; |
226 | ||
72246da4 FB |
227 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
228 | lower_32_bits(evt->dma)); | |
229 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
230 | upper_32_bits(evt->dma)); | |
231 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
68d6a01b | 232 | DWC3_GEVNTSIZ_SIZE(evt->length)); |
72246da4 FB |
233 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
234 | } | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
240 | { | |
241 | struct dwc3_event_buffer *evt; | |
242 | int n; | |
243 | ||
9f622b2a | 244 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 245 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
246 | |
247 | evt->lpos = 0; | |
248 | ||
72246da4 FB |
249 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
250 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
68d6a01b FB |
251 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK |
252 | | DWC3_GEVNTSIZ_SIZE(0)); | |
72246da4 FB |
253 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); |
254 | } | |
255 | } | |
256 | ||
0ffcaf37 FB |
257 | static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) |
258 | { | |
259 | if (!dwc->has_hibernation) | |
260 | return 0; | |
261 | ||
262 | if (!dwc->nr_scratch) | |
263 | return 0; | |
264 | ||
265 | dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, | |
266 | DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); | |
267 | if (!dwc->scratchbuf) | |
268 | return -ENOMEM; | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) | |
274 | { | |
275 | dma_addr_t scratch_addr; | |
276 | u32 param; | |
277 | int ret; | |
278 | ||
279 | if (!dwc->has_hibernation) | |
280 | return 0; | |
281 | ||
282 | if (!dwc->nr_scratch) | |
283 | return 0; | |
284 | ||
285 | /* should never fall here */ | |
286 | if (!WARN_ON(dwc->scratchbuf)) | |
287 | return 0; | |
288 | ||
289 | scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf, | |
290 | dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, | |
291 | DMA_BIDIRECTIONAL); | |
292 | if (dma_mapping_error(dwc->dev, scratch_addr)) { | |
293 | dev_err(dwc->dev, "failed to map scratch buffer\n"); | |
294 | ret = -EFAULT; | |
295 | goto err0; | |
296 | } | |
297 | ||
298 | dwc->scratch_addr = scratch_addr; | |
299 | ||
300 | param = lower_32_bits(scratch_addr); | |
301 | ||
302 | ret = dwc3_send_gadget_generic_command(dwc, | |
303 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); | |
304 | if (ret < 0) | |
305 | goto err1; | |
306 | ||
307 | param = upper_32_bits(scratch_addr); | |
308 | ||
309 | ret = dwc3_send_gadget_generic_command(dwc, | |
310 | DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); | |
311 | if (ret < 0) | |
312 | goto err1; | |
313 | ||
314 | return 0; | |
315 | ||
316 | err1: | |
317 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
318 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
319 | ||
320 | err0: | |
321 | return ret; | |
322 | } | |
323 | ||
324 | static void dwc3_free_scratch_buffers(struct dwc3 *dwc) | |
325 | { | |
326 | if (!dwc->has_hibernation) | |
327 | return; | |
328 | ||
329 | if (!dwc->nr_scratch) | |
330 | return; | |
331 | ||
332 | /* should never fall here */ | |
333 | if (!WARN_ON(dwc->scratchbuf)) | |
334 | return; | |
335 | ||
336 | dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch * | |
337 | DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); | |
338 | kfree(dwc->scratchbuf); | |
339 | } | |
340 | ||
789451f6 FB |
341 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
342 | { | |
343 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
344 | ||
345 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
346 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
347 | ||
348 | dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", | |
349 | dwc->num_in_eps, dwc->num_out_eps); | |
350 | } | |
351 | ||
41ac7b3a | 352 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
353 | { |
354 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
355 | ||
356 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
357 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
358 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
359 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
360 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
361 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
362 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
363 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
364 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
365 | } | |
366 | ||
b5a65c40 HR |
367 | /** |
368 | * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core | |
369 | * @dwc: Pointer to our controller context structure | |
370 | */ | |
371 | static void dwc3_phy_setup(struct dwc3 *dwc) | |
372 | { | |
373 | u32 reg; | |
374 | ||
375 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
376 | ||
377 | if (dwc->u2ss_inp3_quirk) | |
378 | reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; | |
379 | ||
df31f5b3 HR |
380 | if (dwc->req_p1p2p3_quirk) |
381 | reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; | |
382 | ||
b5a65c40 HR |
383 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); |
384 | ||
385 | mdelay(100); | |
386 | } | |
387 | ||
72246da4 FB |
388 | /** |
389 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
390 | * @dwc: Pointer to our controller context structure | |
391 | * | |
392 | * Returns 0 on success otherwise negative errno. | |
393 | */ | |
41ac7b3a | 394 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 FB |
395 | { |
396 | unsigned long timeout; | |
0ffcaf37 | 397 | u32 hwparams4 = dwc->hwparams.hwparams4; |
72246da4 FB |
398 | u32 reg; |
399 | int ret; | |
400 | ||
7650bd74 SAS |
401 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
402 | /* This should read as U3 followed by revision number */ | |
403 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
404 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
405 | ret = -ENODEV; | |
406 | goto err0; | |
407 | } | |
248b122b | 408 | dwc->revision = reg; |
7650bd74 | 409 | |
fa0ea13e FB |
410 | /* |
411 | * Write Linux Version Code to our GUID register so it's easy to figure | |
412 | * out which kernel version a bug was found. | |
413 | */ | |
414 | dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); | |
415 | ||
0e1e5c47 PZ |
416 | /* Handle USB2.0-only core configuration */ |
417 | if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == | |
418 | DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { | |
419 | if (dwc->maximum_speed == USB_SPEED_SUPER) | |
420 | dwc->maximum_speed = USB_SPEED_HIGH; | |
421 | } | |
422 | ||
72246da4 FB |
423 | /* issue device SoftReset too */ |
424 | timeout = jiffies + msecs_to_jiffies(500); | |
425 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
426 | do { | |
427 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
428 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
429 | break; | |
430 | ||
431 | if (time_after(jiffies, timeout)) { | |
432 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
433 | ret = -ETIMEDOUT; | |
434 | goto err0; | |
435 | } | |
436 | ||
437 | cpu_relax(); | |
438 | } while (true); | |
439 | ||
57303488 KVA |
440 | ret = dwc3_core_soft_reset(dwc); |
441 | if (ret) | |
442 | goto err0; | |
58a0f23f | 443 | |
4878a028 | 444 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 445 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 | 446 | |
164d7731 | 447 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 | 448 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
32a4a135 FB |
449 | /** |
450 | * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an | |
451 | * issue which would cause xHCI compliance tests to fail. | |
452 | * | |
453 | * Because of that we cannot enable clock gating on such | |
454 | * configurations. | |
455 | * | |
456 | * Refers to: | |
457 | * | |
458 | * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based | |
459 | * SOF/ITP Mode Used | |
460 | */ | |
461 | if ((dwc->dr_mode == USB_DR_MODE_HOST || | |
462 | dwc->dr_mode == USB_DR_MODE_OTG) && | |
463 | (dwc->revision >= DWC3_REVISION_210A && | |
464 | dwc->revision <= DWC3_REVISION_250A)) | |
465 | reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; | |
466 | else | |
467 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
4878a028 | 468 | break; |
0ffcaf37 FB |
469 | case DWC3_GHWPARAMS1_EN_PWROPT_HIB: |
470 | /* enable hibernation here */ | |
471 | dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); | |
2eac3992 HR |
472 | |
473 | /* | |
474 | * REVISIT Enabling this bit so that host-mode hibernation | |
475 | * will work. Device-mode hibernation is not yet implemented. | |
476 | */ | |
477 | reg |= DWC3_GCTL_GBLHIBERNATIONEN; | |
0ffcaf37 | 478 | break; |
4878a028 SAS |
479 | default: |
480 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
481 | } | |
482 | ||
946bd579 HR |
483 | /* check if current dwc3 is on simulation board */ |
484 | if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { | |
485 | dev_dbg(dwc->dev, "it is on FPGA board\n"); | |
486 | dwc->is_fpga = true; | |
487 | } | |
488 | ||
3b81221a HR |
489 | WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, |
490 | "disable_scramble cannot be used on non-FPGA builds\n"); | |
491 | ||
492 | if (dwc->disable_scramble_quirk && dwc->is_fpga) | |
493 | reg |= DWC3_GCTL_DISSCRAMBLE; | |
494 | else | |
495 | reg &= ~DWC3_GCTL_DISSCRAMBLE; | |
496 | ||
9a5b2f31 HR |
497 | if (dwc->u2exit_lfps_quirk) |
498 | reg |= DWC3_GCTL_U2EXIT_LFPS; | |
499 | ||
4878a028 SAS |
500 | /* |
501 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 502 | * where the device can fail to connect at SuperSpeed |
4878a028 | 503 | * and falls back to high-speed mode which causes |
1d046793 | 504 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
505 | */ |
506 | if (dwc->revision < DWC3_REVISION_190A) | |
507 | reg |= DWC3_GCTL_U2RSTECN; | |
508 | ||
789451f6 FB |
509 | dwc3_core_num_eps(dwc); |
510 | ||
4878a028 SAS |
511 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
512 | ||
b5a65c40 HR |
513 | dwc3_phy_setup(dwc); |
514 | ||
0ffcaf37 FB |
515 | ret = dwc3_alloc_scratch_buffers(dwc); |
516 | if (ret) | |
517 | goto err1; | |
518 | ||
519 | ret = dwc3_setup_scratch_buffers(dwc); | |
520 | if (ret) | |
521 | goto err2; | |
522 | ||
72246da4 FB |
523 | return 0; |
524 | ||
0ffcaf37 FB |
525 | err2: |
526 | dwc3_free_scratch_buffers(dwc); | |
527 | ||
528 | err1: | |
529 | usb_phy_shutdown(dwc->usb2_phy); | |
530 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
531 | phy_exit(dwc->usb2_generic_phy); |
532 | phy_exit(dwc->usb3_generic_phy); | |
0ffcaf37 | 533 | |
72246da4 FB |
534 | err0: |
535 | return ret; | |
536 | } | |
537 | ||
538 | static void dwc3_core_exit(struct dwc3 *dwc) | |
539 | { | |
0ffcaf37 | 540 | dwc3_free_scratch_buffers(dwc); |
01b8daf7 VG |
541 | usb_phy_shutdown(dwc->usb2_phy); |
542 | usb_phy_shutdown(dwc->usb3_phy); | |
57303488 KVA |
543 | phy_exit(dwc->usb2_generic_phy); |
544 | phy_exit(dwc->usb3_generic_phy); | |
72246da4 FB |
545 | } |
546 | ||
3c9f94ac | 547 | static int dwc3_core_get_phy(struct dwc3 *dwc) |
72246da4 | 548 | { |
3c9f94ac | 549 | struct device *dev = dwc->dev; |
941ea361 | 550 | struct device_node *node = dev->of_node; |
3c9f94ac | 551 | int ret; |
72246da4 | 552 | |
5088b6f5 KVA |
553 | if (node) { |
554 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
555 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
bb674907 FB |
556 | } else { |
557 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
558 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
5088b6f5 KVA |
559 | } |
560 | ||
d105e7f8 FB |
561 | if (IS_ERR(dwc->usb2_phy)) { |
562 | ret = PTR_ERR(dwc->usb2_phy); | |
122f06e6 KVA |
563 | if (ret == -ENXIO || ret == -ENODEV) { |
564 | dwc->usb2_phy = NULL; | |
565 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 566 | return ret; |
122f06e6 KVA |
567 | } else { |
568 | dev_err(dev, "no usb2 phy configured\n"); | |
569 | return ret; | |
570 | } | |
51e1e7bc FB |
571 | } |
572 | ||
d105e7f8 | 573 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 574 | ret = PTR_ERR(dwc->usb3_phy); |
122f06e6 KVA |
575 | if (ret == -ENXIO || ret == -ENODEV) { |
576 | dwc->usb3_phy = NULL; | |
577 | } else if (ret == -EPROBE_DEFER) { | |
d105e7f8 | 578 | return ret; |
122f06e6 KVA |
579 | } else { |
580 | dev_err(dev, "no usb3 phy configured\n"); | |
581 | return ret; | |
582 | } | |
51e1e7bc FB |
583 | } |
584 | ||
57303488 KVA |
585 | dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); |
586 | if (IS_ERR(dwc->usb2_generic_phy)) { | |
587 | ret = PTR_ERR(dwc->usb2_generic_phy); | |
588 | if (ret == -ENOSYS || ret == -ENODEV) { | |
589 | dwc->usb2_generic_phy = NULL; | |
590 | } else if (ret == -EPROBE_DEFER) { | |
591 | return ret; | |
592 | } else { | |
593 | dev_err(dev, "no usb2 phy configured\n"); | |
594 | return ret; | |
595 | } | |
596 | } | |
597 | ||
598 | dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); | |
599 | if (IS_ERR(dwc->usb3_generic_phy)) { | |
600 | ret = PTR_ERR(dwc->usb3_generic_phy); | |
601 | if (ret == -ENOSYS || ret == -ENODEV) { | |
602 | dwc->usb3_generic_phy = NULL; | |
603 | } else if (ret == -EPROBE_DEFER) { | |
604 | return ret; | |
605 | } else { | |
606 | dev_err(dev, "no usb3 phy configured\n"); | |
607 | return ret; | |
608 | } | |
609 | } | |
610 | ||
3c9f94ac FB |
611 | return 0; |
612 | } | |
613 | ||
5f94adfe FB |
614 | static int dwc3_core_init_mode(struct dwc3 *dwc) |
615 | { | |
616 | struct device *dev = dwc->dev; | |
617 | int ret; | |
618 | ||
619 | switch (dwc->dr_mode) { | |
620 | case USB_DR_MODE_PERIPHERAL: | |
621 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); | |
622 | ret = dwc3_gadget_init(dwc); | |
623 | if (ret) { | |
624 | dev_err(dev, "failed to initialize gadget\n"); | |
625 | return ret; | |
626 | } | |
627 | break; | |
628 | case USB_DR_MODE_HOST: | |
629 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); | |
630 | ret = dwc3_host_init(dwc); | |
631 | if (ret) { | |
632 | dev_err(dev, "failed to initialize host\n"); | |
633 | return ret; | |
634 | } | |
635 | break; | |
636 | case USB_DR_MODE_OTG: | |
637 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); | |
638 | ret = dwc3_host_init(dwc); | |
639 | if (ret) { | |
640 | dev_err(dev, "failed to initialize host\n"); | |
641 | return ret; | |
642 | } | |
643 | ||
644 | ret = dwc3_gadget_init(dwc); | |
645 | if (ret) { | |
646 | dev_err(dev, "failed to initialize gadget\n"); | |
647 | return ret; | |
648 | } | |
649 | break; | |
650 | default: | |
651 | dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); | |
652 | return -EINVAL; | |
653 | } | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
658 | static void dwc3_core_exit_mode(struct dwc3 *dwc) | |
659 | { | |
660 | switch (dwc->dr_mode) { | |
661 | case USB_DR_MODE_PERIPHERAL: | |
662 | dwc3_gadget_exit(dwc); | |
663 | break; | |
664 | case USB_DR_MODE_HOST: | |
665 | dwc3_host_exit(dwc); | |
666 | break; | |
667 | case USB_DR_MODE_OTG: | |
668 | dwc3_host_exit(dwc); | |
669 | dwc3_gadget_exit(dwc); | |
670 | break; | |
671 | default: | |
672 | /* do nothing */ | |
673 | break; | |
674 | } | |
675 | } | |
676 | ||
3c9f94ac FB |
677 | #define DWC3_ALIGN_MASK (16 - 1) |
678 | ||
679 | static int dwc3_probe(struct platform_device *pdev) | |
680 | { | |
681 | struct device *dev = &pdev->dev; | |
682 | struct dwc3_platform_data *pdata = dev_get_platdata(dev); | |
683 | struct device_node *node = dev->of_node; | |
684 | struct resource *res; | |
685 | struct dwc3 *dwc; | |
80caf7d2 | 686 | u8 lpm_nyet_threshold; |
3c9f94ac | 687 | |
b09e99ee | 688 | int ret; |
3c9f94ac FB |
689 | |
690 | void __iomem *regs; | |
691 | void *mem; | |
692 | ||
693 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); | |
734d5a53 | 694 | if (!mem) |
3c9f94ac | 695 | return -ENOMEM; |
734d5a53 | 696 | |
3c9f94ac FB |
697 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); |
698 | dwc->mem = mem; | |
699 | dwc->dev = dev; | |
700 | ||
701 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
702 | if (!res) { | |
703 | dev_err(dev, "missing IRQ\n"); | |
704 | return -ENODEV; | |
705 | } | |
706 | dwc->xhci_resources[1].start = res->start; | |
707 | dwc->xhci_resources[1].end = res->end; | |
708 | dwc->xhci_resources[1].flags = res->flags; | |
709 | dwc->xhci_resources[1].name = res->name; | |
710 | ||
711 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
712 | if (!res) { | |
713 | dev_err(dev, "missing memory resource\n"); | |
714 | return -ENODEV; | |
715 | } | |
716 | ||
f32a5e23 VG |
717 | dwc->xhci_resources[0].start = res->start; |
718 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + | |
719 | DWC3_XHCI_REGS_END; | |
720 | dwc->xhci_resources[0].flags = res->flags; | |
721 | dwc->xhci_resources[0].name = res->name; | |
722 | ||
723 | res->start += DWC3_GLOBALS_REGS_START; | |
724 | ||
725 | /* | |
726 | * Request memory region but exclude xHCI regs, | |
727 | * since it will be requested by the xhci-plat driver. | |
728 | */ | |
729 | regs = devm_ioremap_resource(dev, res); | |
730 | if (IS_ERR(regs)) | |
731 | return PTR_ERR(regs); | |
732 | ||
733 | dwc->regs = regs; | |
734 | dwc->regs_size = resource_size(res); | |
735 | /* | |
736 | * restore res->start back to its original value so that, | |
737 | * in case the probe is deferred, we don't end up getting error in | |
738 | * request the memory region the next time probe is called. | |
739 | */ | |
740 | res->start -= DWC3_GLOBALS_REGS_START; | |
741 | ||
80caf7d2 HR |
742 | /* default to highest possible threshold */ |
743 | lpm_nyet_threshold = 0xff; | |
744 | ||
3c9f94ac FB |
745 | if (node) { |
746 | dwc->maximum_speed = of_usb_get_maximum_speed(node); | |
80caf7d2 HR |
747 | dwc->has_lpm_erratum = of_property_read_bool(node, |
748 | "snps,has-lpm-erratum"); | |
749 | of_property_read_u8(node, "snps,lpm-nyet-threshold", | |
750 | &lpm_nyet_threshold); | |
3c9f94ac | 751 | |
80caf7d2 HR |
752 | dwc->needs_fifo_resize = of_property_read_bool(node, |
753 | "tx-fifo-resize"); | |
3c9f94ac | 754 | dwc->dr_mode = of_usb_get_dr_mode(node); |
3b81221a HR |
755 | |
756 | dwc->disable_scramble_quirk = of_property_read_bool(node, | |
757 | "snps,disable_scramble_quirk"); | |
9a5b2f31 HR |
758 | dwc->u2exit_lfps_quirk = of_property_read_bool(node, |
759 | "snps,u2exit_lfps_quirk"); | |
b5a65c40 HR |
760 | dwc->u2ss_inp3_quirk = of_property_read_bool(node, |
761 | "snps,u2ss_inp3_quirk"); | |
df31f5b3 HR |
762 | dwc->req_p1p2p3_quirk = of_property_read_bool(node, |
763 | "snps,req_p1p2p3_quirk"); | |
3c9f94ac FB |
764 | } else if (pdata) { |
765 | dwc->maximum_speed = pdata->maximum_speed; | |
80caf7d2 HR |
766 | dwc->has_lpm_erratum = pdata->has_lpm_erratum; |
767 | if (pdata->lpm_nyet_threshold) | |
768 | lpm_nyet_threshold = pdata->lpm_nyet_threshold; | |
3c9f94ac FB |
769 | |
770 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
771 | dwc->dr_mode = pdata->dr_mode; | |
3b81221a HR |
772 | |
773 | dwc->disable_scramble_quirk = pdata->disable_scramble_quirk; | |
9a5b2f31 | 774 | dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk; |
b5a65c40 | 775 | dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk; |
df31f5b3 | 776 | dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk; |
3c9f94ac FB |
777 | } |
778 | ||
779 | /* default to superspeed if no maximum_speed passed */ | |
780 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
781 | dwc->maximum_speed = USB_SPEED_SUPER; | |
782 | ||
80caf7d2 HR |
783 | dwc->lpm_nyet_threshold = lpm_nyet_threshold; |
784 | ||
3c9f94ac FB |
785 | ret = dwc3_core_get_phy(dwc); |
786 | if (ret) | |
787 | return ret; | |
788 | ||
72246da4 FB |
789 | spin_lock_init(&dwc->lock); |
790 | platform_set_drvdata(pdev, dwc); | |
791 | ||
19bacdc9 HK |
792 | if (!dev->dma_mask) { |
793 | dev->dma_mask = dev->parent->dma_mask; | |
794 | dev->dma_parms = dev->parent->dma_parms; | |
795 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
796 | } | |
ddff14f1 | 797 | |
802ca850 CP |
798 | pm_runtime_enable(dev); |
799 | pm_runtime_get_sync(dev); | |
800 | pm_runtime_forbid(dev); | |
72246da4 | 801 | |
4fd24483 KVA |
802 | dwc3_cache_hwparams(dwc); |
803 | ||
3921426b FB |
804 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
805 | if (ret) { | |
806 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
807 | ret = -ENOMEM; | |
808 | goto err0; | |
809 | } | |
810 | ||
32a4a135 FB |
811 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
812 | dwc->dr_mode = USB_DR_MODE_HOST; | |
813 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
814 | dwc->dr_mode = USB_DR_MODE_PERIPHERAL; | |
815 | ||
816 | if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) | |
817 | dwc->dr_mode = USB_DR_MODE_OTG; | |
818 | ||
72246da4 FB |
819 | ret = dwc3_core_init(dwc); |
820 | if (ret) { | |
802ca850 | 821 | dev_err(dev, "failed to initialize core\n"); |
3921426b | 822 | goto err0; |
72246da4 FB |
823 | } |
824 | ||
3088f108 KVA |
825 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
826 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
57303488 KVA |
827 | ret = phy_power_on(dwc->usb2_generic_phy); |
828 | if (ret < 0) | |
829 | goto err1; | |
830 | ||
831 | ret = phy_power_on(dwc->usb3_generic_phy); | |
832 | if (ret < 0) | |
833 | goto err_usb2phy_power; | |
3088f108 | 834 | |
f122d33e FB |
835 | ret = dwc3_event_buffers_setup(dwc); |
836 | if (ret) { | |
837 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
57303488 | 838 | goto err_usb3phy_power; |
f122d33e FB |
839 | } |
840 | ||
5f94adfe FB |
841 | ret = dwc3_core_init_mode(dwc); |
842 | if (ret) | |
f122d33e | 843 | goto err2; |
72246da4 FB |
844 | |
845 | ret = dwc3_debugfs_init(dwc); | |
846 | if (ret) { | |
802ca850 | 847 | dev_err(dev, "failed to initialize debugfs\n"); |
f122d33e | 848 | goto err3; |
72246da4 FB |
849 | } |
850 | ||
802ca850 | 851 | pm_runtime_allow(dev); |
72246da4 FB |
852 | |
853 | return 0; | |
854 | ||
f122d33e | 855 | err3: |
5f94adfe | 856 | dwc3_core_exit_mode(dwc); |
72246da4 | 857 | |
f122d33e FB |
858 | err2: |
859 | dwc3_event_buffers_cleanup(dwc); | |
860 | ||
57303488 KVA |
861 | err_usb3phy_power: |
862 | phy_power_off(dwc->usb3_generic_phy); | |
863 | ||
864 | err_usb2phy_power: | |
865 | phy_power_off(dwc->usb2_generic_phy); | |
866 | ||
72246da4 | 867 | err1: |
501fae51 KVA |
868 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
869 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
802ca850 | 870 | dwc3_core_exit(dwc); |
72246da4 | 871 | |
3921426b FB |
872 | err0: |
873 | dwc3_free_event_buffers(dwc); | |
874 | ||
72246da4 FB |
875 | return ret; |
876 | } | |
877 | ||
fb4e98ab | 878 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 879 | { |
72246da4 | 880 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
72246da4 | 881 | |
dc99f16f FB |
882 | dwc3_debugfs_exit(dwc); |
883 | dwc3_core_exit_mode(dwc); | |
884 | dwc3_event_buffers_cleanup(dwc); | |
885 | dwc3_free_event_buffers(dwc); | |
886 | ||
8ba007a9 KVA |
887 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
888 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
57303488 KVA |
889 | phy_power_off(dwc->usb2_generic_phy); |
890 | phy_power_off(dwc->usb3_generic_phy); | |
8ba007a9 | 891 | |
72246da4 | 892 | dwc3_core_exit(dwc); |
72246da4 | 893 | |
16b972a5 | 894 | pm_runtime_put_sync(&pdev->dev); |
72246da4 FB |
895 | pm_runtime_disable(&pdev->dev); |
896 | ||
72246da4 FB |
897 | return 0; |
898 | } | |
899 | ||
19fda7cd | 900 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
901 | static int dwc3_suspend(struct device *dev) |
902 | { | |
903 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
904 | unsigned long flags; | |
905 | ||
906 | spin_lock_irqsave(&dwc->lock, flags); | |
907 | ||
a45c82b8 RK |
908 | switch (dwc->dr_mode) { |
909 | case USB_DR_MODE_PERIPHERAL: | |
910 | case USB_DR_MODE_OTG: | |
7415f17c FB |
911 | dwc3_gadget_suspend(dwc); |
912 | /* FALLTHROUGH */ | |
a45c82b8 | 913 | case USB_DR_MODE_HOST: |
7415f17c | 914 | default: |
0b0231aa | 915 | dwc3_event_buffers_cleanup(dwc); |
7415f17c FB |
916 | break; |
917 | } | |
918 | ||
919 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
920 | spin_unlock_irqrestore(&dwc->lock, flags); | |
921 | ||
922 | usb_phy_shutdown(dwc->usb3_phy); | |
923 | usb_phy_shutdown(dwc->usb2_phy); | |
57303488 KVA |
924 | phy_exit(dwc->usb2_generic_phy); |
925 | phy_exit(dwc->usb3_generic_phy); | |
7415f17c FB |
926 | |
927 | return 0; | |
928 | } | |
929 | ||
930 | static int dwc3_resume(struct device *dev) | |
931 | { | |
932 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
933 | unsigned long flags; | |
57303488 | 934 | int ret; |
7415f17c FB |
935 | |
936 | usb_phy_init(dwc->usb3_phy); | |
937 | usb_phy_init(dwc->usb2_phy); | |
57303488 KVA |
938 | ret = phy_init(dwc->usb2_generic_phy); |
939 | if (ret < 0) | |
940 | return ret; | |
941 | ||
942 | ret = phy_init(dwc->usb3_generic_phy); | |
943 | if (ret < 0) | |
944 | goto err_usb2phy_init; | |
7415f17c FB |
945 | |
946 | spin_lock_irqsave(&dwc->lock, flags); | |
947 | ||
0b0231aa | 948 | dwc3_event_buffers_setup(dwc); |
7415f17c FB |
949 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); |
950 | ||
a45c82b8 RK |
951 | switch (dwc->dr_mode) { |
952 | case USB_DR_MODE_PERIPHERAL: | |
953 | case USB_DR_MODE_OTG: | |
7415f17c FB |
954 | dwc3_gadget_resume(dwc); |
955 | /* FALLTHROUGH */ | |
a45c82b8 | 956 | case USB_DR_MODE_HOST: |
7415f17c FB |
957 | default: |
958 | /* do nothing */ | |
959 | break; | |
960 | } | |
961 | ||
962 | spin_unlock_irqrestore(&dwc->lock, flags); | |
963 | ||
964 | pm_runtime_disable(dev); | |
965 | pm_runtime_set_active(dev); | |
966 | pm_runtime_enable(dev); | |
967 | ||
968 | return 0; | |
57303488 KVA |
969 | |
970 | err_usb2phy_init: | |
971 | phy_exit(dwc->usb2_generic_phy); | |
972 | ||
973 | return ret; | |
7415f17c FB |
974 | } |
975 | ||
976 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
7415f17c FB |
977 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) |
978 | }; | |
979 | ||
980 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
981 | #else | |
982 | #define DWC3_PM_OPS NULL | |
983 | #endif | |
984 | ||
5088b6f5 KVA |
985 | #ifdef CONFIG_OF |
986 | static const struct of_device_id of_dwc3_match[] = { | |
22a5aa17 FB |
987 | { |
988 | .compatible = "snps,dwc3" | |
989 | }, | |
5088b6f5 KVA |
990 | { |
991 | .compatible = "synopsys,dwc3" | |
992 | }, | |
993 | { }, | |
994 | }; | |
995 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
996 | #endif | |
997 | ||
404905a6 HK |
998 | #ifdef CONFIG_ACPI |
999 | ||
1000 | #define ACPI_ID_INTEL_BSW "808622B7" | |
1001 | ||
1002 | static const struct acpi_device_id dwc3_acpi_match[] = { | |
1003 | { ACPI_ID_INTEL_BSW, 0 }, | |
1004 | { }, | |
1005 | }; | |
1006 | MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); | |
1007 | #endif | |
1008 | ||
72246da4 FB |
1009 | static struct platform_driver dwc3_driver = { |
1010 | .probe = dwc3_probe, | |
7690417d | 1011 | .remove = dwc3_remove, |
72246da4 FB |
1012 | .driver = { |
1013 | .name = "dwc3", | |
5088b6f5 | 1014 | .of_match_table = of_match_ptr(of_dwc3_match), |
404905a6 | 1015 | .acpi_match_table = ACPI_PTR(dwc3_acpi_match), |
7415f17c | 1016 | .pm = DWC3_PM_OPS, |
72246da4 | 1017 | }, |
72246da4 FB |
1018 | }; |
1019 | ||
b1116dcc TK |
1020 | module_platform_driver(dwc3_driver); |
1021 | ||
7ae4fc4d | 1022 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 1023 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 1024 | MODULE_LICENSE("GPL v2"); |
72246da4 | 1025 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |