Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
a72e658b | 22 | #include <linux/module.h> |
72246da4 FB |
23 | #include <linux/kernel.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
457e84b6 | 34 | #include <linux/of.h> |
72246da4 | 35 | |
51e1e7bc | 36 | #include <linux/usb/otg.h> |
72246da4 FB |
37 | #include <linux/usb/ch9.h> |
38 | #include <linux/usb/gadget.h> | |
f7e846f0 | 39 | #include <linux/usb/of.h> |
72246da4 | 40 | |
6462cbd5 | 41 | #include "platform_data.h" |
72246da4 FB |
42 | #include "core.h" |
43 | #include "gadget.h" | |
44 | #include "io.h" | |
45 | ||
46 | #include "debug.h" | |
47 | ||
8300dd23 FB |
48 | /* -------------------------------------------------------------------------- */ |
49 | ||
3140e8cb SAS |
50 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
51 | { | |
52 | u32 reg; | |
53 | ||
54 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
55 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
56 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
57 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
58 | } | |
8300dd23 | 59 | |
72246da4 FB |
60 | /** |
61 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
62 | * @dwc: pointer to our context structure | |
63 | */ | |
64 | static void dwc3_core_soft_reset(struct dwc3 *dwc) | |
65 | { | |
66 | u32 reg; | |
67 | ||
68 | /* Before Resetting PHY, put Core in Reset */ | |
69 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
70 | reg |= DWC3_GCTL_CORESOFTRESET; | |
71 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
72 | ||
73 | /* Assert USB3 PHY reset */ | |
74 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
75 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
76 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
77 | ||
78 | /* Assert USB2 PHY reset */ | |
79 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
80 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
81 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
82 | ||
51e1e7bc FB |
83 | usb_phy_init(dwc->usb2_phy); |
84 | usb_phy_init(dwc->usb3_phy); | |
72246da4 FB |
85 | mdelay(100); |
86 | ||
87 | /* Clear USB3 PHY reset */ | |
88 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
89 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
90 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
91 | ||
92 | /* Clear USB2 PHY reset */ | |
93 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
94 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
95 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
96 | ||
45627ac6 PA |
97 | mdelay(100); |
98 | ||
72246da4 FB |
99 | /* After PHYs are stable we can take Core out of reset state */ |
100 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
101 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
102 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
103 | } | |
104 | ||
105 | /** | |
106 | * dwc3_free_one_event_buffer - Frees one event buffer | |
107 | * @dwc: Pointer to our controller context structure | |
108 | * @evt: Pointer to event buffer to be freed | |
109 | */ | |
110 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
111 | struct dwc3_event_buffer *evt) | |
112 | { | |
113 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
114 | } |
115 | ||
116 | /** | |
1d046793 | 117 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
118 | * @dwc: Pointer to our controller context structure |
119 | * @length: size of the event buffer | |
120 | * | |
1d046793 | 121 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
122 | * otherwise ERR_PTR(errno). |
123 | */ | |
67d0b500 FB |
124 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
125 | unsigned length) | |
72246da4 FB |
126 | { |
127 | struct dwc3_event_buffer *evt; | |
128 | ||
380f0d28 | 129 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
130 | if (!evt) |
131 | return ERR_PTR(-ENOMEM); | |
132 | ||
133 | evt->dwc = dwc; | |
134 | evt->length = length; | |
135 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
136 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 137 | if (!evt->buf) |
72246da4 | 138 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
139 | |
140 | return evt; | |
141 | } | |
142 | ||
143 | /** | |
144 | * dwc3_free_event_buffers - frees all allocated event buffers | |
145 | * @dwc: Pointer to our controller context structure | |
146 | */ | |
147 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
148 | { | |
149 | struct dwc3_event_buffer *evt; | |
150 | int i; | |
151 | ||
9f622b2a | 152 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 153 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 154 | if (evt) |
72246da4 | 155 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
156 | } |
157 | } | |
158 | ||
159 | /** | |
160 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 161 | * @dwc: pointer to our controller context structure |
72246da4 FB |
162 | * @length: size of event buffer |
163 | * | |
1d046793 | 164 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
165 | * may contain some buffers allocated but not all which were requested. |
166 | */ | |
41ac7b3a | 167 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 168 | { |
9f622b2a | 169 | int num; |
72246da4 FB |
170 | int i; |
171 | ||
9f622b2a FB |
172 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
173 | dwc->num_event_buffers = num; | |
174 | ||
380f0d28 FB |
175 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
176 | GFP_KERNEL); | |
457d3f21 FB |
177 | if (!dwc->ev_buffs) { |
178 | dev_err(dwc->dev, "can't allocate event buffers array\n"); | |
179 | return -ENOMEM; | |
180 | } | |
181 | ||
72246da4 FB |
182 | for (i = 0; i < num; i++) { |
183 | struct dwc3_event_buffer *evt; | |
184 | ||
185 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
186 | if (IS_ERR(evt)) { | |
187 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
188 | return PTR_ERR(evt); | |
189 | } | |
190 | dwc->ev_buffs[i] = evt; | |
191 | } | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | /** | |
197 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 198 | * @dwc: pointer to our controller context structure |
72246da4 FB |
199 | * |
200 | * Returns 0 on success otherwise negative errno. | |
201 | */ | |
7acd85e0 | 202 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
203 | { |
204 | struct dwc3_event_buffer *evt; | |
205 | int n; | |
206 | ||
9f622b2a | 207 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
208 | evt = dwc->ev_buffs[n]; |
209 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
210 | evt->buf, (unsigned long long) evt->dma, | |
211 | evt->length); | |
212 | ||
7acd85e0 PZ |
213 | evt->lpos = 0; |
214 | ||
72246da4 FB |
215 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
216 | lower_32_bits(evt->dma)); | |
217 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
218 | upper_32_bits(evt->dma)); | |
219 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
220 | evt->length & 0xffff); | |
221 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
222 | } | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
228 | { | |
229 | struct dwc3_event_buffer *evt; | |
230 | int n; | |
231 | ||
9f622b2a | 232 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 233 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
234 | |
235 | evt->lpos = 0; | |
236 | ||
72246da4 FB |
237 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
238 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
239 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0); | |
240 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
241 | } | |
242 | } | |
243 | ||
789451f6 FB |
244 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
245 | { | |
246 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
247 | ||
248 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
249 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
250 | ||
251 | dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", | |
252 | dwc->num_in_eps, dwc->num_out_eps); | |
253 | } | |
254 | ||
41ac7b3a | 255 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
256 | { |
257 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
258 | ||
259 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
260 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
261 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
262 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
263 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
264 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
265 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
266 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
267 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
268 | } | |
269 | ||
72246da4 FB |
270 | /** |
271 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
272 | * @dwc: Pointer to our controller context structure | |
273 | * | |
274 | * Returns 0 on success otherwise negative errno. | |
275 | */ | |
41ac7b3a | 276 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 FB |
277 | { |
278 | unsigned long timeout; | |
279 | u32 reg; | |
280 | int ret; | |
281 | ||
7650bd74 SAS |
282 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
283 | /* This should read as U3 followed by revision number */ | |
284 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
285 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
286 | ret = -ENODEV; | |
287 | goto err0; | |
288 | } | |
248b122b | 289 | dwc->revision = reg; |
7650bd74 | 290 | |
72246da4 FB |
291 | /* issue device SoftReset too */ |
292 | timeout = jiffies + msecs_to_jiffies(500); | |
293 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
294 | do { | |
295 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
296 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
297 | break; | |
298 | ||
299 | if (time_after(jiffies, timeout)) { | |
300 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
301 | ret = -ETIMEDOUT; | |
302 | goto err0; | |
303 | } | |
304 | ||
305 | cpu_relax(); | |
306 | } while (true); | |
307 | ||
58a0f23f PA |
308 | dwc3_core_soft_reset(dwc); |
309 | ||
4878a028 | 310 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 311 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 SAS |
312 | reg &= ~DWC3_GCTL_DISSCRAMBLE; |
313 | ||
164d7731 | 314 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 SAS |
315 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
316 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
317 | break; | |
318 | default: | |
319 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
320 | } | |
321 | ||
322 | /* | |
323 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 324 | * where the device can fail to connect at SuperSpeed |
4878a028 | 325 | * and falls back to high-speed mode which causes |
1d046793 | 326 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
327 | */ |
328 | if (dwc->revision < DWC3_REVISION_190A) | |
329 | reg |= DWC3_GCTL_U2RSTECN; | |
330 | ||
789451f6 FB |
331 | dwc3_core_num_eps(dwc); |
332 | ||
4878a028 SAS |
333 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
334 | ||
72246da4 FB |
335 | return 0; |
336 | ||
72246da4 FB |
337 | err0: |
338 | return ret; | |
339 | } | |
340 | ||
341 | static void dwc3_core_exit(struct dwc3 *dwc) | |
342 | { | |
01b8daf7 VG |
343 | usb_phy_shutdown(dwc->usb2_phy); |
344 | usb_phy_shutdown(dwc->usb3_phy); | |
72246da4 FB |
345 | } |
346 | ||
347 | #define DWC3_ALIGN_MASK (16 - 1) | |
348 | ||
41ac7b3a | 349 | static int dwc3_probe(struct platform_device *pdev) |
72246da4 | 350 | { |
6462cbd5 | 351 | struct dwc3_platform_data *pdata = pdev->dev.platform_data; |
457e84b6 | 352 | struct device_node *node = pdev->dev.of_node; |
72246da4 FB |
353 | struct resource *res; |
354 | struct dwc3 *dwc; | |
802ca850 | 355 | struct device *dev = &pdev->dev; |
0949e99b | 356 | |
72246da4 | 357 | int ret = -ENOMEM; |
0949e99b FB |
358 | |
359 | void __iomem *regs; | |
72246da4 FB |
360 | void *mem; |
361 | ||
0949e99b FB |
362 | u8 mode; |
363 | ||
802ca850 | 364 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); |
72246da4 | 365 | if (!mem) { |
802ca850 CP |
366 | dev_err(dev, "not enough memory\n"); |
367 | return -ENOMEM; | |
72246da4 FB |
368 | } |
369 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); | |
370 | dwc->mem = mem; | |
371 | ||
51249dca | 372 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
72246da4 | 373 | if (!res) { |
51249dca | 374 | dev_err(dev, "missing IRQ\n"); |
802ca850 | 375 | return -ENODEV; |
72246da4 | 376 | } |
066618bc KVA |
377 | dwc->xhci_resources[1].start = res->start; |
378 | dwc->xhci_resources[1].end = res->end; | |
379 | dwc->xhci_resources[1].flags = res->flags; | |
380 | dwc->xhci_resources[1].name = res->name; | |
72246da4 | 381 | |
51249dca IS |
382 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
383 | if (!res) { | |
384 | dev_err(dev, "missing memory resource\n"); | |
385 | return -ENODEV; | |
386 | } | |
066618bc | 387 | dwc->xhci_resources[0].start = res->start; |
51249dca IS |
388 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + |
389 | DWC3_XHCI_REGS_END; | |
066618bc KVA |
390 | dwc->xhci_resources[0].flags = res->flags; |
391 | dwc->xhci_resources[0].name = res->name; | |
51249dca IS |
392 | |
393 | /* | |
394 | * Request memory region but exclude xHCI regs, | |
395 | * since it will be requested by the xhci-plat driver. | |
396 | */ | |
397 | res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START, | |
398 | resource_size(res) - DWC3_GLOBALS_REGS_START, | |
802ca850 | 399 | dev_name(dev)); |
72246da4 | 400 | if (!res) { |
802ca850 CP |
401 | dev_err(dev, "can't request mem region\n"); |
402 | return -ENOMEM; | |
72246da4 FB |
403 | } |
404 | ||
b7e38aa6 | 405 | regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); |
72246da4 | 406 | if (!regs) { |
802ca850 CP |
407 | dev_err(dev, "ioremap failed\n"); |
408 | return -ENOMEM; | |
72246da4 FB |
409 | } |
410 | ||
5088b6f5 | 411 | if (node) { |
f7e846f0 FB |
412 | dwc->maximum_speed = of_usb_get_maximum_speed(node); |
413 | ||
5088b6f5 KVA |
414 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); |
415 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
6462cbd5 FB |
416 | |
417 | dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize"); | |
5088b6f5 | 418 | } else { |
f7e846f0 FB |
419 | dwc->maximum_speed = pdata->maximum_speed; |
420 | ||
5088b6f5 KVA |
421 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); |
422 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
6462cbd5 FB |
423 | |
424 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
5088b6f5 KVA |
425 | } |
426 | ||
f7e846f0 FB |
427 | /* default to superspeed if no maximum_speed passed */ |
428 | if (dwc->maximum_speed == USB_SPEED_UNKNOWN) | |
429 | dwc->maximum_speed = USB_SPEED_SUPER; | |
430 | ||
d105e7f8 FB |
431 | if (IS_ERR(dwc->usb2_phy)) { |
432 | ret = PTR_ERR(dwc->usb2_phy); | |
433 | ||
434 | /* | |
435 | * if -ENXIO is returned, it means PHY layer wasn't | |
436 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
437 | * in that case, since no PHY driver will ever probe. | |
438 | */ | |
439 | if (ret == -ENXIO) | |
440 | return ret; | |
441 | ||
51e1e7bc FB |
442 | dev_err(dev, "no usb2 phy configured\n"); |
443 | return -EPROBE_DEFER; | |
444 | } | |
445 | ||
d105e7f8 | 446 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 447 | ret = PTR_ERR(dwc->usb3_phy); |
d105e7f8 FB |
448 | |
449 | /* | |
450 | * if -ENXIO is returned, it means PHY layer wasn't | |
451 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
452 | * in that case, since no PHY driver will ever probe. | |
453 | */ | |
454 | if (ret == -ENXIO) | |
455 | return ret; | |
456 | ||
51e1e7bc FB |
457 | dev_err(dev, "no usb3 phy configured\n"); |
458 | return -EPROBE_DEFER; | |
459 | } | |
460 | ||
8ba007a9 KVA |
461 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
462 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
463 | ||
72246da4 FB |
464 | spin_lock_init(&dwc->lock); |
465 | platform_set_drvdata(pdev, dwc); | |
466 | ||
467 | dwc->regs = regs; | |
468 | dwc->regs_size = resource_size(res); | |
802ca850 | 469 | dwc->dev = dev; |
72246da4 | 470 | |
ddff14f1 KVA |
471 | dev->dma_mask = dev->parent->dma_mask; |
472 | dev->dma_parms = dev->parent->dma_parms; | |
473 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
474 | ||
802ca850 CP |
475 | pm_runtime_enable(dev); |
476 | pm_runtime_get_sync(dev); | |
477 | pm_runtime_forbid(dev); | |
72246da4 | 478 | |
4fd24483 KVA |
479 | dwc3_cache_hwparams(dwc); |
480 | ||
3921426b FB |
481 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
482 | if (ret) { | |
483 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
484 | ret = -ENOMEM; | |
485 | goto err0; | |
486 | } | |
487 | ||
72246da4 FB |
488 | ret = dwc3_core_init(dwc); |
489 | if (ret) { | |
802ca850 | 490 | dev_err(dev, "failed to initialize core\n"); |
3921426b | 491 | goto err0; |
72246da4 FB |
492 | } |
493 | ||
f122d33e FB |
494 | ret = dwc3_event_buffers_setup(dwc); |
495 | if (ret) { | |
496 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
497 | goto err1; | |
498 | } | |
499 | ||
cd051da2 VG |
500 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
501 | mode = DWC3_MODE_HOST; | |
502 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
503 | mode = DWC3_MODE_DEVICE; | |
504 | else | |
505 | mode = DWC3_MODE_DRD; | |
0949e99b FB |
506 | |
507 | switch (mode) { | |
0949e99b | 508 | case DWC3_MODE_DEVICE: |
3140e8cb | 509 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
72246da4 FB |
510 | ret = dwc3_gadget_init(dwc); |
511 | if (ret) { | |
802ca850 | 512 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 513 | goto err2; |
72246da4 | 514 | } |
d07e8819 FB |
515 | break; |
516 | case DWC3_MODE_HOST: | |
3140e8cb | 517 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); |
d07e8819 FB |
518 | ret = dwc3_host_init(dwc); |
519 | if (ret) { | |
802ca850 | 520 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 521 | goto err2; |
d07e8819 FB |
522 | } |
523 | break; | |
524 | case DWC3_MODE_DRD: | |
3140e8cb | 525 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); |
d07e8819 FB |
526 | ret = dwc3_host_init(dwc); |
527 | if (ret) { | |
802ca850 | 528 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 529 | goto err2; |
d07e8819 FB |
530 | } |
531 | ||
72246da4 FB |
532 | ret = dwc3_gadget_init(dwc); |
533 | if (ret) { | |
802ca850 | 534 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 535 | goto err2; |
72246da4 | 536 | } |
0949e99b FB |
537 | break; |
538 | default: | |
802ca850 | 539 | dev_err(dev, "Unsupported mode of operation %d\n", mode); |
f122d33e | 540 | goto err2; |
72246da4 | 541 | } |
0949e99b | 542 | dwc->mode = mode; |
72246da4 FB |
543 | |
544 | ret = dwc3_debugfs_init(dwc); | |
545 | if (ret) { | |
802ca850 | 546 | dev_err(dev, "failed to initialize debugfs\n"); |
f122d33e | 547 | goto err3; |
72246da4 FB |
548 | } |
549 | ||
802ca850 | 550 | pm_runtime_allow(dev); |
72246da4 FB |
551 | |
552 | return 0; | |
553 | ||
f122d33e | 554 | err3: |
0949e99b | 555 | switch (mode) { |
0949e99b | 556 | case DWC3_MODE_DEVICE: |
72246da4 | 557 | dwc3_gadget_exit(dwc); |
0949e99b | 558 | break; |
d07e8819 FB |
559 | case DWC3_MODE_HOST: |
560 | dwc3_host_exit(dwc); | |
561 | break; | |
562 | case DWC3_MODE_DRD: | |
563 | dwc3_host_exit(dwc); | |
72246da4 | 564 | dwc3_gadget_exit(dwc); |
d07e8819 | 565 | break; |
0949e99b FB |
566 | default: |
567 | /* do nothing */ | |
568 | break; | |
569 | } | |
72246da4 | 570 | |
f122d33e FB |
571 | err2: |
572 | dwc3_event_buffers_cleanup(dwc); | |
573 | ||
72246da4 | 574 | err1: |
802ca850 | 575 | dwc3_core_exit(dwc); |
72246da4 | 576 | |
3921426b FB |
577 | err0: |
578 | dwc3_free_event_buffers(dwc); | |
579 | ||
72246da4 FB |
580 | return ret; |
581 | } | |
582 | ||
fb4e98ab | 583 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 584 | { |
72246da4 | 585 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
72246da4 | 586 | |
8ba007a9 KVA |
587 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
588 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
589 | ||
72246da4 FB |
590 | pm_runtime_put(&pdev->dev); |
591 | pm_runtime_disable(&pdev->dev); | |
592 | ||
593 | dwc3_debugfs_exit(dwc); | |
594 | ||
0949e99b | 595 | switch (dwc->mode) { |
0949e99b | 596 | case DWC3_MODE_DEVICE: |
72246da4 | 597 | dwc3_gadget_exit(dwc); |
0949e99b | 598 | break; |
d07e8819 FB |
599 | case DWC3_MODE_HOST: |
600 | dwc3_host_exit(dwc); | |
601 | break; | |
602 | case DWC3_MODE_DRD: | |
603 | dwc3_host_exit(dwc); | |
72246da4 | 604 | dwc3_gadget_exit(dwc); |
d07e8819 | 605 | break; |
0949e99b FB |
606 | default: |
607 | /* do nothing */ | |
608 | break; | |
609 | } | |
72246da4 | 610 | |
f122d33e | 611 | dwc3_event_buffers_cleanup(dwc); |
d9b4330a | 612 | dwc3_free_event_buffers(dwc); |
72246da4 | 613 | dwc3_core_exit(dwc); |
72246da4 FB |
614 | |
615 | return 0; | |
616 | } | |
617 | ||
19fda7cd | 618 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
619 | static int dwc3_prepare(struct device *dev) |
620 | { | |
621 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
622 | unsigned long flags; | |
623 | ||
624 | spin_lock_irqsave(&dwc->lock, flags); | |
625 | ||
626 | switch (dwc->mode) { | |
627 | case DWC3_MODE_DEVICE: | |
628 | case DWC3_MODE_DRD: | |
629 | dwc3_gadget_prepare(dwc); | |
630 | /* FALLTHROUGH */ | |
631 | case DWC3_MODE_HOST: | |
632 | default: | |
633 | dwc3_event_buffers_cleanup(dwc); | |
634 | break; | |
635 | } | |
636 | ||
637 | spin_unlock_irqrestore(&dwc->lock, flags); | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
642 | static void dwc3_complete(struct device *dev) | |
643 | { | |
644 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
645 | unsigned long flags; | |
646 | ||
647 | spin_lock_irqsave(&dwc->lock, flags); | |
648 | ||
649 | switch (dwc->mode) { | |
650 | case DWC3_MODE_DEVICE: | |
651 | case DWC3_MODE_DRD: | |
652 | dwc3_gadget_complete(dwc); | |
653 | /* FALLTHROUGH */ | |
654 | case DWC3_MODE_HOST: | |
655 | default: | |
656 | dwc3_event_buffers_setup(dwc); | |
657 | break; | |
658 | } | |
659 | ||
660 | spin_unlock_irqrestore(&dwc->lock, flags); | |
661 | } | |
662 | ||
663 | static int dwc3_suspend(struct device *dev) | |
664 | { | |
665 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
666 | unsigned long flags; | |
667 | ||
668 | spin_lock_irqsave(&dwc->lock, flags); | |
669 | ||
670 | switch (dwc->mode) { | |
671 | case DWC3_MODE_DEVICE: | |
672 | case DWC3_MODE_DRD: | |
673 | dwc3_gadget_suspend(dwc); | |
674 | /* FALLTHROUGH */ | |
675 | case DWC3_MODE_HOST: | |
676 | default: | |
677 | /* do nothing */ | |
678 | break; | |
679 | } | |
680 | ||
681 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
682 | spin_unlock_irqrestore(&dwc->lock, flags); | |
683 | ||
684 | usb_phy_shutdown(dwc->usb3_phy); | |
685 | usb_phy_shutdown(dwc->usb2_phy); | |
686 | ||
687 | return 0; | |
688 | } | |
689 | ||
690 | static int dwc3_resume(struct device *dev) | |
691 | { | |
692 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
693 | unsigned long flags; | |
694 | ||
695 | usb_phy_init(dwc->usb3_phy); | |
696 | usb_phy_init(dwc->usb2_phy); | |
697 | msleep(100); | |
698 | ||
699 | spin_lock_irqsave(&dwc->lock, flags); | |
700 | ||
701 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); | |
702 | ||
703 | switch (dwc->mode) { | |
704 | case DWC3_MODE_DEVICE: | |
705 | case DWC3_MODE_DRD: | |
706 | dwc3_gadget_resume(dwc); | |
707 | /* FALLTHROUGH */ | |
708 | case DWC3_MODE_HOST: | |
709 | default: | |
710 | /* do nothing */ | |
711 | break; | |
712 | } | |
713 | ||
714 | spin_unlock_irqrestore(&dwc->lock, flags); | |
715 | ||
716 | pm_runtime_disable(dev); | |
717 | pm_runtime_set_active(dev); | |
718 | pm_runtime_enable(dev); | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
724 | .prepare = dwc3_prepare, | |
725 | .complete = dwc3_complete, | |
726 | ||
727 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) | |
728 | }; | |
729 | ||
730 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
731 | #else | |
732 | #define DWC3_PM_OPS NULL | |
733 | #endif | |
734 | ||
5088b6f5 KVA |
735 | #ifdef CONFIG_OF |
736 | static const struct of_device_id of_dwc3_match[] = { | |
737 | { | |
738 | .compatible = "synopsys,dwc3" | |
739 | }, | |
740 | { }, | |
741 | }; | |
742 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
743 | #endif | |
744 | ||
72246da4 FB |
745 | static struct platform_driver dwc3_driver = { |
746 | .probe = dwc3_probe, | |
7690417d | 747 | .remove = dwc3_remove, |
72246da4 FB |
748 | .driver = { |
749 | .name = "dwc3", | |
5088b6f5 | 750 | .of_match_table = of_match_ptr(of_dwc3_match), |
7415f17c | 751 | .pm = DWC3_PM_OPS, |
72246da4 | 752 | }, |
72246da4 FB |
753 | }; |
754 | ||
b1116dcc TK |
755 | module_platform_driver(dwc3_driver); |
756 | ||
7ae4fc4d | 757 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 758 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 759 | MODULE_LICENSE("GPL v2"); |
72246da4 | 760 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |