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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/pm_runtime.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | ||
49 | #include <linux/usb/ch9.h> | |
50 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 51 | #include <linux/usb/composite.h> |
72246da4 FB |
52 | |
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
5bdb1dcc SAS |
57 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum); |
58 | ||
72246da4 FB |
59 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) |
60 | { | |
61 | switch (state) { | |
62 | case EP0_UNCONNECTED: | |
63 | return "Unconnected"; | |
c7fcdeb2 FB |
64 | case EP0_SETUP_PHASE: |
65 | return "Setup Phase"; | |
66 | case EP0_DATA_PHASE: | |
67 | return "Data Phase"; | |
68 | case EP0_STATUS_PHASE: | |
69 | return "Status Phase"; | |
72246da4 FB |
70 | default: |
71 | return "UNKNOWN"; | |
72 | } | |
73 | } | |
74 | ||
75 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 76 | u32 len, u32 type) |
72246da4 FB |
77 | { |
78 | struct dwc3_gadget_ep_cmd_params params; | |
79 | struct dwc3_trb_hw *trb_hw; | |
80 | struct dwc3_trb trb; | |
81 | struct dwc3_ep *dep; | |
82 | ||
83 | int ret; | |
84 | ||
85 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
86 | if (dep->flags & DWC3_EP_BUSY) { |
87 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
88 | return 0; | |
89 | } | |
72246da4 FB |
90 | |
91 | trb_hw = dwc->ep0_trb; | |
92 | memset(&trb, 0, sizeof(trb)); | |
93 | ||
c7fcdeb2 | 94 | trb.trbctl = type; |
72246da4 FB |
95 | trb.bplh = buf_dma; |
96 | trb.length = len; | |
97 | ||
98 | trb.hwo = 1; | |
99 | trb.lst = 1; | |
100 | trb.ioc = 1; | |
101 | trb.isp_imi = 1; | |
102 | ||
103 | dwc3_trb_to_hw(&trb, trb_hw); | |
104 | ||
105 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
106 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
107 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
108 | |
109 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
110 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
111 | if (ret < 0) { | |
112 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
113 | return ret; | |
114 | } | |
115 | ||
c7fcdeb2 | 116 | dep->flags |= DWC3_EP_BUSY; |
72246da4 FB |
117 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, |
118 | dep->number); | |
119 | ||
1ddcb218 FB |
120 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
121 | ||
72246da4 FB |
122 | return 0; |
123 | } | |
124 | ||
125 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
126 | struct dwc3_request *req) | |
127 | { | |
5bdb1dcc SAS |
128 | struct dwc3 *dwc = dep->dwc; |
129 | u32 type; | |
c7fcdeb2 | 130 | int ret = 0; |
72246da4 FB |
131 | |
132 | req->request.actual = 0; | |
133 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
134 | req->epnum = dep->number; |
135 | ||
136 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 137 | |
c7fcdeb2 FB |
138 | /* |
139 | * Gadget driver might not be quick enough to queue a request | |
140 | * before we get a Transfer Not Ready event on this endpoint. | |
141 | * | |
142 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
143 | * flag is set, it's telling us that as soon as Gadget queues the | |
144 | * required request, we should kick the transfer here because the | |
145 | * IRQ we were waiting for is long gone. | |
146 | */ | |
147 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 148 | unsigned direction; |
c7fcdeb2 FB |
149 | |
150 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
151 | ||
152 | if (dwc->ep0state == EP0_STATUS_PHASE) { | |
153 | type = dwc->three_stage_setup | |
154 | ? DWC3_TRBCTL_CONTROL_STATUS3 | |
155 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
156 | } else if (dwc->ep0state == EP0_DATA_PHASE) { | |
157 | type = DWC3_TRBCTL_CONTROL_DATA; | |
158 | } else { | |
159 | /* should never happen */ | |
160 | WARN_ON(1); | |
161 | return 0; | |
162 | } | |
72246da4 | 163 | |
c7fcdeb2 FB |
164 | ret = dwc3_ep0_start_trans(dwc, direction, |
165 | req->request.dma, req->request.length, type); | |
166 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | | |
167 | DWC3_EP0_DIR_IN); | |
5bdb1dcc SAS |
168 | |
169 | } else if (dwc->delayed_status && (dwc->ep0state == EP0_STATUS_PHASE)) { | |
170 | dwc->delayed_status = false; | |
171 | dwc3_ep0_do_control_status(dwc, 1); | |
72246da4 FB |
172 | } |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
177 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
178 | gfp_t gfp_flags) | |
179 | { | |
180 | struct dwc3_request *req = to_dwc3_request(request); | |
181 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
182 | struct dwc3 *dwc = dep->dwc; | |
183 | ||
184 | unsigned long flags; | |
185 | ||
186 | int ret; | |
187 | ||
72246da4 FB |
188 | spin_lock_irqsave(&dwc->lock, flags); |
189 | if (!dep->desc) { | |
190 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", | |
191 | request, dep->name); | |
192 | ret = -ESHUTDOWN; | |
193 | goto out; | |
194 | } | |
195 | ||
196 | /* we share one TRB for ep0/1 */ | |
c2da2ff0 | 197 | if (!list_empty(&dep->request_list)) { |
72246da4 FB |
198 | ret = -EBUSY; |
199 | goto out; | |
200 | } | |
201 | ||
202 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
203 | request, dep->name, request->length, | |
204 | dwc3_ep0_state_string(dwc->ep0state)); | |
205 | ||
206 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
207 | ||
208 | out: | |
209 | spin_unlock_irqrestore(&dwc->lock, flags); | |
210 | ||
211 | return ret; | |
212 | } | |
213 | ||
214 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
215 | { | |
d742220b FB |
216 | struct dwc3_ep *dep = dwc->eps[0]; |
217 | ||
72246da4 | 218 | /* stall is always issued on EP0 */ |
c2da2ff0 SAS |
219 | __dwc3_gadget_ep_set_halt(dep, 1); |
220 | dep->flags = DWC3_EP_ENABLED; | |
5bdb1dcc | 221 | dwc->delayed_status = false; |
d742220b FB |
222 | |
223 | if (!list_empty(&dep->request_list)) { | |
224 | struct dwc3_request *req; | |
225 | ||
226 | req = next_request(&dep->request_list); | |
227 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
228 | } | |
229 | ||
c7fcdeb2 | 230 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
231 | dwc3_ep0_out_start(dwc); |
232 | } | |
233 | ||
234 | void dwc3_ep0_out_start(struct dwc3 *dwc) | |
235 | { | |
72246da4 FB |
236 | int ret; |
237 | ||
c7fcdeb2 FB |
238 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
239 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
240 | WARN_ON(ret < 0); |
241 | } | |
242 | ||
72246da4 FB |
243 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
244 | { | |
245 | struct dwc3_ep *dep; | |
246 | u32 windex = le16_to_cpu(wIndex_le); | |
247 | u32 epnum; | |
248 | ||
249 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
250 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
251 | epnum |= 1; | |
252 | ||
253 | dep = dwc->eps[epnum]; | |
254 | if (dep->flags & DWC3_EP_ENABLED) | |
255 | return dep; | |
256 | ||
257 | return NULL; | |
258 | } | |
259 | ||
8ee6270c | 260 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 261 | { |
72246da4 | 262 | } |
72246da4 FB |
263 | /* |
264 | * ch 9.4.5 | |
265 | */ | |
25b8ff68 FB |
266 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
267 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
268 | { |
269 | struct dwc3_ep *dep; | |
270 | u32 recip; | |
271 | u16 usb_status = 0; | |
272 | __le16 *response_pkt; | |
273 | ||
274 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
275 | switch (recip) { | |
276 | case USB_RECIP_DEVICE: | |
277 | /* | |
278 | * We are self-powered. U1/U2/LTM will be set later | |
279 | * once we handle this states. RemoteWakeup is 0 on SS | |
280 | */ | |
281 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
282 | break; | |
283 | ||
284 | case USB_RECIP_INTERFACE: | |
285 | /* | |
286 | * Function Remote Wake Capable D0 | |
287 | * Function Remote Wakeup D1 | |
288 | */ | |
289 | break; | |
290 | ||
291 | case USB_RECIP_ENDPOINT: | |
292 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
293 | if (!dep) | |
25b8ff68 | 294 | return -EINVAL; |
72246da4 FB |
295 | |
296 | if (dep->flags & DWC3_EP_STALL) | |
297 | usb_status = 1 << USB_ENDPOINT_HALT; | |
298 | break; | |
299 | default: | |
300 | return -EINVAL; | |
301 | }; | |
302 | ||
303 | response_pkt = (__le16 *) dwc->setup_buf; | |
304 | *response_pkt = cpu_to_le16(usb_status); | |
305 | dwc->ep0_usb_req.length = sizeof(*response_pkt); | |
8ee6270c SAS |
306 | dwc->ep0_usb_req.dma = dwc->setup_buf_addr; |
307 | dwc->ep0_usb_req.complete = dwc3_ep0_status_cmpl; | |
c2da2ff0 | 308 | return usb_ep_queue(&dwc->eps[0]->endpoint, &dwc->ep0_usb_req, |
8ee6270c | 309 | GFP_ATOMIC); |
72246da4 FB |
310 | } |
311 | ||
312 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
313 | struct usb_ctrlrequest *ctrl, int set) | |
314 | { | |
315 | struct dwc3_ep *dep; | |
316 | u32 recip; | |
317 | u32 wValue; | |
318 | u32 wIndex; | |
319 | u32 reg; | |
320 | int ret; | |
321 | u32 mode; | |
322 | ||
323 | wValue = le16_to_cpu(ctrl->wValue); | |
324 | wIndex = le16_to_cpu(ctrl->wIndex); | |
325 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
326 | switch (recip) { | |
327 | case USB_RECIP_DEVICE: | |
328 | ||
329 | /* | |
330 | * 9.4.1 says only only for SS, in AddressState only for | |
331 | * default control pipe | |
332 | */ | |
333 | switch (wValue) { | |
334 | case USB_DEVICE_U1_ENABLE: | |
335 | case USB_DEVICE_U2_ENABLE: | |
336 | case USB_DEVICE_LTM_ENABLE: | |
337 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) | |
338 | return -EINVAL; | |
339 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
340 | return -EINVAL; | |
341 | } | |
342 | ||
343 | /* XXX add U[12] & LTM */ | |
344 | switch (wValue) { | |
345 | case USB_DEVICE_REMOTE_WAKEUP: | |
346 | break; | |
347 | case USB_DEVICE_U1_ENABLE: | |
348 | break; | |
349 | case USB_DEVICE_U2_ENABLE: | |
350 | break; | |
351 | case USB_DEVICE_LTM_ENABLE: | |
352 | break; | |
353 | ||
354 | case USB_DEVICE_TEST_MODE: | |
355 | if ((wIndex & 0xff) != 0) | |
356 | return -EINVAL; | |
357 | if (!set) | |
358 | return -EINVAL; | |
359 | ||
360 | mode = wIndex >> 8; | |
361 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
362 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
363 | ||
364 | switch (mode) { | |
365 | case TEST_J: | |
366 | case TEST_K: | |
367 | case TEST_SE0_NAK: | |
368 | case TEST_PACKET: | |
369 | case TEST_FORCE_EN: | |
370 | reg |= mode << 1; | |
371 | break; | |
372 | default: | |
373 | return -EINVAL; | |
374 | } | |
375 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
376 | break; | |
377 | default: | |
378 | return -EINVAL; | |
379 | } | |
380 | break; | |
381 | ||
382 | case USB_RECIP_INTERFACE: | |
383 | switch (wValue) { | |
384 | case USB_INTRF_FUNC_SUSPEND: | |
385 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
386 | /* XXX enable Low power suspend */ | |
387 | ; | |
388 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
389 | /* XXX enable remote wakeup */ | |
390 | ; | |
391 | break; | |
392 | default: | |
393 | return -EINVAL; | |
394 | } | |
395 | break; | |
396 | ||
397 | case USB_RECIP_ENDPOINT: | |
398 | switch (wValue) { | |
399 | case USB_ENDPOINT_HALT: | |
1e7618d8 | 400 | dep = dwc3_wIndex_to_dep(dwc, wIndex); |
72246da4 FB |
401 | if (!dep) |
402 | return -EINVAL; | |
403 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
404 | if (ret) | |
405 | return -EINVAL; | |
406 | break; | |
407 | default: | |
408 | return -EINVAL; | |
409 | } | |
410 | break; | |
411 | ||
412 | default: | |
413 | return -EINVAL; | |
414 | }; | |
415 | ||
72246da4 FB |
416 | return 0; |
417 | } | |
418 | ||
419 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
420 | { | |
72246da4 FB |
421 | u32 addr; |
422 | u32 reg; | |
423 | ||
424 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 FB |
425 | if (addr > 127) { |
426 | dev_dbg(dwc->dev, "invalid device address %d\n", addr); | |
72246da4 | 427 | return -EINVAL; |
f96a6ec1 FB |
428 | } |
429 | ||
430 | if (dwc->dev_state == DWC3_CONFIGURED_STATE) { | |
431 | dev_dbg(dwc->dev, "trying to set address when configured\n"); | |
432 | return -EINVAL; | |
433 | } | |
72246da4 | 434 | |
2646021e FB |
435 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
436 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
437 | reg |= DWC3_DCFG_DEVADDR(addr); | |
438 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 439 | |
2646021e FB |
440 | if (addr) |
441 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
442 | else | |
443 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
c7fcdeb2 | 444 | |
2646021e | 445 | return 0; |
72246da4 FB |
446 | } |
447 | ||
448 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
449 | { | |
450 | int ret; | |
451 | ||
452 | spin_unlock(&dwc->lock); | |
453 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
454 | spin_lock(&dwc->lock); | |
455 | return ret; | |
456 | } | |
457 | ||
458 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
459 | { | |
460 | u32 cfg; | |
461 | int ret; | |
462 | ||
b23c8439 | 463 | dwc->start_config_issued = false; |
72246da4 FB |
464 | cfg = le16_to_cpu(ctrl->wValue); |
465 | ||
466 | switch (dwc->dev_state) { | |
467 | case DWC3_DEFAULT_STATE: | |
468 | return -EINVAL; | |
469 | break; | |
470 | ||
471 | case DWC3_ADDRESS_STATE: | |
472 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
473 | /* if the cfg matches and the cfg is non zero */ | |
474 | if (!ret && cfg) | |
475 | dwc->dev_state = DWC3_CONFIGURED_STATE; | |
476 | break; | |
477 | ||
478 | case DWC3_CONFIGURED_STATE: | |
479 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
480 | if (!cfg) | |
481 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
482 | break; | |
5bdb1dcc SAS |
483 | default: |
484 | ret = -EINVAL; | |
72246da4 | 485 | } |
5bdb1dcc | 486 | return ret; |
72246da4 FB |
487 | } |
488 | ||
489 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
490 | { | |
491 | int ret; | |
492 | ||
493 | switch (ctrl->bRequest) { | |
494 | case USB_REQ_GET_STATUS: | |
495 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
496 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
497 | break; | |
498 | case USB_REQ_CLEAR_FEATURE: | |
499 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
500 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
501 | break; | |
502 | case USB_REQ_SET_FEATURE: | |
503 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
504 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
505 | break; | |
506 | case USB_REQ_SET_ADDRESS: | |
507 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
508 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
509 | break; | |
510 | case USB_REQ_SET_CONFIGURATION: | |
511 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
512 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
513 | break; | |
514 | default: | |
515 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
516 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
517 | break; | |
518 | }; | |
519 | ||
520 | return ret; | |
521 | } | |
522 | ||
523 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
524 | const struct dwc3_event_depevt *event) | |
525 | { | |
526 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
527 | int ret; | |
528 | u32 len; | |
529 | ||
530 | if (!dwc->gadget_driver) | |
531 | goto err; | |
532 | ||
533 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 534 | if (!len) { |
d95b09b9 FB |
535 | dwc->three_stage_setup = false; |
536 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
537 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
538 | } else { | |
d95b09b9 FB |
539 | dwc->three_stage_setup = true; |
540 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
541 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
542 | } | |
72246da4 FB |
543 | |
544 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
545 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
546 | else | |
547 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
548 | ||
5bdb1dcc SAS |
549 | if (ret == USB_GADGET_DELAYED_STATUS) |
550 | dwc->delayed_status = true; | |
551 | ||
72246da4 FB |
552 | if (ret >= 0) |
553 | return; | |
554 | ||
555 | err: | |
556 | dwc3_ep0_stall_and_restart(dwc); | |
557 | } | |
558 | ||
559 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
560 | const struct dwc3_event_depevt *event) | |
561 | { | |
562 | struct dwc3_request *r = NULL; | |
563 | struct usb_request *ur; | |
564 | struct dwc3_trb trb; | |
c2da2ff0 | 565 | struct dwc3_ep *ep0; |
c611ccb4 | 566 | u32 transferred; |
72246da4 FB |
567 | u8 epnum; |
568 | ||
569 | epnum = event->endpoint_number; | |
c2da2ff0 | 570 | ep0 = dwc->eps[0]; |
72246da4 | 571 | |
1ddcb218 FB |
572 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
573 | ||
c2da2ff0 | 574 | r = next_request(&ep0->request_list); |
8ee6270c | 575 | ur = &r->request; |
72246da4 FB |
576 | |
577 | dwc3_trb_to_nat(dwc->ep0_trb, &trb); | |
578 | ||
a6829706 | 579 | if (dwc->ep0_bounced) { |
a6829706 | 580 | |
c7fcdeb2 FB |
581 | transferred = min_t(u32, ur->length, |
582 | ep0->endpoint.maxpacket - trb.length); | |
a6829706 FB |
583 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
584 | dwc->ep0_bounced = false; | |
585 | } else { | |
586 | transferred = ur->length - trb.length; | |
587 | ur->actual += transferred; | |
588 | } | |
72246da4 FB |
589 | |
590 | if ((epnum & 1) && ur->actual < ur->length) { | |
591 | /* for some reason we did not get everything out */ | |
592 | ||
593 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
594 | } else { |
595 | /* | |
596 | * handle the case where we have to send a zero packet. This | |
597 | * seems to be case when req.length > maxpacket. Could it be? | |
598 | */ | |
72246da4 | 599 | if (r) |
c2da2ff0 | 600 | dwc3_gadget_giveback(ep0, r, 0); |
72246da4 FB |
601 | } |
602 | } | |
603 | ||
604 | static void dwc3_ep0_complete_req(struct dwc3 *dwc, | |
605 | const struct dwc3_event_depevt *event) | |
606 | { | |
607 | struct dwc3_request *r; | |
608 | struct dwc3_ep *dep; | |
72246da4 | 609 | |
c7fcdeb2 | 610 | dep = dwc->eps[0]; |
72246da4 FB |
611 | |
612 | if (!list_empty(&dep->request_list)) { | |
613 | r = next_request(&dep->request_list); | |
614 | ||
615 | dwc3_gadget_giveback(dep, r, 0); | |
616 | } | |
617 | ||
c7fcdeb2 | 618 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
619 | dwc3_ep0_out_start(dwc); |
620 | } | |
621 | ||
622 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
623 | const struct dwc3_event_depevt *event) | |
624 | { | |
c7fcdeb2 FB |
625 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
626 | ||
627 | dep->flags &= ~DWC3_EP_BUSY; | |
628 | ||
72246da4 | 629 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
630 | case EP0_SETUP_PHASE: |
631 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
632 | dwc3_ep0_inspect_setup(dwc, event); |
633 | break; | |
634 | ||
c7fcdeb2 FB |
635 | case EP0_DATA_PHASE: |
636 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
637 | dwc3_ep0_complete_data(dwc, event); |
638 | break; | |
639 | ||
c7fcdeb2 FB |
640 | case EP0_STATUS_PHASE: |
641 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
72246da4 FB |
642 | dwc3_ep0_complete_req(dwc, event); |
643 | break; | |
c7fcdeb2 FB |
644 | default: |
645 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
646 | } | |
647 | } | |
72246da4 | 648 | |
c7fcdeb2 FB |
649 | static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, |
650 | const struct dwc3_event_depevt *event) | |
651 | { | |
c7fcdeb2 FB |
652 | dwc3_ep0_out_start(dwc); |
653 | } | |
654 | ||
655 | static void dwc3_ep0_do_control_data(struct dwc3 *dwc, | |
656 | const struct dwc3_event_depevt *event) | |
657 | { | |
658 | struct dwc3_ep *dep; | |
659 | struct dwc3_request *req; | |
660 | int ret; | |
661 | ||
662 | dep = dwc->eps[0]; | |
c7fcdeb2 FB |
663 | |
664 | if (list_empty(&dep->request_list)) { | |
665 | dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); | |
666 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
667 | ||
668 | if (event->endpoint_number) | |
669 | dep->flags |= DWC3_EP0_DIR_IN; | |
670 | return; | |
72246da4 | 671 | } |
c7fcdeb2 FB |
672 | |
673 | req = next_request(&dep->request_list); | |
674 | req->direction = !!event->endpoint_number; | |
675 | ||
c7fcdeb2 FB |
676 | if (req->request.length == 0) { |
677 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
678 | dwc->ctrl_req_addr, 0, | |
679 | DWC3_TRBCTL_CONTROL_DATA); | |
680 | } else if ((req->request.length % dep->endpoint.maxpacket) | |
681 | && (event->endpoint_number == 0)) { | |
682 | dwc3_map_buffer_to_dma(req); | |
683 | ||
684 | WARN_ON(req->request.length > dep->endpoint.maxpacket); | |
685 | ||
686 | dwc->ep0_bounced = true; | |
687 | ||
688 | /* | |
689 | * REVISIT in case request length is bigger than EP0 | |
690 | * wMaxPacketSize, we will need two chained TRBs to handle | |
691 | * the transfer. | |
692 | */ | |
693 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
694 | dwc->ep0_bounce_addr, dep->endpoint.maxpacket, | |
695 | DWC3_TRBCTL_CONTROL_DATA); | |
696 | } else { | |
697 | dwc3_map_buffer_to_dma(req); | |
698 | ||
699 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
700 | req->request.dma, req->request.length, | |
701 | DWC3_TRBCTL_CONTROL_DATA); | |
702 | } | |
703 | ||
704 | WARN_ON(ret < 0); | |
72246da4 FB |
705 | } |
706 | ||
f0f2b2a2 | 707 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 708 | { |
f0f2b2a2 | 709 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 710 | u32 type; |
72246da4 | 711 | |
c7fcdeb2 FB |
712 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
713 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
714 | ||
f0f2b2a2 | 715 | return dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 | 716 | dwc->ctrl_req_addr, 0, type); |
f0f2b2a2 | 717 | } |
c7fcdeb2 | 718 | |
f0f2b2a2 SAS |
719 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum) |
720 | { | |
721 | struct dwc3_ep *dep = dwc->eps[epnum]; | |
722 | ||
723 | WARN_ON(dwc3_ep0_start_control_status(dep)); | |
c7fcdeb2 FB |
724 | } |
725 | ||
726 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, | |
727 | const struct dwc3_event_depevt *event) | |
728 | { | |
9cc9bcd5 FB |
729 | /* |
730 | * This part is very tricky: If we has just handled | |
731 | * XferNotReady(Setup) and we're now expecting a | |
732 | * XferComplete but, instead, we receive another | |
733 | * XferNotReady(Setup), we should STALL and restart | |
734 | * the state machine. | |
735 | * | |
736 | * In all other cases, we just continue waiting | |
737 | * for the XferComplete event. | |
738 | * | |
739 | * We are a little bit unsafe here because we're | |
740 | * not trying to ensure that last event was, indeed, | |
741 | * XferNotReady(Setup). | |
742 | * | |
743 | * Still, we don't expect any condition where that | |
744 | * should happen and, even if it does, it would be | |
745 | * another error condition. | |
746 | */ | |
747 | if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) { | |
748 | switch (event->status) { | |
749 | case DEPEVT_STATUS_CONTROL_SETUP: | |
750 | dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n"); | |
751 | dwc3_ep0_stall_and_restart(dwc); | |
752 | break; | |
753 | case DEPEVT_STATUS_CONTROL_DATA: | |
754 | /* FALLTHROUGH */ | |
755 | case DEPEVT_STATUS_CONTROL_STATUS: | |
756 | /* FALLTHROUGH */ | |
757 | default: | |
758 | dev_vdbg(dwc->dev, "waiting for XferComplete\n"); | |
759 | } | |
760 | ||
761 | return; | |
762 | } | |
763 | ||
c7fcdeb2 FB |
764 | switch (event->status) { |
765 | case DEPEVT_STATUS_CONTROL_SETUP: | |
766 | dev_vdbg(dwc->dev, "Control Setup\n"); | |
f0f2b2a2 SAS |
767 | |
768 | dwc->ep0state = EP0_SETUP_PHASE; | |
769 | ||
c7fcdeb2 FB |
770 | dwc3_ep0_do_control_setup(dwc, event); |
771 | break; | |
1ddcb218 | 772 | |
c7fcdeb2 FB |
773 | case DEPEVT_STATUS_CONTROL_DATA: |
774 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 | 775 | |
f0f2b2a2 SAS |
776 | dwc->ep0state = EP0_DATA_PHASE; |
777 | ||
1ddcb218 FB |
778 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { |
779 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
780 | dwc->ep0_next_event, |
781 | DWC3_EP0_NRDY_DATA); | |
1ddcb218 FB |
782 | |
783 | dwc3_ep0_stall_and_restart(dwc); | |
784 | return; | |
785 | } | |
786 | ||
55f3fba6 FB |
787 | /* |
788 | * One of the possible error cases is when Host _does_ | |
789 | * request for Data Phase, but it does so on the wrong | |
790 | * direction. | |
791 | * | |
792 | * Here, we already know ep0_next_event is DATA (see above), | |
793 | * so we only need to check for direction. | |
794 | */ | |
795 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
796 | dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); | |
797 | dwc3_ep0_stall_and_restart(dwc); | |
798 | return; | |
799 | } | |
800 | ||
c7fcdeb2 FB |
801 | dwc3_ep0_do_control_data(dwc, event); |
802 | break; | |
1ddcb218 | 803 | |
c7fcdeb2 FB |
804 | case DEPEVT_STATUS_CONTROL_STATUS: |
805 | dev_vdbg(dwc->dev, "Control Status\n"); | |
1ddcb218 | 806 | |
f0f2b2a2 SAS |
807 | dwc->ep0state = EP0_STATUS_PHASE; |
808 | ||
1ddcb218 FB |
809 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { |
810 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
811 | dwc->ep0_next_event, |
812 | DWC3_EP0_NRDY_STATUS); | |
1ddcb218 FB |
813 | |
814 | dwc3_ep0_stall_and_restart(dwc); | |
815 | return; | |
816 | } | |
5bdb1dcc SAS |
817 | |
818 | if (dwc->delayed_status) { | |
819 | WARN_ON_ONCE(event->endpoint_number != 1); | |
820 | dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); | |
821 | return; | |
822 | } | |
823 | ||
f0f2b2a2 | 824 | dwc3_ep0_do_control_status(dwc, event->endpoint_number); |
72246da4 FB |
825 | } |
826 | } | |
827 | ||
828 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 829 | const struct dwc3_event_depevt *event) |
72246da4 FB |
830 | { |
831 | u8 epnum = event->endpoint_number; | |
832 | ||
833 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
834 | dwc3_ep_event_string(event->endpoint_event), | |
b147f357 | 835 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
836 | dwc3_ep0_state_string(dwc->ep0state)); |
837 | ||
838 | switch (event->endpoint_event) { | |
839 | case DWC3_DEPEVT_XFERCOMPLETE: | |
840 | dwc3_ep0_xfer_complete(dwc, event); | |
841 | break; | |
842 | ||
843 | case DWC3_DEPEVT_XFERNOTREADY: | |
844 | dwc3_ep0_xfernotready(dwc, event); | |
845 | break; | |
846 | ||
847 | case DWC3_DEPEVT_XFERINPROGRESS: | |
848 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
849 | case DWC3_DEPEVT_STREAMEVT: | |
850 | case DWC3_DEPEVT_EPCMDCMPLT: | |
851 | break; | |
852 | } | |
853 | } |