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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/pm_runtime.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | ||
49 | #include <linux/usb/ch9.h> | |
50 | #include <linux/usb/gadget.h> | |
5bdb1dcc | 51 | #include <linux/usb/composite.h> |
72246da4 FB |
52 | |
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
5bdb1dcc SAS |
57 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum); |
58 | ||
72246da4 FB |
59 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) |
60 | { | |
61 | switch (state) { | |
62 | case EP0_UNCONNECTED: | |
63 | return "Unconnected"; | |
c7fcdeb2 FB |
64 | case EP0_SETUP_PHASE: |
65 | return "Setup Phase"; | |
66 | case EP0_DATA_PHASE: | |
67 | return "Data Phase"; | |
68 | case EP0_STATUS_PHASE: | |
69 | return "Status Phase"; | |
72246da4 FB |
70 | default: |
71 | return "UNKNOWN"; | |
72 | } | |
73 | } | |
74 | ||
75 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 76 | u32 len, u32 type) |
72246da4 FB |
77 | { |
78 | struct dwc3_gadget_ep_cmd_params params; | |
79 | struct dwc3_trb_hw *trb_hw; | |
80 | struct dwc3_trb trb; | |
81 | struct dwc3_ep *dep; | |
82 | ||
83 | int ret; | |
84 | ||
85 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
86 | if (dep->flags & DWC3_EP_BUSY) { |
87 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
88 | return 0; | |
89 | } | |
72246da4 FB |
90 | |
91 | trb_hw = dwc->ep0_trb; | |
92 | memset(&trb, 0, sizeof(trb)); | |
93 | ||
c7fcdeb2 | 94 | trb.trbctl = type; |
72246da4 FB |
95 | trb.bplh = buf_dma; |
96 | trb.length = len; | |
97 | ||
98 | trb.hwo = 1; | |
99 | trb.lst = 1; | |
100 | trb.ioc = 1; | |
101 | trb.isp_imi = 1; | |
102 | ||
103 | dwc3_trb_to_hw(&trb, trb_hw); | |
104 | ||
105 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
106 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
107 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
108 | |
109 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
110 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
111 | if (ret < 0) { | |
112 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
113 | return ret; | |
114 | } | |
115 | ||
c7fcdeb2 | 116 | dep->flags |= DWC3_EP_BUSY; |
72246da4 FB |
117 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, |
118 | dep->number); | |
119 | ||
1ddcb218 FB |
120 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
121 | ||
72246da4 FB |
122 | return 0; |
123 | } | |
124 | ||
125 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
126 | struct dwc3_request *req) | |
127 | { | |
5bdb1dcc | 128 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 129 | int ret = 0; |
72246da4 FB |
130 | |
131 | req->request.actual = 0; | |
132 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
133 | req->epnum = dep->number; |
134 | ||
135 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 136 | |
c7fcdeb2 FB |
137 | /* |
138 | * Gadget driver might not be quick enough to queue a request | |
139 | * before we get a Transfer Not Ready event on this endpoint. | |
140 | * | |
141 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
142 | * flag is set, it's telling us that as soon as Gadget queues the | |
143 | * required request, we should kick the transfer here because the | |
144 | * IRQ we were waiting for is long gone. | |
145 | */ | |
146 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
c7fcdeb2 | 147 | unsigned direction; |
c7fcdeb2 FB |
148 | |
149 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
150 | ||
68d8a781 FB |
151 | if (dwc->ep0state != EP0_DATA_PHASE) { |
152 | dev_WARN(dwc->dev, "Unexpected pending request\n"); | |
c7fcdeb2 FB |
153 | return 0; |
154 | } | |
72246da4 | 155 | |
c7fcdeb2 | 156 | ret = dwc3_ep0_start_trans(dwc, direction, |
68d8a781 FB |
157 | req->request.dma, req->request.length, |
158 | DWC3_TRBCTL_CONTROL_DATA); | |
c7fcdeb2 FB |
159 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | |
160 | DWC3_EP0_DIR_IN); | |
68d3e668 | 161 | } else if (dwc->delayed_status) { |
5bdb1dcc | 162 | dwc->delayed_status = false; |
68d3e668 FB |
163 | |
164 | if (dwc->ep0state == EP0_STATUS_PHASE) | |
165 | dwc3_ep0_do_control_status(dwc, 1); | |
166 | else | |
167 | dev_dbg(dwc->dev, "too early for delayed status\n"); | |
72246da4 FB |
168 | } |
169 | ||
170 | return ret; | |
171 | } | |
172 | ||
173 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
174 | gfp_t gfp_flags) | |
175 | { | |
176 | struct dwc3_request *req = to_dwc3_request(request); | |
177 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
180 | unsigned long flags; | |
181 | ||
182 | int ret; | |
183 | ||
72246da4 FB |
184 | spin_lock_irqsave(&dwc->lock, flags); |
185 | if (!dep->desc) { | |
186 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", | |
187 | request, dep->name); | |
188 | ret = -ESHUTDOWN; | |
189 | goto out; | |
190 | } | |
191 | ||
192 | /* we share one TRB for ep0/1 */ | |
c2da2ff0 | 193 | if (!list_empty(&dep->request_list)) { |
72246da4 FB |
194 | ret = -EBUSY; |
195 | goto out; | |
196 | } | |
197 | ||
198 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
199 | request, dep->name, request->length, | |
200 | dwc3_ep0_state_string(dwc->ep0state)); | |
201 | ||
202 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
203 | ||
204 | out: | |
205 | spin_unlock_irqrestore(&dwc->lock, flags); | |
206 | ||
207 | return ret; | |
208 | } | |
209 | ||
210 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
211 | { | |
d742220b FB |
212 | struct dwc3_ep *dep = dwc->eps[0]; |
213 | ||
72246da4 | 214 | /* stall is always issued on EP0 */ |
c2da2ff0 SAS |
215 | __dwc3_gadget_ep_set_halt(dep, 1); |
216 | dep->flags = DWC3_EP_ENABLED; | |
5bdb1dcc | 217 | dwc->delayed_status = false; |
d742220b FB |
218 | |
219 | if (!list_empty(&dep->request_list)) { | |
220 | struct dwc3_request *req; | |
221 | ||
222 | req = next_request(&dep->request_list); | |
223 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
224 | } | |
225 | ||
c7fcdeb2 | 226 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
227 | dwc3_ep0_out_start(dwc); |
228 | } | |
229 | ||
230 | void dwc3_ep0_out_start(struct dwc3 *dwc) | |
231 | { | |
72246da4 FB |
232 | int ret; |
233 | ||
c7fcdeb2 FB |
234 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
235 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
236 | WARN_ON(ret < 0); |
237 | } | |
238 | ||
72246da4 FB |
239 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
240 | { | |
241 | struct dwc3_ep *dep; | |
242 | u32 windex = le16_to_cpu(wIndex_le); | |
243 | u32 epnum; | |
244 | ||
245 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
246 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
247 | epnum |= 1; | |
248 | ||
249 | dep = dwc->eps[epnum]; | |
250 | if (dep->flags & DWC3_EP_ENABLED) | |
251 | return dep; | |
252 | ||
253 | return NULL; | |
254 | } | |
255 | ||
8ee6270c | 256 | static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) |
72246da4 | 257 | { |
72246da4 | 258 | } |
72246da4 FB |
259 | /* |
260 | * ch 9.4.5 | |
261 | */ | |
25b8ff68 FB |
262 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, |
263 | struct usb_ctrlrequest *ctrl) | |
72246da4 FB |
264 | { |
265 | struct dwc3_ep *dep; | |
266 | u32 recip; | |
267 | u16 usb_status = 0; | |
268 | __le16 *response_pkt; | |
269 | ||
270 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
271 | switch (recip) { | |
272 | case USB_RECIP_DEVICE: | |
273 | /* | |
274 | * We are self-powered. U1/U2/LTM will be set later | |
275 | * once we handle this states. RemoteWakeup is 0 on SS | |
276 | */ | |
277 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
278 | break; | |
279 | ||
280 | case USB_RECIP_INTERFACE: | |
281 | /* | |
282 | * Function Remote Wake Capable D0 | |
283 | * Function Remote Wakeup D1 | |
284 | */ | |
285 | break; | |
286 | ||
287 | case USB_RECIP_ENDPOINT: | |
288 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
289 | if (!dep) | |
25b8ff68 | 290 | return -EINVAL; |
72246da4 FB |
291 | |
292 | if (dep->flags & DWC3_EP_STALL) | |
293 | usb_status = 1 << USB_ENDPOINT_HALT; | |
294 | break; | |
295 | default: | |
296 | return -EINVAL; | |
297 | }; | |
298 | ||
299 | response_pkt = (__le16 *) dwc->setup_buf; | |
300 | *response_pkt = cpu_to_le16(usb_status); | |
e2617796 FB |
301 | |
302 | dep = dwc->eps[0]; | |
303 | dwc->ep0_usb_req.dep = dep; | |
e0ce0b0a SAS |
304 | dwc->ep0_usb_req.request.length = sizeof(*response_pkt); |
305 | dwc->ep0_usb_req.request.dma = dwc->setup_buf_addr; | |
306 | dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; | |
e2617796 FB |
307 | |
308 | return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); | |
72246da4 FB |
309 | } |
310 | ||
311 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
312 | struct usb_ctrlrequest *ctrl, int set) | |
313 | { | |
314 | struct dwc3_ep *dep; | |
315 | u32 recip; | |
316 | u32 wValue; | |
317 | u32 wIndex; | |
72246da4 | 318 | int ret; |
72246da4 FB |
319 | |
320 | wValue = le16_to_cpu(ctrl->wValue); | |
321 | wIndex = le16_to_cpu(ctrl->wIndex); | |
322 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
323 | switch (recip) { | |
324 | case USB_RECIP_DEVICE: | |
325 | ||
326 | /* | |
327 | * 9.4.1 says only only for SS, in AddressState only for | |
328 | * default control pipe | |
329 | */ | |
330 | switch (wValue) { | |
331 | case USB_DEVICE_U1_ENABLE: | |
332 | case USB_DEVICE_U2_ENABLE: | |
333 | case USB_DEVICE_LTM_ENABLE: | |
334 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) | |
335 | return -EINVAL; | |
336 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
337 | return -EINVAL; | |
338 | } | |
339 | ||
340 | /* XXX add U[12] & LTM */ | |
341 | switch (wValue) { | |
342 | case USB_DEVICE_REMOTE_WAKEUP: | |
343 | break; | |
344 | case USB_DEVICE_U1_ENABLE: | |
345 | break; | |
346 | case USB_DEVICE_U2_ENABLE: | |
347 | break; | |
348 | case USB_DEVICE_LTM_ENABLE: | |
349 | break; | |
350 | ||
351 | case USB_DEVICE_TEST_MODE: | |
352 | if ((wIndex & 0xff) != 0) | |
353 | return -EINVAL; | |
354 | if (!set) | |
355 | return -EINVAL; | |
356 | ||
3b637367 GC |
357 | dwc->test_mode_nr = wIndex >> 8; |
358 | dwc->test_mode = true; | |
72246da4 FB |
359 | } |
360 | break; | |
361 | ||
362 | case USB_RECIP_INTERFACE: | |
363 | switch (wValue) { | |
364 | case USB_INTRF_FUNC_SUSPEND: | |
365 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
366 | /* XXX enable Low power suspend */ | |
367 | ; | |
368 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
369 | /* XXX enable remote wakeup */ | |
370 | ; | |
371 | break; | |
372 | default: | |
373 | return -EINVAL; | |
374 | } | |
375 | break; | |
376 | ||
377 | case USB_RECIP_ENDPOINT: | |
378 | switch (wValue) { | |
379 | case USB_ENDPOINT_HALT: | |
1e7618d8 | 380 | dep = dwc3_wIndex_to_dep(dwc, wIndex); |
72246da4 FB |
381 | if (!dep) |
382 | return -EINVAL; | |
383 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
384 | if (ret) | |
385 | return -EINVAL; | |
386 | break; | |
387 | default: | |
388 | return -EINVAL; | |
389 | } | |
390 | break; | |
391 | ||
392 | default: | |
393 | return -EINVAL; | |
394 | }; | |
395 | ||
72246da4 FB |
396 | return 0; |
397 | } | |
398 | ||
399 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
400 | { | |
72246da4 FB |
401 | u32 addr; |
402 | u32 reg; | |
403 | ||
404 | addr = le16_to_cpu(ctrl->wValue); | |
f96a6ec1 FB |
405 | if (addr > 127) { |
406 | dev_dbg(dwc->dev, "invalid device address %d\n", addr); | |
72246da4 | 407 | return -EINVAL; |
f96a6ec1 FB |
408 | } |
409 | ||
410 | if (dwc->dev_state == DWC3_CONFIGURED_STATE) { | |
411 | dev_dbg(dwc->dev, "trying to set address when configured\n"); | |
412 | return -EINVAL; | |
413 | } | |
72246da4 | 414 | |
2646021e FB |
415 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
416 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
417 | reg |= DWC3_DCFG_DEVADDR(addr); | |
418 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 419 | |
2646021e FB |
420 | if (addr) |
421 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
422 | else | |
423 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
c7fcdeb2 | 424 | |
2646021e | 425 | return 0; |
72246da4 FB |
426 | } |
427 | ||
428 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
429 | { | |
430 | int ret; | |
431 | ||
432 | spin_unlock(&dwc->lock); | |
433 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
434 | spin_lock(&dwc->lock); | |
435 | return ret; | |
436 | } | |
437 | ||
438 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
439 | { | |
440 | u32 cfg; | |
441 | int ret; | |
442 | ||
b23c8439 | 443 | dwc->start_config_issued = false; |
72246da4 FB |
444 | cfg = le16_to_cpu(ctrl->wValue); |
445 | ||
446 | switch (dwc->dev_state) { | |
447 | case DWC3_DEFAULT_STATE: | |
448 | return -EINVAL; | |
449 | break; | |
450 | ||
451 | case DWC3_ADDRESS_STATE: | |
452 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
453 | /* if the cfg matches and the cfg is non zero */ | |
457e84b6 | 454 | if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { |
72246da4 | 455 | dwc->dev_state = DWC3_CONFIGURED_STATE; |
457e84b6 FB |
456 | dwc->resize_fifos = true; |
457 | dev_dbg(dwc->dev, "resize fifos flag SET\n"); | |
458 | } | |
72246da4 FB |
459 | break; |
460 | ||
461 | case DWC3_CONFIGURED_STATE: | |
462 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
463 | if (!cfg) | |
464 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
465 | break; | |
5bdb1dcc SAS |
466 | default: |
467 | ret = -EINVAL; | |
72246da4 | 468 | } |
5bdb1dcc | 469 | return ret; |
72246da4 FB |
470 | } |
471 | ||
472 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
473 | { | |
474 | int ret; | |
475 | ||
476 | switch (ctrl->bRequest) { | |
477 | case USB_REQ_GET_STATUS: | |
478 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
479 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
480 | break; | |
481 | case USB_REQ_CLEAR_FEATURE: | |
482 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
483 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
484 | break; | |
485 | case USB_REQ_SET_FEATURE: | |
486 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
487 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
488 | break; | |
489 | case USB_REQ_SET_ADDRESS: | |
490 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
491 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
492 | break; | |
493 | case USB_REQ_SET_CONFIGURATION: | |
494 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
495 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
496 | break; | |
497 | default: | |
498 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
499 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
500 | break; | |
501 | }; | |
502 | ||
503 | return ret; | |
504 | } | |
505 | ||
506 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
507 | const struct dwc3_event_depevt *event) | |
508 | { | |
509 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
510 | int ret; | |
511 | u32 len; | |
512 | ||
513 | if (!dwc->gadget_driver) | |
514 | goto err; | |
515 | ||
516 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 517 | if (!len) { |
d95b09b9 FB |
518 | dwc->three_stage_setup = false; |
519 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
520 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
521 | } else { | |
d95b09b9 FB |
522 | dwc->three_stage_setup = true; |
523 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
524 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
525 | } | |
72246da4 FB |
526 | |
527 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
528 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
529 | else | |
530 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
531 | ||
5bdb1dcc SAS |
532 | if (ret == USB_GADGET_DELAYED_STATUS) |
533 | dwc->delayed_status = true; | |
534 | ||
72246da4 FB |
535 | if (ret >= 0) |
536 | return; | |
537 | ||
538 | err: | |
539 | dwc3_ep0_stall_and_restart(dwc); | |
540 | } | |
541 | ||
542 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
543 | const struct dwc3_event_depevt *event) | |
544 | { | |
545 | struct dwc3_request *r = NULL; | |
546 | struct usb_request *ur; | |
547 | struct dwc3_trb trb; | |
c2da2ff0 | 548 | struct dwc3_ep *ep0; |
c611ccb4 | 549 | u32 transferred; |
72246da4 FB |
550 | u8 epnum; |
551 | ||
552 | epnum = event->endpoint_number; | |
c2da2ff0 | 553 | ep0 = dwc->eps[0]; |
72246da4 | 554 | |
1ddcb218 FB |
555 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
556 | ||
c2da2ff0 | 557 | r = next_request(&ep0->request_list); |
8ee6270c | 558 | ur = &r->request; |
72246da4 FB |
559 | |
560 | dwc3_trb_to_nat(dwc->ep0_trb, &trb); | |
561 | ||
a6829706 | 562 | if (dwc->ep0_bounced) { |
a6829706 | 563 | |
c7fcdeb2 FB |
564 | transferred = min_t(u32, ur->length, |
565 | ep0->endpoint.maxpacket - trb.length); | |
a6829706 FB |
566 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
567 | dwc->ep0_bounced = false; | |
568 | } else { | |
569 | transferred = ur->length - trb.length; | |
570 | ur->actual += transferred; | |
571 | } | |
72246da4 FB |
572 | |
573 | if ((epnum & 1) && ur->actual < ur->length) { | |
574 | /* for some reason we did not get everything out */ | |
575 | ||
576 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
577 | } else { |
578 | /* | |
579 | * handle the case where we have to send a zero packet. This | |
580 | * seems to be case when req.length > maxpacket. Could it be? | |
581 | */ | |
72246da4 | 582 | if (r) |
c2da2ff0 | 583 | dwc3_gadget_giveback(ep0, r, 0); |
72246da4 FB |
584 | } |
585 | } | |
586 | ||
587 | static void dwc3_ep0_complete_req(struct dwc3 *dwc, | |
588 | const struct dwc3_event_depevt *event) | |
589 | { | |
590 | struct dwc3_request *r; | |
591 | struct dwc3_ep *dep; | |
72246da4 | 592 | |
c7fcdeb2 | 593 | dep = dwc->eps[0]; |
72246da4 FB |
594 | |
595 | if (!list_empty(&dep->request_list)) { | |
596 | r = next_request(&dep->request_list); | |
597 | ||
598 | dwc3_gadget_giveback(dep, r, 0); | |
599 | } | |
600 | ||
3b637367 GC |
601 | if (dwc->test_mode) { |
602 | int ret; | |
603 | ||
604 | ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); | |
605 | if (ret < 0) { | |
606 | dev_dbg(dwc->dev, "Invalid Test #%d\n", | |
607 | dwc->test_mode_nr); | |
608 | dwc3_ep0_stall_and_restart(dwc); | |
609 | } | |
610 | } | |
611 | ||
c7fcdeb2 | 612 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
613 | dwc3_ep0_out_start(dwc); |
614 | } | |
615 | ||
616 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
617 | const struct dwc3_event_depevt *event) | |
618 | { | |
c7fcdeb2 FB |
619 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
620 | ||
621 | dep->flags &= ~DWC3_EP_BUSY; | |
df62df56 | 622 | dwc->setup_packet_pending = false; |
c7fcdeb2 | 623 | |
72246da4 | 624 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
625 | case EP0_SETUP_PHASE: |
626 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
627 | dwc3_ep0_inspect_setup(dwc, event); |
628 | break; | |
629 | ||
c7fcdeb2 FB |
630 | case EP0_DATA_PHASE: |
631 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
632 | dwc3_ep0_complete_data(dwc, event); |
633 | break; | |
634 | ||
c7fcdeb2 FB |
635 | case EP0_STATUS_PHASE: |
636 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
72246da4 FB |
637 | dwc3_ep0_complete_req(dwc, event); |
638 | break; | |
c7fcdeb2 FB |
639 | default: |
640 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
641 | } | |
642 | } | |
72246da4 | 643 | |
c7fcdeb2 FB |
644 | static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, |
645 | const struct dwc3_event_depevt *event) | |
646 | { | |
c7fcdeb2 FB |
647 | dwc3_ep0_out_start(dwc); |
648 | } | |
649 | ||
650 | static void dwc3_ep0_do_control_data(struct dwc3 *dwc, | |
651 | const struct dwc3_event_depevt *event) | |
652 | { | |
653 | struct dwc3_ep *dep; | |
654 | struct dwc3_request *req; | |
655 | int ret; | |
656 | ||
657 | dep = dwc->eps[0]; | |
c7fcdeb2 FB |
658 | |
659 | if (list_empty(&dep->request_list)) { | |
660 | dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); | |
661 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
662 | ||
663 | if (event->endpoint_number) | |
664 | dep->flags |= DWC3_EP0_DIR_IN; | |
665 | return; | |
72246da4 | 666 | } |
c7fcdeb2 FB |
667 | |
668 | req = next_request(&dep->request_list); | |
669 | req->direction = !!event->endpoint_number; | |
670 | ||
c7fcdeb2 FB |
671 | if (req->request.length == 0) { |
672 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
673 | dwc->ctrl_req_addr, 0, | |
674 | DWC3_TRBCTL_CONTROL_DATA); | |
675 | } else if ((req->request.length % dep->endpoint.maxpacket) | |
676 | && (event->endpoint_number == 0)) { | |
677 | dwc3_map_buffer_to_dma(req); | |
678 | ||
679 | WARN_ON(req->request.length > dep->endpoint.maxpacket); | |
680 | ||
681 | dwc->ep0_bounced = true; | |
682 | ||
683 | /* | |
684 | * REVISIT in case request length is bigger than EP0 | |
685 | * wMaxPacketSize, we will need two chained TRBs to handle | |
686 | * the transfer. | |
687 | */ | |
688 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
689 | dwc->ep0_bounce_addr, dep->endpoint.maxpacket, | |
690 | DWC3_TRBCTL_CONTROL_DATA); | |
691 | } else { | |
692 | dwc3_map_buffer_to_dma(req); | |
693 | ||
694 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
695 | req->request.dma, req->request.length, | |
696 | DWC3_TRBCTL_CONTROL_DATA); | |
697 | } | |
698 | ||
699 | WARN_ON(ret < 0); | |
72246da4 FB |
700 | } |
701 | ||
f0f2b2a2 | 702 | static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
72246da4 | 703 | { |
f0f2b2a2 | 704 | struct dwc3 *dwc = dep->dwc; |
c7fcdeb2 | 705 | u32 type; |
72246da4 | 706 | |
c7fcdeb2 FB |
707 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
708 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
709 | ||
f0f2b2a2 | 710 | return dwc3_ep0_start_trans(dwc, dep->number, |
c7fcdeb2 | 711 | dwc->ctrl_req_addr, 0, type); |
f0f2b2a2 | 712 | } |
c7fcdeb2 | 713 | |
f0f2b2a2 SAS |
714 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum) |
715 | { | |
716 | struct dwc3_ep *dep = dwc->eps[epnum]; | |
717 | ||
457e84b6 FB |
718 | if (dwc->resize_fifos) { |
719 | dev_dbg(dwc->dev, "starting to resize fifos\n"); | |
720 | dwc3_gadget_resize_tx_fifos(dwc); | |
721 | dwc->resize_fifos = 0; | |
722 | } | |
723 | ||
f0f2b2a2 | 724 | WARN_ON(dwc3_ep0_start_control_status(dep)); |
c7fcdeb2 FB |
725 | } |
726 | ||
727 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, | |
728 | const struct dwc3_event_depevt *event) | |
729 | { | |
df62df56 FB |
730 | dwc->setup_packet_pending = true; |
731 | ||
9cc9bcd5 FB |
732 | /* |
733 | * This part is very tricky: If we has just handled | |
734 | * XferNotReady(Setup) and we're now expecting a | |
735 | * XferComplete but, instead, we receive another | |
736 | * XferNotReady(Setup), we should STALL and restart | |
737 | * the state machine. | |
738 | * | |
739 | * In all other cases, we just continue waiting | |
740 | * for the XferComplete event. | |
741 | * | |
742 | * We are a little bit unsafe here because we're | |
743 | * not trying to ensure that last event was, indeed, | |
744 | * XferNotReady(Setup). | |
745 | * | |
746 | * Still, we don't expect any condition where that | |
747 | * should happen and, even if it does, it would be | |
748 | * another error condition. | |
749 | */ | |
750 | if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) { | |
751 | switch (event->status) { | |
752 | case DEPEVT_STATUS_CONTROL_SETUP: | |
753 | dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n"); | |
754 | dwc3_ep0_stall_and_restart(dwc); | |
755 | break; | |
756 | case DEPEVT_STATUS_CONTROL_DATA: | |
757 | /* FALLTHROUGH */ | |
758 | case DEPEVT_STATUS_CONTROL_STATUS: | |
759 | /* FALLTHROUGH */ | |
760 | default: | |
761 | dev_vdbg(dwc->dev, "waiting for XferComplete\n"); | |
762 | } | |
763 | ||
764 | return; | |
765 | } | |
766 | ||
c7fcdeb2 FB |
767 | switch (event->status) { |
768 | case DEPEVT_STATUS_CONTROL_SETUP: | |
769 | dev_vdbg(dwc->dev, "Control Setup\n"); | |
f0f2b2a2 SAS |
770 | |
771 | dwc->ep0state = EP0_SETUP_PHASE; | |
772 | ||
c7fcdeb2 FB |
773 | dwc3_ep0_do_control_setup(dwc, event); |
774 | break; | |
1ddcb218 | 775 | |
c7fcdeb2 FB |
776 | case DEPEVT_STATUS_CONTROL_DATA: |
777 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 | 778 | |
f0f2b2a2 SAS |
779 | dwc->ep0state = EP0_DATA_PHASE; |
780 | ||
1ddcb218 FB |
781 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { |
782 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
783 | dwc->ep0_next_event, |
784 | DWC3_EP0_NRDY_DATA); | |
1ddcb218 FB |
785 | |
786 | dwc3_ep0_stall_and_restart(dwc); | |
787 | return; | |
788 | } | |
789 | ||
55f3fba6 FB |
790 | /* |
791 | * One of the possible error cases is when Host _does_ | |
792 | * request for Data Phase, but it does so on the wrong | |
793 | * direction. | |
794 | * | |
795 | * Here, we already know ep0_next_event is DATA (see above), | |
796 | * so we only need to check for direction. | |
797 | */ | |
798 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
799 | dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); | |
800 | dwc3_ep0_stall_and_restart(dwc); | |
801 | return; | |
802 | } | |
803 | ||
c7fcdeb2 FB |
804 | dwc3_ep0_do_control_data(dwc, event); |
805 | break; | |
1ddcb218 | 806 | |
c7fcdeb2 FB |
807 | case DEPEVT_STATUS_CONTROL_STATUS: |
808 | dev_vdbg(dwc->dev, "Control Status\n"); | |
1ddcb218 | 809 | |
f0f2b2a2 SAS |
810 | dwc->ep0state = EP0_STATUS_PHASE; |
811 | ||
1ddcb218 FB |
812 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { |
813 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
814 | dwc->ep0_next_event, |
815 | DWC3_EP0_NRDY_STATUS); | |
1ddcb218 FB |
816 | |
817 | dwc3_ep0_stall_and_restart(dwc); | |
818 | return; | |
819 | } | |
5bdb1dcc SAS |
820 | |
821 | if (dwc->delayed_status) { | |
822 | WARN_ON_ONCE(event->endpoint_number != 1); | |
823 | dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); | |
824 | return; | |
825 | } | |
826 | ||
f0f2b2a2 | 827 | dwc3_ep0_do_control_status(dwc, event->endpoint_number); |
72246da4 FB |
828 | } |
829 | } | |
830 | ||
831 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
8becf270 | 832 | const struct dwc3_event_depevt *event) |
72246da4 FB |
833 | { |
834 | u8 epnum = event->endpoint_number; | |
835 | ||
836 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
837 | dwc3_ep_event_string(event->endpoint_event), | |
b147f357 | 838 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
839 | dwc3_ep0_state_string(dwc->ep0state)); |
840 | ||
841 | switch (event->endpoint_event) { | |
842 | case DWC3_DEPEVT_XFERCOMPLETE: | |
843 | dwc3_ep0_xfer_complete(dwc, event); | |
844 | break; | |
845 | ||
846 | case DWC3_DEPEVT_XFERNOTREADY: | |
847 | dwc3_ep0_xfernotready(dwc, event); | |
848 | break; | |
849 | ||
850 | case DWC3_DEPEVT_XFERINPROGRESS: | |
851 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
852 | case DWC3_DEPEVT_STREAMEVT: | |
853 | case DWC3_DEPEVT_EPCMDCMPLT: | |
854 | break; | |
855 | } | |
856 | } |