[deliverable/linux.git] / drivers / usb / dwc3 / ep0.c

/**
 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 * All rights reserved.
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/dma-mapping.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event);

static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
{
	switch (state) {
	case EP0_UNCONNECTED:
		return "Unconnected";
	case EP0_SETUP_PHASE:
		return "Setup Phase";
	case EP0_DATA_PHASE:
		return "Data Phase";
	case EP0_STATUS_PHASE:
		return "Status Phase";
	default:
		return "UNKNOWN";
	}
}

static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
		u32 len, u32 type)
{
	struct dwc3_gadget_ep_cmd_params params;
	struct dwc3_trb_hw		*trb_hw;
	struct dwc3_trb			trb;
	struct dwc3_ep			*dep;

	int				ret;

	dep = dwc->eps[epnum];
	if (dep->flags & DWC3_EP_BUSY) {
		dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
		return 0;
	}

	trb_hw = dwc->ep0_trb;
	memset(&trb, 0, sizeof(trb));

	trb.trbctl = type;
	trb.bplh = buf_dma;
	trb.length = len;

	trb.hwo	= 1;
	trb.lst	= 1;
	trb.ioc	= 1;
	trb.isp_imi = 1;

	dwc3_trb_to_hw(&trb, trb_hw);

	memset(&params, 0, sizeof(params));
	params.param0.depstrtxfer.transfer_desc_addr_high =
		upper_32_bits(dwc->ep0_trb_addr);
	params.param1.depstrtxfer.transfer_desc_addr_low =
		lower_32_bits(dwc->ep0_trb_addr);

	ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
			DWC3_DEPCMD_STARTTRANSFER, &params);
	if (ret < 0) {
		dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
		return ret;
	}

	dep->flags |= DWC3_EP_BUSY;
	dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
			dep->number);

	return 0;
}

static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
		struct dwc3_request *req)
{
	int			ret = 0;

	req->request.actual	= 0;
	req->request.status	= -EINPROGRESS;
	req->epnum		= dep->number;

	list_add_tail(&req->list, &dep->request_list);

	/*
	 * Gadget driver might not be quick enough to queue a request
	 * before we get a Transfer Not Ready event on this endpoint.
	 *
	 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
	 * flag is set, it's telling us that as soon as Gadget queues the
	 * required request, we should kick the transfer here because the
	 * IRQ we were waiting for is long gone.
	 */
	if (dep->flags & DWC3_EP_PENDING_REQUEST) {
		struct dwc3	*dwc = dep->dwc;
		unsigned	direction;
		u32		type;

		direction = !!(dep->flags & DWC3_EP0_DIR_IN);

		if (dwc->ep0state == EP0_STATUS_PHASE) {
			type = dwc->three_stage_setup
				? DWC3_TRBCTL_CONTROL_STATUS3
				: DWC3_TRBCTL_CONTROL_STATUS2;
		} else if (dwc->ep0state == EP0_DATA_PHASE) {
			type = DWC3_TRBCTL_CONTROL_DATA;
		} else {
			/* should never happen */
			WARN_ON(1);
			return 0;
		}

		ret = dwc3_ep0_start_trans(dwc, direction,
				req->request.dma, req->request.length, type);
		dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
				DWC3_EP0_DIR_IN);
	}

	return ret;
}

int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
		gfp_t gfp_flags)
{
	struct dwc3_request		*req = to_dwc3_request(request);
	struct dwc3_ep			*dep = to_dwc3_ep(ep);
	struct dwc3			*dwc = dep->dwc;

	unsigned long			flags;

	int				ret;

	spin_lock_irqsave(&dwc->lock, flags);
	if (!dep->desc) {
		dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
				request, dep->name);
		ret = -ESHUTDOWN;
		goto out;
	}

	/* we share one TRB for ep0/1 */
	if (!list_empty(&dwc->eps[0]->request_list) ||
			!list_empty(&dwc->eps[1]->request_list) ||
			dwc->ep0_status_pending) {
		ret = -EBUSY;
		goto out;
	}

	dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
			request, dep->name, request->length,
			dwc3_ep0_state_string(dwc->ep0state));

	ret = __dwc3_gadget_ep0_queue(dep, req);

out:
	spin_unlock_irqrestore(&dwc->lock, flags);

	return ret;
}

static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
{
	/* stall is always issued on EP0 */
	__dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
	dwc->eps[0]->flags = DWC3_EP_ENABLED;
	dwc->ep0state = EP0_SETUP_PHASE;
	dwc3_ep0_out_start(dwc);
}

void dwc3_ep0_out_start(struct dwc3 *dwc)
{
	int				ret;

	ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
			DWC3_TRBCTL_CONTROL_SETUP);
	WARN_ON(ret < 0);
}

static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
{
	struct dwc3_ep		*dep;
	u32			windex = le16_to_cpu(wIndex_le);
	u32			epnum;

	epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
	if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
		epnum |= 1;

	dep = dwc->eps[epnum];
	if (dep->flags & DWC3_EP_ENABLED)
		return dep;

	return NULL;
}

static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
{
	dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
			dwc->ep0_usb_req.length,
			DWC3_TRBCTL_CONTROL_DATA);
	dwc->ep0_status_pending = 1;
}

/*
 * ch 9.4.5
 */
static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	struct dwc3_ep		*dep;
	u32			recip;
	u16			usb_status = 0;
	__le16			*response_pkt;

	recip = ctrl->bRequestType & USB_RECIP_MASK;
	switch (recip) {
	case USB_RECIP_DEVICE:
		/*
		 * We are self-powered. U1/U2/LTM will be set later
		 * once we handle this states. RemoteWakeup is 0 on SS
		 */
		usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
		break;

	case USB_RECIP_INTERFACE:
		/*
		 * Function Remote Wake Capable	D0
		 * Function Remote Wakeup	D1
		 */
		break;

	case USB_RECIP_ENDPOINT:
		dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
		if (!dep)
		       return -EINVAL;

		if (dep->flags & DWC3_EP_STALL)
			usb_status = 1 << USB_ENDPOINT_HALT;
		break;
	default:
		return -EINVAL;
	};

	response_pkt = (__le16 *) dwc->setup_buf;
	*response_pkt = cpu_to_le16(usb_status);
	dwc->ep0_usb_req.length = sizeof(*response_pkt);
	dwc3_ep0_send_status_response(dwc);

	return 0;
}

static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
		struct usb_ctrlrequest *ctrl, int set)
{
	struct dwc3_ep		*dep;
	u32			recip;
	u32			wValue;
	u32			wIndex;
	u32			reg;
	int			ret;
	u32			mode;

	wValue = le16_to_cpu(ctrl->wValue);
	wIndex = le16_to_cpu(ctrl->wIndex);
	recip = ctrl->bRequestType & USB_RECIP_MASK;
	switch (recip) {
	case USB_RECIP_DEVICE:

		/*
		 * 9.4.1 says only only for SS, in AddressState only for
		 * default control pipe
		 */
		switch (wValue) {
		case USB_DEVICE_U1_ENABLE:
		case USB_DEVICE_U2_ENABLE:
		case USB_DEVICE_LTM_ENABLE:
			if (dwc->dev_state != DWC3_CONFIGURED_STATE)
				return -EINVAL;
			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
				return -EINVAL;
		}

		/* XXX add U[12] & LTM */
		switch (wValue) {
		case USB_DEVICE_REMOTE_WAKEUP:
			break;
		case USB_DEVICE_U1_ENABLE:
			break;
		case USB_DEVICE_U2_ENABLE:
			break;
		case USB_DEVICE_LTM_ENABLE:
			break;

		case USB_DEVICE_TEST_MODE:
			if ((wIndex & 0xff) != 0)
				return -EINVAL;
			if (!set)
				return -EINVAL;

			mode = wIndex >> 8;
			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
			reg &= ~DWC3_DCTL_TSTCTRL_MASK;

			switch (mode) {
			case TEST_J:
			case TEST_K:
			case TEST_SE0_NAK:
			case TEST_PACKET:
			case TEST_FORCE_EN:
				reg |= mode << 1;
				break;
			default:
				return -EINVAL;
			}
			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
			break;
		default:
			return -EINVAL;
		}
		break;

	case USB_RECIP_INTERFACE:
		switch (wValue) {
		case USB_INTRF_FUNC_SUSPEND:
			if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
				/* XXX enable Low power suspend */
				;
			if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
				/* XXX enable remote wakeup */
				;
			break;
		default:
			return -EINVAL;
		}
		break;

	case USB_RECIP_ENDPOINT:
		switch (wValue) {
		case USB_ENDPOINT_HALT:

			dep =  dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
			if (!dep)
				return -EINVAL;
			ret = __dwc3_gadget_ep_set_halt(dep, set);
			if (ret)
				return -EINVAL;
			break;
		default:
			return -EINVAL;
		}
		break;

	default:
		return -EINVAL;
	};

	return 0;
}

static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	int ret = 0;
	u32 addr;
	u32 reg;

	addr = le16_to_cpu(ctrl->wValue);
	if (addr > 127)
		return -EINVAL;

	switch (dwc->dev_state) {
	case DWC3_DEFAULT_STATE:
	case DWC3_ADDRESS_STATE:
		/*
		 * Not sure if we should program DevAddr now or later
		 */
		reg = dwc3_readl(dwc->regs, DWC3_DCFG);
		reg &= ~(DWC3_DCFG_DEVADDR_MASK);
		reg |= DWC3_DCFG_DEVADDR(addr);
		dwc3_writel(dwc->regs, DWC3_DCFG, reg);

		if (addr)
			dwc->dev_state = DWC3_ADDRESS_STATE;
		else
			dwc->dev_state = DWC3_DEFAULT_STATE;
		break;

	case DWC3_CONFIGURED_STATE:
		ret = -EINVAL;
		break;
	}

	return ret;
}

static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	int ret;

	spin_unlock(&dwc->lock);
	ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
	spin_lock(&dwc->lock);
	return ret;
}

static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	u32 cfg;
	int ret;

	cfg = le16_to_cpu(ctrl->wValue);

	switch (dwc->dev_state) {
	case DWC3_DEFAULT_STATE:
		return -EINVAL;
		break;

	case DWC3_ADDRESS_STATE:
		ret = dwc3_ep0_delegate_req(dwc, ctrl);
		/* if the cfg matches and the cfg is non zero */
		if (!ret && cfg)
			dwc->dev_state = DWC3_CONFIGURED_STATE;
		break;

	case DWC3_CONFIGURED_STATE:
		ret = dwc3_ep0_delegate_req(dwc, ctrl);
		if (!cfg)
			dwc->dev_state = DWC3_ADDRESS_STATE;
		break;
	}
	return 0;
}

static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
	int ret;

	switch (ctrl->bRequest) {
	case USB_REQ_GET_STATUS:
		dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
		ret = dwc3_ep0_handle_status(dwc, ctrl);
		break;
	case USB_REQ_CLEAR_FEATURE:
		dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
		ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
		break;
	case USB_REQ_SET_FEATURE:
		dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
		ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
		break;
	case USB_REQ_SET_ADDRESS:
		dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
		ret = dwc3_ep0_set_address(dwc, ctrl);
		break;
	case USB_REQ_SET_CONFIGURATION:
		dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
		ret = dwc3_ep0_set_config(dwc, ctrl);
		break;
	default:
		dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
		ret = dwc3_ep0_delegate_req(dwc, ctrl);
		break;
	};

	return ret;
}

static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
	int ret;
	u32 len;

	if (!dwc->gadget_driver)
		goto err;

	len = le16_to_cpu(ctrl->wLength);
	if (!len)
		dwc->three_stage_setup = 0;
	else
		dwc->three_stage_setup = 1;

	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
		ret = dwc3_ep0_std_request(dwc, ctrl);
	else
		ret = dwc3_ep0_delegate_req(dwc, ctrl);

	if (ret >= 0)
		return;

err:
	dwc3_ep0_stall_and_restart(dwc);
}

static void dwc3_ep0_complete_data(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct dwc3_request	*r = NULL;
	struct usb_request	*ur;
	struct dwc3_trb		trb;
	struct dwc3_ep		*dep;
	u32			transferred;
	u8			epnum;

	epnum = event->endpoint_number;
	dep = dwc->eps[epnum];

	if (!dwc->ep0_status_pending) {
		r = next_request(&dwc->eps[0]->request_list);
		ur = &r->request;
	} else {
		ur = &dwc->ep0_usb_req;
		dwc->ep0_status_pending = 0;
	}

	dwc3_trb_to_nat(dwc->ep0_trb, &trb);

	if (dwc->ep0_bounced) {
		struct dwc3_ep	*ep0 = dwc->eps[0];

		transferred = min_t(u32, ur->length,
				ep0->endpoint.maxpacket - trb.length);
		memcpy(ur->buf, dwc->ep0_bounce, transferred);
		dwc->ep0_bounced = false;
	} else {
		transferred = ur->length - trb.length;
		ur->actual += transferred;
	}

	if ((epnum & 1) && ur->actual < ur->length) {
		/* for some reason we did not get everything out */

		dwc3_ep0_stall_and_restart(dwc);
		dwc3_gadget_giveback(dep, r, -ECONNRESET);
	} else {
		/*
		 * handle the case where we have to send a zero packet. This
		 * seems to be case when req.length > maxpacket. Could it be?
		 */
		if (r)
			dwc3_gadget_giveback(dep, r, 0);
	}
}

static void dwc3_ep0_complete_req(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct dwc3_request	*r;
	struct dwc3_ep		*dep;

	dep = dwc->eps[0];

	if (!list_empty(&dep->request_list)) {
		r = next_request(&dep->request_list);

		dwc3_gadget_giveback(dep, r, 0);
	}

	dwc->ep0state = EP0_SETUP_PHASE;
	dwc3_ep0_out_start(dwc);
}

static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
			const struct dwc3_event_depevt *event)
{
	struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];

	dep->flags &= ~DWC3_EP_BUSY;

	switch (dwc->ep0state) {
	case EP0_SETUP_PHASE:
		dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
		dwc3_ep0_inspect_setup(dwc, event);
		break;

	case EP0_DATA_PHASE:
		dev_vdbg(dwc->dev, "Data Phase\n");
		dwc3_ep0_complete_data(dwc, event);
		break;

	case EP0_STATUS_PHASE:
		dev_vdbg(dwc->dev, "Status Phase\n");
		dwc3_ep0_complete_req(dwc, event);
		break;
	default:
		WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
	}
}

static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	dwc->ep0state = EP0_SETUP_PHASE;
	dwc3_ep0_out_start(dwc);
}

static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	struct dwc3_ep		*dep;
	struct dwc3_request	*req;
	int			ret;

	dep = dwc->eps[0];
	dwc->ep0state = EP0_DATA_PHASE;

	if (list_empty(&dep->request_list)) {
		dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
		dep->flags |= DWC3_EP_PENDING_REQUEST;

		if (event->endpoint_number)
			dep->flags |= DWC3_EP0_DIR_IN;
		return;
	}

	req = next_request(&dep->request_list);
	req->direction = !!event->endpoint_number;

	dwc->ep0state = EP0_DATA_PHASE;
	if (req->request.length == 0) {
		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
				dwc->ctrl_req_addr, 0,
				DWC3_TRBCTL_CONTROL_DATA);
	} else if ((req->request.length % dep->endpoint.maxpacket)
			&& (event->endpoint_number == 0)) {
		dwc3_map_buffer_to_dma(req);

		WARN_ON(req->request.length > dep->endpoint.maxpacket);

		dwc->ep0_bounced = true;

		/*
		 * REVISIT in case request length is bigger than EP0
		 * wMaxPacketSize, we will need two chained TRBs to handle
		 * the transfer.
		 */
		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
				dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
				DWC3_TRBCTL_CONTROL_DATA);
	} else {
		dwc3_map_buffer_to_dma(req);

		ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
				req->request.dma, req->request.length,
				DWC3_TRBCTL_CONTROL_DATA);
	}

	WARN_ON(ret < 0);
}

static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	u32			type;
	int			ret;

	dwc->ep0state = EP0_STATUS_PHASE;

	type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
		: DWC3_TRBCTL_CONTROL_STATUS2;

	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
			dwc->ctrl_req_addr, 0, type);

	WARN_ON(ret < 0);
}

static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
		const struct dwc3_event_depevt *event)
{
	switch (event->status) {
	case DEPEVT_STATUS_CONTROL_SETUP:
		dev_vdbg(dwc->dev, "Control Setup\n");
		dwc3_ep0_do_control_setup(dwc, event);
		break;
	case DEPEVT_STATUS_CONTROL_DATA:
		dev_vdbg(dwc->dev, "Control Data\n");
		dwc3_ep0_do_control_data(dwc, event);
		break;
	case DEPEVT_STATUS_CONTROL_STATUS:
		dev_vdbg(dwc->dev, "Control Status\n");
		dwc3_ep0_do_control_status(dwc, event);
	}
}

void dwc3_ep0_interrupt(struct dwc3 *dwc,
		const const struct dwc3_event_depevt *event)
{
	u8			epnum = event->endpoint_number;

	dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
			dwc3_ep_event_string(event->endpoint_event),
			epnum, (epnum & 1) ? "in" : "out",
			dwc3_ep0_state_string(dwc->ep0state));

	switch (event->endpoint_event) {
	case DWC3_DEPEVT_XFERCOMPLETE:
		dwc3_ep0_xfer_complete(dwc, event);
		break;

	case DWC3_DEPEVT_XFERNOTREADY:
		dwc3_ep0_xfernotready(dwc, event);
		break;

	case DWC3_DEPEVT_XFERINPROGRESS:
	case DWC3_DEPEVT_RXTXFIFOEVT:
	case DWC3_DEPEVT_STREAMEVT:
	case DWC3_DEPEVT_EPCMDCMPLT:
		break;
	}
}
Commit	Line	Data
72246da4 FB	1	/**
	2	* ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
	5	* All rights reserved.
	6	*
	7	* Authors: Felipe Balbi <balbi@ti.com>,
	8	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	9	*
	10	* Redistribution and use in source and binary forms, with or without
	11	* modification, are permitted provided that the following conditions
	12	* are met:
	13	* 1. Redistributions of source code must retain the above copyright
	14	* notice, this list of conditions, and the following disclaimer,
	15	* without modification.
	16	* 2. Redistributions in binary form must reproduce the above copyright
	17	* notice, this list of conditions and the following disclaimer in the
	18	* documentation and/or other materials provided with the distribution.
	19	* 3. The names of the above-listed copyright holders may not be used
	20	* to endorse or promote products derived from this software without
	21	* specific prior written permission.
	22	*
	23	* ALTERNATIVELY, this software may be distributed under the terms of the
	24	* GNU General Public License ("GPL") version 2, as published by the Free
	25	* Software Foundation.
	26	*
	27	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	28	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	29	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	30	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	31	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	32	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	33	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	34	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	35	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	36	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	37	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	38	*/
	39
	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/io.h>
	47	#include <linux/list.h>
	48	#include <linux/dma-mapping.h>
	49
	50	#include <linux/usb/ch9.h>
	51	#include <linux/usb/gadget.h>
	52
	53	#include "core.h"
	54	#include "gadget.h"
	55	#include "io.h"
	56
	57	static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
	58	const struct dwc3_event_depevt *event);
	59
	60	static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
	61	{
	62	switch (state) {
	63	case EP0_UNCONNECTED:
	64	return "Unconnected";
c7fcdeb2 FB	65	case EP0_SETUP_PHASE:
	66	return "Setup Phase";
	67	case EP0_DATA_PHASE:
	68	return "Data Phase";
	69	case EP0_STATUS_PHASE:
	70	return "Status Phase";
72246da4 FB	71	default:
	72	return "UNKNOWN";
	73	}
	74	}
	75
	76	static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
c7fcdeb2	77	u32 len, u32 type)
72246da4 FB	78	{
	79	struct dwc3_gadget_ep_cmd_params params;
	80	struct dwc3_trb_hw *trb_hw;
	81	struct dwc3_trb trb;
	82	struct dwc3_ep *dep;
	83
	84	int ret;
	85
	86	dep = dwc->eps[epnum];
c7fcdeb2 FB	87	if (dep->flags & DWC3_EP_BUSY) {
	88	dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
	89	return 0;
	90	}
72246da4 FB	91
	92	trb_hw = dwc->ep0_trb;
	93	memset(&trb, 0, sizeof(trb));
	94
c7fcdeb2	95	trb.trbctl = type;
72246da4 FB	96	trb.bplh = buf_dma;
	97	trb.length = len;
	98
	99	trb.hwo = 1;
	100	trb.lst = 1;
	101	trb.ioc = 1;
	102	trb.isp_imi = 1;
	103
	104	dwc3_trb_to_hw(&trb, trb_hw);
	105
	106	memset(&params, 0, sizeof(params));
	107	params.param0.depstrtxfer.transfer_desc_addr_high =
	108	upper_32_bits(dwc->ep0_trb_addr);
	109	params.param1.depstrtxfer.transfer_desc_addr_low =
	110	lower_32_bits(dwc->ep0_trb_addr);
	111
	112	ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
	113	DWC3_DEPCMD_STARTTRANSFER, &params);
	114	if (ret < 0) {
	115	dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
	116	return ret;
	117	}
	118
c7fcdeb2	119	dep->flags \|= DWC3_EP_BUSY;
72246da4 FB	120	dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
	121	dep->number);
	122
	123	return 0;
	124	}
	125
	126	static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
	127	struct dwc3_request *req)
	128	{
c7fcdeb2	129	int ret = 0;
72246da4 FB	130
	131	req->request.actual = 0;
	132	req->request.status = -EINPROGRESS;
72246da4 FB	133	req->epnum = dep->number;
	134
	135	list_add_tail(&req->list, &dep->request_list);
a6829706	136
c7fcdeb2 FB	137	/*
	138	* Gadget driver might not be quick enough to queue a request
	139	* before we get a Transfer Not Ready event on this endpoint.
	140	*
	141	* In that case, we will set DWC3_EP_PENDING_REQUEST. When that
	142	* flag is set, it's telling us that as soon as Gadget queues the
	143	* required request, we should kick the transfer here because the
	144	* IRQ we were waiting for is long gone.
	145	*/
	146	if (dep->flags & DWC3_EP_PENDING_REQUEST) {
	147	struct dwc3 *dwc = dep->dwc;
	148	unsigned direction;
	149	u32 type;
	150
	151	direction = !!(dep->flags & DWC3_EP0_DIR_IN);
	152
	153	if (dwc->ep0state == EP0_STATUS_PHASE) {
	154	type = dwc->three_stage_setup
	155	? DWC3_TRBCTL_CONTROL_STATUS3
	156	: DWC3_TRBCTL_CONTROL_STATUS2;
	157	} else if (dwc->ep0state == EP0_DATA_PHASE) {
	158	type = DWC3_TRBCTL_CONTROL_DATA;
	159	} else {
	160	/* should never happen */
	161	WARN_ON(1);
	162	return 0;
	163	}
72246da4	164
c7fcdeb2 FB	165	ret = dwc3_ep0_start_trans(dwc, direction,
	166	req->request.dma, req->request.length, type);
	167	dep->flags &= ~(DWC3_EP_PENDING_REQUEST \|
	168	DWC3_EP0_DIR_IN);
72246da4 FB	169	}
	170
	171	return ret;
	172	}
	173
	174	int dwc3_gadget_ep0_queue(struct usb_ep ep, struct usb_request request,
	175	gfp_t gfp_flags)
	176	{
	177	struct dwc3_request *req = to_dwc3_request(request);
	178	struct dwc3_ep *dep = to_dwc3_ep(ep);
	179	struct dwc3 *dwc = dep->dwc;
	180
	181	unsigned long flags;
	182
	183	int ret;
	184
72246da4 FB	185	spin_lock_irqsave(&dwc->lock, flags);
	186	if (!dep->desc) {
	187	dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
	188	request, dep->name);
	189	ret = -ESHUTDOWN;
	190	goto out;
	191	}
	192
	193	/* we share one TRB for ep0/1 */
	194	if (!list_empty(&dwc->eps[0]->request_list) \|\|
	195	!list_empty(&dwc->eps[1]->request_list) \|\|
	196	dwc->ep0_status_pending) {
	197	ret = -EBUSY;
	198	goto out;
	199	}
	200
	201	dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
	202	request, dep->name, request->length,
	203	dwc3_ep0_state_string(dwc->ep0state));
	204
	205	ret = __dwc3_gadget_ep0_queue(dep, req);
	206
	207	out:
	208	spin_unlock_irqrestore(&dwc->lock, flags);
	209
	210	return ret;
	211	}
	212
	213	static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
	214	{
	215	/* stall is always issued on EP0 */
	216	__dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
76cb323f	217	dwc->eps[0]->flags = DWC3_EP_ENABLED;
c7fcdeb2	218	dwc->ep0state = EP0_SETUP_PHASE;
72246da4 FB	219	dwc3_ep0_out_start(dwc);
	220	}
	221
	222	void dwc3_ep0_out_start(struct dwc3 *dwc)
	223	{
72246da4 FB	224	int ret;
72246da4 FB	225
c7fcdeb2 FB	226	ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
c7fcdeb2 FB	227	DWC3_TRBCTL_CONTROL_SETUP);
72246da4 FB	228	WARN_ON(ret < 0);
	229	}
	230
72246da4 FB	231	static struct dwc3_ep dwc3_wIndex_to_dep(struct dwc3 dwc, __le16 wIndex_le)
	232	{
	233	struct dwc3_ep *dep;
	234	u32 windex = le16_to_cpu(wIndex_le);
	235	u32 epnum;
	236
	237	epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
	238	if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
	239	epnum \|= 1;
	240
	241	dep = dwc->eps[epnum];
	242	if (dep->flags & DWC3_EP_ENABLED)
	243	return dep;
	244
	245	return NULL;
	246	}
	247
	248	static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
	249	{
b673cf30	250	dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
c7fcdeb2 FB	251	dwc->ep0_usb_req.length,
c7fcdeb2 FB	252	DWC3_TRBCTL_CONTROL_DATA);
72246da4 FB	253	dwc->ep0_status_pending = 1;
	254	}
	255
	256	/*
	257	* ch 9.4.5
	258	*/
	259	static int dwc3_ep0_handle_status(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	260	{
	261	struct dwc3_ep *dep;
	262	u32 recip;
	263	u16 usb_status = 0;
	264	__le16 *response_pkt;
	265
	266	recip = ctrl->bRequestType & USB_RECIP_MASK;
	267	switch (recip) {
	268	case USB_RECIP_DEVICE:
	269	/*
	270	* We are self-powered. U1/U2/LTM will be set later
	271	* once we handle this states. RemoteWakeup is 0 on SS
	272	*/
	273	usb_status \|= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
	274	break;
	275
	276	case USB_RECIP_INTERFACE:
	277	/*
	278	* Function Remote Wake Capable D0
	279	* Function Remote Wakeup D1
	280	*/
	281	break;
	282
	283	case USB_RECIP_ENDPOINT:
	284	dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
	285	if (!dep)
	286	return -EINVAL;
	287
	288	if (dep->flags & DWC3_EP_STALL)
	289	usb_status = 1 << USB_ENDPOINT_HALT;
	290	break;
	291	default:
	292	return -EINVAL;
	293	};
	294
	295	response_pkt = (__le16 *) dwc->setup_buf;
	296	*response_pkt = cpu_to_le16(usb_status);
	297	dwc->ep0_usb_req.length = sizeof(*response_pkt);
	298	dwc3_ep0_send_status_response(dwc);
	299
	300	return 0;
	301	}
	302
	303	static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
	304	struct usb_ctrlrequest *ctrl, int set)
	305	{
	306	struct dwc3_ep *dep;
	307	u32 recip;
	308	u32 wValue;
	309	u32 wIndex;
	310	u32 reg;
	311	int ret;
	312	u32 mode;
	313
	314	wValue = le16_to_cpu(ctrl->wValue);
	315	wIndex = le16_to_cpu(ctrl->wIndex);
	316	recip = ctrl->bRequestType & USB_RECIP_MASK;
317	switch (recip) {
318	case USB_RECIP_DEVICE:
319
320	/*
321	* 9.4.1 says only only for SS, in AddressState only for
322	* default control pipe
323	*/
324	switch (wValue) {
325	case USB_DEVICE_U1_ENABLE:
326	case USB_DEVICE_U2_ENABLE:
327	case USB_DEVICE_LTM_ENABLE:
328	if (dwc->dev_state != DWC3_CONFIGURED_STATE)
329	return -EINVAL;
330	if (dwc->speed != DWC3_DSTS_SUPERSPEED)
331	return -EINVAL;
332	}
333
334	/* XXX add U[12] & LTM */
335	switch (wValue) {
336	case USB_DEVICE_REMOTE_WAKEUP:
337	break;
338	case USB_DEVICE_U1_ENABLE:
339	break;
340	case USB_DEVICE_U2_ENABLE:
341	break;
342	case USB_DEVICE_LTM_ENABLE:
343	break;
344
345	case USB_DEVICE_TEST_MODE:
346	if ((wIndex & 0xff) != 0)
347	return -EINVAL;
348	if (!set)
349	return -EINVAL;
350
351	mode = wIndex >> 8;
352	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
353	reg &= ~DWC3_DCTL_TSTCTRL_MASK;
354
355	switch (mode) {
356	case TEST_J:
357	case TEST_K:
358	case TEST_SE0_NAK:
359	case TEST_PACKET:
360	case TEST_FORCE_EN:
361	reg \|= mode << 1;
362	break;
363	default:
364	return -EINVAL;
365	}
366	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
367	break;
368	default:
369	return -EINVAL;
370	}
371	break;
372
373	case USB_RECIP_INTERFACE:
374	switch (wValue) {
375	case USB_INTRF_FUNC_SUSPEND:
376	if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
377	/* XXX enable Low power suspend */
378	;
379	if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
380	/* XXX enable remote wakeup */
381	;
382	break;
383	default:
384	return -EINVAL;
385	}
386	break;
387
388	case USB_RECIP_ENDPOINT:
389	switch (wValue) {
390	case USB_ENDPOINT_HALT:
391
392	dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
393	if (!dep)
394	return -EINVAL;
395	ret = __dwc3_gadget_ep_set_halt(dep, set);
396	if (ret)
397	return -EINVAL;
398	break;
399	default:
400	return -EINVAL;
401	}
402	break;
403
404	default:
405	return -EINVAL;
406	};
407
72246da4 FB	408	return 0;
	409	}
	410
	411	static int dwc3_ep0_set_address(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	412	{
	413	int ret = 0;
	414	u32 addr;
	415	u32 reg;
	416
	417	addr = le16_to_cpu(ctrl->wValue);
	418	if (addr > 127)
	419	return -EINVAL;
	420
	421	switch (dwc->dev_state) {
	422	case DWC3_DEFAULT_STATE:
	423	case DWC3_ADDRESS_STATE:
	424	/*
	425	* Not sure if we should program DevAddr now or later
	426	*/
	427	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
	428	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
	429	reg \|= DWC3_DCFG_DEVADDR(addr);
	430	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
	431
	432	if (addr)
	433	dwc->dev_state = DWC3_ADDRESS_STATE;
	434	else
	435	dwc->dev_state = DWC3_DEFAULT_STATE;
	436	break;
	437
	438	case DWC3_CONFIGURED_STATE:
	439	ret = -EINVAL;
	440	break;
	441	}
c7fcdeb2	442
72246da4 FB	443	return ret;
	444	}
	445
	446	static int dwc3_ep0_delegate_req(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	447	{
	448	int ret;
	449
	450	spin_unlock(&dwc->lock);
	451	ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
	452	spin_lock(&dwc->lock);
	453	return ret;
	454	}
	455
	456	static int dwc3_ep0_set_config(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	457	{
	458	u32 cfg;
	459	int ret;
	460
	461	cfg = le16_to_cpu(ctrl->wValue);
	462
	463	switch (dwc->dev_state) {
	464	case DWC3_DEFAULT_STATE:
	465	return -EINVAL;
	466	break;
	467
	468	case DWC3_ADDRESS_STATE:
	469	ret = dwc3_ep0_delegate_req(dwc, ctrl);
	470	/* if the cfg matches and the cfg is non zero */
	471	if (!ret && cfg)
	472	dwc->dev_state = DWC3_CONFIGURED_STATE;
	473	break;
	474
	475	case DWC3_CONFIGURED_STATE:
	476	ret = dwc3_ep0_delegate_req(dwc, ctrl);
	477	if (!cfg)
	478	dwc->dev_state = DWC3_ADDRESS_STATE;
	479	break;
	480	}
	481	return 0;
	482	}
	483
	484	static int dwc3_ep0_std_request(struct dwc3 dwc, struct usb_ctrlrequest ctrl)
	485	{
	486	int ret;
	487
	488	switch (ctrl->bRequest) {
	489	case USB_REQ_GET_STATUS:
	490	dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
	491	ret = dwc3_ep0_handle_status(dwc, ctrl);
	492	break;
	493	case USB_REQ_CLEAR_FEATURE:
	494	dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
	495	ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
	496	break;
	497	case USB_REQ_SET_FEATURE:
	498	dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
	499	ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
	500	break;
	501	case USB_REQ_SET_ADDRESS:
	502	dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
	503	ret = dwc3_ep0_set_address(dwc, ctrl);
	504	break;
	505	case USB_REQ_SET_CONFIGURATION:
	506	dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
507	ret = dwc3_ep0_set_config(dwc, ctrl);
508	break;
509	default:
510	dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
511	ret = dwc3_ep0_delegate_req(dwc, ctrl);
512	break;
513	};
514
515	return ret;
516	}
517
518	static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
519	const struct dwc3_event_depevt *event)
520	{
521	struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
522	int ret;
523	u32 len;
524
525	if (!dwc->gadget_driver)
526	goto err;
527
528	len = le16_to_cpu(ctrl->wLength);
c7fcdeb2	529	if (!len)
72246da4	530	dwc->three_stage_setup = 0;
c7fcdeb2	531	else
72246da4	532	dwc->three_stage_setup = 1;
72246da4 FB	533
	534	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
	535	ret = dwc3_ep0_std_request(dwc, ctrl);
	536	else
	537	ret = dwc3_ep0_delegate_req(dwc, ctrl);
	538
	539	if (ret >= 0)
	540	return;
	541
	542	err:
	543	dwc3_ep0_stall_and_restart(dwc);
	544	}
	545
	546	static void dwc3_ep0_complete_data(struct dwc3 *dwc,
	547	const struct dwc3_event_depevt *event)
	548	{
	549	struct dwc3_request *r = NULL;
	550	struct usb_request *ur;
	551	struct dwc3_trb trb;
	552	struct dwc3_ep *dep;
c611ccb4	553	u32 transferred;
72246da4 FB	554	u8 epnum;
	555
	556	epnum = event->endpoint_number;
	557	dep = dwc->eps[epnum];
	558
	559	if (!dwc->ep0_status_pending) {
c7fcdeb2	560	r = next_request(&dwc->eps[0]->request_list);
72246da4 FB	561	ur = &r->request;
	562	} else {
	563	ur = &dwc->ep0_usb_req;
	564	dwc->ep0_status_pending = 0;
	565	}
	566
	567	dwc3_trb_to_nat(dwc->ep0_trb, &trb);
	568
a6829706 FB	569	if (dwc->ep0_bounced) {
	570	struct dwc3_ep *ep0 = dwc->eps[0];
	571
c7fcdeb2 FB	572	transferred = min_t(u32, ur->length,
c7fcdeb2 FB	573	ep0->endpoint.maxpacket - trb.length);
a6829706 FB	574	memcpy(ur->buf, dwc->ep0_bounce, transferred);
	575	dwc->ep0_bounced = false;
	576	} else {
	577	transferred = ur->length - trb.length;
	578	ur->actual += transferred;
	579	}
72246da4 FB	580
	581	if ((epnum & 1) && ur->actual < ur->length) {
	582	/* for some reason we did not get everything out */
	583
	584	dwc3_ep0_stall_and_restart(dwc);
	585	dwc3_gadget_giveback(dep, r, -ECONNRESET);
	586	} else {
	587	/*
	588	* handle the case where we have to send a zero packet. This
	589	* seems to be case when req.length > maxpacket. Could it be?
	590	*/
72246da4 FB	591	if (r)
	592	dwc3_gadget_giveback(dep, r, 0);
	593	}
	594	}
	595
	596	static void dwc3_ep0_complete_req(struct dwc3 *dwc,
	597	const struct dwc3_event_depevt *event)
	598	{
	599	struct dwc3_request *r;
	600	struct dwc3_ep *dep;
72246da4	601
c7fcdeb2	602	dep = dwc->eps[0];
72246da4 FB	603
	604	if (!list_empty(&dep->request_list)) {
	605	r = next_request(&dep->request_list);
	606
	607	dwc3_gadget_giveback(dep, r, 0);
	608	}
	609
c7fcdeb2	610	dwc->ep0state = EP0_SETUP_PHASE;
72246da4 FB	611	dwc3_ep0_out_start(dwc);
	612	}
	613
	614	static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
	615	const struct dwc3_event_depevt *event)
	616	{
c7fcdeb2 FB	617	struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
	618
	619	dep->flags &= ~DWC3_EP_BUSY;
	620
72246da4	621	switch (dwc->ep0state) {
c7fcdeb2 FB	622	case EP0_SETUP_PHASE:
c7fcdeb2 FB	623	dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
72246da4 FB	624	dwc3_ep0_inspect_setup(dwc, event);
	625	break;
	626
c7fcdeb2 FB	627	case EP0_DATA_PHASE:
c7fcdeb2 FB	628	dev_vdbg(dwc->dev, "Data Phase\n");
72246da4 FB	629	dwc3_ep0_complete_data(dwc, event);
	630	break;
	631
c7fcdeb2 FB	632	case EP0_STATUS_PHASE:
c7fcdeb2 FB	633	dev_vdbg(dwc->dev, "Status Phase\n");
72246da4 FB	634	dwc3_ep0_complete_req(dwc, event);
72246da4 FB	635	break;
c7fcdeb2 FB	636	default:
	637	WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
	638	}
	639	}
72246da4	640
c7fcdeb2 FB	641	static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
	642	const struct dwc3_event_depevt *event)
	643	{
	644	dwc->ep0state = EP0_SETUP_PHASE;
	645	dwc3_ep0_out_start(dwc);
	646	}
	647
	648	static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
	649	const struct dwc3_event_depevt *event)
	650	{
	651	struct dwc3_ep *dep;
	652	struct dwc3_request *req;
	653	int ret;
	654
	655	dep = dwc->eps[0];
	656	dwc->ep0state = EP0_DATA_PHASE;
	657
	658	if (list_empty(&dep->request_list)) {
	659	dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
	660	dep->flags \|= DWC3_EP_PENDING_REQUEST;
	661
	662	if (event->endpoint_number)
	663	dep->flags \|= DWC3_EP0_DIR_IN;
	664	return;
72246da4	665	}
c7fcdeb2 FB	666
	667	req = next_request(&dep->request_list);
	668	req->direction = !!event->endpoint_number;
	669
	670	dwc->ep0state = EP0_DATA_PHASE;
	671	if (req->request.length == 0) {
	672	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	673	dwc->ctrl_req_addr, 0,
	674	DWC3_TRBCTL_CONTROL_DATA);
	675	} else if ((req->request.length % dep->endpoint.maxpacket)
	676	&& (event->endpoint_number == 0)) {
	677	dwc3_map_buffer_to_dma(req);
	678
	679	WARN_ON(req->request.length > dep->endpoint.maxpacket);
	680
	681	dwc->ep0_bounced = true;
	682
	683	/*
	684	* REVISIT in case request length is bigger than EP0
	685	* wMaxPacketSize, we will need two chained TRBs to handle
	686	* the transfer.
	687	*/
	688	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	689	dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
	690	DWC3_TRBCTL_CONTROL_DATA);
	691	} else {
	692	dwc3_map_buffer_to_dma(req);
	693
	694	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	695	req->request.dma, req->request.length,
	696	DWC3_TRBCTL_CONTROL_DATA);
	697	}
	698
	699	WARN_ON(ret < 0);
72246da4 FB	700	}
72246da4 FB	701
c7fcdeb2	702	static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
72246da4 FB	703	const struct dwc3_event_depevt *event)
72246da4 FB	704	{
c7fcdeb2 FB	705	u32 type;
c7fcdeb2 FB	706	int ret;
72246da4	707
c7fcdeb2	708	dwc->ep0state = EP0_STATUS_PHASE;
72246da4	709
c7fcdeb2 FB	710	type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
	711	: DWC3_TRBCTL_CONTROL_STATUS2;
	712
	713	ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
	714	dwc->ctrl_req_addr, 0, type);
	715
	716	WARN_ON(ret < 0);
	717	}
	718
	719	static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
	720	const struct dwc3_event_depevt *event)
	721	{
	722	switch (event->status) {
	723	case DEPEVT_STATUS_CONTROL_SETUP:
	724	dev_vdbg(dwc->dev, "Control Setup\n");
	725	dwc3_ep0_do_control_setup(dwc, event);
	726	break;
	727	case DEPEVT_STATUS_CONTROL_DATA:
	728	dev_vdbg(dwc->dev, "Control Data\n");
	729	dwc3_ep0_do_control_data(dwc, event);
	730	break;
	731	case DEPEVT_STATUS_CONTROL_STATUS:
	732	dev_vdbg(dwc->dev, "Control Status\n");
	733	dwc3_ep0_do_control_status(dwc, event);
72246da4 FB	734	}
	735	}
	736
	737	void dwc3_ep0_interrupt(struct dwc3 *dwc,
	738	const const struct dwc3_event_depevt *event)
	739	{
	740	u8 epnum = event->endpoint_number;
	741
	742	dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
	743	dwc3_ep_event_string(event->endpoint_event),
	744	epnum, (epnum & 1) ? "in" : "out",
	745	dwc3_ep0_state_string(dwc->ep0state));
	746
	747	switch (event->endpoint_event) {
	748	case DWC3_DEPEVT_XFERCOMPLETE:
	749	dwc3_ep0_xfer_complete(dwc, event);
	750	break;
	751
	752	case DWC3_DEPEVT_XFERNOTREADY:
	753	dwc3_ep0_xfernotready(dwc, event);
	754	break;
	755
	756	case DWC3_DEPEVT_XFERINPROGRESS:
	757	case DWC3_DEPEVT_RXTXFIFOEVT:
	758	case DWC3_DEPEVT_STREAMEVT:
	759	case DWC3_DEPEVT_EPCMDCMPLT:
	760	break;
	761	}
	762	}