Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
5 | * All rights reserved. | |
6 | * | |
7 | * Authors: Felipe Balbi <balbi@ti.com>, | |
8 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions, and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce the above copyright | |
17 | * notice, this list of conditions and the following disclaimer in the | |
18 | * documentation and/or other materials provided with the distribution. | |
19 | * 3. The names of the above-listed copyright holders may not be used | |
20 | * to endorse or promote products derived from this software without | |
21 | * specific prior written permission. | |
22 | * | |
23 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
24 | * GNU General Public License ("GPL") version 2, as published by the Free | |
25 | * Software Foundation. | |
26 | * | |
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
28 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
29 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
30 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
31 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
32 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
33 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
34 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
35 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
36 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
37 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
38 | */ | |
39 | ||
40 | #include <linux/kernel.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/platform_device.h> | |
44 | #include <linux/pm_runtime.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/list.h> | |
48 | #include <linux/dma-mapping.h> | |
49 | ||
50 | #include <linux/usb/ch9.h> | |
51 | #include <linux/usb/gadget.h> | |
52 | ||
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
57 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
58 | const struct dwc3_event_depevt *event); | |
59 | ||
60 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) | |
61 | { | |
62 | switch (state) { | |
63 | case EP0_UNCONNECTED: | |
64 | return "Unconnected"; | |
c7fcdeb2 FB |
65 | case EP0_SETUP_PHASE: |
66 | return "Setup Phase"; | |
67 | case EP0_DATA_PHASE: | |
68 | return "Data Phase"; | |
69 | case EP0_STATUS_PHASE: | |
70 | return "Status Phase"; | |
72246da4 FB |
71 | default: |
72 | return "UNKNOWN"; | |
73 | } | |
74 | } | |
75 | ||
76 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 77 | u32 len, u32 type) |
72246da4 FB |
78 | { |
79 | struct dwc3_gadget_ep_cmd_params params; | |
80 | struct dwc3_trb_hw *trb_hw; | |
81 | struct dwc3_trb trb; | |
82 | struct dwc3_ep *dep; | |
83 | ||
84 | int ret; | |
85 | ||
86 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
87 | if (dep->flags & DWC3_EP_BUSY) { |
88 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
89 | return 0; | |
90 | } | |
72246da4 FB |
91 | |
92 | trb_hw = dwc->ep0_trb; | |
93 | memset(&trb, 0, sizeof(trb)); | |
94 | ||
c7fcdeb2 | 95 | trb.trbctl = type; |
72246da4 FB |
96 | trb.bplh = buf_dma; |
97 | trb.length = len; | |
98 | ||
99 | trb.hwo = 1; | |
100 | trb.lst = 1; | |
101 | trb.ioc = 1; | |
102 | trb.isp_imi = 1; | |
103 | ||
104 | dwc3_trb_to_hw(&trb, trb_hw); | |
105 | ||
106 | memset(¶ms, 0, sizeof(params)); | |
107 | params.param0.depstrtxfer.transfer_desc_addr_high = | |
108 | upper_32_bits(dwc->ep0_trb_addr); | |
109 | params.param1.depstrtxfer.transfer_desc_addr_low = | |
110 | lower_32_bits(dwc->ep0_trb_addr); | |
111 | ||
112 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
113 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
114 | if (ret < 0) { | |
115 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
116 | return ret; | |
117 | } | |
118 | ||
c7fcdeb2 | 119 | dep->flags |= DWC3_EP_BUSY; |
72246da4 FB |
120 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, |
121 | dep->number); | |
122 | ||
1ddcb218 FB |
123 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
124 | ||
72246da4 FB |
125 | return 0; |
126 | } | |
127 | ||
128 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
129 | struct dwc3_request *req) | |
130 | { | |
c7fcdeb2 | 131 | int ret = 0; |
72246da4 FB |
132 | |
133 | req->request.actual = 0; | |
134 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
135 | req->epnum = dep->number; |
136 | ||
137 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 138 | |
c7fcdeb2 FB |
139 | /* |
140 | * Gadget driver might not be quick enough to queue a request | |
141 | * before we get a Transfer Not Ready event on this endpoint. | |
142 | * | |
143 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
144 | * flag is set, it's telling us that as soon as Gadget queues the | |
145 | * required request, we should kick the transfer here because the | |
146 | * IRQ we were waiting for is long gone. | |
147 | */ | |
148 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
149 | struct dwc3 *dwc = dep->dwc; | |
150 | unsigned direction; | |
151 | u32 type; | |
152 | ||
153 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
154 | ||
155 | if (dwc->ep0state == EP0_STATUS_PHASE) { | |
156 | type = dwc->three_stage_setup | |
157 | ? DWC3_TRBCTL_CONTROL_STATUS3 | |
158 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
159 | } else if (dwc->ep0state == EP0_DATA_PHASE) { | |
160 | type = DWC3_TRBCTL_CONTROL_DATA; | |
161 | } else { | |
162 | /* should never happen */ | |
163 | WARN_ON(1); | |
164 | return 0; | |
165 | } | |
72246da4 | 166 | |
c7fcdeb2 FB |
167 | ret = dwc3_ep0_start_trans(dwc, direction, |
168 | req->request.dma, req->request.length, type); | |
169 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | | |
170 | DWC3_EP0_DIR_IN); | |
72246da4 FB |
171 | } |
172 | ||
173 | return ret; | |
174 | } | |
175 | ||
176 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
177 | gfp_t gfp_flags) | |
178 | { | |
179 | struct dwc3_request *req = to_dwc3_request(request); | |
180 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
181 | struct dwc3 *dwc = dep->dwc; | |
182 | ||
183 | unsigned long flags; | |
184 | ||
185 | int ret; | |
186 | ||
72246da4 FB |
187 | spin_lock_irqsave(&dwc->lock, flags); |
188 | if (!dep->desc) { | |
189 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", | |
190 | request, dep->name); | |
191 | ret = -ESHUTDOWN; | |
192 | goto out; | |
193 | } | |
194 | ||
195 | /* we share one TRB for ep0/1 */ | |
196 | if (!list_empty(&dwc->eps[0]->request_list) || | |
197 | !list_empty(&dwc->eps[1]->request_list) || | |
198 | dwc->ep0_status_pending) { | |
199 | ret = -EBUSY; | |
200 | goto out; | |
201 | } | |
202 | ||
203 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
204 | request, dep->name, request->length, | |
205 | dwc3_ep0_state_string(dwc->ep0state)); | |
206 | ||
207 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
208 | ||
209 | out: | |
210 | spin_unlock_irqrestore(&dwc->lock, flags); | |
211 | ||
212 | return ret; | |
213 | } | |
214 | ||
215 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
216 | { | |
217 | /* stall is always issued on EP0 */ | |
218 | __dwc3_gadget_ep_set_halt(dwc->eps[0], 1); | |
76cb323f | 219 | dwc->eps[0]->flags = DWC3_EP_ENABLED; |
c7fcdeb2 | 220 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
221 | dwc3_ep0_out_start(dwc); |
222 | } | |
223 | ||
224 | void dwc3_ep0_out_start(struct dwc3 *dwc) | |
225 | { | |
72246da4 FB |
226 | int ret; |
227 | ||
c7fcdeb2 FB |
228 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
229 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
230 | WARN_ON(ret < 0); |
231 | } | |
232 | ||
72246da4 FB |
233 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
234 | { | |
235 | struct dwc3_ep *dep; | |
236 | u32 windex = le16_to_cpu(wIndex_le); | |
237 | u32 epnum; | |
238 | ||
239 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
240 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
241 | epnum |= 1; | |
242 | ||
243 | dep = dwc->eps[epnum]; | |
244 | if (dep->flags & DWC3_EP_ENABLED) | |
245 | return dep; | |
246 | ||
247 | return NULL; | |
248 | } | |
249 | ||
250 | static void dwc3_ep0_send_status_response(struct dwc3 *dwc) | |
251 | { | |
b673cf30 | 252 | dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr, |
c7fcdeb2 FB |
253 | dwc->ep0_usb_req.length, |
254 | DWC3_TRBCTL_CONTROL_DATA); | |
72246da4 FB |
255 | } |
256 | ||
257 | /* | |
258 | * ch 9.4.5 | |
259 | */ | |
260 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
261 | { | |
262 | struct dwc3_ep *dep; | |
263 | u32 recip; | |
264 | u16 usb_status = 0; | |
265 | __le16 *response_pkt; | |
266 | ||
267 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
268 | switch (recip) { | |
269 | case USB_RECIP_DEVICE: | |
270 | /* | |
271 | * We are self-powered. U1/U2/LTM will be set later | |
272 | * once we handle this states. RemoteWakeup is 0 on SS | |
273 | */ | |
274 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
275 | break; | |
276 | ||
277 | case USB_RECIP_INTERFACE: | |
278 | /* | |
279 | * Function Remote Wake Capable D0 | |
280 | * Function Remote Wakeup D1 | |
281 | */ | |
282 | break; | |
283 | ||
284 | case USB_RECIP_ENDPOINT: | |
285 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
286 | if (!dep) | |
287 | return -EINVAL; | |
288 | ||
289 | if (dep->flags & DWC3_EP_STALL) | |
290 | usb_status = 1 << USB_ENDPOINT_HALT; | |
291 | break; | |
292 | default: | |
293 | return -EINVAL; | |
294 | }; | |
295 | ||
296 | response_pkt = (__le16 *) dwc->setup_buf; | |
297 | *response_pkt = cpu_to_le16(usb_status); | |
298 | dwc->ep0_usb_req.length = sizeof(*response_pkt); | |
1ddcb218 | 299 | dwc->ep0_status_pending = 1; |
72246da4 FB |
300 | |
301 | return 0; | |
302 | } | |
303 | ||
304 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
305 | struct usb_ctrlrequest *ctrl, int set) | |
306 | { | |
307 | struct dwc3_ep *dep; | |
308 | u32 recip; | |
309 | u32 wValue; | |
310 | u32 wIndex; | |
311 | u32 reg; | |
312 | int ret; | |
313 | u32 mode; | |
314 | ||
315 | wValue = le16_to_cpu(ctrl->wValue); | |
316 | wIndex = le16_to_cpu(ctrl->wIndex); | |
317 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
318 | switch (recip) { | |
319 | case USB_RECIP_DEVICE: | |
320 | ||
321 | /* | |
322 | * 9.4.1 says only only for SS, in AddressState only for | |
323 | * default control pipe | |
324 | */ | |
325 | switch (wValue) { | |
326 | case USB_DEVICE_U1_ENABLE: | |
327 | case USB_DEVICE_U2_ENABLE: | |
328 | case USB_DEVICE_LTM_ENABLE: | |
329 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) | |
330 | return -EINVAL; | |
331 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
332 | return -EINVAL; | |
333 | } | |
334 | ||
335 | /* XXX add U[12] & LTM */ | |
336 | switch (wValue) { | |
337 | case USB_DEVICE_REMOTE_WAKEUP: | |
338 | break; | |
339 | case USB_DEVICE_U1_ENABLE: | |
340 | break; | |
341 | case USB_DEVICE_U2_ENABLE: | |
342 | break; | |
343 | case USB_DEVICE_LTM_ENABLE: | |
344 | break; | |
345 | ||
346 | case USB_DEVICE_TEST_MODE: | |
347 | if ((wIndex & 0xff) != 0) | |
348 | return -EINVAL; | |
349 | if (!set) | |
350 | return -EINVAL; | |
351 | ||
352 | mode = wIndex >> 8; | |
353 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
354 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
355 | ||
356 | switch (mode) { | |
357 | case TEST_J: | |
358 | case TEST_K: | |
359 | case TEST_SE0_NAK: | |
360 | case TEST_PACKET: | |
361 | case TEST_FORCE_EN: | |
362 | reg |= mode << 1; | |
363 | break; | |
364 | default: | |
365 | return -EINVAL; | |
366 | } | |
367 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
368 | break; | |
369 | default: | |
370 | return -EINVAL; | |
371 | } | |
372 | break; | |
373 | ||
374 | case USB_RECIP_INTERFACE: | |
375 | switch (wValue) { | |
376 | case USB_INTRF_FUNC_SUSPEND: | |
377 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
378 | /* XXX enable Low power suspend */ | |
379 | ; | |
380 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
381 | /* XXX enable remote wakeup */ | |
382 | ; | |
383 | break; | |
384 | default: | |
385 | return -EINVAL; | |
386 | } | |
387 | break; | |
388 | ||
389 | case USB_RECIP_ENDPOINT: | |
390 | switch (wValue) { | |
391 | case USB_ENDPOINT_HALT: | |
392 | ||
393 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
394 | if (!dep) | |
395 | return -EINVAL; | |
396 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
397 | if (ret) | |
398 | return -EINVAL; | |
399 | break; | |
400 | default: | |
401 | return -EINVAL; | |
402 | } | |
403 | break; | |
404 | ||
405 | default: | |
406 | return -EINVAL; | |
407 | }; | |
408 | ||
72246da4 FB |
409 | return 0; |
410 | } | |
411 | ||
412 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
413 | { | |
414 | int ret = 0; | |
415 | u32 addr; | |
416 | u32 reg; | |
417 | ||
418 | addr = le16_to_cpu(ctrl->wValue); | |
419 | if (addr > 127) | |
420 | return -EINVAL; | |
421 | ||
422 | switch (dwc->dev_state) { | |
423 | case DWC3_DEFAULT_STATE: | |
424 | case DWC3_ADDRESS_STATE: | |
425 | /* | |
426 | * Not sure if we should program DevAddr now or later | |
427 | */ | |
428 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
429 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
430 | reg |= DWC3_DCFG_DEVADDR(addr); | |
431 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
432 | ||
433 | if (addr) | |
434 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
435 | else | |
436 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
437 | break; | |
438 | ||
439 | case DWC3_CONFIGURED_STATE: | |
440 | ret = -EINVAL; | |
441 | break; | |
442 | } | |
c7fcdeb2 | 443 | |
72246da4 FB |
444 | return ret; |
445 | } | |
446 | ||
447 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
448 | { | |
449 | int ret; | |
450 | ||
451 | spin_unlock(&dwc->lock); | |
452 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
453 | spin_lock(&dwc->lock); | |
454 | return ret; | |
455 | } | |
456 | ||
457 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
458 | { | |
459 | u32 cfg; | |
460 | int ret; | |
461 | ||
462 | cfg = le16_to_cpu(ctrl->wValue); | |
463 | ||
464 | switch (dwc->dev_state) { | |
465 | case DWC3_DEFAULT_STATE: | |
466 | return -EINVAL; | |
467 | break; | |
468 | ||
469 | case DWC3_ADDRESS_STATE: | |
470 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
471 | /* if the cfg matches and the cfg is non zero */ | |
472 | if (!ret && cfg) | |
473 | dwc->dev_state = DWC3_CONFIGURED_STATE; | |
474 | break; | |
475 | ||
476 | case DWC3_CONFIGURED_STATE: | |
477 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
478 | if (!cfg) | |
479 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
480 | break; | |
481 | } | |
482 | return 0; | |
483 | } | |
484 | ||
485 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
486 | { | |
487 | int ret; | |
488 | ||
489 | switch (ctrl->bRequest) { | |
490 | case USB_REQ_GET_STATUS: | |
491 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
492 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
493 | break; | |
494 | case USB_REQ_CLEAR_FEATURE: | |
495 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
496 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
497 | break; | |
498 | case USB_REQ_SET_FEATURE: | |
499 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
500 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
501 | break; | |
502 | case USB_REQ_SET_ADDRESS: | |
503 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
504 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
505 | break; | |
506 | case USB_REQ_SET_CONFIGURATION: | |
507 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
508 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
509 | break; | |
510 | default: | |
511 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
512 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
513 | break; | |
514 | }; | |
515 | ||
516 | return ret; | |
517 | } | |
518 | ||
519 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
520 | const struct dwc3_event_depevt *event) | |
521 | { | |
522 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
523 | int ret; | |
524 | u32 len; | |
525 | ||
526 | if (!dwc->gadget_driver) | |
527 | goto err; | |
528 | ||
529 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 530 | if (!len) { |
72246da4 | 531 | dwc->three_stage_setup = 0; |
1ddcb218 FB |
532 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
533 | } else { | |
72246da4 | 534 | dwc->three_stage_setup = 1; |
1ddcb218 FB |
535 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
536 | } | |
72246da4 FB |
537 | |
538 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
539 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
540 | else | |
541 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
542 | ||
543 | if (ret >= 0) | |
544 | return; | |
545 | ||
546 | err: | |
547 | dwc3_ep0_stall_and_restart(dwc); | |
548 | } | |
549 | ||
550 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
551 | const struct dwc3_event_depevt *event) | |
552 | { | |
553 | struct dwc3_request *r = NULL; | |
554 | struct usb_request *ur; | |
555 | struct dwc3_trb trb; | |
556 | struct dwc3_ep *dep; | |
c611ccb4 | 557 | u32 transferred; |
72246da4 FB |
558 | u8 epnum; |
559 | ||
560 | epnum = event->endpoint_number; | |
561 | dep = dwc->eps[epnum]; | |
562 | ||
1ddcb218 FB |
563 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
564 | ||
72246da4 | 565 | if (!dwc->ep0_status_pending) { |
c7fcdeb2 | 566 | r = next_request(&dwc->eps[0]->request_list); |
72246da4 FB |
567 | ur = &r->request; |
568 | } else { | |
569 | ur = &dwc->ep0_usb_req; | |
570 | dwc->ep0_status_pending = 0; | |
571 | } | |
572 | ||
573 | dwc3_trb_to_nat(dwc->ep0_trb, &trb); | |
574 | ||
a6829706 FB |
575 | if (dwc->ep0_bounced) { |
576 | struct dwc3_ep *ep0 = dwc->eps[0]; | |
577 | ||
c7fcdeb2 FB |
578 | transferred = min_t(u32, ur->length, |
579 | ep0->endpoint.maxpacket - trb.length); | |
a6829706 FB |
580 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
581 | dwc->ep0_bounced = false; | |
582 | } else { | |
583 | transferred = ur->length - trb.length; | |
584 | ur->actual += transferred; | |
585 | } | |
72246da4 FB |
586 | |
587 | if ((epnum & 1) && ur->actual < ur->length) { | |
588 | /* for some reason we did not get everything out */ | |
589 | ||
590 | dwc3_ep0_stall_and_restart(dwc); | |
591 | dwc3_gadget_giveback(dep, r, -ECONNRESET); | |
592 | } else { | |
593 | /* | |
594 | * handle the case where we have to send a zero packet. This | |
595 | * seems to be case when req.length > maxpacket. Could it be? | |
596 | */ | |
72246da4 FB |
597 | if (r) |
598 | dwc3_gadget_giveback(dep, r, 0); | |
599 | } | |
600 | } | |
601 | ||
602 | static void dwc3_ep0_complete_req(struct dwc3 *dwc, | |
603 | const struct dwc3_event_depevt *event) | |
604 | { | |
605 | struct dwc3_request *r; | |
606 | struct dwc3_ep *dep; | |
72246da4 | 607 | |
c7fcdeb2 | 608 | dep = dwc->eps[0]; |
72246da4 FB |
609 | |
610 | if (!list_empty(&dep->request_list)) { | |
611 | r = next_request(&dep->request_list); | |
612 | ||
613 | dwc3_gadget_giveback(dep, r, 0); | |
614 | } | |
615 | ||
c7fcdeb2 | 616 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
617 | dwc3_ep0_out_start(dwc); |
618 | } | |
619 | ||
620 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
621 | const struct dwc3_event_depevt *event) | |
622 | { | |
c7fcdeb2 FB |
623 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
624 | ||
625 | dep->flags &= ~DWC3_EP_BUSY; | |
626 | ||
72246da4 | 627 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
628 | case EP0_SETUP_PHASE: |
629 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
630 | dwc3_ep0_inspect_setup(dwc, event); |
631 | break; | |
632 | ||
c7fcdeb2 FB |
633 | case EP0_DATA_PHASE: |
634 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
635 | dwc3_ep0_complete_data(dwc, event); |
636 | break; | |
637 | ||
c7fcdeb2 FB |
638 | case EP0_STATUS_PHASE: |
639 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
72246da4 FB |
640 | dwc3_ep0_complete_req(dwc, event); |
641 | break; | |
c7fcdeb2 FB |
642 | default: |
643 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
644 | } | |
645 | } | |
72246da4 | 646 | |
c7fcdeb2 FB |
647 | static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, |
648 | const struct dwc3_event_depevt *event) | |
649 | { | |
650 | dwc->ep0state = EP0_SETUP_PHASE; | |
651 | dwc3_ep0_out_start(dwc); | |
652 | } | |
653 | ||
654 | static void dwc3_ep0_do_control_data(struct dwc3 *dwc, | |
655 | const struct dwc3_event_depevt *event) | |
656 | { | |
657 | struct dwc3_ep *dep; | |
658 | struct dwc3_request *req; | |
659 | int ret; | |
660 | ||
661 | dep = dwc->eps[0]; | |
662 | dwc->ep0state = EP0_DATA_PHASE; | |
663 | ||
1ddcb218 FB |
664 | if (dwc->ep0_status_pending) { |
665 | dwc3_ep0_send_status_response(dwc); | |
666 | return; | |
667 | } | |
668 | ||
c7fcdeb2 FB |
669 | if (list_empty(&dep->request_list)) { |
670 | dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); | |
671 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
672 | ||
673 | if (event->endpoint_number) | |
674 | dep->flags |= DWC3_EP0_DIR_IN; | |
675 | return; | |
72246da4 | 676 | } |
c7fcdeb2 FB |
677 | |
678 | req = next_request(&dep->request_list); | |
679 | req->direction = !!event->endpoint_number; | |
680 | ||
681 | dwc->ep0state = EP0_DATA_PHASE; | |
682 | if (req->request.length == 0) { | |
683 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
684 | dwc->ctrl_req_addr, 0, | |
685 | DWC3_TRBCTL_CONTROL_DATA); | |
686 | } else if ((req->request.length % dep->endpoint.maxpacket) | |
687 | && (event->endpoint_number == 0)) { | |
688 | dwc3_map_buffer_to_dma(req); | |
689 | ||
690 | WARN_ON(req->request.length > dep->endpoint.maxpacket); | |
691 | ||
692 | dwc->ep0_bounced = true; | |
693 | ||
694 | /* | |
695 | * REVISIT in case request length is bigger than EP0 | |
696 | * wMaxPacketSize, we will need two chained TRBs to handle | |
697 | * the transfer. | |
698 | */ | |
699 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
700 | dwc->ep0_bounce_addr, dep->endpoint.maxpacket, | |
701 | DWC3_TRBCTL_CONTROL_DATA); | |
702 | } else { | |
703 | dwc3_map_buffer_to_dma(req); | |
704 | ||
705 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
706 | req->request.dma, req->request.length, | |
707 | DWC3_TRBCTL_CONTROL_DATA); | |
708 | } | |
709 | ||
710 | WARN_ON(ret < 0); | |
72246da4 FB |
711 | } |
712 | ||
c7fcdeb2 | 713 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
72246da4 FB |
714 | const struct dwc3_event_depevt *event) |
715 | { | |
c7fcdeb2 FB |
716 | u32 type; |
717 | int ret; | |
72246da4 | 718 | |
c7fcdeb2 | 719 | dwc->ep0state = EP0_STATUS_PHASE; |
72246da4 | 720 | |
c7fcdeb2 FB |
721 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
722 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
723 | ||
724 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
725 | dwc->ctrl_req_addr, 0, type); | |
726 | ||
727 | WARN_ON(ret < 0); | |
728 | } | |
729 | ||
730 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, | |
731 | const struct dwc3_event_depevt *event) | |
732 | { | |
733 | switch (event->status) { | |
734 | case DEPEVT_STATUS_CONTROL_SETUP: | |
735 | dev_vdbg(dwc->dev, "Control Setup\n"); | |
736 | dwc3_ep0_do_control_setup(dwc, event); | |
737 | break; | |
1ddcb218 | 738 | |
c7fcdeb2 FB |
739 | case DEPEVT_STATUS_CONTROL_DATA: |
740 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 FB |
741 | |
742 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { | |
743 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
744 | DEPEVT_STATUS_CONTROL_DATA, | |
745 | event->status); | |
746 | ||
747 | dwc3_ep0_stall_and_restart(dwc); | |
748 | return; | |
749 | } | |
750 | ||
c7fcdeb2 FB |
751 | dwc3_ep0_do_control_data(dwc, event); |
752 | break; | |
1ddcb218 | 753 | |
c7fcdeb2 FB |
754 | case DEPEVT_STATUS_CONTROL_STATUS: |
755 | dev_vdbg(dwc->dev, "Control Status\n"); | |
1ddcb218 FB |
756 | |
757 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { | |
758 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
759 | DEPEVT_STATUS_CONTROL_STATUS, | |
760 | event->status); | |
761 | ||
762 | dwc3_ep0_stall_and_restart(dwc); | |
763 | return; | |
764 | } | |
c7fcdeb2 | 765 | dwc3_ep0_do_control_status(dwc, event); |
72246da4 FB |
766 | } |
767 | } | |
768 | ||
769 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
770 | const const struct dwc3_event_depevt *event) | |
771 | { | |
772 | u8 epnum = event->endpoint_number; | |
773 | ||
774 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
775 | dwc3_ep_event_string(event->endpoint_event), | |
776 | epnum, (epnum & 1) ? "in" : "out", | |
777 | dwc3_ep0_state_string(dwc->ep0state)); | |
778 | ||
779 | switch (event->endpoint_event) { | |
780 | case DWC3_DEPEVT_XFERCOMPLETE: | |
781 | dwc3_ep0_xfer_complete(dwc, event); | |
782 | break; | |
783 | ||
784 | case DWC3_DEPEVT_XFERNOTREADY: | |
785 | dwc3_ep0_xfernotready(dwc, event); | |
786 | break; | |
787 | ||
788 | case DWC3_DEPEVT_XFERINPROGRESS: | |
789 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
790 | case DWC3_DEPEVT_STREAMEVT: | |
791 | case DWC3_DEPEVT_EPCMDCMPLT: | |
792 | break; | |
793 | } | |
794 | } |