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72246da4 FB |
1 | /** |
2 | * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/platform_device.h> | |
43 | #include <linux/pm_runtime.h> | |
44 | #include <linux/interrupt.h> | |
45 | #include <linux/io.h> | |
46 | #include <linux/list.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | ||
49 | #include <linux/usb/ch9.h> | |
50 | #include <linux/usb/gadget.h> | |
51 | ||
52 | #include "core.h" | |
53 | #include "gadget.h" | |
54 | #include "io.h" | |
55 | ||
56 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
57 | const struct dwc3_event_depevt *event); | |
58 | ||
59 | static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) | |
60 | { | |
61 | switch (state) { | |
62 | case EP0_UNCONNECTED: | |
63 | return "Unconnected"; | |
c7fcdeb2 FB |
64 | case EP0_SETUP_PHASE: |
65 | return "Setup Phase"; | |
66 | case EP0_DATA_PHASE: | |
67 | return "Data Phase"; | |
68 | case EP0_STATUS_PHASE: | |
69 | return "Status Phase"; | |
72246da4 FB |
70 | default: |
71 | return "UNKNOWN"; | |
72 | } | |
73 | } | |
74 | ||
75 | static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, | |
c7fcdeb2 | 76 | u32 len, u32 type) |
72246da4 FB |
77 | { |
78 | struct dwc3_gadget_ep_cmd_params params; | |
79 | struct dwc3_trb_hw *trb_hw; | |
80 | struct dwc3_trb trb; | |
81 | struct dwc3_ep *dep; | |
82 | ||
83 | int ret; | |
84 | ||
85 | dep = dwc->eps[epnum]; | |
c7fcdeb2 FB |
86 | if (dep->flags & DWC3_EP_BUSY) { |
87 | dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); | |
88 | return 0; | |
89 | } | |
72246da4 FB |
90 | |
91 | trb_hw = dwc->ep0_trb; | |
92 | memset(&trb, 0, sizeof(trb)); | |
93 | ||
c7fcdeb2 | 94 | trb.trbctl = type; |
72246da4 FB |
95 | trb.bplh = buf_dma; |
96 | trb.length = len; | |
97 | ||
98 | trb.hwo = 1; | |
99 | trb.lst = 1; | |
100 | trb.ioc = 1; | |
101 | trb.isp_imi = 1; | |
102 | ||
103 | dwc3_trb_to_hw(&trb, trb_hw); | |
104 | ||
105 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
106 | params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
107 | params.param1 = lower_32_bits(dwc->ep0_trb_addr); | |
72246da4 FB |
108 | |
109 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
110 | DWC3_DEPCMD_STARTTRANSFER, ¶ms); | |
111 | if (ret < 0) { | |
112 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
113 | return ret; | |
114 | } | |
115 | ||
c7fcdeb2 | 116 | dep->flags |= DWC3_EP_BUSY; |
72246da4 FB |
117 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, |
118 | dep->number); | |
119 | ||
1ddcb218 FB |
120 | dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
121 | ||
72246da4 FB |
122 | return 0; |
123 | } | |
124 | ||
125 | static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, | |
126 | struct dwc3_request *req) | |
127 | { | |
c7fcdeb2 | 128 | int ret = 0; |
72246da4 FB |
129 | |
130 | req->request.actual = 0; | |
131 | req->request.status = -EINPROGRESS; | |
72246da4 FB |
132 | req->epnum = dep->number; |
133 | ||
134 | list_add_tail(&req->list, &dep->request_list); | |
a6829706 | 135 | |
c7fcdeb2 FB |
136 | /* |
137 | * Gadget driver might not be quick enough to queue a request | |
138 | * before we get a Transfer Not Ready event on this endpoint. | |
139 | * | |
140 | * In that case, we will set DWC3_EP_PENDING_REQUEST. When that | |
141 | * flag is set, it's telling us that as soon as Gadget queues the | |
142 | * required request, we should kick the transfer here because the | |
143 | * IRQ we were waiting for is long gone. | |
144 | */ | |
145 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
146 | struct dwc3 *dwc = dep->dwc; | |
147 | unsigned direction; | |
148 | u32 type; | |
149 | ||
150 | direction = !!(dep->flags & DWC3_EP0_DIR_IN); | |
151 | ||
152 | if (dwc->ep0state == EP0_STATUS_PHASE) { | |
153 | type = dwc->three_stage_setup | |
154 | ? DWC3_TRBCTL_CONTROL_STATUS3 | |
155 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
156 | } else if (dwc->ep0state == EP0_DATA_PHASE) { | |
157 | type = DWC3_TRBCTL_CONTROL_DATA; | |
158 | } else { | |
159 | /* should never happen */ | |
160 | WARN_ON(1); | |
161 | return 0; | |
162 | } | |
72246da4 | 163 | |
c7fcdeb2 FB |
164 | ret = dwc3_ep0_start_trans(dwc, direction, |
165 | req->request.dma, req->request.length, type); | |
166 | dep->flags &= ~(DWC3_EP_PENDING_REQUEST | | |
167 | DWC3_EP0_DIR_IN); | |
72246da4 FB |
168 | } |
169 | ||
170 | return ret; | |
171 | } | |
172 | ||
173 | int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, | |
174 | gfp_t gfp_flags) | |
175 | { | |
176 | struct dwc3_request *req = to_dwc3_request(request); | |
177 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
178 | struct dwc3 *dwc = dep->dwc; | |
179 | ||
180 | unsigned long flags; | |
181 | ||
182 | int ret; | |
183 | ||
72246da4 FB |
184 | spin_lock_irqsave(&dwc->lock, flags); |
185 | if (!dep->desc) { | |
186 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", | |
187 | request, dep->name); | |
188 | ret = -ESHUTDOWN; | |
189 | goto out; | |
190 | } | |
191 | ||
192 | /* we share one TRB for ep0/1 */ | |
193 | if (!list_empty(&dwc->eps[0]->request_list) || | |
194 | !list_empty(&dwc->eps[1]->request_list) || | |
195 | dwc->ep0_status_pending) { | |
196 | ret = -EBUSY; | |
197 | goto out; | |
198 | } | |
199 | ||
200 | dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", | |
201 | request, dep->name, request->length, | |
202 | dwc3_ep0_state_string(dwc->ep0state)); | |
203 | ||
204 | ret = __dwc3_gadget_ep0_queue(dep, req); | |
205 | ||
206 | out: | |
207 | spin_unlock_irqrestore(&dwc->lock, flags); | |
208 | ||
209 | return ret; | |
210 | } | |
211 | ||
212 | static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) | |
213 | { | |
d742220b FB |
214 | struct dwc3_ep *dep = dwc->eps[0]; |
215 | ||
72246da4 FB |
216 | /* stall is always issued on EP0 */ |
217 | __dwc3_gadget_ep_set_halt(dwc->eps[0], 1); | |
76cb323f | 218 | dwc->eps[0]->flags = DWC3_EP_ENABLED; |
d742220b FB |
219 | |
220 | if (!list_empty(&dep->request_list)) { | |
221 | struct dwc3_request *req; | |
222 | ||
223 | req = next_request(&dep->request_list); | |
224 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
225 | } | |
226 | ||
c7fcdeb2 | 227 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
228 | dwc3_ep0_out_start(dwc); |
229 | } | |
230 | ||
231 | void dwc3_ep0_out_start(struct dwc3 *dwc) | |
232 | { | |
72246da4 FB |
233 | int ret; |
234 | ||
c7fcdeb2 FB |
235 | ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
236 | DWC3_TRBCTL_CONTROL_SETUP); | |
72246da4 FB |
237 | WARN_ON(ret < 0); |
238 | } | |
239 | ||
72246da4 FB |
240 | static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) |
241 | { | |
242 | struct dwc3_ep *dep; | |
243 | u32 windex = le16_to_cpu(wIndex_le); | |
244 | u32 epnum; | |
245 | ||
246 | epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; | |
247 | if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) | |
248 | epnum |= 1; | |
249 | ||
250 | dep = dwc->eps[epnum]; | |
251 | if (dep->flags & DWC3_EP_ENABLED) | |
252 | return dep; | |
253 | ||
254 | return NULL; | |
255 | } | |
256 | ||
257 | static void dwc3_ep0_send_status_response(struct dwc3 *dwc) | |
258 | { | |
b673cf30 | 259 | dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr, |
c7fcdeb2 FB |
260 | dwc->ep0_usb_req.length, |
261 | DWC3_TRBCTL_CONTROL_DATA); | |
72246da4 FB |
262 | } |
263 | ||
264 | /* | |
265 | * ch 9.4.5 | |
266 | */ | |
267 | static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
268 | { | |
269 | struct dwc3_ep *dep; | |
270 | u32 recip; | |
271 | u16 usb_status = 0; | |
272 | __le16 *response_pkt; | |
273 | ||
274 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
275 | switch (recip) { | |
276 | case USB_RECIP_DEVICE: | |
277 | /* | |
278 | * We are self-powered. U1/U2/LTM will be set later | |
279 | * once we handle this states. RemoteWakeup is 0 on SS | |
280 | */ | |
281 | usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; | |
282 | break; | |
283 | ||
284 | case USB_RECIP_INTERFACE: | |
285 | /* | |
286 | * Function Remote Wake Capable D0 | |
287 | * Function Remote Wakeup D1 | |
288 | */ | |
289 | break; | |
290 | ||
291 | case USB_RECIP_ENDPOINT: | |
292 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
293 | if (!dep) | |
294 | return -EINVAL; | |
295 | ||
296 | if (dep->flags & DWC3_EP_STALL) | |
297 | usb_status = 1 << USB_ENDPOINT_HALT; | |
298 | break; | |
299 | default: | |
300 | return -EINVAL; | |
301 | }; | |
302 | ||
303 | response_pkt = (__le16 *) dwc->setup_buf; | |
304 | *response_pkt = cpu_to_le16(usb_status); | |
305 | dwc->ep0_usb_req.length = sizeof(*response_pkt); | |
1ddcb218 | 306 | dwc->ep0_status_pending = 1; |
72246da4 FB |
307 | |
308 | return 0; | |
309 | } | |
310 | ||
311 | static int dwc3_ep0_handle_feature(struct dwc3 *dwc, | |
312 | struct usb_ctrlrequest *ctrl, int set) | |
313 | { | |
314 | struct dwc3_ep *dep; | |
315 | u32 recip; | |
316 | u32 wValue; | |
317 | u32 wIndex; | |
318 | u32 reg; | |
319 | int ret; | |
320 | u32 mode; | |
321 | ||
322 | wValue = le16_to_cpu(ctrl->wValue); | |
323 | wIndex = le16_to_cpu(ctrl->wIndex); | |
324 | recip = ctrl->bRequestType & USB_RECIP_MASK; | |
325 | switch (recip) { | |
326 | case USB_RECIP_DEVICE: | |
327 | ||
328 | /* | |
329 | * 9.4.1 says only only for SS, in AddressState only for | |
330 | * default control pipe | |
331 | */ | |
332 | switch (wValue) { | |
333 | case USB_DEVICE_U1_ENABLE: | |
334 | case USB_DEVICE_U2_ENABLE: | |
335 | case USB_DEVICE_LTM_ENABLE: | |
336 | if (dwc->dev_state != DWC3_CONFIGURED_STATE) | |
337 | return -EINVAL; | |
338 | if (dwc->speed != DWC3_DSTS_SUPERSPEED) | |
339 | return -EINVAL; | |
340 | } | |
341 | ||
342 | /* XXX add U[12] & LTM */ | |
343 | switch (wValue) { | |
344 | case USB_DEVICE_REMOTE_WAKEUP: | |
345 | break; | |
346 | case USB_DEVICE_U1_ENABLE: | |
347 | break; | |
348 | case USB_DEVICE_U2_ENABLE: | |
349 | break; | |
350 | case USB_DEVICE_LTM_ENABLE: | |
351 | break; | |
352 | ||
353 | case USB_DEVICE_TEST_MODE: | |
354 | if ((wIndex & 0xff) != 0) | |
355 | return -EINVAL; | |
356 | if (!set) | |
357 | return -EINVAL; | |
358 | ||
359 | mode = wIndex >> 8; | |
360 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
361 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
362 | ||
363 | switch (mode) { | |
364 | case TEST_J: | |
365 | case TEST_K: | |
366 | case TEST_SE0_NAK: | |
367 | case TEST_PACKET: | |
368 | case TEST_FORCE_EN: | |
369 | reg |= mode << 1; | |
370 | break; | |
371 | default: | |
372 | return -EINVAL; | |
373 | } | |
374 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
375 | break; | |
376 | default: | |
377 | return -EINVAL; | |
378 | } | |
379 | break; | |
380 | ||
381 | case USB_RECIP_INTERFACE: | |
382 | switch (wValue) { | |
383 | case USB_INTRF_FUNC_SUSPEND: | |
384 | if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) | |
385 | /* XXX enable Low power suspend */ | |
386 | ; | |
387 | if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) | |
388 | /* XXX enable remote wakeup */ | |
389 | ; | |
390 | break; | |
391 | default: | |
392 | return -EINVAL; | |
393 | } | |
394 | break; | |
395 | ||
396 | case USB_RECIP_ENDPOINT: | |
397 | switch (wValue) { | |
398 | case USB_ENDPOINT_HALT: | |
399 | ||
400 | dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); | |
401 | if (!dep) | |
402 | return -EINVAL; | |
403 | ret = __dwc3_gadget_ep_set_halt(dep, set); | |
404 | if (ret) | |
405 | return -EINVAL; | |
406 | break; | |
407 | default: | |
408 | return -EINVAL; | |
409 | } | |
410 | break; | |
411 | ||
412 | default: | |
413 | return -EINVAL; | |
414 | }; | |
415 | ||
72246da4 FB |
416 | return 0; |
417 | } | |
418 | ||
419 | static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
420 | { | |
72246da4 FB |
421 | u32 addr; |
422 | u32 reg; | |
423 | ||
424 | addr = le16_to_cpu(ctrl->wValue); | |
425 | if (addr > 127) | |
426 | return -EINVAL; | |
427 | ||
2646021e FB |
428 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
429 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
430 | reg |= DWC3_DCFG_DEVADDR(addr); | |
431 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 | 432 | |
2646021e FB |
433 | if (addr) |
434 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
435 | else | |
436 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
c7fcdeb2 | 437 | |
2646021e | 438 | return 0; |
72246da4 FB |
439 | } |
440 | ||
441 | static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
442 | { | |
443 | int ret; | |
444 | ||
445 | spin_unlock(&dwc->lock); | |
446 | ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); | |
447 | spin_lock(&dwc->lock); | |
448 | return ret; | |
449 | } | |
450 | ||
451 | static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
452 | { | |
453 | u32 cfg; | |
454 | int ret; | |
455 | ||
b23c8439 | 456 | dwc->start_config_issued = false; |
72246da4 FB |
457 | cfg = le16_to_cpu(ctrl->wValue); |
458 | ||
459 | switch (dwc->dev_state) { | |
460 | case DWC3_DEFAULT_STATE: | |
461 | return -EINVAL; | |
462 | break; | |
463 | ||
464 | case DWC3_ADDRESS_STATE: | |
465 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
466 | /* if the cfg matches and the cfg is non zero */ | |
467 | if (!ret && cfg) | |
468 | dwc->dev_state = DWC3_CONFIGURED_STATE; | |
469 | break; | |
470 | ||
471 | case DWC3_CONFIGURED_STATE: | |
472 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
473 | if (!cfg) | |
474 | dwc->dev_state = DWC3_ADDRESS_STATE; | |
475 | break; | |
476 | } | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) | |
481 | { | |
482 | int ret; | |
483 | ||
484 | switch (ctrl->bRequest) { | |
485 | case USB_REQ_GET_STATUS: | |
486 | dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); | |
487 | ret = dwc3_ep0_handle_status(dwc, ctrl); | |
488 | break; | |
489 | case USB_REQ_CLEAR_FEATURE: | |
490 | dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); | |
491 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); | |
492 | break; | |
493 | case USB_REQ_SET_FEATURE: | |
494 | dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); | |
495 | ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); | |
496 | break; | |
497 | case USB_REQ_SET_ADDRESS: | |
498 | dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); | |
499 | ret = dwc3_ep0_set_address(dwc, ctrl); | |
500 | break; | |
501 | case USB_REQ_SET_CONFIGURATION: | |
502 | dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); | |
503 | ret = dwc3_ep0_set_config(dwc, ctrl); | |
504 | break; | |
505 | default: | |
506 | dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); | |
507 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
508 | break; | |
509 | }; | |
510 | ||
511 | return ret; | |
512 | } | |
513 | ||
514 | static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, | |
515 | const struct dwc3_event_depevt *event) | |
516 | { | |
517 | struct usb_ctrlrequest *ctrl = dwc->ctrl_req; | |
518 | int ret; | |
519 | u32 len; | |
520 | ||
521 | if (!dwc->gadget_driver) | |
522 | goto err; | |
523 | ||
524 | len = le16_to_cpu(ctrl->wLength); | |
1ddcb218 | 525 | if (!len) { |
d95b09b9 FB |
526 | dwc->three_stage_setup = false; |
527 | dwc->ep0_expect_in = false; | |
1ddcb218 FB |
528 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
529 | } else { | |
d95b09b9 FB |
530 | dwc->three_stage_setup = true; |
531 | dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); | |
1ddcb218 FB |
532 | dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; |
533 | } | |
72246da4 FB |
534 | |
535 | if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) | |
536 | ret = dwc3_ep0_std_request(dwc, ctrl); | |
537 | else | |
538 | ret = dwc3_ep0_delegate_req(dwc, ctrl); | |
539 | ||
540 | if (ret >= 0) | |
541 | return; | |
542 | ||
543 | err: | |
544 | dwc3_ep0_stall_and_restart(dwc); | |
545 | } | |
546 | ||
547 | static void dwc3_ep0_complete_data(struct dwc3 *dwc, | |
548 | const struct dwc3_event_depevt *event) | |
549 | { | |
550 | struct dwc3_request *r = NULL; | |
551 | struct usb_request *ur; | |
552 | struct dwc3_trb trb; | |
553 | struct dwc3_ep *dep; | |
c611ccb4 | 554 | u32 transferred; |
72246da4 FB |
555 | u8 epnum; |
556 | ||
557 | epnum = event->endpoint_number; | |
558 | dep = dwc->eps[epnum]; | |
559 | ||
1ddcb218 FB |
560 | dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; |
561 | ||
72246da4 | 562 | if (!dwc->ep0_status_pending) { |
c7fcdeb2 | 563 | r = next_request(&dwc->eps[0]->request_list); |
72246da4 FB |
564 | ur = &r->request; |
565 | } else { | |
566 | ur = &dwc->ep0_usb_req; | |
567 | dwc->ep0_status_pending = 0; | |
568 | } | |
569 | ||
570 | dwc3_trb_to_nat(dwc->ep0_trb, &trb); | |
571 | ||
a6829706 FB |
572 | if (dwc->ep0_bounced) { |
573 | struct dwc3_ep *ep0 = dwc->eps[0]; | |
574 | ||
c7fcdeb2 FB |
575 | transferred = min_t(u32, ur->length, |
576 | ep0->endpoint.maxpacket - trb.length); | |
a6829706 FB |
577 | memcpy(ur->buf, dwc->ep0_bounce, transferred); |
578 | dwc->ep0_bounced = false; | |
579 | } else { | |
580 | transferred = ur->length - trb.length; | |
581 | ur->actual += transferred; | |
582 | } | |
72246da4 FB |
583 | |
584 | if ((epnum & 1) && ur->actual < ur->length) { | |
585 | /* for some reason we did not get everything out */ | |
586 | ||
587 | dwc3_ep0_stall_and_restart(dwc); | |
72246da4 FB |
588 | } else { |
589 | /* | |
590 | * handle the case where we have to send a zero packet. This | |
591 | * seems to be case when req.length > maxpacket. Could it be? | |
592 | */ | |
72246da4 FB |
593 | if (r) |
594 | dwc3_gadget_giveback(dep, r, 0); | |
595 | } | |
596 | } | |
597 | ||
598 | static void dwc3_ep0_complete_req(struct dwc3 *dwc, | |
599 | const struct dwc3_event_depevt *event) | |
600 | { | |
601 | struct dwc3_request *r; | |
602 | struct dwc3_ep *dep; | |
72246da4 | 603 | |
c7fcdeb2 | 604 | dep = dwc->eps[0]; |
72246da4 FB |
605 | |
606 | if (!list_empty(&dep->request_list)) { | |
607 | r = next_request(&dep->request_list); | |
608 | ||
609 | dwc3_gadget_giveback(dep, r, 0); | |
610 | } | |
611 | ||
c7fcdeb2 | 612 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
613 | dwc3_ep0_out_start(dwc); |
614 | } | |
615 | ||
616 | static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, | |
617 | const struct dwc3_event_depevt *event) | |
618 | { | |
c7fcdeb2 FB |
619 | struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; |
620 | ||
621 | dep->flags &= ~DWC3_EP_BUSY; | |
622 | ||
72246da4 | 623 | switch (dwc->ep0state) { |
c7fcdeb2 FB |
624 | case EP0_SETUP_PHASE: |
625 | dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); | |
72246da4 FB |
626 | dwc3_ep0_inspect_setup(dwc, event); |
627 | break; | |
628 | ||
c7fcdeb2 FB |
629 | case EP0_DATA_PHASE: |
630 | dev_vdbg(dwc->dev, "Data Phase\n"); | |
72246da4 FB |
631 | dwc3_ep0_complete_data(dwc, event); |
632 | break; | |
633 | ||
c7fcdeb2 FB |
634 | case EP0_STATUS_PHASE: |
635 | dev_vdbg(dwc->dev, "Status Phase\n"); | |
72246da4 FB |
636 | dwc3_ep0_complete_req(dwc, event); |
637 | break; | |
c7fcdeb2 FB |
638 | default: |
639 | WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); | |
640 | } | |
641 | } | |
72246da4 | 642 | |
c7fcdeb2 FB |
643 | static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, |
644 | const struct dwc3_event_depevt *event) | |
645 | { | |
646 | dwc->ep0state = EP0_SETUP_PHASE; | |
647 | dwc3_ep0_out_start(dwc); | |
648 | } | |
649 | ||
650 | static void dwc3_ep0_do_control_data(struct dwc3 *dwc, | |
651 | const struct dwc3_event_depevt *event) | |
652 | { | |
653 | struct dwc3_ep *dep; | |
654 | struct dwc3_request *req; | |
655 | int ret; | |
656 | ||
657 | dep = dwc->eps[0]; | |
658 | dwc->ep0state = EP0_DATA_PHASE; | |
659 | ||
1ddcb218 FB |
660 | if (dwc->ep0_status_pending) { |
661 | dwc3_ep0_send_status_response(dwc); | |
662 | return; | |
663 | } | |
664 | ||
c7fcdeb2 FB |
665 | if (list_empty(&dep->request_list)) { |
666 | dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); | |
667 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
668 | ||
669 | if (event->endpoint_number) | |
670 | dep->flags |= DWC3_EP0_DIR_IN; | |
671 | return; | |
72246da4 | 672 | } |
c7fcdeb2 FB |
673 | |
674 | req = next_request(&dep->request_list); | |
675 | req->direction = !!event->endpoint_number; | |
676 | ||
677 | dwc->ep0state = EP0_DATA_PHASE; | |
678 | if (req->request.length == 0) { | |
679 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
680 | dwc->ctrl_req_addr, 0, | |
681 | DWC3_TRBCTL_CONTROL_DATA); | |
682 | } else if ((req->request.length % dep->endpoint.maxpacket) | |
683 | && (event->endpoint_number == 0)) { | |
684 | dwc3_map_buffer_to_dma(req); | |
685 | ||
686 | WARN_ON(req->request.length > dep->endpoint.maxpacket); | |
687 | ||
688 | dwc->ep0_bounced = true; | |
689 | ||
690 | /* | |
691 | * REVISIT in case request length is bigger than EP0 | |
692 | * wMaxPacketSize, we will need two chained TRBs to handle | |
693 | * the transfer. | |
694 | */ | |
695 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
696 | dwc->ep0_bounce_addr, dep->endpoint.maxpacket, | |
697 | DWC3_TRBCTL_CONTROL_DATA); | |
698 | } else { | |
699 | dwc3_map_buffer_to_dma(req); | |
700 | ||
701 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
702 | req->request.dma, req->request.length, | |
703 | DWC3_TRBCTL_CONTROL_DATA); | |
704 | } | |
705 | ||
706 | WARN_ON(ret < 0); | |
72246da4 FB |
707 | } |
708 | ||
c7fcdeb2 | 709 | static void dwc3_ep0_do_control_status(struct dwc3 *dwc, |
72246da4 FB |
710 | const struct dwc3_event_depevt *event) |
711 | { | |
c7fcdeb2 FB |
712 | u32 type; |
713 | int ret; | |
72246da4 | 714 | |
c7fcdeb2 | 715 | dwc->ep0state = EP0_STATUS_PHASE; |
72246da4 | 716 | |
c7fcdeb2 FB |
717 | type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
718 | : DWC3_TRBCTL_CONTROL_STATUS2; | |
719 | ||
720 | ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, | |
721 | dwc->ctrl_req_addr, 0, type); | |
722 | ||
723 | WARN_ON(ret < 0); | |
724 | } | |
725 | ||
726 | static void dwc3_ep0_xfernotready(struct dwc3 *dwc, | |
727 | const struct dwc3_event_depevt *event) | |
728 | { | |
729 | switch (event->status) { | |
730 | case DEPEVT_STATUS_CONTROL_SETUP: | |
731 | dev_vdbg(dwc->dev, "Control Setup\n"); | |
732 | dwc3_ep0_do_control_setup(dwc, event); | |
733 | break; | |
1ddcb218 | 734 | |
c7fcdeb2 FB |
735 | case DEPEVT_STATUS_CONTROL_DATA: |
736 | dev_vdbg(dwc->dev, "Control Data\n"); | |
1ddcb218 FB |
737 | |
738 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { | |
739 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
740 | dwc->ep0_next_event, |
741 | DWC3_EP0_NRDY_DATA); | |
1ddcb218 FB |
742 | |
743 | dwc3_ep0_stall_and_restart(dwc); | |
744 | return; | |
745 | } | |
746 | ||
55f3fba6 FB |
747 | /* |
748 | * One of the possible error cases is when Host _does_ | |
749 | * request for Data Phase, but it does so on the wrong | |
750 | * direction. | |
751 | * | |
752 | * Here, we already know ep0_next_event is DATA (see above), | |
753 | * so we only need to check for direction. | |
754 | */ | |
755 | if (dwc->ep0_expect_in != event->endpoint_number) { | |
756 | dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); | |
757 | dwc3_ep0_stall_and_restart(dwc); | |
758 | return; | |
759 | } | |
760 | ||
c7fcdeb2 FB |
761 | dwc3_ep0_do_control_data(dwc, event); |
762 | break; | |
1ddcb218 | 763 | |
c7fcdeb2 FB |
764 | case DEPEVT_STATUS_CONTROL_STATUS: |
765 | dev_vdbg(dwc->dev, "Control Status\n"); | |
1ddcb218 FB |
766 | |
767 | if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { | |
768 | dev_vdbg(dwc->dev, "Expected %d got %d\n", | |
25355be6 FB |
769 | dwc->ep0_next_event, |
770 | DWC3_EP0_NRDY_STATUS); | |
1ddcb218 FB |
771 | |
772 | dwc3_ep0_stall_and_restart(dwc); | |
773 | return; | |
774 | } | |
c7fcdeb2 | 775 | dwc3_ep0_do_control_status(dwc, event); |
72246da4 FB |
776 | } |
777 | } | |
778 | ||
779 | void dwc3_ep0_interrupt(struct dwc3 *dwc, | |
780 | const const struct dwc3_event_depevt *event) | |
781 | { | |
782 | u8 epnum = event->endpoint_number; | |
783 | ||
784 | dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", | |
785 | dwc3_ep_event_string(event->endpoint_event), | |
b147f357 | 786 | epnum >> 1, (epnum & 1) ? "in" : "out", |
72246da4 FB |
787 | dwc3_ep0_state_string(dwc->ep0state)); |
788 | ||
789 | switch (event->endpoint_event) { | |
790 | case DWC3_DEPEVT_XFERCOMPLETE: | |
791 | dwc3_ep0_xfer_complete(dwc, event); | |
792 | break; | |
793 | ||
794 | case DWC3_DEPEVT_XFERNOTREADY: | |
795 | dwc3_ep0_xfernotready(dwc, event); | |
796 | break; | |
797 | ||
798 | case DWC3_DEPEVT_XFERINPROGRESS: | |
799 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
800 | case DWC3_DEPEVT_STREAMEVT: | |
801 | case DWC3_DEPEVT_EPCMDCMPLT: | |
802 | break; | |
803 | } | |
804 | } |