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usb: dwc3: gadget: don't call stop_active_transfers() on disconnect
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
04a9bfcd
FB		 57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
8598bde7
FB		 90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
aee63e3c 96 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
aee63e3c 100 int retries = 10000;
8598bde7
FB		 101 u32 reg;
102
802fde98
PZ		 103 /*
104 * Wait until device controller is ready. Only applies to 1.94a and
105 * later RTL.
106 */
107 if (dwc->revision >= DWC3_REVISION_194A) {
108 while (--retries) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
111 udelay(5);
112 else
113 break;
114 }
115
116 if (retries <= 0)
117 return -ETIMEDOUT;
118 }
119
8598bde7
FB		 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
122
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
126
802fde98
PZ		 127 /*
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
130 */
131 if (dwc->revision >= DWC3_REVISION_194A)
132 return 0;
133
8598bde7 134 /* wait for a change in DSTS */
aed430e5 135 retries = 10000;
8598bde7
FB		 136 while (--retries) {
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
138
8598bde7
FB		 139 if (DWC3_DSTS_USBLNKST(reg) == state)
140 return 0;
141
aee63e3c 142 udelay(5);
8598bde7
FB		 143 }
144
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
146
147 return -ETIMEDOUT;
148}
149
457e84b6
FB		 150/**
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
153 *
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
157 *
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
162 *
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
165 *
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
168 *
169 * Unfortunately, due to many variables that's not always the case.
170 */
171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
172{
173 int last_fifo_depth = 0;
174 int ram1_depth;
175 int fifo_size;
176 int mdwidth;
177 int num;
178
179 if (!dwc->needs_fifo_resize)
180 return 0;
181
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
184
185 /* MDWIDTH is represented in bits, we need it in bytes */
186 mdwidth >>= 3;
187
188 /*
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
192 * FIFO space
193 */
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
2e81c36a 197 int mult = 1;
457e84b6
FB		 198 int tmp;
199
200 if (!(dep->number & 1))
201 continue;
202
203 if (!(dep->flags & DWC3_EP_ENABLED))
204 continue;
205
16e78db7
IS		 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
2e81c36a
FB		 208 mult = 3;
209
210 /*
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
214 * accordingly.
215 *
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
219 * packets
220 */
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
457e84b6
FB		 222 tmp += mdwidth;
223
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
2e81c36a 225
457e84b6
FB		 226 fifo_size |= (last_fifo_depth << 16);
227
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
230
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
232 fifo_size);
233
234 last_fifo_depth += (fifo_size & 0xffff);
235 }
236
237 return 0;
238}
239
72246da4
FB		 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
241 int status)
242{
243 struct dwc3 *dwc = dep->dwc;
244
245 if (req->queued) {
eeb720fb
FB		 246 if (req->request.num_mapped_sgs)
247 dep->busy_slot += req->request.num_mapped_sgs;
248 else
249 dep->busy_slot++;
250
72246da4
FB		 251 /*
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
255 */
256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
16e78db7 257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
72246da4
FB		 258 dep->busy_slot++;
259 }
260 list_del(&req->list);
eeb720fb 261 req->trb = NULL;
72246da4
FB		 262
263 if (req->request.status == -EINPROGRESS)
264 req->request.status = status;
265
0fc9a1be
FB		 266 usb_gadget_unmap_request(&dwc->gadget, &req->request,
267 req->direction);
72246da4
FB		 268
269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
270 req, dep->name, req->request.actual,
271 req->request.length, status);
272
273 spin_unlock(&dwc->lock);
0fc9a1be 274 req->request.complete(&dep->endpoint, &req->request);
72246da4
FB		 275 spin_lock(&dwc->lock);
276}
277
278static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
279{
280 switch (cmd) {
281 case DWC3_DEPCMD_DEPSTARTCFG:
282 return "Start New Configuration";
283 case DWC3_DEPCMD_ENDTRANSFER:
284 return "End Transfer";
285 case DWC3_DEPCMD_UPDATETRANSFER:
286 return "Update Transfer";
287 case DWC3_DEPCMD_STARTTRANSFER:
288 return "Start Transfer";
289 case DWC3_DEPCMD_CLEARSTALL:
290 return "Clear Stall";
291 case DWC3_DEPCMD_SETSTALL:
292 return "Set Stall";
802fde98
PZ		 293 case DWC3_DEPCMD_GETEPSTATE:
294 return "Get Endpoint State";
72246da4
FB		 295 case DWC3_DEPCMD_SETTRANSFRESOURCE:
296 return "Set Endpoint Transfer Resource";
297 case DWC3_DEPCMD_SETEPCONFIG:
298 return "Set Endpoint Configuration";
299 default:
300 return "UNKNOWN command";
301 }
302}
303
b09bb642
FB		 304int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
305{
306 u32 timeout = 500;
307 u32 reg;
308
309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
311
312 do {
313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
314 if (!(reg & DWC3_DGCMD_CMDACT)) {
315 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
316 DWC3_DGCMD_STATUS(reg));
317 return 0;
318 }
319
320 /*
321 * We can't sleep here, because it's also called from
322 * interrupt context.
323 */
324 timeout--;
325 if (!timeout)
326 return -ETIMEDOUT;
327 udelay(1);
328 } while (1);
329}
330
72246da4
FB		 331int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
333{
334 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 335 u32 timeout = 500;
72246da4
FB		 336 u32 reg;
337
338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
339 dep->name,
dc1c70a7
FB		 340 dwc3_gadget_ep_cmd_string(cmd), params->param0,
341 params->param1, params->param2);
72246da4 342
dc1c70a7
FB		 343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 346
347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
348 do {
349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
350 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 351 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
352 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 353 return 0;
354 }
355
356 /*
72246da4
FB		 357 * We can't sleep here, because it is also called from
358 * interrupt context.
359 */
360 timeout--;
361 if (!timeout)
362 return -ETIMEDOUT;
363
61d58242 364 udelay(1);
72246da4
FB		 365 } while (1);
366}
367
368static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 369 struct dwc3_trb *trb)
72246da4 370{
c439ef87 371 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 372
373 return dep->trb_pool_dma + offset;
374}
375
376static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
377{
378 struct dwc3 *dwc = dep->dwc;
379
380 if (dep->trb_pool)
381 return 0;
382
383 if (dep->number == 0 || dep->number == 1)
384 return 0;
385
386 dep->trb_pool = dma_alloc_coherent(dwc->dev,
387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
388 &dep->trb_pool_dma, GFP_KERNEL);
389 if (!dep->trb_pool) {
390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
391 dep->name);
392 return -ENOMEM;
393 }
394
395 return 0;
396}
397
398static void dwc3_free_trb_pool(struct dwc3_ep *dep)
399{
400 struct dwc3 *dwc = dep->dwc;
401
402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
403 dep->trb_pool, dep->trb_pool_dma);
404
405 dep->trb_pool = NULL;
406 dep->trb_pool_dma = 0;
407}
408
409static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
410{
411 struct dwc3_gadget_ep_cmd_params params;
412 u32 cmd;
413
414 memset(&params, 0x00, sizeof(params));
415
416 if (dep->number != 1) {
417 cmd = DWC3_DEPCMD_DEPSTARTCFG;
418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 419 if (dep->number > 1) {
420 if (dwc->start_config_issued)
421 return 0;
422 dwc->start_config_issued = true;
72246da4 423 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 424 }
72246da4
FB		 425
426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
427 }
428
429 return 0;
430}
431
432static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec
FB		 433 const struct usb_endpoint_descriptor *desc,
434 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 435{
436 struct dwc3_gadget_ep_cmd_params params;
437
438 memset(&params, 0x00, sizeof(params));
439
dc1c70a7
FB		 440 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
442 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
72246da4 443
dc1c70a7
FB		 444 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
445 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 446
18b7ede5 447 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 448 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
449 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 450 dep->stream_capable = true;
451 }
452
72246da4 453 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 454 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 455
456 /*
457 * We are doing 1:1 mapping for endpoints, meaning
458 * Physical Endpoints 2 maps to Logical Endpoint 2 and
459 * so on. We consider the direction bit as part of the physical
460 * endpoint number. So USB endpoint 0x81 is 0x03.
461 */
dc1c70a7 462 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 463
464 /*
465 * We must use the lower 16 TX FIFOs even though
466 * HW might have more
467 */
468 if (dep->direction)
dc1c70a7 469 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 470
471 if (desc->bInterval) {
dc1c70a7 472 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 473 dep->interval = 1 << (desc->bInterval - 1);
474 }
475
476 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
477 DWC3_DEPCMD_SETEPCONFIG, &params);
478}
479
480static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
481{
482 struct dwc3_gadget_ep_cmd_params params;
483
484 memset(&params, 0x00, sizeof(params));
485
dc1c70a7 486 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 487
488 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
489 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
490}
491
492/**
493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
494 * @dep: endpoint to be initialized
495 * @desc: USB Endpoint Descriptor
496 *
497 * Caller should take care of locking
498 */
499static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec
FB		 500 const struct usb_endpoint_descriptor *desc,
501 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 502{
503 struct dwc3 *dwc = dep->dwc;
504 u32 reg;
505 int ret = -ENOMEM;
506
507 if (!(dep->flags & DWC3_EP_ENABLED)) {
508 ret = dwc3_gadget_start_config(dwc, dep);
509 if (ret)
510 return ret;
511 }
512
c90bfaec 513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
72246da4
FB		 514 if (ret)
515 return ret;
516
517 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 518 struct dwc3_trb *trb_st_hw;
519 struct dwc3_trb *trb_link;
72246da4
FB		 520
521 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
522 if (ret)
523 return ret;
524
16e78db7 525 dep->endpoint.desc = desc;
c90bfaec 526 dep->comp_desc = comp_desc;
72246da4
FB		 527 dep->type = usb_endpoint_type(desc);
528 dep->flags |= DWC3_EP_ENABLED;
529
530 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
531 reg |= DWC3_DALEPENA_EP(dep->number);
532 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
533
534 if (!usb_endpoint_xfer_isoc(desc))
535 return 0;
536
537 memset(&trb_link, 0, sizeof(trb_link));
538
1d046793 539 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 540 trb_st_hw = &dep->trb_pool[0];
541
f6bafc6a 542 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
72246da4 543
f6bafc6a
FB		 544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 548 }
549
550 return 0;
551}
552
624407f9
SAS		 553static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
554static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 555{
556 struct dwc3_request *req;
557
ea53b882 558 if (!list_empty(&dep->req_queued)) {
624407f9
SAS		 559 dwc3_stop_active_transfer(dwc, dep->number);
560
ea53b882
FB		 561 /*
562 * NOTICE: We are violating what the Databook says about the
563 * EndTransfer command. Ideally we would _always_ wait for the
564 * EndTransfer Command Completion IRQ, but that's causing too
565 * much trouble synchronizing between us and gadget driver.
566 *
567 * We have discussed this with the IP Provider and it was
568 * suggested to giveback all requests here, but give HW some
569 * extra time to synchronize with the interconnect. We're using
570 * an arbitraty 100us delay for that.
571 *
572 * Note also that a similar handling was tested by Synopsys
573 * (thanks a lot Paul) and nothing bad has come out of it.
574 * In short, what we're doing is:
575 *
576 * - Issue EndTransfer WITH CMDIOC bit set
577 * - Wait 100us
578 * - giveback all requests to gadget driver
579 */
580 udelay(100);
581
582 req = next_request(&dep->req_queued);
583 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
584 }
585
72246da4
FB		 586 while (!list_empty(&dep->request_list)) {
587 req = next_request(&dep->request_list);
588
624407f9 589 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 590 }
72246da4
FB		 591}
592
593/**
594 * __dwc3_gadget_ep_disable - Disables a HW endpoint
595 * @dep: the endpoint to disable
596 *
624407f9
SAS		 597 * This function also removes requests which are currently processed ny the
598 * hardware and those which are not yet scheduled.
599 * Caller should take care of locking.
72246da4 600 */
72246da4
FB		 601static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
602{
603 struct dwc3 *dwc = dep->dwc;
604 u32 reg;
605
624407f9 606 dwc3_remove_requests(dwc, dep);
72246da4
FB		 607
608 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
609 reg &= ~DWC3_DALEPENA_EP(dep->number);
610 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
611
879631aa 612 dep->stream_capable = false;
f9c56cdd 613 dep->endpoint.desc = NULL;
c90bfaec 614 dep->comp_desc = NULL;
72246da4 615 dep->type = 0;
879631aa 616 dep->flags = 0;
72246da4
FB		 617
618 return 0;
619}
620
621/* -------------------------------------------------------------------------- */
622
623static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
624 const struct usb_endpoint_descriptor *desc)
625{
626 return -EINVAL;
627}
628
629static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
630{
631 return -EINVAL;
632}
633
634/* -------------------------------------------------------------------------- */
635
636static int dwc3_gadget_ep_enable(struct usb_ep *ep,
637 const struct usb_endpoint_descriptor *desc)
638{
639 struct dwc3_ep *dep;
640 struct dwc3 *dwc;
641 unsigned long flags;
642 int ret;
643
644 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
645 pr_debug("dwc3: invalid parameters\n");
646 return -EINVAL;
647 }
648
649 if (!desc->wMaxPacketSize) {
650 pr_debug("dwc3: missing wMaxPacketSize\n");
651 return -EINVAL;
652 }
653
654 dep = to_dwc3_ep(ep);
655 dwc = dep->dwc;
656
657 switch (usb_endpoint_type(desc)) {
658 case USB_ENDPOINT_XFER_CONTROL:
27a78d6a 659 strlcat(dep->name, "-control", sizeof(dep->name));
72246da4
FB		 660 break;
661 case USB_ENDPOINT_XFER_ISOC:
27a78d6a 662 strlcat(dep->name, "-isoc", sizeof(dep->name));
72246da4
FB		 663 break;
664 case USB_ENDPOINT_XFER_BULK:
27a78d6a 665 strlcat(dep->name, "-bulk", sizeof(dep->name));
72246da4
FB		 666 break;
667 case USB_ENDPOINT_XFER_INT:
27a78d6a 668 strlcat(dep->name, "-int", sizeof(dep->name));
72246da4
FB		 669 break;
670 default:
671 dev_err(dwc->dev, "invalid endpoint transfer type\n");
672 }
673
674 if (dep->flags & DWC3_EP_ENABLED) {
675 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
676 dep->name);
677 return 0;
678 }
679
680 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
681
682 spin_lock_irqsave(&dwc->lock, flags);
c90bfaec 683 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
72246da4
FB		 684 spin_unlock_irqrestore(&dwc->lock, flags);
685
686 return ret;
687}
688
689static int dwc3_gadget_ep_disable(struct usb_ep *ep)
690{
691 struct dwc3_ep *dep;
692 struct dwc3 *dwc;
693 unsigned long flags;
694 int ret;
695
696 if (!ep) {
697 pr_debug("dwc3: invalid parameters\n");
698 return -EINVAL;
699 }
700
701 dep = to_dwc3_ep(ep);
702 dwc = dep->dwc;
703
704 if (!(dep->flags & DWC3_EP_ENABLED)) {
705 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
706 dep->name);
707 return 0;
708 }
709
710 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
711 dep->number >> 1,
712 (dep->number & 1) ? "in" : "out");
713
714 spin_lock_irqsave(&dwc->lock, flags);
715 ret = __dwc3_gadget_ep_disable(dep);
716 spin_unlock_irqrestore(&dwc->lock, flags);
717
718 return ret;
719}
720
721static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
722 gfp_t gfp_flags)
723{
724 struct dwc3_request *req;
725 struct dwc3_ep *dep = to_dwc3_ep(ep);
726 struct dwc3 *dwc = dep->dwc;
727
728 req = kzalloc(sizeof(*req), gfp_flags);
729 if (!req) {
730 dev_err(dwc->dev, "not enough memory\n");
731 return NULL;
732 }
733
734 req->epnum = dep->number;
735 req->dep = dep;
72246da4
FB		 736
737 return &req->request;
738}
739
740static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
741 struct usb_request *request)
742{
743 struct dwc3_request *req = to_dwc3_request(request);
744
745 kfree(req);
746}
747
c71fc37c
FB		 748/**
749 * dwc3_prepare_one_trb - setup one TRB from one request
750 * @dep: endpoint for which this request is prepared
751 * @req: dwc3_request pointer
752 */
68e823e2 753static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb
FB		 754 struct dwc3_request *req, dma_addr_t dma,
755 unsigned length, unsigned last, unsigned chain)
c71fc37c 756{
eeb720fb 757 struct dwc3 *dwc = dep->dwc;
f6bafc6a 758 struct dwc3_trb *trb;
c71fc37c
FB		 759
760 unsigned int cur_slot;
761
eeb720fb
FB		 762 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
763 dep->name, req, (unsigned long long) dma,
764 length, last ? " last" : "",
765 chain ? " chain" : "");
766
f6bafc6a 767 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c
FB		 768 cur_slot = dep->free_slot;
769 dep->free_slot++;
770
771 /* Skip the LINK-TRB on ISOC */
772 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
16e78db7 773 usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 774 return;
c71fc37c 775
eeb720fb
FB		 776 if (!req->trb) {
777 dwc3_gadget_move_request_queued(req);
f6bafc6a
FB		 778 req->trb = trb;
779 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
eeb720fb 780 }
c71fc37c 781
f6bafc6a
FB		 782 trb->size = DWC3_TRB_SIZE_LENGTH(length);
783 trb->bpl = lower_32_bits(dma);
784 trb->bph = upper_32_bits(dma);
c71fc37c 785
16e78db7 786 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 787 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 788 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 789 break;
790
791 case USB_ENDPOINT_XFER_ISOC:
f6bafc6a 792 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
c71fc37c 793
206dd69a 794 if (!req->request.no_interrupt)
f6bafc6a 795 trb->ctrl |= DWC3_TRB_CTRL_IOC;
c71fc37c
FB		 796 break;
797
798 case USB_ENDPOINT_XFER_BULK:
799 case USB_ENDPOINT_XFER_INT:
f6bafc6a 800 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 801 break;
802 default:
803 /*
804 * This is only possible with faulty memory because we
805 * checked it already :)
806 */
807 BUG();
808 }
809
16e78db7 810 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
f6bafc6a
FB		 811 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
812 trb->ctrl |= DWC3_TRB_CTRL_CSP;
813 } else {
814 if (chain)
815 trb->ctrl |= DWC3_TRB_CTRL_CHN;
816
817 if (last)
818 trb->ctrl |= DWC3_TRB_CTRL_LST;
819 }
c71fc37c 820
16e78db7 821 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 822 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 823
f6bafc6a 824 trb->ctrl |= DWC3_TRB_CTRL_HWO;
c71fc37c
FB		 825}
826
72246da4
FB		 827/*
828 * dwc3_prepare_trbs - setup TRBs from requests
829 * @dep: endpoint for which requests are being prepared
830 * @starting: true if the endpoint is idle and no requests are queued.
831 *
1d046793
PZ		 832 * The function goes through the requests list and sets up TRBs for the
833 * transfers. The function returns once there are no more TRBs available or
834 * it runs out of requests.
72246da4 835 */
68e823e2 836static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 837{
68e823e2 838 struct dwc3_request *req, *n;
72246da4 839 u32 trbs_left;
8d62cd65 840 u32 max;
c71fc37c 841 unsigned int last_one = 0;
72246da4
FB		 842
843 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
844
845 /* the first request must not be queued */
846 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 847
8d62cd65 848 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 849 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 850 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
851 if (trbs_left > max)
852 trbs_left = max;
853 }
854
72246da4 855 /*
1d046793
PZ		 856 * If busy & slot are equal than it is either full or empty. If we are
857 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 858 * full and don't do anything
859 */
860 if (!trbs_left) {
861 if (!starting)
68e823e2 862 return;
72246da4
FB		 863 trbs_left = DWC3_TRB_NUM;
864 /*
865 * In case we start from scratch, we queue the ISOC requests
866 * starting from slot 1. This is done because we use ring
867 * buffer and have no LST bit to stop us. Instead, we place
1d046793 868 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 869 * after the first request so we start at slot 1 and have
870 * 7 requests proceed before we hit the first IOC.
871 * Other transfer types don't use the ring buffer and are
872 * processed from the first TRB until the last one. Since we
873 * don't wrap around we have to start at the beginning.
874 */
16e78db7 875 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 876 dep->busy_slot = 1;
877 dep->free_slot = 1;
878 } else {
879 dep->busy_slot = 0;
880 dep->free_slot = 0;
881 }
882 }
883
884 /* The last TRB is a link TRB, not used for xfer */
16e78db7 885 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 886 return;
72246da4
FB		 887
888 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 889 unsigned length;
890 dma_addr_t dma;
72246da4 891
eeb720fb
FB		 892 if (req->request.num_mapped_sgs > 0) {
893 struct usb_request *request = &req->request;
894 struct scatterlist *sg = request->sg;
895 struct scatterlist *s;
896 int i;
72246da4 897
eeb720fb
FB		 898 for_each_sg(sg, s, request->num_mapped_sgs, i) {
899 unsigned chain = true;
72246da4 900
eeb720fb
FB		 901 length = sg_dma_len(s);
902 dma = sg_dma_address(s);
72246da4 903
1d046793
PZ		 904 if (i == (request->num_mapped_sgs - 1) ||
905 sg_is_last(s)) {
eeb720fb
FB		 906 last_one = true;
907 chain = false;
908 }
72246da4 909
eeb720fb
FB		 910 trbs_left--;
911 if (!trbs_left)
912 last_one = true;
72246da4 913
eeb720fb
FB		 914 if (last_one)
915 chain = false;
72246da4 916
eeb720fb
FB		 917 dwc3_prepare_one_trb(dep, req, dma, length,
918 last_one, chain);
72246da4 919
eeb720fb
FB		 920 if (last_one)
921 break;
922 }
72246da4 923 } else {
eeb720fb
FB		 924 dma = req->request.dma;
925 length = req->request.length;
926 trbs_left--;
72246da4 927
eeb720fb
FB		 928 if (!trbs_left)
929 last_one = 1;
879631aa 930
eeb720fb
FB		 931 /* Is this the last request? */
932 if (list_is_last(&req->list, &dep->request_list))
933 last_one = 1;
72246da4 934
eeb720fb
FB		 935 dwc3_prepare_one_trb(dep, req, dma, length,
936 last_one, false);
72246da4 937
eeb720fb
FB		 938 if (last_one)
939 break;
72246da4 940 }
72246da4 941 }
72246da4
FB		 942}
943
944static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
945 int start_new)
946{
947 struct dwc3_gadget_ep_cmd_params params;
948 struct dwc3_request *req;
949 struct dwc3 *dwc = dep->dwc;
950 int ret;
951 u32 cmd;
952
953 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
954 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
955 return -EBUSY;
956 }
957 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
958
959 /*
960 * If we are getting here after a short-out-packet we don't enqueue any
961 * new requests as we try to set the IOC bit only on the last request.
962 */
963 if (start_new) {
964 if (list_empty(&dep->req_queued))
965 dwc3_prepare_trbs(dep, start_new);
966
967 /* req points to the first request which will be sent */
968 req = next_request(&dep->req_queued);
969 } else {
68e823e2
FB		 970 dwc3_prepare_trbs(dep, start_new);
971
72246da4 972 /*
1d046793 973 * req points to the first request where HWO changed from 0 to 1
72246da4 974 */
68e823e2 975 req = next_request(&dep->req_queued);
72246da4
FB		 976 }
977 if (!req) {
978 dep->flags |= DWC3_EP_PENDING_REQUEST;
979 return 0;
980 }
981
982 memset(&params, 0, sizeof(params));
dc1c70a7
FB		 983 params.param0 = upper_32_bits(req->trb_dma);
984 params.param1 = lower_32_bits(req->trb_dma);
72246da4
FB		 985
986 if (start_new)
987 cmd = DWC3_DEPCMD_STARTTRANSFER;
988 else
989 cmd = DWC3_DEPCMD_UPDATETRANSFER;
990
991 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
992 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
993 if (ret < 0) {
994 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
995
996 /*
997 * FIXME we need to iterate over the list of requests
998 * here and stop, unmap, free and del each of the linked
1d046793 999 * requests instead of what we do now.
72246da4 1000 */
0fc9a1be
FB		 1001 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1002 req->direction);
72246da4
FB		 1003 list_del(&req->list);
1004 return ret;
1005 }
1006
1007 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1008
f898ae09
PZ		 1009 if (start_new) {
1010 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
1011 dep->number);
1012 WARN_ON_ONCE(!dep->res_trans_idx);
1013 }
25b8ff68 1014
72246da4
FB		 1015 return 0;
1016}
1017
d6d6ec7b
PA		 1018static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1019 struct dwc3_ep *dep, u32 cur_uf)
1020{
1021 u32 uf;
1022
1023 if (list_empty(&dep->request_list)) {
1024 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1025 dep->name);
1026 return;
1027 }
1028
1029 /* 4 micro frames in the future */
1030 uf = cur_uf + dep->interval * 4;
1031
1032 __dwc3_gadget_kick_transfer(dep, uf, 1);
1033}
1034
1035static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1036 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1037{
1038 u32 cur_uf, mask;
1039
1040 mask = ~(dep->interval - 1);
1041 cur_uf = event->parameters & mask;
1042
1043 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1044}
1045
72246da4
FB		 1046static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1047{
0fc9a1be
FB		 1048 struct dwc3 *dwc = dep->dwc;
1049 int ret;
1050
72246da4
FB		 1051 req->request.actual = 0;
1052 req->request.status = -EINPROGRESS;
1053 req->direction = dep->direction;
1054 req->epnum = dep->number;
1055
1056 /*
1057 * We only add to our list of requests now and
1058 * start consuming the list once we get XferNotReady
1059 * IRQ.
1060 *
1061 * That way, we avoid doing anything that we don't need
1062 * to do now and defer it until the point we receive a
1063 * particular token from the Host side.
1064 *
1065 * This will also avoid Host cancelling URBs due to too
1d046793 1066 * many NAKs.
72246da4 1067 */
0fc9a1be
FB		 1068 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1069 dep->direction);
1070 if (ret)
1071 return ret;
1072
72246da4
FB		 1073 list_add_tail(&req->list, &dep->request_list);
1074
d6d6ec7b
PA		 1075 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1076 if (dep->flags & DWC3_EP_BUSY) {
1077 dep->flags |= DWC3_EP_PENDING_REQUEST;
1078 } else if (dep->flags & DWC3_EP_MISSED_ISOC) {
1079 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1080 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1081 }
1082 }
f898ae09 1083
72246da4 1084 /*
f898ae09 1085 * There are two special cases:
72246da4 1086 *
f898ae09
PZ		 1087 * 1. XferNotReady with empty list of requests. We need to kick the
1088 * transfer here in that situation, otherwise we will be NAKing
1089 * forever. If we get XferNotReady before gadget driver has a
1090 * chance to queue a request, we will ACK the IRQ but won't be
1091 * able to receive the data until the next request is queued.
1092 * The following code is handling exactly that.
72246da4 1093 *
f898ae09
PZ		 1094 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1095 * kick the transfer here after queuing a request, otherwise the
1096 * core may not see the modified TRB(s).
72246da4
FB		 1097 */
1098 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f898ae09
PZ		 1099 int ret;
1100 int start_trans = 1;
1101 u8 trans_idx = dep->res_trans_idx;
72246da4 1102
16e78db7 1103 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
f898ae09 1104 (dep->flags & DWC3_EP_BUSY)) {
72246da4 1105 start_trans = 0;
f898ae09
PZ		 1106 WARN_ON_ONCE(!trans_idx);
1107 } else {
1108 trans_idx = 0;
1109 }
72246da4 1110
f898ae09 1111 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
72246da4
FB		 1112 if (ret && ret != -EBUSY) {
1113 struct dwc3 *dwc = dep->dwc;
1114
1115 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1116 dep->name);
1117 }
a0925324 1118 }
72246da4
FB		 1119
1120 return 0;
1121}
1122
1123static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1124 gfp_t gfp_flags)
1125{
1126 struct dwc3_request *req = to_dwc3_request(request);
1127 struct dwc3_ep *dep = to_dwc3_ep(ep);
1128 struct dwc3 *dwc = dep->dwc;
1129
1130 unsigned long flags;
1131
1132 int ret;
1133
16e78db7 1134 if (!dep->endpoint.desc) {
72246da4
FB		 1135 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1136 request, ep->name);
1137 return -ESHUTDOWN;
1138 }
1139
1140 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1141 request, ep->name, request->length);
1142
1143 spin_lock_irqsave(&dwc->lock, flags);
1144 ret = __dwc3_gadget_ep_queue(dep, req);
1145 spin_unlock_irqrestore(&dwc->lock, flags);
1146
1147 return ret;
1148}
1149
1150static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1151 struct usb_request *request)
1152{
1153 struct dwc3_request *req = to_dwc3_request(request);
1154 struct dwc3_request *r = NULL;
1155
1156 struct dwc3_ep *dep = to_dwc3_ep(ep);
1157 struct dwc3 *dwc = dep->dwc;
1158
1159 unsigned long flags;
1160 int ret = 0;
1161
1162 spin_lock_irqsave(&dwc->lock, flags);
1163
1164 list_for_each_entry(r, &dep->request_list, list) {
1165 if (r == req)
1166 break;
1167 }
1168
1169 if (r != req) {
1170 list_for_each_entry(r, &dep->req_queued, list) {
1171 if (r == req)
1172 break;
1173 }
1174 if (r == req) {
1175 /* wait until it is processed */
1176 dwc3_stop_active_transfer(dwc, dep->number);
1177 goto out0;
1178 }
1179 dev_err(dwc->dev, "request %p was not queued to %s\n",
1180 request, ep->name);
1181 ret = -EINVAL;
1182 goto out0;
1183 }
1184
1185 /* giveback the request */
1186 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1187
1188out0:
1189 spin_unlock_irqrestore(&dwc->lock, flags);
1190
1191 return ret;
1192}
1193
1194int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1195{
1196 struct dwc3_gadget_ep_cmd_params params;
1197 struct dwc3 *dwc = dep->dwc;
1198 int ret;
1199
1200 memset(&params, 0x00, sizeof(params));
1201
1202 if (value) {
0b7836a9
FB		 1203 if (dep->number == 0 || dep->number == 1) {
1204 /*
1205 * Whenever EP0 is stalled, we will restart
1206 * the state machine, thus moving back to
1207 * Setup Phase
1208 */
1209 dwc->ep0state = EP0_SETUP_PHASE;
1210 }
72246da4
FB		 1211
1212 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1213 DWC3_DEPCMD_SETSTALL, &params);
1214 if (ret)
1215 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1216 value ? "set" : "clear",
1217 dep->name);
1218 else
1219 dep->flags |= DWC3_EP_STALL;
1220 } else {
5275455a
PZ		 1221 if (dep->flags & DWC3_EP_WEDGE)
1222 return 0;
1223
72246da4
FB		 1224 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1225 DWC3_DEPCMD_CLEARSTALL, &params);
1226 if (ret)
1227 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1228 value ? "set" : "clear",
1229 dep->name);
1230 else
1231 dep->flags &= ~DWC3_EP_STALL;
1232 }
5275455a 1233
72246da4
FB		 1234 return ret;
1235}
1236
1237static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1238{
1239 struct dwc3_ep *dep = to_dwc3_ep(ep);
1240 struct dwc3 *dwc = dep->dwc;
1241
1242 unsigned long flags;
1243
1244 int ret;
1245
1246 spin_lock_irqsave(&dwc->lock, flags);
1247
16e78db7 1248 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1249 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1250 ret = -EINVAL;
1251 goto out;
1252 }
1253
1254 ret = __dwc3_gadget_ep_set_halt(dep, value);
1255out:
1256 spin_unlock_irqrestore(&dwc->lock, flags);
1257
1258 return ret;
1259}
1260
1261static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1262{
1263 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1264 struct dwc3 *dwc = dep->dwc;
1265 unsigned long flags;
72246da4 1266
249a4569 1267 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1268 dep->flags |= DWC3_EP_WEDGE;
249a4569 1269 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4 1270
5275455a 1271 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 1272}
1273
1274/* -------------------------------------------------------------------------- */
1275
1276static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1277 .bLength = USB_DT_ENDPOINT_SIZE,
1278 .bDescriptorType = USB_DT_ENDPOINT,
1279 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1280};
1281
1282static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1283 .enable = dwc3_gadget_ep0_enable,
1284 .disable = dwc3_gadget_ep0_disable,
1285 .alloc_request = dwc3_gadget_ep_alloc_request,
1286 .free_request = dwc3_gadget_ep_free_request,
1287 .queue = dwc3_gadget_ep0_queue,
1288 .dequeue = dwc3_gadget_ep_dequeue,
1289 .set_halt = dwc3_gadget_ep_set_halt,
1290 .set_wedge = dwc3_gadget_ep_set_wedge,
1291};
1292
1293static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1294 .enable = dwc3_gadget_ep_enable,
1295 .disable = dwc3_gadget_ep_disable,
1296 .alloc_request = dwc3_gadget_ep_alloc_request,
1297 .free_request = dwc3_gadget_ep_free_request,
1298 .queue = dwc3_gadget_ep_queue,
1299 .dequeue = dwc3_gadget_ep_dequeue,
1300 .set_halt = dwc3_gadget_ep_set_halt,
1301 .set_wedge = dwc3_gadget_ep_set_wedge,
1302};
1303
1304/* -------------------------------------------------------------------------- */
1305
1306static int dwc3_gadget_get_frame(struct usb_gadget *g)
1307{
1308 struct dwc3 *dwc = gadget_to_dwc(g);
1309 u32 reg;
1310
1311 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1312 return DWC3_DSTS_SOFFN(reg);
1313}
1314
1315static int dwc3_gadget_wakeup(struct usb_gadget *g)
1316{
1317 struct dwc3 *dwc = gadget_to_dwc(g);
1318
1319 unsigned long timeout;
1320 unsigned long flags;
1321
1322 u32 reg;
1323
1324 int ret = 0;
1325
1326 u8 link_state;
1327 u8 speed;
1328
1329 spin_lock_irqsave(&dwc->lock, flags);
1330
1331 /*
1332 * According to the Databook Remote wakeup request should
1333 * be issued only when the device is in early suspend state.
1334 *
1335 * We can check that via USB Link State bits in DSTS register.
1336 */
1337 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1338
1339 speed = reg & DWC3_DSTS_CONNECTSPD;
1340 if (speed == DWC3_DSTS_SUPERSPEED) {
1341 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1342 ret = -EINVAL;
1343 goto out;
1344 }
1345
1346 link_state = DWC3_DSTS_USBLNKST(reg);
1347
1348 switch (link_state) {
1349 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1350 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1351 break;
1352 default:
1353 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1354 link_state);
1355 ret = -EINVAL;
1356 goto out;
1357 }
1358
8598bde7
FB		 1359 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1360 if (ret < 0) {
1361 dev_err(dwc->dev, "failed to put link in Recovery\n");
1362 goto out;
1363 }
72246da4 1364
802fde98
PZ		 1365 /* Recent versions do this automatically */
1366 if (dwc->revision < DWC3_REVISION_194A) {
1367 /* write zeroes to Link Change Request */
fcc023c7 1368 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1369 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1370 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1371 }
72246da4 1372
1d046793 1373 /* poll until Link State changes to ON */
72246da4
FB		 1374 timeout = jiffies + msecs_to_jiffies(100);
1375
1d046793 1376 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1377 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1378
1379 /* in HS, means ON */
1380 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1381 break;
1382 }
1383
1384 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1385 dev_err(dwc->dev, "failed to send remote wakeup\n");
1386 ret = -EINVAL;
1387 }
1388
1389out:
1390 spin_unlock_irqrestore(&dwc->lock, flags);
1391
1392 return ret;
1393}
1394
1395static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1396 int is_selfpowered)
1397{
1398 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1399 unsigned long flags;
72246da4 1400
249a4569 1401 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1402 dwc->is_selfpowered = !!is_selfpowered;
249a4569 1403 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1404
1405 return 0;
1406}
1407
1408static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1409{
1410 u32 reg;
61d58242 1411 u32 timeout = 500;
72246da4
FB		 1412
1413 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1414 if (is_on) {
802fde98
PZ		 1415 if (dwc->revision <= DWC3_REVISION_187A) {
1416 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1417 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1418 }
1419
1420 if (dwc->revision >= DWC3_REVISION_194A)
1421 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1422 reg |= DWC3_DCTL_RUN_STOP;
8db7ed15 1423 } else {
72246da4 1424 reg &= ~DWC3_DCTL_RUN_STOP;
8db7ed15 1425 }
72246da4
FB		 1426
1427 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1428
1429 do {
1430 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1431 if (is_on) {
1432 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1433 break;
1434 } else {
1435 if (reg & DWC3_DSTS_DEVCTRLHLT)
1436 break;
1437 }
72246da4
FB		 1438 timeout--;
1439 if (!timeout)
1440 break;
61d58242 1441 udelay(1);
72246da4
FB		 1442 } while (1);
1443
1444 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1445 dwc->gadget_driver
1446 ? dwc->gadget_driver->function : "no-function",
1447 is_on ? "connect" : "disconnect");
1448}
1449
1450static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1451{
1452 struct dwc3 *dwc = gadget_to_dwc(g);
1453 unsigned long flags;
1454
1455 is_on = !!is_on;
1456
1457 spin_lock_irqsave(&dwc->lock, flags);
1458 dwc3_gadget_run_stop(dwc, is_on);
1459 spin_unlock_irqrestore(&dwc->lock, flags);
1460
1461 return 0;
1462}
1463
1464static int dwc3_gadget_start(struct usb_gadget *g,
1465 struct usb_gadget_driver *driver)
1466{
1467 struct dwc3 *dwc = gadget_to_dwc(g);
1468 struct dwc3_ep *dep;
1469 unsigned long flags;
1470 int ret = 0;
1471 u32 reg;
1472
1473 spin_lock_irqsave(&dwc->lock, flags);
1474
1475 if (dwc->gadget_driver) {
1476 dev_err(dwc->dev, "%s is already bound to %s\n",
1477 dwc->gadget.name,
1478 dwc->gadget_driver->driver.name);
1479 ret = -EBUSY;
1480 goto err0;
1481 }
1482
1483 dwc->gadget_driver = driver;
1484 dwc->gadget.dev.driver = &driver->driver;
1485
72246da4
FB		 1486 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1487 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1488
1489 /**
1490 * WORKAROUND: DWC3 revision < 2.20a have an issue
1491 * which would cause metastability state on Run/Stop
1492 * bit if we try to force the IP to USB2-only mode.
1493 *
1494 * Because of that, we cannot configure the IP to any
1495 * speed other than the SuperSpeed
1496 *
1497 * Refers to:
1498 *
1499 * STAR#9000525659: Clock Domain Crossing on DCTL in
1500 * USB 2.0 Mode
1501 */
1502 if (dwc->revision < DWC3_REVISION_220A)
1503 reg |= DWC3_DCFG_SUPERSPEED;
1504 else
1505 reg |= dwc->maximum_speed;
72246da4
FB		 1506 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1507
b23c8439
PZ		 1508 dwc->start_config_issued = false;
1509
72246da4
FB		 1510 /* Start with SuperSpeed Default */
1511 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1512
1513 dep = dwc->eps[0];
c90bfaec 1514 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1515 if (ret) {
1516 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1517 goto err0;
1518 }
1519
1520 dep = dwc->eps[1];
c90bfaec 1521 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1522 if (ret) {
1523 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1524 goto err1;
1525 }
1526
1527 /* begin to receive SETUP packets */
c7fcdeb2 1528 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1529 dwc3_ep0_out_start(dwc);
1530
1531 spin_unlock_irqrestore(&dwc->lock, flags);
1532
1533 return 0;
1534
1535err1:
1536 __dwc3_gadget_ep_disable(dwc->eps[0]);
1537
1538err0:
1539 spin_unlock_irqrestore(&dwc->lock, flags);
1540
1541 return ret;
1542}
1543
1544static int dwc3_gadget_stop(struct usb_gadget *g,
1545 struct usb_gadget_driver *driver)
1546{
1547 struct dwc3 *dwc = gadget_to_dwc(g);
1548 unsigned long flags;
1549
1550 spin_lock_irqsave(&dwc->lock, flags);
1551
1552 __dwc3_gadget_ep_disable(dwc->eps[0]);
1553 __dwc3_gadget_ep_disable(dwc->eps[1]);
1554
1555 dwc->gadget_driver = NULL;
1556 dwc->gadget.dev.driver = NULL;
1557
1558 spin_unlock_irqrestore(&dwc->lock, flags);
1559
1560 return 0;
1561}
802fde98 1562
72246da4
FB		 1563static const struct usb_gadget_ops dwc3_gadget_ops = {
1564 .get_frame = dwc3_gadget_get_frame,
1565 .wakeup = dwc3_gadget_wakeup,
1566 .set_selfpowered = dwc3_gadget_set_selfpowered,
1567 .pullup = dwc3_gadget_pullup,
1568 .udc_start = dwc3_gadget_start,
1569 .udc_stop = dwc3_gadget_stop,
1570};
1571
1572/* -------------------------------------------------------------------------- */
1573
1574static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1575{
1576 struct dwc3_ep *dep;
1577 u8 epnum;
1578
1579 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1580
1581 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1582 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1583 if (!dep) {
1584 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1585 epnum);
1586 return -ENOMEM;
1587 }
1588
1589 dep->dwc = dwc;
1590 dep->number = epnum;
1591 dwc->eps[epnum] = dep;
1592
1593 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1594 (epnum & 1) ? "in" : "out");
1595 dep->endpoint.name = dep->name;
1596 dep->direction = (epnum & 1);
1597
1598 if (epnum == 0 || epnum == 1) {
1599 dep->endpoint.maxpacket = 512;
1600 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1601 if (!epnum)
1602 dwc->gadget.ep0 = &dep->endpoint;
1603 } else {
1604 int ret;
1605
1606 dep->endpoint.maxpacket = 1024;
12d36c16 1607 dep->endpoint.max_streams = 15;
72246da4
FB		 1608 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1609 list_add_tail(&dep->endpoint.ep_list,
1610 &dwc->gadget.ep_list);
1611
1612 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1613 if (ret)
72246da4 1614 return ret;
72246da4 1615 }
25b8ff68 1616
72246da4
FB		 1617 INIT_LIST_HEAD(&dep->request_list);
1618 INIT_LIST_HEAD(&dep->req_queued);
1619 }
1620
1621 return 0;
1622}
1623
1624static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1625{
1626 struct dwc3_ep *dep;
1627 u8 epnum;
1628
1629 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1630 dep = dwc->eps[epnum];
1631 dwc3_free_trb_pool(dep);
1632
1633 if (epnum != 0 && epnum != 1)
1634 list_del(&dep->endpoint.ep_list);
1635
1636 kfree(dep);
1637 }
1638}
1639
1640static void dwc3_gadget_release(struct device *dev)
1641{
1642 dev_dbg(dev, "%s\n", __func__);
1643}
1644
1645/* -------------------------------------------------------------------------- */
1646static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1647 const struct dwc3_event_depevt *event, int status)
1648{
1649 struct dwc3_request *req;
f6bafc6a 1650 struct dwc3_trb *trb;
72246da4
FB		 1651 unsigned int count;
1652 unsigned int s_pkt = 0;
d6d6ec7b 1653 unsigned int trb_status;
72246da4
FB		 1654
1655 do {
1656 req = next_request(&dep->req_queued);
d39ee7be
SAS		 1657 if (!req) {
1658 WARN_ON_ONCE(1);
1659 return 1;
1660 }
72246da4 1661
f6bafc6a 1662 trb = req->trb;
72246da4 1663
f6bafc6a 1664 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
0d2f4758
SAS		 1665 /*
1666 * We continue despite the error. There is not much we
1d046793
PZ		 1667 * can do. If we don't clean it up we loop forever. If
1668 * we skip the TRB then it gets overwritten after a
1669 * while since we use them in a ring buffer. A BUG()
1670 * would help. Lets hope that if this occurs, someone
0d2f4758
SAS		 1671 * fixes the root cause instead of looking away :)
1672 */
72246da4
FB		 1673 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1674 dep->name, req->trb);
f6bafc6a 1675 count = trb->size & DWC3_TRB_SIZE_MASK;
72246da4
FB		 1676
1677 if (dep->direction) {
1678 if (count) {
d6d6ec7b
PA		 1679 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1680 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1681 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1682 dep->name);
1683 dep->current_uf = event->parameters &
1684 ~(dep->interval - 1);
1685 dep->flags |= DWC3_EP_MISSED_ISOC;
1686 } else {
1687 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1688 dep->name);
1689 status = -ECONNRESET;
1690 }
72246da4
FB		 1691 }
1692 } else {
1693 if (count && (event->status & DEPEVT_STATUS_SHORT))
1694 s_pkt = 1;
1695 }
1696
1697 /*
1698 * We assume here we will always receive the entire data block
1699 * which we should receive. Meaning, if we program RX to
1700 * receive 4K but we receive only 2K, we assume that's all we
1701 * should receive and we simply bounce the request back to the
1702 * gadget driver for further processing.
1703 */
1704 req->request.actual += req->request.length - count;
1705 dwc3_gadget_giveback(dep, req, status);
1706 if (s_pkt)
1707 break;
f6bafc6a 1708 if ((event->status & DEPEVT_STATUS_LST) &&
70b674bf
PA		 1709 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1710 DWC3_TRB_CTRL_HWO)))
72246da4 1711 break;
f6bafc6a
FB		 1712 if ((event->status & DEPEVT_STATUS_IOC) &&
1713 (trb->ctrl & DWC3_TRB_CTRL_IOC))
72246da4
FB		 1714 break;
1715 } while (1);
1716
f6bafc6a
FB		 1717 if ((event->status & DEPEVT_STATUS_IOC) &&
1718 (trb->ctrl & DWC3_TRB_CTRL_IOC))
72246da4
FB		 1719 return 0;
1720 return 1;
1721}
1722
1723static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1724 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1725 int start_new)
1726{
1727 unsigned status = 0;
1728 int clean_busy;
1729
1730 if (event->status & DEPEVT_STATUS_BUSERR)
1731 status = -ECONNRESET;
1732
1d046793 1733 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
c2df85ca 1734 if (clean_busy)
72246da4 1735 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 1736
1737 /*
1738 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1739 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1740 */
1741 if (dwc->revision < DWC3_REVISION_183A) {
1742 u32 reg;
1743 int i;
1744
1745 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1746 struct dwc3_ep *dep = dwc->eps[i];
1747
1748 if (!(dep->flags & DWC3_EP_ENABLED))
1749 continue;
1750
1751 if (!list_empty(&dep->req_queued))
1752 return;
1753 }
1754
1755 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1756 reg |= dwc->u1u2;
1757 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1758
1759 dwc->u1u2 = 0;
1760 }
72246da4
FB		 1761}
1762
72246da4
FB		 1763static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1764 const struct dwc3_event_depevt *event)
1765{
1766 struct dwc3_ep *dep;
1767 u8 epnum = event->endpoint_number;
1768
1769 dep = dwc->eps[epnum];
1770
1771 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1772 dwc3_ep_event_string(event->endpoint_event));
1773
1774 if (epnum == 0 || epnum == 1) {
1775 dwc3_ep0_interrupt(dwc, event);
1776 return;
1777 }
1778
1779 switch (event->endpoint_event) {
1780 case DWC3_DEPEVT_XFERCOMPLETE:
c2df85ca
PZ		 1781 dep->res_trans_idx = 0;
1782
16e78db7 1783 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1784 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1785 dep->name);
1786 return;
1787 }
1788
1789 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1790 break;
1791 case DWC3_DEPEVT_XFERINPROGRESS:
16e78db7 1792 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1793 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1794 dep->name);
1795 return;
1796 }
1797
1798 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1799 break;
1800 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 1801 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1802 dwc3_gadget_start_isoc(dwc, dep, event);
1803 } else {
1804 int ret;
1805
1806 dev_vdbg(dwc->dev, "%s: reason %s\n",
40aa41fb
FB		 1807 dep->name, event->status &
1808 DEPEVT_STATUS_TRANSFER_ACTIVE
72246da4
FB		 1809 ? "Transfer Active"
1810 : "Transfer Not Active");
1811
1812 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1813 if (!ret || ret == -EBUSY)
1814 return;
1815
1816 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1817 dep->name);
1818 }
1819
879631aa
FB		 1820 break;
1821 case DWC3_DEPEVT_STREAMEVT:
16e78db7 1822 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 1823 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1824 dep->name);
1825 return;
1826 }
1827
1828 switch (event->status) {
1829 case DEPEVT_STREAMEVT_FOUND:
1830 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1831 event->parameters);
1832
1833 break;
1834 case DEPEVT_STREAMEVT_NOTFOUND:
1835 /* FALLTHROUGH */
1836 default:
1837 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1838 }
72246da4
FB		 1839 break;
1840 case DWC3_DEPEVT_RXTXFIFOEVT:
1841 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1842 break;
72246da4 1843 case DWC3_DEPEVT_EPCMDCMPLT:
ea53b882 1844 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
72246da4
FB		 1845 break;
1846 }
1847}
1848
1849static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1850{
1851 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1852 spin_unlock(&dwc->lock);
1853 dwc->gadget_driver->disconnect(&dwc->gadget);
1854 spin_lock(&dwc->lock);
1855 }
1856}
1857
1858static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1859{
1860 struct dwc3_ep *dep;
1861 struct dwc3_gadget_ep_cmd_params params;
1862 u32 cmd;
1863 int ret;
1864
1865 dep = dwc->eps[epnum];
1866
624407f9 1867 WARN_ON(!dep->res_trans_idx);
72246da4
FB		 1868 if (dep->res_trans_idx) {
1869 cmd = DWC3_DEPCMD_ENDTRANSFER;
1870 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1871 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1872 memset(&params, 0, sizeof(params));
1873 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1874 WARN_ON_ONCE(ret);
a1ae9be5 1875 dep->res_trans_idx = 0;
72246da4
FB		 1876 }
1877}
1878
1879static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1880{
1881 u32 epnum;
1882
1883 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1884 struct dwc3_ep *dep;
1885
1886 dep = dwc->eps[epnum];
1887 if (!(dep->flags & DWC3_EP_ENABLED))
1888 continue;
1889
624407f9 1890 dwc3_remove_requests(dwc, dep);
72246da4
FB		 1891 }
1892}
1893
1894static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1895{
1896 u32 epnum;
1897
1898 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1899 struct dwc3_ep *dep;
1900 struct dwc3_gadget_ep_cmd_params params;
1901 int ret;
1902
1903 dep = dwc->eps[epnum];
1904
1905 if (!(dep->flags & DWC3_EP_STALL))
1906 continue;
1907
1908 dep->flags &= ~DWC3_EP_STALL;
1909
1910 memset(&params, 0, sizeof(params));
1911 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1912 DWC3_DEPCMD_CLEARSTALL, &params);
1913 WARN_ON_ONCE(ret);
1914 }
1915}
1916
1917static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1918{
c4430a26
FB		 1919 int reg;
1920
72246da4 1921 dev_vdbg(dwc->dev, "%s\n", __func__);
72246da4
FB		 1922
1923 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1924 reg &= ~DWC3_DCTL_INITU1ENA;
1925 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1926
1927 reg &= ~DWC3_DCTL_INITU2ENA;
1928 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 1929
72246da4 1930 dwc3_disconnect_gadget(dwc);
b23c8439 1931 dwc->start_config_issued = false;
72246da4
FB		 1932
1933 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 1934 dwc->setup_packet_pending = false;
72246da4
FB		 1935}
1936
d7a46a8d 1937static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 1938{
1939 u32 reg;
1940
1941 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1942
d7a46a8d 1943 if (suspend)
72246da4 1944 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
d7a46a8d
PZ		 1945 else
1946 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
72246da4
FB		 1947
1948 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1949}
1950
d7a46a8d 1951static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 1952{
1953 u32 reg;
1954
1955 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1956
d7a46a8d 1957 if (suspend)
72246da4 1958 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
d7a46a8d
PZ		 1959 else
1960 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
72246da4
FB		 1961
1962 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1963}
1964
1965static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1966{
1967 u32 reg;
1968
1969 dev_vdbg(dwc->dev, "%s\n", __func__);
1970
df62df56
FB		 1971 /*
1972 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1973 * would cause a missing Disconnect Event if there's a
1974 * pending Setup Packet in the FIFO.
1975 *
1976 * There's no suggested workaround on the official Bug
1977 * report, which states that "unless the driver/application
1978 * is doing any special handling of a disconnect event,
1979 * there is no functional issue".
1980 *
1981 * Unfortunately, it turns out that we _do_ some special
1982 * handling of a disconnect event, namely complete all
1983 * pending transfers, notify gadget driver of the
1984 * disconnection, and so on.
1985 *
1986 * Our suggested workaround is to follow the Disconnect
1987 * Event steps here, instead, based on a setup_packet_pending
1988 * flag. Such flag gets set whenever we have a XferNotReady
1989 * event on EP0 and gets cleared on XferComplete for the
1990 * same endpoint.
1991 *
1992 * Refers to:
1993 *
1994 * STAR#9000466709: RTL: Device : Disconnect event not
1995 * generated if setup packet pending in FIFO
1996 */
1997 if (dwc->revision < DWC3_REVISION_188A) {
1998 if (dwc->setup_packet_pending)
1999 dwc3_gadget_disconnect_interrupt(dwc);
2000 }
2001
961906ed
FB		 2002 /* after reset -> Default State */
2003 dwc->dev_state = DWC3_DEFAULT_STATE;
2004
802fde98
PZ		 2005 /* Recent versions support automatic phy suspend and don't need this */
2006 if (dwc->revision < DWC3_REVISION_194A) {
2007 /* Resume PHYs */
2008 dwc3_gadget_usb2_phy_suspend(dwc, false);
2009 dwc3_gadget_usb3_phy_suspend(dwc, false);
2010 }
72246da4
FB		 2011
2012 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2013 dwc3_disconnect_gadget(dwc);
2014
2015 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2016 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
e6a3b5e2 2017 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
5cbe8c22 2018 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
72246da4 2019 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2020 dwc->test_mode = false;
72246da4
FB		 2021
2022 dwc3_stop_active_transfers(dwc);
2023 dwc3_clear_stall_all_ep(dwc);
b23c8439 2024 dwc->start_config_issued = false;
72246da4
FB		 2025
2026 /* Reset device address to zero */
2027 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2028 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2029 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2030}
2031
2032static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2033{
2034 u32 reg;
2035 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2036
2037 /*
2038 * We change the clock only at SS but I dunno why I would want to do
2039 * this. Maybe it becomes part of the power saving plan.
2040 */
2041
2042 if (speed != DWC3_DSTS_SUPERSPEED)
2043 return;
2044
2045 /*
2046 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2047 * each time on Connect Done.
2048 */
2049 if (!usb30_clock)
2050 return;
2051
2052 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2053 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2054 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2055}
2056
d7a46a8d 2057static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
72246da4
FB		 2058{
2059 switch (speed) {
2060 case USB_SPEED_SUPER:
d7a46a8d 2061 dwc3_gadget_usb2_phy_suspend(dwc, true);
72246da4
FB		 2062 break;
2063 case USB_SPEED_HIGH:
2064 case USB_SPEED_FULL:
2065 case USB_SPEED_LOW:
d7a46a8d 2066 dwc3_gadget_usb3_phy_suspend(dwc, true);
72246da4
FB		 2067 break;
2068 }
2069}
2070
2071static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2072{
2073 struct dwc3_gadget_ep_cmd_params params;
2074 struct dwc3_ep *dep;
2075 int ret;
2076 u32 reg;
2077 u8 speed;
2078
2079 dev_vdbg(dwc->dev, "%s\n", __func__);
2080
2081 memset(&params, 0x00, sizeof(params));
2082
72246da4
FB		 2083 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2084 speed = reg & DWC3_DSTS_CONNECTSPD;
2085 dwc->speed = speed;
2086
2087 dwc3_update_ram_clk_sel(dwc, speed);
2088
2089 switch (speed) {
2090 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2091 /*
2092 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2093 * would cause a missing USB3 Reset event.
2094 *
2095 * In such situations, we should force a USB3 Reset
2096 * event by calling our dwc3_gadget_reset_interrupt()
2097 * routine.
2098 *
2099 * Refers to:
2100 *
2101 * STAR#9000483510: RTL: SS : USB3 reset event may
2102 * not be generated always when the link enters poll
2103 */
2104 if (dwc->revision < DWC3_REVISION_190A)
2105 dwc3_gadget_reset_interrupt(dwc);
2106
72246da4
FB		 2107 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2108 dwc->gadget.ep0->maxpacket = 512;
2109 dwc->gadget.speed = USB_SPEED_SUPER;
2110 break;
2111 case DWC3_DCFG_HIGHSPEED:
2112 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2113 dwc->gadget.ep0->maxpacket = 64;
2114 dwc->gadget.speed = USB_SPEED_HIGH;
2115 break;
2116 case DWC3_DCFG_FULLSPEED2:
2117 case DWC3_DCFG_FULLSPEED1:
2118 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2119 dwc->gadget.ep0->maxpacket = 64;
2120 dwc->gadget.speed = USB_SPEED_FULL;
2121 break;
2122 case DWC3_DCFG_LOWSPEED:
2123 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2124 dwc->gadget.ep0->maxpacket = 8;
2125 dwc->gadget.speed = USB_SPEED_LOW;
2126 break;
2127 }
2128
802fde98
PZ		 2129 /* Recent versions support automatic phy suspend and don't need this */
2130 if (dwc->revision < DWC3_REVISION_194A) {
2131 /* Suspend unneeded PHY */
2132 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2133 }
72246da4
FB		 2134
2135 dep = dwc->eps[0];
c90bfaec 2136 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 2137 if (ret) {
2138 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2139 return;
2140 }
2141
2142 dep = dwc->eps[1];
c90bfaec 2143 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 2144 if (ret) {
2145 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2146 return;
2147 }
2148
2149 /*
2150 * Configure PHY via GUSB3PIPECTLn if required.
2151 *
2152 * Update GTXFIFOSIZn
2153 *
2154 * In both cases reset values should be sufficient.
2155 */
2156}
2157
2158static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2159{
2160 dev_vdbg(dwc->dev, "%s\n", __func__);
2161
2162 /*
2163 * TODO take core out of low power mode when that's
2164 * implemented.
2165 */
2166
2167 dwc->gadget_driver->resume(&dwc->gadget);
2168}
2169
2170static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2171 unsigned int evtinfo)
2172{
fae2b904
FB		 2173 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2174
2175 /*
2176 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2177 * on the link partner, the USB session might do multiple entry/exit
2178 * of low power states before a transfer takes place.
2179 *
2180 * Due to this problem, we might experience lower throughput. The
2181 * suggested workaround is to disable DCTL[12:9] bits if we're
2182 * transitioning from U1/U2 to U0 and enable those bits again
2183 * after a transfer completes and there are no pending transfers
2184 * on any of the enabled endpoints.
2185 *
2186 * This is the first half of that workaround.
2187 *
2188 * Refers to:
2189 *
2190 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2191 * core send LGO_Ux entering U0
2192 */
2193 if (dwc->revision < DWC3_REVISION_183A) {
2194 if (next == DWC3_LINK_STATE_U0) {
2195 u32 u1u2;
2196 u32 reg;
2197
2198 switch (dwc->link_state) {
2199 case DWC3_LINK_STATE_U1:
2200 case DWC3_LINK_STATE_U2:
2201 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2202 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2203 | DWC3_DCTL_ACCEPTU2ENA
2204 | DWC3_DCTL_INITU1ENA
2205 | DWC3_DCTL_ACCEPTU1ENA);
2206
2207 if (!dwc->u1u2)
2208 dwc->u1u2 = reg & u1u2;
2209
2210 reg &= ~u1u2;
2211
2212 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2213 break;
2214 default:
2215 /* do nothing */
2216 break;
2217 }
2218 }
2219 }
2220
2221 dwc->link_state = next;
019ac832
FB		 2222
2223 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 2224}
2225
2226static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2227 const struct dwc3_event_devt *event)
2228{
2229 switch (event->type) {
2230 case DWC3_DEVICE_EVENT_DISCONNECT:
2231 dwc3_gadget_disconnect_interrupt(dwc);
2232 break;
2233 case DWC3_DEVICE_EVENT_RESET:
2234 dwc3_gadget_reset_interrupt(dwc);
2235 break;
2236 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2237 dwc3_gadget_conndone_interrupt(dwc);
2238 break;
2239 case DWC3_DEVICE_EVENT_WAKEUP:
2240 dwc3_gadget_wakeup_interrupt(dwc);
2241 break;
2242 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2243 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2244 break;
2245 case DWC3_DEVICE_EVENT_EOPF:
2246 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2247 break;
2248 case DWC3_DEVICE_EVENT_SOF:
2249 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2250 break;
2251 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2252 dev_vdbg(dwc->dev, "Erratic Error\n");
2253 break;
2254 case DWC3_DEVICE_EVENT_CMD_CMPL:
2255 dev_vdbg(dwc->dev, "Command Complete\n");
2256 break;
2257 case DWC3_DEVICE_EVENT_OVERFLOW:
2258 dev_vdbg(dwc->dev, "Overflow\n");
2259 break;
2260 default:
2261 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2262 }
2263}
2264
2265static void dwc3_process_event_entry(struct dwc3 *dwc,
2266 const union dwc3_event *event)
2267{
2268 /* Endpoint IRQ, handle it and return early */
2269 if (event->type.is_devspec == 0) {
2270 /* depevt */
2271 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2272 }
2273
2274 switch (event->type.type) {
2275 case DWC3_EVENT_TYPE_DEV:
2276 dwc3_gadget_interrupt(dwc, &event->devt);
2277 break;
2278 /* REVISIT what to do with Carkit and I2C events ? */
2279 default:
2280 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2281 }
2282}
2283
2284static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2285{
2286 struct dwc3_event_buffer *evt;
2287 int left;
2288 u32 count;
2289
2290 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2291 count &= DWC3_GEVNTCOUNT_MASK;
2292 if (!count)
2293 return IRQ_NONE;
2294
2295 evt = dwc->ev_buffs[buf];
2296 left = count;
2297
2298 while (left > 0) {
2299 union dwc3_event event;
2300
d70d8442
FB		 2301 event.raw = *(u32 *) (evt->buf + evt->lpos);
2302
72246da4
FB		 2303 dwc3_process_event_entry(dwc, &event);
2304 /*
2305 * XXX we wrap around correctly to the next entry as almost all
2306 * entries are 4 bytes in size. There is one entry which has 12
2307 * bytes which is a regular entry followed by 8 bytes data. ATM
2308 * I don't know how things are organized if were get next to the
2309 * a boundary so I worry about that once we try to handle that.
2310 */
2311 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2312 left -= 4;
2313
2314 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2315 }
2316
2317 return IRQ_HANDLED;
2318}
2319
2320static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2321{
2322 struct dwc3 *dwc = _dwc;
2323 int i;
2324 irqreturn_t ret = IRQ_NONE;
2325
2326 spin_lock(&dwc->lock);
2327
9f622b2a 2328 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2329 irqreturn_t status;
2330
2331 status = dwc3_process_event_buf(dwc, i);
2332 if (status == IRQ_HANDLED)
2333 ret = status;
2334 }
2335
2336 spin_unlock(&dwc->lock);
2337
2338 return ret;
2339}
2340
2341/**
2342 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2343 * @dwc: pointer to our controller context structure
72246da4
FB		 2344 *
2345 * Returns 0 on success otherwise negative errno.
2346 */
2347int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2348{
2349 u32 reg;
2350 int ret;
2351 int irq;
2352
2353 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2354 &dwc->ctrl_req_addr, GFP_KERNEL);
2355 if (!dwc->ctrl_req) {
2356 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2357 ret = -ENOMEM;
2358 goto err0;
2359 }
2360
2361 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2362 &dwc->ep0_trb_addr, GFP_KERNEL);
2363 if (!dwc->ep0_trb) {
2364 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2365 ret = -ENOMEM;
2366 goto err1;
2367 }
2368
3ef35faf 2369 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4
FB		 2370 if (!dwc->setup_buf) {
2371 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2372 ret = -ENOMEM;
2373 goto err2;
2374 }
2375
5812b1c2 2376 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2377 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2378 GFP_KERNEL);
5812b1c2
FB		 2379 if (!dwc->ep0_bounce) {
2380 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2381 ret = -ENOMEM;
2382 goto err3;
2383 }
2384
72246da4
FB		 2385 dev_set_name(&dwc->gadget.dev, "gadget");
2386
2387 dwc->gadget.ops = &dwc3_gadget_ops;
d327ab5b 2388 dwc->gadget.max_speed = USB_SPEED_SUPER;
72246da4
FB		 2389 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2390 dwc->gadget.dev.parent = dwc->dev;
eeb720fb 2391 dwc->gadget.sg_supported = true;
72246da4
FB		 2392
2393 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2394
2395 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2396 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2397 dwc->gadget.dev.release = dwc3_gadget_release;
2398 dwc->gadget.name = "dwc3-gadget";
2399
2400 /*
2401 * REVISIT: Here we should clear all pending IRQs to be
2402 * sure we're starting from a well known location.
2403 */
2404
2405 ret = dwc3_gadget_init_endpoints(dwc);
2406 if (ret)
5812b1c2 2407 goto err4;
72246da4
FB		 2408
2409 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2410
2411 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2412 "dwc3", dwc);
2413 if (ret) {
2414 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2415 irq, ret);
5812b1c2 2416 goto err5;
72246da4
FB		 2417 }
2418
e6a3b5e2
SAS		 2419 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2420 reg |= DWC3_DCFG_LPM_CAP;
2421 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2422
72246da4
FB		 2423 /* Enable all but Start and End of Frame IRQs */
2424 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2425 DWC3_DEVTEN_EVNTOVERFLOWEN |
2426 DWC3_DEVTEN_CMDCMPLTEN |
2427 DWC3_DEVTEN_ERRTICERREN |
2428 DWC3_DEVTEN_WKUPEVTEN |
2429 DWC3_DEVTEN_ULSTCNGEN |
2430 DWC3_DEVTEN_CONNECTDONEEN |
2431 DWC3_DEVTEN_USBRSTEN |
2432 DWC3_DEVTEN_DISCONNEVTEN);
2433 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2434
802fde98
PZ		 2435 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2436 if (dwc->revision >= DWC3_REVISION_194A) {
2437 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2438 reg |= DWC3_DCFG_LPM_CAP;
2439 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2440
2441 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2442 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2443
2444 /* TODO: This should be configurable */
2445 reg |= DWC3_DCTL_HIRD_THRES(31);
2446
2447 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2448
2449 dwc3_gadget_usb2_phy_suspend(dwc, true);
2450 dwc3_gadget_usb3_phy_suspend(dwc, true);
2451 }
2452
72246da4
FB		 2453 ret = device_register(&dwc->gadget.dev);
2454 if (ret) {
2455 dev_err(dwc->dev, "failed to register gadget device\n");
2456 put_device(&dwc->gadget.dev);
5812b1c2 2457 goto err6;
72246da4
FB		 2458 }
2459
2460 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2461 if (ret) {
2462 dev_err(dwc->dev, "failed to register udc\n");
5812b1c2 2463 goto err7;
72246da4
FB		 2464 }
2465
2466 return 0;
2467
5812b1c2 2468err7:
72246da4
FB		 2469 device_unregister(&dwc->gadget.dev);
2470
5812b1c2 2471err6:
72246da4
FB		 2472 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2473 free_irq(irq, dwc);
2474
5812b1c2 2475err5:
72246da4
FB		 2476 dwc3_gadget_free_endpoints(dwc);
2477
5812b1c2 2478err4:
3ef35faf
FB		 2479 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2480 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2481
72246da4 2482err3:
0fc9a1be 2483 kfree(dwc->setup_buf);
72246da4
FB		 2484
2485err2:
2486 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2487 dwc->ep0_trb, dwc->ep0_trb_addr);
2488
2489err1:
2490 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2491 dwc->ctrl_req, dwc->ctrl_req_addr);
2492
2493err0:
2494 return ret;
2495}
2496
2497void dwc3_gadget_exit(struct dwc3 *dwc)
2498{
2499 int irq;
72246da4
FB		 2500
2501 usb_del_gadget_udc(&dwc->gadget);
2502 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2503
2504 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2505 free_irq(irq, dwc);
2506
72246da4
FB		 2507 dwc3_gadget_free_endpoints(dwc);
2508
3ef35faf
FB		 2509 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2510 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2511
0fc9a1be 2512 kfree(dwc->setup_buf);
72246da4
FB		 2513
2514 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2515 dwc->ep0_trb, dwc->ep0_trb_addr);
2516
2517 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2518 dwc->ctrl_req, dwc->ctrl_req_addr);
2519
2520 device_unregister(&dwc->gadget.dev);
2521}
Linux kernel - Deliverables
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