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72246da4 FB |
1 | /** |
2 | * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
9 | * Redistribution and use in source and binary forms, with or without | |
10 | * modification, are permitted provided that the following conditions | |
11 | * are met: | |
12 | * 1. Redistributions of source code must retain the above copyright | |
13 | * notice, this list of conditions, and the following disclaimer, | |
14 | * without modification. | |
15 | * 2. Redistributions in binary form must reproduce the above copyright | |
16 | * notice, this list of conditions and the following disclaimer in the | |
17 | * documentation and/or other materials provided with the distribution. | |
18 | * 3. The names of the above-listed copyright holders may not be used | |
19 | * to endorse or promote products derived from this software without | |
20 | * specific prior written permission. | |
21 | * | |
22 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
23 | * GNU General Public License ("GPL") version 2, as published by the Free | |
24 | * Software Foundation. | |
25 | * | |
26 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS | |
27 | * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, | |
28 | * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | |
29 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR | |
30 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, | |
31 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, | |
32 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR | |
33 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF | |
34 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING | |
35 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
36 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
37 | */ | |
38 | ||
39 | #include <linux/kernel.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/spinlock.h> | |
43 | #include <linux/platform_device.h> | |
44 | #include <linux/pm_runtime.h> | |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/list.h> | |
48 | #include <linux/dma-mapping.h> | |
49 | ||
50 | #include <linux/usb/ch9.h> | |
51 | #include <linux/usb/gadget.h> | |
52 | ||
53 | #include "core.h" | |
54 | #include "gadget.h" | |
55 | #include "io.h" | |
56 | ||
04a9bfcd FB |
57 | /** |
58 | * dwc3_gadget_set_test_mode - Enables USB2 Test Modes | |
59 | * @dwc: pointer to our context structure | |
60 | * @mode: the mode to set (J, K SE0 NAK, Force Enable) | |
61 | * | |
62 | * Caller should take care of locking. This function will | |
63 | * return 0 on success or -EINVAL if wrong Test Selector | |
64 | * is passed | |
65 | */ | |
66 | int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) | |
67 | { | |
68 | u32 reg; | |
69 | ||
70 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
71 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
72 | ||
73 | switch (mode) { | |
74 | case TEST_J: | |
75 | case TEST_K: | |
76 | case TEST_SE0_NAK: | |
77 | case TEST_PACKET: | |
78 | case TEST_FORCE_EN: | |
79 | reg |= mode << 1; | |
80 | break; | |
81 | default: | |
82 | return -EINVAL; | |
83 | } | |
84 | ||
85 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
8598bde7 FB |
90 | /** |
91 | * dwc3_gadget_set_link_state - Sets USB Link to a particular State | |
92 | * @dwc: pointer to our context structure | |
93 | * @state: the state to put link into | |
94 | * | |
95 | * Caller should take care of locking. This function will | |
aee63e3c | 96 | * return 0 on success or -ETIMEDOUT. |
8598bde7 FB |
97 | */ |
98 | int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) | |
99 | { | |
aee63e3c | 100 | int retries = 10000; |
8598bde7 FB |
101 | u32 reg; |
102 | ||
103 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
104 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
105 | ||
106 | /* set requested state */ | |
107 | reg |= DWC3_DCTL_ULSTCHNGREQ(state); | |
108 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
109 | ||
110 | /* wait for a change in DSTS */ | |
111 | while (--retries) { | |
112 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
113 | ||
8598bde7 FB |
114 | if (DWC3_DSTS_USBLNKST(reg) == state) |
115 | return 0; | |
116 | ||
aee63e3c | 117 | udelay(5); |
8598bde7 FB |
118 | } |
119 | ||
120 | dev_vdbg(dwc->dev, "link state change request timed out\n"); | |
121 | ||
122 | return -ETIMEDOUT; | |
123 | } | |
124 | ||
457e84b6 FB |
125 | /** |
126 | * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case | |
127 | * @dwc: pointer to our context structure | |
128 | * | |
129 | * This function will a best effort FIFO allocation in order | |
130 | * to improve FIFO usage and throughput, while still allowing | |
131 | * us to enable as many endpoints as possible. | |
132 | * | |
133 | * Keep in mind that this operation will be highly dependent | |
134 | * on the configured size for RAM1 - which contains TxFifo -, | |
135 | * the amount of endpoints enabled on coreConsultant tool, and | |
136 | * the width of the Master Bus. | |
137 | * | |
138 | * In the ideal world, we would always be able to satisfy the | |
139 | * following equation: | |
140 | * | |
141 | * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ | |
142 | * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes | |
143 | * | |
144 | * Unfortunately, due to many variables that's not always the case. | |
145 | */ | |
146 | int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) | |
147 | { | |
148 | int last_fifo_depth = 0; | |
149 | int ram1_depth; | |
150 | int fifo_size; | |
151 | int mdwidth; | |
152 | int num; | |
153 | ||
154 | if (!dwc->needs_fifo_resize) | |
155 | return 0; | |
156 | ||
157 | ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); | |
158 | mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); | |
159 | ||
160 | /* MDWIDTH is represented in bits, we need it in bytes */ | |
161 | mdwidth >>= 3; | |
162 | ||
163 | /* | |
164 | * FIXME For now we will only allocate 1 wMaxPacketSize space | |
165 | * for each enabled endpoint, later patches will come to | |
166 | * improve this algorithm so that we better use the internal | |
167 | * FIFO space | |
168 | */ | |
169 | for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) { | |
170 | struct dwc3_ep *dep = dwc->eps[num]; | |
171 | int fifo_number = dep->number >> 1; | |
2e81c36a | 172 | int mult = 1; |
457e84b6 FB |
173 | int tmp; |
174 | ||
175 | if (!(dep->number & 1)) | |
176 | continue; | |
177 | ||
178 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
179 | continue; | |
180 | ||
16e78db7 IS |
181 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) |
182 | || usb_endpoint_xfer_isoc(dep->endpoint.desc)) | |
2e81c36a FB |
183 | mult = 3; |
184 | ||
185 | /* | |
186 | * REVISIT: the following assumes we will always have enough | |
187 | * space available on the FIFO RAM for all possible use cases. | |
188 | * Make sure that's true somehow and change FIFO allocation | |
189 | * accordingly. | |
190 | * | |
191 | * If we have Bulk or Isochronous endpoints, we want | |
192 | * them to be able to be very, very fast. So we're giving | |
193 | * those endpoints a fifo_size which is enough for 3 full | |
194 | * packets | |
195 | */ | |
196 | tmp = mult * (dep->endpoint.maxpacket + mdwidth); | |
457e84b6 FB |
197 | tmp += mdwidth; |
198 | ||
199 | fifo_size = DIV_ROUND_UP(tmp, mdwidth); | |
2e81c36a | 200 | |
457e84b6 FB |
201 | fifo_size |= (last_fifo_depth << 16); |
202 | ||
203 | dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", | |
204 | dep->name, last_fifo_depth, fifo_size & 0xffff); | |
205 | ||
206 | dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number), | |
207 | fifo_size); | |
208 | ||
209 | last_fifo_depth += (fifo_size & 0xffff); | |
210 | } | |
211 | ||
212 | return 0; | |
213 | } | |
214 | ||
72246da4 FB |
215 | void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, |
216 | int status) | |
217 | { | |
218 | struct dwc3 *dwc = dep->dwc; | |
219 | ||
220 | if (req->queued) { | |
eeb720fb FB |
221 | if (req->request.num_mapped_sgs) |
222 | dep->busy_slot += req->request.num_mapped_sgs; | |
223 | else | |
224 | dep->busy_slot++; | |
225 | ||
72246da4 FB |
226 | /* |
227 | * Skip LINK TRB. We can't use req->trb and check for | |
228 | * DWC3_TRBCTL_LINK_TRB because it points the TRB we just | |
229 | * completed (not the LINK TRB). | |
230 | */ | |
231 | if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && | |
16e78db7 | 232 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
72246da4 FB |
233 | dep->busy_slot++; |
234 | } | |
235 | list_del(&req->list); | |
eeb720fb | 236 | req->trb = NULL; |
72246da4 FB |
237 | |
238 | if (req->request.status == -EINPROGRESS) | |
239 | req->request.status = status; | |
240 | ||
0fc9a1be FB |
241 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
242 | req->direction); | |
72246da4 FB |
243 | |
244 | dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", | |
245 | req, dep->name, req->request.actual, | |
246 | req->request.length, status); | |
247 | ||
248 | spin_unlock(&dwc->lock); | |
0fc9a1be | 249 | req->request.complete(&dep->endpoint, &req->request); |
72246da4 FB |
250 | spin_lock(&dwc->lock); |
251 | } | |
252 | ||
253 | static const char *dwc3_gadget_ep_cmd_string(u8 cmd) | |
254 | { | |
255 | switch (cmd) { | |
256 | case DWC3_DEPCMD_DEPSTARTCFG: | |
257 | return "Start New Configuration"; | |
258 | case DWC3_DEPCMD_ENDTRANSFER: | |
259 | return "End Transfer"; | |
260 | case DWC3_DEPCMD_UPDATETRANSFER: | |
261 | return "Update Transfer"; | |
262 | case DWC3_DEPCMD_STARTTRANSFER: | |
263 | return "Start Transfer"; | |
264 | case DWC3_DEPCMD_CLEARSTALL: | |
265 | return "Clear Stall"; | |
266 | case DWC3_DEPCMD_SETSTALL: | |
267 | return "Set Stall"; | |
268 | case DWC3_DEPCMD_GETSEQNUMBER: | |
269 | return "Get Data Sequence Number"; | |
270 | case DWC3_DEPCMD_SETTRANSFRESOURCE: | |
271 | return "Set Endpoint Transfer Resource"; | |
272 | case DWC3_DEPCMD_SETEPCONFIG: | |
273 | return "Set Endpoint Configuration"; | |
274 | default: | |
275 | return "UNKNOWN command"; | |
276 | } | |
277 | } | |
278 | ||
b09bb642 FB |
279 | int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param) |
280 | { | |
281 | u32 timeout = 500; | |
282 | u32 reg; | |
283 | ||
284 | dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); | |
285 | dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); | |
286 | ||
287 | do { | |
288 | reg = dwc3_readl(dwc->regs, DWC3_DGCMD); | |
289 | if (!(reg & DWC3_DGCMD_CMDACT)) { | |
290 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", | |
291 | DWC3_DGCMD_STATUS(reg)); | |
292 | return 0; | |
293 | } | |
294 | ||
295 | /* | |
296 | * We can't sleep here, because it's also called from | |
297 | * interrupt context. | |
298 | */ | |
299 | timeout--; | |
300 | if (!timeout) | |
301 | return -ETIMEDOUT; | |
302 | udelay(1); | |
303 | } while (1); | |
304 | } | |
305 | ||
72246da4 FB |
306 | int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, |
307 | unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) | |
308 | { | |
309 | struct dwc3_ep *dep = dwc->eps[ep]; | |
61d58242 | 310 | u32 timeout = 500; |
72246da4 FB |
311 | u32 reg; |
312 | ||
313 | dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n", | |
314 | dep->name, | |
dc1c70a7 FB |
315 | dwc3_gadget_ep_cmd_string(cmd), params->param0, |
316 | params->param1, params->param2); | |
72246da4 | 317 | |
dc1c70a7 FB |
318 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); |
319 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); | |
320 | dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); | |
72246da4 FB |
321 | |
322 | dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); | |
323 | do { | |
324 | reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); | |
325 | if (!(reg & DWC3_DEPCMD_CMDACT)) { | |
164f6e14 FB |
326 | dev_vdbg(dwc->dev, "Command Complete --> %d\n", |
327 | DWC3_DEPCMD_STATUS(reg)); | |
72246da4 FB |
328 | return 0; |
329 | } | |
330 | ||
331 | /* | |
72246da4 FB |
332 | * We can't sleep here, because it is also called from |
333 | * interrupt context. | |
334 | */ | |
335 | timeout--; | |
336 | if (!timeout) | |
337 | return -ETIMEDOUT; | |
338 | ||
61d58242 | 339 | udelay(1); |
72246da4 FB |
340 | } while (1); |
341 | } | |
342 | ||
343 | static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, | |
f6bafc6a | 344 | struct dwc3_trb *trb) |
72246da4 | 345 | { |
c439ef87 | 346 | u32 offset = (char *) trb - (char *) dep->trb_pool; |
72246da4 FB |
347 | |
348 | return dep->trb_pool_dma + offset; | |
349 | } | |
350 | ||
351 | static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) | |
352 | { | |
353 | struct dwc3 *dwc = dep->dwc; | |
354 | ||
355 | if (dep->trb_pool) | |
356 | return 0; | |
357 | ||
358 | if (dep->number == 0 || dep->number == 1) | |
359 | return 0; | |
360 | ||
361 | dep->trb_pool = dma_alloc_coherent(dwc->dev, | |
362 | sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
363 | &dep->trb_pool_dma, GFP_KERNEL); | |
364 | if (!dep->trb_pool) { | |
365 | dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", | |
366 | dep->name); | |
367 | return -ENOMEM; | |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static void dwc3_free_trb_pool(struct dwc3_ep *dep) | |
374 | { | |
375 | struct dwc3 *dwc = dep->dwc; | |
376 | ||
377 | dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, | |
378 | dep->trb_pool, dep->trb_pool_dma); | |
379 | ||
380 | dep->trb_pool = NULL; | |
381 | dep->trb_pool_dma = 0; | |
382 | } | |
383 | ||
384 | static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) | |
385 | { | |
386 | struct dwc3_gadget_ep_cmd_params params; | |
387 | u32 cmd; | |
388 | ||
389 | memset(¶ms, 0x00, sizeof(params)); | |
390 | ||
391 | if (dep->number != 1) { | |
392 | cmd = DWC3_DEPCMD_DEPSTARTCFG; | |
393 | /* XferRscIdx == 0 for ep0 and 2 for the remaining */ | |
b23c8439 PZ |
394 | if (dep->number > 1) { |
395 | if (dwc->start_config_issued) | |
396 | return 0; | |
397 | dwc->start_config_issued = true; | |
72246da4 | 398 | cmd |= DWC3_DEPCMD_PARAM(2); |
b23c8439 | 399 | } |
72246da4 FB |
400 | |
401 | return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); | |
402 | } | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, | |
c90bfaec FB |
408 | const struct usb_endpoint_descriptor *desc, |
409 | const struct usb_ss_ep_comp_descriptor *comp_desc) | |
72246da4 FB |
410 | { |
411 | struct dwc3_gadget_ep_cmd_params params; | |
412 | ||
413 | memset(¶ms, 0x00, sizeof(params)); | |
414 | ||
dc1c70a7 FB |
415 | params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) |
416 | | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)) | |
417 | | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst); | |
72246da4 | 418 | |
dc1c70a7 FB |
419 | params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN |
420 | | DWC3_DEPCFG_XFER_NOT_READY_EN; | |
72246da4 | 421 | |
18b7ede5 | 422 | if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { |
dc1c70a7 FB |
423 | params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE |
424 | | DWC3_DEPCFG_STREAM_EVENT_EN; | |
879631aa FB |
425 | dep->stream_capable = true; |
426 | } | |
427 | ||
72246da4 | 428 | if (usb_endpoint_xfer_isoc(desc)) |
dc1c70a7 | 429 | params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; |
72246da4 FB |
430 | |
431 | /* | |
432 | * We are doing 1:1 mapping for endpoints, meaning | |
433 | * Physical Endpoints 2 maps to Logical Endpoint 2 and | |
434 | * so on. We consider the direction bit as part of the physical | |
435 | * endpoint number. So USB endpoint 0x81 is 0x03. | |
436 | */ | |
dc1c70a7 | 437 | params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); |
72246da4 FB |
438 | |
439 | /* | |
440 | * We must use the lower 16 TX FIFOs even though | |
441 | * HW might have more | |
442 | */ | |
443 | if (dep->direction) | |
dc1c70a7 | 444 | params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); |
72246da4 FB |
445 | |
446 | if (desc->bInterval) { | |
dc1c70a7 | 447 | params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); |
72246da4 FB |
448 | dep->interval = 1 << (desc->bInterval - 1); |
449 | } | |
450 | ||
451 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
452 | DWC3_DEPCMD_SETEPCONFIG, ¶ms); | |
453 | } | |
454 | ||
455 | static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) | |
456 | { | |
457 | struct dwc3_gadget_ep_cmd_params params; | |
458 | ||
459 | memset(¶ms, 0x00, sizeof(params)); | |
460 | ||
dc1c70a7 | 461 | params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); |
72246da4 FB |
462 | |
463 | return dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
464 | DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); | |
465 | } | |
466 | ||
467 | /** | |
468 | * __dwc3_gadget_ep_enable - Initializes a HW endpoint | |
469 | * @dep: endpoint to be initialized | |
470 | * @desc: USB Endpoint Descriptor | |
471 | * | |
472 | * Caller should take care of locking | |
473 | */ | |
474 | static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, | |
c90bfaec FB |
475 | const struct usb_endpoint_descriptor *desc, |
476 | const struct usb_ss_ep_comp_descriptor *comp_desc) | |
72246da4 FB |
477 | { |
478 | struct dwc3 *dwc = dep->dwc; | |
479 | u32 reg; | |
480 | int ret = -ENOMEM; | |
481 | ||
482 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
483 | ret = dwc3_gadget_start_config(dwc, dep); | |
484 | if (ret) | |
485 | return ret; | |
486 | } | |
487 | ||
c90bfaec | 488 | ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc); |
72246da4 FB |
489 | if (ret) |
490 | return ret; | |
491 | ||
492 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
f6bafc6a FB |
493 | struct dwc3_trb *trb_st_hw; |
494 | struct dwc3_trb *trb_link; | |
72246da4 FB |
495 | |
496 | ret = dwc3_gadget_set_xfer_resource(dwc, dep); | |
497 | if (ret) | |
498 | return ret; | |
499 | ||
16e78db7 | 500 | dep->endpoint.desc = desc; |
c90bfaec | 501 | dep->comp_desc = comp_desc; |
72246da4 FB |
502 | dep->type = usb_endpoint_type(desc); |
503 | dep->flags |= DWC3_EP_ENABLED; | |
504 | ||
505 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
506 | reg |= DWC3_DALEPENA_EP(dep->number); | |
507 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
508 | ||
509 | if (!usb_endpoint_xfer_isoc(desc)) | |
510 | return 0; | |
511 | ||
512 | memset(&trb_link, 0, sizeof(trb_link)); | |
513 | ||
1d046793 | 514 | /* Link TRB for ISOC. The HWO bit is never reset */ |
72246da4 FB |
515 | trb_st_hw = &dep->trb_pool[0]; |
516 | ||
f6bafc6a | 517 | trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; |
72246da4 | 518 | |
f6bafc6a FB |
519 | trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); |
520 | trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); | |
521 | trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; | |
522 | trb_link->ctrl |= DWC3_TRB_CTRL_HWO; | |
72246da4 FB |
523 | } |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
624407f9 SAS |
528 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum); |
529 | static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) | |
72246da4 FB |
530 | { |
531 | struct dwc3_request *req; | |
532 | ||
624407f9 SAS |
533 | if (!list_empty(&dep->req_queued)) |
534 | dwc3_stop_active_transfer(dwc, dep->number); | |
535 | ||
72246da4 FB |
536 | while (!list_empty(&dep->request_list)) { |
537 | req = next_request(&dep->request_list); | |
538 | ||
624407f9 | 539 | dwc3_gadget_giveback(dep, req, -ESHUTDOWN); |
72246da4 | 540 | } |
72246da4 FB |
541 | } |
542 | ||
543 | /** | |
544 | * __dwc3_gadget_ep_disable - Disables a HW endpoint | |
545 | * @dep: the endpoint to disable | |
546 | * | |
624407f9 SAS |
547 | * This function also removes requests which are currently processed ny the |
548 | * hardware and those which are not yet scheduled. | |
549 | * Caller should take care of locking. | |
72246da4 | 550 | */ |
72246da4 FB |
551 | static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) |
552 | { | |
553 | struct dwc3 *dwc = dep->dwc; | |
554 | u32 reg; | |
555 | ||
624407f9 | 556 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
557 | |
558 | reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); | |
559 | reg &= ~DWC3_DALEPENA_EP(dep->number); | |
560 | dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); | |
561 | ||
879631aa | 562 | dep->stream_capable = false; |
f9c56cdd | 563 | dep->endpoint.desc = NULL; |
c90bfaec | 564 | dep->comp_desc = NULL; |
72246da4 | 565 | dep->type = 0; |
879631aa | 566 | dep->flags = 0; |
72246da4 FB |
567 | |
568 | return 0; | |
569 | } | |
570 | ||
571 | /* -------------------------------------------------------------------------- */ | |
572 | ||
573 | static int dwc3_gadget_ep0_enable(struct usb_ep *ep, | |
574 | const struct usb_endpoint_descriptor *desc) | |
575 | { | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
579 | static int dwc3_gadget_ep0_disable(struct usb_ep *ep) | |
580 | { | |
581 | return -EINVAL; | |
582 | } | |
583 | ||
584 | /* -------------------------------------------------------------------------- */ | |
585 | ||
586 | static int dwc3_gadget_ep_enable(struct usb_ep *ep, | |
587 | const struct usb_endpoint_descriptor *desc) | |
588 | { | |
589 | struct dwc3_ep *dep; | |
590 | struct dwc3 *dwc; | |
591 | unsigned long flags; | |
592 | int ret; | |
593 | ||
594 | if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { | |
595 | pr_debug("dwc3: invalid parameters\n"); | |
596 | return -EINVAL; | |
597 | } | |
598 | ||
599 | if (!desc->wMaxPacketSize) { | |
600 | pr_debug("dwc3: missing wMaxPacketSize\n"); | |
601 | return -EINVAL; | |
602 | } | |
603 | ||
604 | dep = to_dwc3_ep(ep); | |
605 | dwc = dep->dwc; | |
606 | ||
607 | switch (usb_endpoint_type(desc)) { | |
608 | case USB_ENDPOINT_XFER_CONTROL: | |
27a78d6a | 609 | strlcat(dep->name, "-control", sizeof(dep->name)); |
72246da4 FB |
610 | break; |
611 | case USB_ENDPOINT_XFER_ISOC: | |
27a78d6a | 612 | strlcat(dep->name, "-isoc", sizeof(dep->name)); |
72246da4 FB |
613 | break; |
614 | case USB_ENDPOINT_XFER_BULK: | |
27a78d6a | 615 | strlcat(dep->name, "-bulk", sizeof(dep->name)); |
72246da4 FB |
616 | break; |
617 | case USB_ENDPOINT_XFER_INT: | |
27a78d6a | 618 | strlcat(dep->name, "-int", sizeof(dep->name)); |
72246da4 FB |
619 | break; |
620 | default: | |
621 | dev_err(dwc->dev, "invalid endpoint transfer type\n"); | |
622 | } | |
623 | ||
624 | if (dep->flags & DWC3_EP_ENABLED) { | |
625 | dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", | |
626 | dep->name); | |
627 | return 0; | |
628 | } | |
629 | ||
630 | dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); | |
631 | ||
632 | spin_lock_irqsave(&dwc->lock, flags); | |
c90bfaec | 633 | ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc); |
72246da4 FB |
634 | spin_unlock_irqrestore(&dwc->lock, flags); |
635 | ||
636 | return ret; | |
637 | } | |
638 | ||
639 | static int dwc3_gadget_ep_disable(struct usb_ep *ep) | |
640 | { | |
641 | struct dwc3_ep *dep; | |
642 | struct dwc3 *dwc; | |
643 | unsigned long flags; | |
644 | int ret; | |
645 | ||
646 | if (!ep) { | |
647 | pr_debug("dwc3: invalid parameters\n"); | |
648 | return -EINVAL; | |
649 | } | |
650 | ||
651 | dep = to_dwc3_ep(ep); | |
652 | dwc = dep->dwc; | |
653 | ||
654 | if (!(dep->flags & DWC3_EP_ENABLED)) { | |
655 | dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", | |
656 | dep->name); | |
657 | return 0; | |
658 | } | |
659 | ||
660 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", | |
661 | dep->number >> 1, | |
662 | (dep->number & 1) ? "in" : "out"); | |
663 | ||
664 | spin_lock_irqsave(&dwc->lock, flags); | |
665 | ret = __dwc3_gadget_ep_disable(dep); | |
666 | spin_unlock_irqrestore(&dwc->lock, flags); | |
667 | ||
668 | return ret; | |
669 | } | |
670 | ||
671 | static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, | |
672 | gfp_t gfp_flags) | |
673 | { | |
674 | struct dwc3_request *req; | |
675 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
676 | struct dwc3 *dwc = dep->dwc; | |
677 | ||
678 | req = kzalloc(sizeof(*req), gfp_flags); | |
679 | if (!req) { | |
680 | dev_err(dwc->dev, "not enough memory\n"); | |
681 | return NULL; | |
682 | } | |
683 | ||
684 | req->epnum = dep->number; | |
685 | req->dep = dep; | |
72246da4 FB |
686 | |
687 | return &req->request; | |
688 | } | |
689 | ||
690 | static void dwc3_gadget_ep_free_request(struct usb_ep *ep, | |
691 | struct usb_request *request) | |
692 | { | |
693 | struct dwc3_request *req = to_dwc3_request(request); | |
694 | ||
695 | kfree(req); | |
696 | } | |
697 | ||
c71fc37c FB |
698 | /** |
699 | * dwc3_prepare_one_trb - setup one TRB from one request | |
700 | * @dep: endpoint for which this request is prepared | |
701 | * @req: dwc3_request pointer | |
702 | */ | |
68e823e2 | 703 | static void dwc3_prepare_one_trb(struct dwc3_ep *dep, |
eeb720fb FB |
704 | struct dwc3_request *req, dma_addr_t dma, |
705 | unsigned length, unsigned last, unsigned chain) | |
c71fc37c | 706 | { |
eeb720fb | 707 | struct dwc3 *dwc = dep->dwc; |
f6bafc6a | 708 | struct dwc3_trb *trb; |
c71fc37c FB |
709 | |
710 | unsigned int cur_slot; | |
711 | ||
eeb720fb FB |
712 | dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", |
713 | dep->name, req, (unsigned long long) dma, | |
714 | length, last ? " last" : "", | |
715 | chain ? " chain" : ""); | |
716 | ||
f6bafc6a | 717 | trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; |
c71fc37c FB |
718 | cur_slot = dep->free_slot; |
719 | dep->free_slot++; | |
720 | ||
721 | /* Skip the LINK-TRB on ISOC */ | |
722 | if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && | |
16e78db7 | 723 | usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 724 | return; |
c71fc37c | 725 | |
eeb720fb FB |
726 | if (!req->trb) { |
727 | dwc3_gadget_move_request_queued(req); | |
f6bafc6a FB |
728 | req->trb = trb; |
729 | req->trb_dma = dwc3_trb_dma_offset(dep, trb); | |
eeb720fb | 730 | } |
c71fc37c | 731 | |
f6bafc6a FB |
732 | trb->size = DWC3_TRB_SIZE_LENGTH(length); |
733 | trb->bpl = lower_32_bits(dma); | |
734 | trb->bph = upper_32_bits(dma); | |
c71fc37c | 735 | |
16e78db7 | 736 | switch (usb_endpoint_type(dep->endpoint.desc)) { |
c71fc37c | 737 | case USB_ENDPOINT_XFER_CONTROL: |
f6bafc6a | 738 | trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; |
c71fc37c FB |
739 | break; |
740 | ||
741 | case USB_ENDPOINT_XFER_ISOC: | |
f6bafc6a | 742 | trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; |
c71fc37c FB |
743 | |
744 | /* IOC every DWC3_TRB_NUM / 4 so we can refill */ | |
745 | if (!(cur_slot % (DWC3_TRB_NUM / 4))) | |
f6bafc6a | 746 | trb->ctrl |= DWC3_TRB_CTRL_IOC; |
c71fc37c FB |
747 | break; |
748 | ||
749 | case USB_ENDPOINT_XFER_BULK: | |
750 | case USB_ENDPOINT_XFER_INT: | |
f6bafc6a | 751 | trb->ctrl = DWC3_TRBCTL_NORMAL; |
c71fc37c FB |
752 | break; |
753 | default: | |
754 | /* | |
755 | * This is only possible with faulty memory because we | |
756 | * checked it already :) | |
757 | */ | |
758 | BUG(); | |
759 | } | |
760 | ||
16e78db7 | 761 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
f6bafc6a FB |
762 | trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; |
763 | trb->ctrl |= DWC3_TRB_CTRL_CSP; | |
764 | } else { | |
765 | if (chain) | |
766 | trb->ctrl |= DWC3_TRB_CTRL_CHN; | |
767 | ||
768 | if (last) | |
769 | trb->ctrl |= DWC3_TRB_CTRL_LST; | |
770 | } | |
c71fc37c | 771 | |
16e78db7 | 772 | if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) |
f6bafc6a | 773 | trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); |
c71fc37c | 774 | |
f6bafc6a | 775 | trb->ctrl |= DWC3_TRB_CTRL_HWO; |
c71fc37c FB |
776 | } |
777 | ||
72246da4 FB |
778 | /* |
779 | * dwc3_prepare_trbs - setup TRBs from requests | |
780 | * @dep: endpoint for which requests are being prepared | |
781 | * @starting: true if the endpoint is idle and no requests are queued. | |
782 | * | |
1d046793 PZ |
783 | * The function goes through the requests list and sets up TRBs for the |
784 | * transfers. The function returns once there are no more TRBs available or | |
785 | * it runs out of requests. | |
72246da4 | 786 | */ |
68e823e2 | 787 | static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) |
72246da4 | 788 | { |
68e823e2 | 789 | struct dwc3_request *req, *n; |
72246da4 | 790 | u32 trbs_left; |
8d62cd65 | 791 | u32 max; |
c71fc37c | 792 | unsigned int last_one = 0; |
72246da4 FB |
793 | |
794 | BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); | |
795 | ||
796 | /* the first request must not be queued */ | |
797 | trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; | |
c71fc37c | 798 | |
8d62cd65 | 799 | /* Can't wrap around on a non-isoc EP since there's no link TRB */ |
16e78db7 | 800 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
8d62cd65 PZ |
801 | max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); |
802 | if (trbs_left > max) | |
803 | trbs_left = max; | |
804 | } | |
805 | ||
72246da4 | 806 | /* |
1d046793 PZ |
807 | * If busy & slot are equal than it is either full or empty. If we are |
808 | * starting to process requests then we are empty. Otherwise we are | |
72246da4 FB |
809 | * full and don't do anything |
810 | */ | |
811 | if (!trbs_left) { | |
812 | if (!starting) | |
68e823e2 | 813 | return; |
72246da4 FB |
814 | trbs_left = DWC3_TRB_NUM; |
815 | /* | |
816 | * In case we start from scratch, we queue the ISOC requests | |
817 | * starting from slot 1. This is done because we use ring | |
818 | * buffer and have no LST bit to stop us. Instead, we place | |
1d046793 | 819 | * IOC bit every TRB_NUM/4. We try to avoid having an interrupt |
72246da4 FB |
820 | * after the first request so we start at slot 1 and have |
821 | * 7 requests proceed before we hit the first IOC. | |
822 | * Other transfer types don't use the ring buffer and are | |
823 | * processed from the first TRB until the last one. Since we | |
824 | * don't wrap around we have to start at the beginning. | |
825 | */ | |
16e78db7 | 826 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
827 | dep->busy_slot = 1; |
828 | dep->free_slot = 1; | |
829 | } else { | |
830 | dep->busy_slot = 0; | |
831 | dep->free_slot = 0; | |
832 | } | |
833 | } | |
834 | ||
835 | /* The last TRB is a link TRB, not used for xfer */ | |
16e78db7 | 836 | if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) |
68e823e2 | 837 | return; |
72246da4 FB |
838 | |
839 | list_for_each_entry_safe(req, n, &dep->request_list, list) { | |
eeb720fb FB |
840 | unsigned length; |
841 | dma_addr_t dma; | |
72246da4 | 842 | |
eeb720fb FB |
843 | if (req->request.num_mapped_sgs > 0) { |
844 | struct usb_request *request = &req->request; | |
845 | struct scatterlist *sg = request->sg; | |
846 | struct scatterlist *s; | |
847 | int i; | |
72246da4 | 848 | |
eeb720fb FB |
849 | for_each_sg(sg, s, request->num_mapped_sgs, i) { |
850 | unsigned chain = true; | |
72246da4 | 851 | |
eeb720fb FB |
852 | length = sg_dma_len(s); |
853 | dma = sg_dma_address(s); | |
72246da4 | 854 | |
1d046793 PZ |
855 | if (i == (request->num_mapped_sgs - 1) || |
856 | sg_is_last(s)) { | |
eeb720fb FB |
857 | last_one = true; |
858 | chain = false; | |
859 | } | |
72246da4 | 860 | |
eeb720fb FB |
861 | trbs_left--; |
862 | if (!trbs_left) | |
863 | last_one = true; | |
72246da4 | 864 | |
eeb720fb FB |
865 | if (last_one) |
866 | chain = false; | |
72246da4 | 867 | |
eeb720fb FB |
868 | dwc3_prepare_one_trb(dep, req, dma, length, |
869 | last_one, chain); | |
72246da4 | 870 | |
eeb720fb FB |
871 | if (last_one) |
872 | break; | |
873 | } | |
72246da4 | 874 | } else { |
eeb720fb FB |
875 | dma = req->request.dma; |
876 | length = req->request.length; | |
877 | trbs_left--; | |
72246da4 | 878 | |
eeb720fb FB |
879 | if (!trbs_left) |
880 | last_one = 1; | |
879631aa | 881 | |
eeb720fb FB |
882 | /* Is this the last request? */ |
883 | if (list_is_last(&req->list, &dep->request_list)) | |
884 | last_one = 1; | |
72246da4 | 885 | |
eeb720fb FB |
886 | dwc3_prepare_one_trb(dep, req, dma, length, |
887 | last_one, false); | |
72246da4 | 888 | |
eeb720fb FB |
889 | if (last_one) |
890 | break; | |
72246da4 | 891 | } |
72246da4 | 892 | } |
72246da4 FB |
893 | } |
894 | ||
895 | static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, | |
896 | int start_new) | |
897 | { | |
898 | struct dwc3_gadget_ep_cmd_params params; | |
899 | struct dwc3_request *req; | |
900 | struct dwc3 *dwc = dep->dwc; | |
901 | int ret; | |
902 | u32 cmd; | |
903 | ||
904 | if (start_new && (dep->flags & DWC3_EP_BUSY)) { | |
905 | dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); | |
906 | return -EBUSY; | |
907 | } | |
908 | dep->flags &= ~DWC3_EP_PENDING_REQUEST; | |
909 | ||
910 | /* | |
911 | * If we are getting here after a short-out-packet we don't enqueue any | |
912 | * new requests as we try to set the IOC bit only on the last request. | |
913 | */ | |
914 | if (start_new) { | |
915 | if (list_empty(&dep->req_queued)) | |
916 | dwc3_prepare_trbs(dep, start_new); | |
917 | ||
918 | /* req points to the first request which will be sent */ | |
919 | req = next_request(&dep->req_queued); | |
920 | } else { | |
68e823e2 FB |
921 | dwc3_prepare_trbs(dep, start_new); |
922 | ||
72246da4 | 923 | /* |
1d046793 | 924 | * req points to the first request where HWO changed from 0 to 1 |
72246da4 | 925 | */ |
68e823e2 | 926 | req = next_request(&dep->req_queued); |
72246da4 FB |
927 | } |
928 | if (!req) { | |
929 | dep->flags |= DWC3_EP_PENDING_REQUEST; | |
930 | return 0; | |
931 | } | |
932 | ||
933 | memset(¶ms, 0, sizeof(params)); | |
dc1c70a7 FB |
934 | params.param0 = upper_32_bits(req->trb_dma); |
935 | params.param1 = lower_32_bits(req->trb_dma); | |
72246da4 FB |
936 | |
937 | if (start_new) | |
938 | cmd = DWC3_DEPCMD_STARTTRANSFER; | |
939 | else | |
940 | cmd = DWC3_DEPCMD_UPDATETRANSFER; | |
941 | ||
942 | cmd |= DWC3_DEPCMD_PARAM(cmd_param); | |
943 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
944 | if (ret < 0) { | |
945 | dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); | |
946 | ||
947 | /* | |
948 | * FIXME we need to iterate over the list of requests | |
949 | * here and stop, unmap, free and del each of the linked | |
1d046793 | 950 | * requests instead of what we do now. |
72246da4 | 951 | */ |
0fc9a1be FB |
952 | usb_gadget_unmap_request(&dwc->gadget, &req->request, |
953 | req->direction); | |
72246da4 FB |
954 | list_del(&req->list); |
955 | return ret; | |
956 | } | |
957 | ||
958 | dep->flags |= DWC3_EP_BUSY; | |
25b8ff68 | 959 | |
f898ae09 PZ |
960 | if (start_new) { |
961 | dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, | |
962 | dep->number); | |
963 | WARN_ON_ONCE(!dep->res_trans_idx); | |
964 | } | |
25b8ff68 | 965 | |
72246da4 FB |
966 | return 0; |
967 | } | |
968 | ||
969 | static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) | |
970 | { | |
0fc9a1be FB |
971 | struct dwc3 *dwc = dep->dwc; |
972 | int ret; | |
973 | ||
72246da4 FB |
974 | req->request.actual = 0; |
975 | req->request.status = -EINPROGRESS; | |
976 | req->direction = dep->direction; | |
977 | req->epnum = dep->number; | |
978 | ||
979 | /* | |
980 | * We only add to our list of requests now and | |
981 | * start consuming the list once we get XferNotReady | |
982 | * IRQ. | |
983 | * | |
984 | * That way, we avoid doing anything that we don't need | |
985 | * to do now and defer it until the point we receive a | |
986 | * particular token from the Host side. | |
987 | * | |
988 | * This will also avoid Host cancelling URBs due to too | |
1d046793 | 989 | * many NAKs. |
72246da4 | 990 | */ |
0fc9a1be FB |
991 | ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
992 | dep->direction); | |
993 | if (ret) | |
994 | return ret; | |
995 | ||
72246da4 FB |
996 | list_add_tail(&req->list, &dep->request_list); |
997 | ||
23063b37 | 998 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && (dep->flags & DWC3_EP_BUSY)) |
f898ae09 PZ |
999 | dep->flags |= DWC3_EP_PENDING_REQUEST; |
1000 | ||
72246da4 | 1001 | /* |
f898ae09 | 1002 | * There are two special cases: |
72246da4 | 1003 | * |
f898ae09 PZ |
1004 | * 1. XferNotReady with empty list of requests. We need to kick the |
1005 | * transfer here in that situation, otherwise we will be NAKing | |
1006 | * forever. If we get XferNotReady before gadget driver has a | |
1007 | * chance to queue a request, we will ACK the IRQ but won't be | |
1008 | * able to receive the data until the next request is queued. | |
1009 | * The following code is handling exactly that. | |
72246da4 | 1010 | * |
f898ae09 PZ |
1011 | * 2. XferInProgress on Isoc EP with an active transfer. We need to |
1012 | * kick the transfer here after queuing a request, otherwise the | |
1013 | * core may not see the modified TRB(s). | |
72246da4 FB |
1014 | */ |
1015 | if (dep->flags & DWC3_EP_PENDING_REQUEST) { | |
f898ae09 PZ |
1016 | int ret; |
1017 | int start_trans = 1; | |
1018 | u8 trans_idx = dep->res_trans_idx; | |
72246da4 | 1019 | |
16e78db7 | 1020 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && |
f898ae09 | 1021 | (dep->flags & DWC3_EP_BUSY)) { |
72246da4 | 1022 | start_trans = 0; |
f898ae09 PZ |
1023 | WARN_ON_ONCE(!trans_idx); |
1024 | } else { | |
1025 | trans_idx = 0; | |
1026 | } | |
72246da4 | 1027 | |
f898ae09 | 1028 | ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans); |
72246da4 FB |
1029 | if (ret && ret != -EBUSY) { |
1030 | struct dwc3 *dwc = dep->dwc; | |
1031 | ||
1032 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1033 | dep->name); | |
1034 | } | |
1035 | }; | |
1036 | ||
1037 | return 0; | |
1038 | } | |
1039 | ||
1040 | static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, | |
1041 | gfp_t gfp_flags) | |
1042 | { | |
1043 | struct dwc3_request *req = to_dwc3_request(request); | |
1044 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1045 | struct dwc3 *dwc = dep->dwc; | |
1046 | ||
1047 | unsigned long flags; | |
1048 | ||
1049 | int ret; | |
1050 | ||
16e78db7 | 1051 | if (!dep->endpoint.desc) { |
72246da4 FB |
1052 | dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", |
1053 | request, ep->name); | |
1054 | return -ESHUTDOWN; | |
1055 | } | |
1056 | ||
1057 | dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", | |
1058 | request, ep->name, request->length); | |
1059 | ||
1060 | spin_lock_irqsave(&dwc->lock, flags); | |
1061 | ret = __dwc3_gadget_ep_queue(dep, req); | |
1062 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1063 | ||
1064 | return ret; | |
1065 | } | |
1066 | ||
1067 | static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, | |
1068 | struct usb_request *request) | |
1069 | { | |
1070 | struct dwc3_request *req = to_dwc3_request(request); | |
1071 | struct dwc3_request *r = NULL; | |
1072 | ||
1073 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1074 | struct dwc3 *dwc = dep->dwc; | |
1075 | ||
1076 | unsigned long flags; | |
1077 | int ret = 0; | |
1078 | ||
1079 | spin_lock_irqsave(&dwc->lock, flags); | |
1080 | ||
1081 | list_for_each_entry(r, &dep->request_list, list) { | |
1082 | if (r == req) | |
1083 | break; | |
1084 | } | |
1085 | ||
1086 | if (r != req) { | |
1087 | list_for_each_entry(r, &dep->req_queued, list) { | |
1088 | if (r == req) | |
1089 | break; | |
1090 | } | |
1091 | if (r == req) { | |
1092 | /* wait until it is processed */ | |
1093 | dwc3_stop_active_transfer(dwc, dep->number); | |
e8d4e8be | 1094 | goto out1; |
72246da4 FB |
1095 | } |
1096 | dev_err(dwc->dev, "request %p was not queued to %s\n", | |
1097 | request, ep->name); | |
1098 | ret = -EINVAL; | |
1099 | goto out0; | |
1100 | } | |
1101 | ||
e8d4e8be | 1102 | out1: |
72246da4 FB |
1103 | /* giveback the request */ |
1104 | dwc3_gadget_giveback(dep, req, -ECONNRESET); | |
1105 | ||
1106 | out0: | |
1107 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1108 | ||
1109 | return ret; | |
1110 | } | |
1111 | ||
1112 | int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) | |
1113 | { | |
1114 | struct dwc3_gadget_ep_cmd_params params; | |
1115 | struct dwc3 *dwc = dep->dwc; | |
1116 | int ret; | |
1117 | ||
1118 | memset(¶ms, 0x00, sizeof(params)); | |
1119 | ||
1120 | if (value) { | |
0b7836a9 FB |
1121 | if (dep->number == 0 || dep->number == 1) { |
1122 | /* | |
1123 | * Whenever EP0 is stalled, we will restart | |
1124 | * the state machine, thus moving back to | |
1125 | * Setup Phase | |
1126 | */ | |
1127 | dwc->ep0state = EP0_SETUP_PHASE; | |
1128 | } | |
72246da4 FB |
1129 | |
1130 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1131 | DWC3_DEPCMD_SETSTALL, ¶ms); | |
1132 | if (ret) | |
1133 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1134 | value ? "set" : "clear", | |
1135 | dep->name); | |
1136 | else | |
1137 | dep->flags |= DWC3_EP_STALL; | |
1138 | } else { | |
5275455a PZ |
1139 | if (dep->flags & DWC3_EP_WEDGE) |
1140 | return 0; | |
1141 | ||
72246da4 FB |
1142 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, |
1143 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1144 | if (ret) | |
1145 | dev_err(dwc->dev, "failed to %s STALL on %s\n", | |
1146 | value ? "set" : "clear", | |
1147 | dep->name); | |
1148 | else | |
1149 | dep->flags &= ~DWC3_EP_STALL; | |
1150 | } | |
5275455a | 1151 | |
72246da4 FB |
1152 | return ret; |
1153 | } | |
1154 | ||
1155 | static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) | |
1156 | { | |
1157 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
1158 | struct dwc3 *dwc = dep->dwc; | |
1159 | ||
1160 | unsigned long flags; | |
1161 | ||
1162 | int ret; | |
1163 | ||
1164 | spin_lock_irqsave(&dwc->lock, flags); | |
1165 | ||
16e78db7 | 1166 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1167 | dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); |
1168 | ret = -EINVAL; | |
1169 | goto out; | |
1170 | } | |
1171 | ||
1172 | ret = __dwc3_gadget_ep_set_halt(dep, value); | |
1173 | out: | |
1174 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1175 | ||
1176 | return ret; | |
1177 | } | |
1178 | ||
1179 | static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) | |
1180 | { | |
1181 | struct dwc3_ep *dep = to_dwc3_ep(ep); | |
249a4569 PZ |
1182 | struct dwc3 *dwc = dep->dwc; |
1183 | unsigned long flags; | |
72246da4 | 1184 | |
249a4569 | 1185 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1186 | dep->flags |= DWC3_EP_WEDGE; |
249a4569 | 1187 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 | 1188 | |
5275455a | 1189 | return dwc3_gadget_ep_set_halt(ep, 1); |
72246da4 FB |
1190 | } |
1191 | ||
1192 | /* -------------------------------------------------------------------------- */ | |
1193 | ||
1194 | static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { | |
1195 | .bLength = USB_DT_ENDPOINT_SIZE, | |
1196 | .bDescriptorType = USB_DT_ENDPOINT, | |
1197 | .bmAttributes = USB_ENDPOINT_XFER_CONTROL, | |
1198 | }; | |
1199 | ||
1200 | static const struct usb_ep_ops dwc3_gadget_ep0_ops = { | |
1201 | .enable = dwc3_gadget_ep0_enable, | |
1202 | .disable = dwc3_gadget_ep0_disable, | |
1203 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1204 | .free_request = dwc3_gadget_ep_free_request, | |
1205 | .queue = dwc3_gadget_ep0_queue, | |
1206 | .dequeue = dwc3_gadget_ep_dequeue, | |
1207 | .set_halt = dwc3_gadget_ep_set_halt, | |
1208 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1209 | }; | |
1210 | ||
1211 | static const struct usb_ep_ops dwc3_gadget_ep_ops = { | |
1212 | .enable = dwc3_gadget_ep_enable, | |
1213 | .disable = dwc3_gadget_ep_disable, | |
1214 | .alloc_request = dwc3_gadget_ep_alloc_request, | |
1215 | .free_request = dwc3_gadget_ep_free_request, | |
1216 | .queue = dwc3_gadget_ep_queue, | |
1217 | .dequeue = dwc3_gadget_ep_dequeue, | |
1218 | .set_halt = dwc3_gadget_ep_set_halt, | |
1219 | .set_wedge = dwc3_gadget_ep_set_wedge, | |
1220 | }; | |
1221 | ||
1222 | /* -------------------------------------------------------------------------- */ | |
1223 | ||
1224 | static int dwc3_gadget_get_frame(struct usb_gadget *g) | |
1225 | { | |
1226 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1227 | u32 reg; | |
1228 | ||
1229 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1230 | return DWC3_DSTS_SOFFN(reg); | |
1231 | } | |
1232 | ||
1233 | static int dwc3_gadget_wakeup(struct usb_gadget *g) | |
1234 | { | |
1235 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1236 | ||
1237 | unsigned long timeout; | |
1238 | unsigned long flags; | |
1239 | ||
1240 | u32 reg; | |
1241 | ||
1242 | int ret = 0; | |
1243 | ||
1244 | u8 link_state; | |
1245 | u8 speed; | |
1246 | ||
1247 | spin_lock_irqsave(&dwc->lock, flags); | |
1248 | ||
1249 | /* | |
1250 | * According to the Databook Remote wakeup request should | |
1251 | * be issued only when the device is in early suspend state. | |
1252 | * | |
1253 | * We can check that via USB Link State bits in DSTS register. | |
1254 | */ | |
1255 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1256 | ||
1257 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
1258 | if (speed == DWC3_DSTS_SUPERSPEED) { | |
1259 | dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); | |
1260 | ret = -EINVAL; | |
1261 | goto out; | |
1262 | } | |
1263 | ||
1264 | link_state = DWC3_DSTS_USBLNKST(reg); | |
1265 | ||
1266 | switch (link_state) { | |
1267 | case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ | |
1268 | case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ | |
1269 | break; | |
1270 | default: | |
1271 | dev_dbg(dwc->dev, "can't wakeup from link state %d\n", | |
1272 | link_state); | |
1273 | ret = -EINVAL; | |
1274 | goto out; | |
1275 | } | |
1276 | ||
8598bde7 FB |
1277 | ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); |
1278 | if (ret < 0) { | |
1279 | dev_err(dwc->dev, "failed to put link in Recovery\n"); | |
1280 | goto out; | |
1281 | } | |
72246da4 FB |
1282 | |
1283 | /* write zeroes to Link Change Request */ | |
1284 | reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; | |
1285 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1286 | ||
1d046793 | 1287 | /* poll until Link State changes to ON */ |
72246da4 FB |
1288 | timeout = jiffies + msecs_to_jiffies(100); |
1289 | ||
1d046793 | 1290 | while (!time_after(jiffies, timeout)) { |
72246da4 FB |
1291 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
1292 | ||
1293 | /* in HS, means ON */ | |
1294 | if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) | |
1295 | break; | |
1296 | } | |
1297 | ||
1298 | if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { | |
1299 | dev_err(dwc->dev, "failed to send remote wakeup\n"); | |
1300 | ret = -EINVAL; | |
1301 | } | |
1302 | ||
1303 | out: | |
1304 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1305 | ||
1306 | return ret; | |
1307 | } | |
1308 | ||
1309 | static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, | |
1310 | int is_selfpowered) | |
1311 | { | |
1312 | struct dwc3 *dwc = gadget_to_dwc(g); | |
249a4569 | 1313 | unsigned long flags; |
72246da4 | 1314 | |
249a4569 | 1315 | spin_lock_irqsave(&dwc->lock, flags); |
72246da4 | 1316 | dwc->is_selfpowered = !!is_selfpowered; |
249a4569 | 1317 | spin_unlock_irqrestore(&dwc->lock, flags); |
72246da4 FB |
1318 | |
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) | |
1323 | { | |
1324 | u32 reg; | |
61d58242 | 1325 | u32 timeout = 500; |
72246da4 FB |
1326 | |
1327 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
8db7ed15 FB |
1328 | if (is_on) { |
1329 | reg &= ~DWC3_DCTL_TRGTULST_MASK; | |
1330 | reg |= (DWC3_DCTL_RUN_STOP | |
1331 | | DWC3_DCTL_TRGTULST_RX_DET); | |
1332 | } else { | |
72246da4 | 1333 | reg &= ~DWC3_DCTL_RUN_STOP; |
8db7ed15 | 1334 | } |
72246da4 FB |
1335 | |
1336 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1337 | ||
1338 | do { | |
1339 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); | |
1340 | if (is_on) { | |
1341 | if (!(reg & DWC3_DSTS_DEVCTRLHLT)) | |
1342 | break; | |
1343 | } else { | |
1344 | if (reg & DWC3_DSTS_DEVCTRLHLT) | |
1345 | break; | |
1346 | } | |
72246da4 FB |
1347 | timeout--; |
1348 | if (!timeout) | |
1349 | break; | |
61d58242 | 1350 | udelay(1); |
72246da4 FB |
1351 | } while (1); |
1352 | ||
1353 | dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", | |
1354 | dwc->gadget_driver | |
1355 | ? dwc->gadget_driver->function : "no-function", | |
1356 | is_on ? "connect" : "disconnect"); | |
1357 | } | |
1358 | ||
1359 | static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) | |
1360 | { | |
1361 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1362 | unsigned long flags; | |
1363 | ||
1364 | is_on = !!is_on; | |
1365 | ||
1366 | spin_lock_irqsave(&dwc->lock, flags); | |
1367 | dwc3_gadget_run_stop(dwc, is_on); | |
1368 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | static int dwc3_gadget_start(struct usb_gadget *g, | |
1374 | struct usb_gadget_driver *driver) | |
1375 | { | |
1376 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1377 | struct dwc3_ep *dep; | |
1378 | unsigned long flags; | |
1379 | int ret = 0; | |
1380 | u32 reg; | |
1381 | ||
1382 | spin_lock_irqsave(&dwc->lock, flags); | |
1383 | ||
1384 | if (dwc->gadget_driver) { | |
1385 | dev_err(dwc->dev, "%s is already bound to %s\n", | |
1386 | dwc->gadget.name, | |
1387 | dwc->gadget_driver->driver.name); | |
1388 | ret = -EBUSY; | |
1389 | goto err0; | |
1390 | } | |
1391 | ||
1392 | dwc->gadget_driver = driver; | |
1393 | dwc->gadget.dev.driver = &driver->driver; | |
1394 | ||
72246da4 FB |
1395 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
1396 | reg &= ~(DWC3_DCFG_SPEED_MASK); | |
07e7f47b FB |
1397 | |
1398 | /** | |
1399 | * WORKAROUND: DWC3 revision < 2.20a have an issue | |
1400 | * which would cause metastability state on Run/Stop | |
1401 | * bit if we try to force the IP to USB2-only mode. | |
1402 | * | |
1403 | * Because of that, we cannot configure the IP to any | |
1404 | * speed other than the SuperSpeed | |
1405 | * | |
1406 | * Refers to: | |
1407 | * | |
1408 | * STAR#9000525659: Clock Domain Crossing on DCTL in | |
1409 | * USB 2.0 Mode | |
1410 | */ | |
1411 | if (dwc->revision < DWC3_REVISION_220A) | |
1412 | reg |= DWC3_DCFG_SUPERSPEED; | |
1413 | else | |
1414 | reg |= dwc->maximum_speed; | |
72246da4 FB |
1415 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); |
1416 | ||
b23c8439 PZ |
1417 | dwc->start_config_issued = false; |
1418 | ||
72246da4 FB |
1419 | /* Start with SuperSpeed Default */ |
1420 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); | |
1421 | ||
1422 | dep = dwc->eps[0]; | |
c90bfaec | 1423 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
1424 | if (ret) { |
1425 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
1426 | goto err0; | |
1427 | } | |
1428 | ||
1429 | dep = dwc->eps[1]; | |
c90bfaec | 1430 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
1431 | if (ret) { |
1432 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
1433 | goto err1; | |
1434 | } | |
1435 | ||
1436 | /* begin to receive SETUP packets */ | |
c7fcdeb2 | 1437 | dwc->ep0state = EP0_SETUP_PHASE; |
72246da4 FB |
1438 | dwc3_ep0_out_start(dwc); |
1439 | ||
1440 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1441 | ||
1442 | return 0; | |
1443 | ||
1444 | err1: | |
1445 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
1446 | ||
1447 | err0: | |
1448 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1449 | ||
1450 | return ret; | |
1451 | } | |
1452 | ||
1453 | static int dwc3_gadget_stop(struct usb_gadget *g, | |
1454 | struct usb_gadget_driver *driver) | |
1455 | { | |
1456 | struct dwc3 *dwc = gadget_to_dwc(g); | |
1457 | unsigned long flags; | |
1458 | ||
1459 | spin_lock_irqsave(&dwc->lock, flags); | |
1460 | ||
1461 | __dwc3_gadget_ep_disable(dwc->eps[0]); | |
1462 | __dwc3_gadget_ep_disable(dwc->eps[1]); | |
1463 | ||
1464 | dwc->gadget_driver = NULL; | |
1465 | dwc->gadget.dev.driver = NULL; | |
1466 | ||
1467 | spin_unlock_irqrestore(&dwc->lock, flags); | |
1468 | ||
1469 | return 0; | |
1470 | } | |
1471 | static const struct usb_gadget_ops dwc3_gadget_ops = { | |
1472 | .get_frame = dwc3_gadget_get_frame, | |
1473 | .wakeup = dwc3_gadget_wakeup, | |
1474 | .set_selfpowered = dwc3_gadget_set_selfpowered, | |
1475 | .pullup = dwc3_gadget_pullup, | |
1476 | .udc_start = dwc3_gadget_start, | |
1477 | .udc_stop = dwc3_gadget_stop, | |
1478 | }; | |
1479 | ||
1480 | /* -------------------------------------------------------------------------- */ | |
1481 | ||
1482 | static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc) | |
1483 | { | |
1484 | struct dwc3_ep *dep; | |
1485 | u8 epnum; | |
1486 | ||
1487 | INIT_LIST_HEAD(&dwc->gadget.ep_list); | |
1488 | ||
1489 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1490 | dep = kzalloc(sizeof(*dep), GFP_KERNEL); | |
1491 | if (!dep) { | |
1492 | dev_err(dwc->dev, "can't allocate endpoint %d\n", | |
1493 | epnum); | |
1494 | return -ENOMEM; | |
1495 | } | |
1496 | ||
1497 | dep->dwc = dwc; | |
1498 | dep->number = epnum; | |
1499 | dwc->eps[epnum] = dep; | |
1500 | ||
1501 | snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, | |
1502 | (epnum & 1) ? "in" : "out"); | |
1503 | dep->endpoint.name = dep->name; | |
1504 | dep->direction = (epnum & 1); | |
1505 | ||
1506 | if (epnum == 0 || epnum == 1) { | |
1507 | dep->endpoint.maxpacket = 512; | |
1508 | dep->endpoint.ops = &dwc3_gadget_ep0_ops; | |
1509 | if (!epnum) | |
1510 | dwc->gadget.ep0 = &dep->endpoint; | |
1511 | } else { | |
1512 | int ret; | |
1513 | ||
1514 | dep->endpoint.maxpacket = 1024; | |
12d36c16 | 1515 | dep->endpoint.max_streams = 15; |
72246da4 FB |
1516 | dep->endpoint.ops = &dwc3_gadget_ep_ops; |
1517 | list_add_tail(&dep->endpoint.ep_list, | |
1518 | &dwc->gadget.ep_list); | |
1519 | ||
1520 | ret = dwc3_alloc_trb_pool(dep); | |
25b8ff68 | 1521 | if (ret) |
72246da4 | 1522 | return ret; |
72246da4 | 1523 | } |
25b8ff68 | 1524 | |
72246da4 FB |
1525 | INIT_LIST_HEAD(&dep->request_list); |
1526 | INIT_LIST_HEAD(&dep->req_queued); | |
1527 | } | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) | |
1533 | { | |
1534 | struct dwc3_ep *dep; | |
1535 | u8 epnum; | |
1536 | ||
1537 | for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1538 | dep = dwc->eps[epnum]; | |
1539 | dwc3_free_trb_pool(dep); | |
1540 | ||
1541 | if (epnum != 0 && epnum != 1) | |
1542 | list_del(&dep->endpoint.ep_list); | |
1543 | ||
1544 | kfree(dep); | |
1545 | } | |
1546 | } | |
1547 | ||
1548 | static void dwc3_gadget_release(struct device *dev) | |
1549 | { | |
1550 | dev_dbg(dev, "%s\n", __func__); | |
1551 | } | |
1552 | ||
1553 | /* -------------------------------------------------------------------------- */ | |
1554 | static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, | |
1555 | const struct dwc3_event_depevt *event, int status) | |
1556 | { | |
1557 | struct dwc3_request *req; | |
f6bafc6a | 1558 | struct dwc3_trb *trb; |
72246da4 FB |
1559 | unsigned int count; |
1560 | unsigned int s_pkt = 0; | |
1561 | ||
1562 | do { | |
1563 | req = next_request(&dep->req_queued); | |
d39ee7be SAS |
1564 | if (!req) { |
1565 | WARN_ON_ONCE(1); | |
1566 | return 1; | |
1567 | } | |
72246da4 | 1568 | |
f6bafc6a | 1569 | trb = req->trb; |
72246da4 | 1570 | |
f6bafc6a | 1571 | if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) |
0d2f4758 SAS |
1572 | /* |
1573 | * We continue despite the error. There is not much we | |
1d046793 PZ |
1574 | * can do. If we don't clean it up we loop forever. If |
1575 | * we skip the TRB then it gets overwritten after a | |
1576 | * while since we use them in a ring buffer. A BUG() | |
1577 | * would help. Lets hope that if this occurs, someone | |
0d2f4758 SAS |
1578 | * fixes the root cause instead of looking away :) |
1579 | */ | |
72246da4 FB |
1580 | dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", |
1581 | dep->name, req->trb); | |
f6bafc6a | 1582 | count = trb->size & DWC3_TRB_SIZE_MASK; |
72246da4 FB |
1583 | |
1584 | if (dep->direction) { | |
1585 | if (count) { | |
1586 | dev_err(dwc->dev, "incomplete IN transfer %s\n", | |
1587 | dep->name); | |
1588 | status = -ECONNRESET; | |
1589 | } | |
1590 | } else { | |
1591 | if (count && (event->status & DEPEVT_STATUS_SHORT)) | |
1592 | s_pkt = 1; | |
1593 | } | |
1594 | ||
1595 | /* | |
1596 | * We assume here we will always receive the entire data block | |
1597 | * which we should receive. Meaning, if we program RX to | |
1598 | * receive 4K but we receive only 2K, we assume that's all we | |
1599 | * should receive and we simply bounce the request back to the | |
1600 | * gadget driver for further processing. | |
1601 | */ | |
1602 | req->request.actual += req->request.length - count; | |
1603 | dwc3_gadget_giveback(dep, req, status); | |
1604 | if (s_pkt) | |
1605 | break; | |
f6bafc6a FB |
1606 | if ((event->status & DEPEVT_STATUS_LST) && |
1607 | (trb->ctrl & DWC3_TRB_CTRL_LST)) | |
72246da4 | 1608 | break; |
f6bafc6a FB |
1609 | if ((event->status & DEPEVT_STATUS_IOC) && |
1610 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
72246da4 FB |
1611 | break; |
1612 | } while (1); | |
1613 | ||
f6bafc6a FB |
1614 | if ((event->status & DEPEVT_STATUS_IOC) && |
1615 | (trb->ctrl & DWC3_TRB_CTRL_IOC)) | |
72246da4 FB |
1616 | return 0; |
1617 | return 1; | |
1618 | } | |
1619 | ||
1620 | static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, | |
1621 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event, | |
1622 | int start_new) | |
1623 | { | |
1624 | unsigned status = 0; | |
1625 | int clean_busy; | |
1626 | ||
1627 | if (event->status & DEPEVT_STATUS_BUSERR) | |
1628 | status = -ECONNRESET; | |
1629 | ||
1d046793 | 1630 | clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); |
c2df85ca | 1631 | if (clean_busy) |
72246da4 | 1632 | dep->flags &= ~DWC3_EP_BUSY; |
fae2b904 FB |
1633 | |
1634 | /* | |
1635 | * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. | |
1636 | * See dwc3_gadget_linksts_change_interrupt() for 1st half. | |
1637 | */ | |
1638 | if (dwc->revision < DWC3_REVISION_183A) { | |
1639 | u32 reg; | |
1640 | int i; | |
1641 | ||
1642 | for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { | |
1643 | struct dwc3_ep *dep = dwc->eps[i]; | |
1644 | ||
1645 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1646 | continue; | |
1647 | ||
1648 | if (!list_empty(&dep->req_queued)) | |
1649 | return; | |
1650 | } | |
1651 | ||
1652 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1653 | reg |= dwc->u1u2; | |
1654 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1655 | ||
1656 | dwc->u1u2 = 0; | |
1657 | } | |
72246da4 FB |
1658 | } |
1659 | ||
1660 | static void dwc3_gadget_start_isoc(struct dwc3 *dwc, | |
1661 | struct dwc3_ep *dep, const struct dwc3_event_depevt *event) | |
1662 | { | |
9bafa56c | 1663 | u32 uf, mask; |
72246da4 FB |
1664 | |
1665 | if (list_empty(&dep->request_list)) { | |
1666 | dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", | |
1667 | dep->name); | |
1668 | return; | |
1669 | } | |
1670 | ||
9bafa56c PZ |
1671 | mask = ~(dep->interval - 1); |
1672 | uf = event->parameters & mask; | |
1673 | /* 4 micro frames in the future */ | |
1674 | uf += dep->interval * 4; | |
72246da4 FB |
1675 | |
1676 | __dwc3_gadget_kick_transfer(dep, uf, 1); | |
1677 | } | |
1678 | ||
1679 | static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep, | |
1680 | const struct dwc3_event_depevt *event) | |
1681 | { | |
1682 | struct dwc3 *dwc = dep->dwc; | |
1683 | struct dwc3_event_depevt mod_ev = *event; | |
1684 | ||
1685 | /* | |
1d046793 PZ |
1686 | * We were asked to remove one request. It is possible that this |
1687 | * request and a few others were started together and have the same | |
72246da4 FB |
1688 | * transfer index. Since we stopped the complete endpoint we don't |
1689 | * know how many requests were already completed (and not yet) | |
1690 | * reported and how could be done (later). We purge them all until | |
1691 | * the end of the list. | |
1692 | */ | |
1693 | mod_ev.status = DEPEVT_STATUS_LST; | |
1694 | dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN); | |
1695 | dep->flags &= ~DWC3_EP_BUSY; | |
1d046793 | 1696 | /* pending requests are ignored and are queued on XferNotReady */ |
72246da4 FB |
1697 | } |
1698 | ||
1699 | static void dwc3_ep_cmd_compl(struct dwc3_ep *dep, | |
1700 | const struct dwc3_event_depevt *event) | |
1701 | { | |
1702 | u32 param = event->parameters; | |
1703 | u32 cmd_type = (param >> 8) & ((1 << 5) - 1); | |
1704 | ||
1705 | switch (cmd_type) { | |
1706 | case DWC3_DEPCMD_ENDTRANSFER: | |
1707 | dwc3_process_ep_cmd_complete(dep, event); | |
1708 | break; | |
1709 | case DWC3_DEPCMD_STARTTRANSFER: | |
1710 | dep->res_trans_idx = param & 0x7f; | |
1711 | break; | |
1712 | default: | |
1713 | printk(KERN_ERR "%s() unknown /unexpected type: %d\n", | |
1714 | __func__, cmd_type); | |
1715 | break; | |
1716 | }; | |
1717 | } | |
1718 | ||
1719 | static void dwc3_endpoint_interrupt(struct dwc3 *dwc, | |
1720 | const struct dwc3_event_depevt *event) | |
1721 | { | |
1722 | struct dwc3_ep *dep; | |
1723 | u8 epnum = event->endpoint_number; | |
1724 | ||
1725 | dep = dwc->eps[epnum]; | |
1726 | ||
1727 | dev_vdbg(dwc->dev, "%s: %s\n", dep->name, | |
1728 | dwc3_ep_event_string(event->endpoint_event)); | |
1729 | ||
1730 | if (epnum == 0 || epnum == 1) { | |
1731 | dwc3_ep0_interrupt(dwc, event); | |
1732 | return; | |
1733 | } | |
1734 | ||
1735 | switch (event->endpoint_event) { | |
1736 | case DWC3_DEPEVT_XFERCOMPLETE: | |
c2df85ca PZ |
1737 | dep->res_trans_idx = 0; |
1738 | ||
16e78db7 | 1739 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1740 | dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", |
1741 | dep->name); | |
1742 | return; | |
1743 | } | |
1744 | ||
1745 | dwc3_endpoint_transfer_complete(dwc, dep, event, 1); | |
1746 | break; | |
1747 | case DWC3_DEPEVT_XFERINPROGRESS: | |
16e78db7 | 1748 | if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1749 | dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n", |
1750 | dep->name); | |
1751 | return; | |
1752 | } | |
1753 | ||
1754 | dwc3_endpoint_transfer_complete(dwc, dep, event, 0); | |
1755 | break; | |
1756 | case DWC3_DEPEVT_XFERNOTREADY: | |
16e78db7 | 1757 | if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { |
72246da4 FB |
1758 | dwc3_gadget_start_isoc(dwc, dep, event); |
1759 | } else { | |
1760 | int ret; | |
1761 | ||
1762 | dev_vdbg(dwc->dev, "%s: reason %s\n", | |
40aa41fb FB |
1763 | dep->name, event->status & |
1764 | DEPEVT_STATUS_TRANSFER_ACTIVE | |
72246da4 FB |
1765 | ? "Transfer Active" |
1766 | : "Transfer Not Active"); | |
1767 | ||
1768 | ret = __dwc3_gadget_kick_transfer(dep, 0, 1); | |
1769 | if (!ret || ret == -EBUSY) | |
1770 | return; | |
1771 | ||
1772 | dev_dbg(dwc->dev, "%s: failed to kick transfers\n", | |
1773 | dep->name); | |
1774 | } | |
1775 | ||
879631aa FB |
1776 | break; |
1777 | case DWC3_DEPEVT_STREAMEVT: | |
16e78db7 | 1778 | if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { |
879631aa FB |
1779 | dev_err(dwc->dev, "Stream event for non-Bulk %s\n", |
1780 | dep->name); | |
1781 | return; | |
1782 | } | |
1783 | ||
1784 | switch (event->status) { | |
1785 | case DEPEVT_STREAMEVT_FOUND: | |
1786 | dev_vdbg(dwc->dev, "Stream %d found and started\n", | |
1787 | event->parameters); | |
1788 | ||
1789 | break; | |
1790 | case DEPEVT_STREAMEVT_NOTFOUND: | |
1791 | /* FALLTHROUGH */ | |
1792 | default: | |
1793 | dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); | |
1794 | } | |
72246da4 FB |
1795 | break; |
1796 | case DWC3_DEPEVT_RXTXFIFOEVT: | |
1797 | dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); | |
1798 | break; | |
72246da4 FB |
1799 | case DWC3_DEPEVT_EPCMDCMPLT: |
1800 | dwc3_ep_cmd_compl(dep, event); | |
1801 | break; | |
1802 | } | |
1803 | } | |
1804 | ||
1805 | static void dwc3_disconnect_gadget(struct dwc3 *dwc) | |
1806 | { | |
1807 | if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { | |
1808 | spin_unlock(&dwc->lock); | |
1809 | dwc->gadget_driver->disconnect(&dwc->gadget); | |
1810 | spin_lock(&dwc->lock); | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum) | |
1815 | { | |
1816 | struct dwc3_ep *dep; | |
1817 | struct dwc3_gadget_ep_cmd_params params; | |
1818 | u32 cmd; | |
1819 | int ret; | |
1820 | ||
1821 | dep = dwc->eps[epnum]; | |
1822 | ||
624407f9 | 1823 | WARN_ON(!dep->res_trans_idx); |
72246da4 FB |
1824 | if (dep->res_trans_idx) { |
1825 | cmd = DWC3_DEPCMD_ENDTRANSFER; | |
1826 | cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC; | |
1827 | cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx); | |
1828 | memset(¶ms, 0, sizeof(params)); | |
1829 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); | |
1830 | WARN_ON_ONCE(ret); | |
a1ae9be5 | 1831 | dep->res_trans_idx = 0; |
72246da4 FB |
1832 | } |
1833 | } | |
1834 | ||
1835 | static void dwc3_stop_active_transfers(struct dwc3 *dwc) | |
1836 | { | |
1837 | u32 epnum; | |
1838 | ||
1839 | for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1840 | struct dwc3_ep *dep; | |
1841 | ||
1842 | dep = dwc->eps[epnum]; | |
1843 | if (!(dep->flags & DWC3_EP_ENABLED)) | |
1844 | continue; | |
1845 | ||
624407f9 | 1846 | dwc3_remove_requests(dwc, dep); |
72246da4 FB |
1847 | } |
1848 | } | |
1849 | ||
1850 | static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) | |
1851 | { | |
1852 | u32 epnum; | |
1853 | ||
1854 | for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { | |
1855 | struct dwc3_ep *dep; | |
1856 | struct dwc3_gadget_ep_cmd_params params; | |
1857 | int ret; | |
1858 | ||
1859 | dep = dwc->eps[epnum]; | |
1860 | ||
1861 | if (!(dep->flags & DWC3_EP_STALL)) | |
1862 | continue; | |
1863 | ||
1864 | dep->flags &= ~DWC3_EP_STALL; | |
1865 | ||
1866 | memset(¶ms, 0, sizeof(params)); | |
1867 | ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, | |
1868 | DWC3_DEPCMD_CLEARSTALL, ¶ms); | |
1869 | WARN_ON_ONCE(ret); | |
1870 | } | |
1871 | } | |
1872 | ||
1873 | static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) | |
1874 | { | |
1875 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
1876 | #if 0 | |
1877 | XXX | |
1878 | U1/U2 is powersave optimization. Skip it for now. Anyway we need to | |
1879 | enable it before we can disable it. | |
1880 | ||
1881 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1882 | reg &= ~DWC3_DCTL_INITU1ENA; | |
1883 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1884 | ||
1885 | reg &= ~DWC3_DCTL_INITU2ENA; | |
1886 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
1887 | #endif | |
1888 | ||
1889 | dwc3_stop_active_transfers(dwc); | |
1890 | dwc3_disconnect_gadget(dwc); | |
b23c8439 | 1891 | dwc->start_config_issued = false; |
72246da4 FB |
1892 | |
1893 | dwc->gadget.speed = USB_SPEED_UNKNOWN; | |
df62df56 | 1894 | dwc->setup_packet_pending = false; |
72246da4 FB |
1895 | } |
1896 | ||
1897 | static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on) | |
1898 | { | |
1899 | u32 reg; | |
1900 | ||
1901 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
1902 | ||
1903 | if (on) | |
1904 | reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; | |
1905 | else | |
1906 | reg |= DWC3_GUSB3PIPECTL_SUSPHY; | |
1907 | ||
1908 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
1909 | } | |
1910 | ||
1911 | static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on) | |
1912 | { | |
1913 | u32 reg; | |
1914 | ||
1915 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
1916 | ||
1917 | if (on) | |
1918 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
1919 | else | |
1920 | reg |= DWC3_GUSB2PHYCFG_SUSPHY; | |
1921 | ||
1922 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
1923 | } | |
1924 | ||
1925 | static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) | |
1926 | { | |
1927 | u32 reg; | |
1928 | ||
1929 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
1930 | ||
df62df56 FB |
1931 | /* |
1932 | * WORKAROUND: DWC3 revisions <1.88a have an issue which | |
1933 | * would cause a missing Disconnect Event if there's a | |
1934 | * pending Setup Packet in the FIFO. | |
1935 | * | |
1936 | * There's no suggested workaround on the official Bug | |
1937 | * report, which states that "unless the driver/application | |
1938 | * is doing any special handling of a disconnect event, | |
1939 | * there is no functional issue". | |
1940 | * | |
1941 | * Unfortunately, it turns out that we _do_ some special | |
1942 | * handling of a disconnect event, namely complete all | |
1943 | * pending transfers, notify gadget driver of the | |
1944 | * disconnection, and so on. | |
1945 | * | |
1946 | * Our suggested workaround is to follow the Disconnect | |
1947 | * Event steps here, instead, based on a setup_packet_pending | |
1948 | * flag. Such flag gets set whenever we have a XferNotReady | |
1949 | * event on EP0 and gets cleared on XferComplete for the | |
1950 | * same endpoint. | |
1951 | * | |
1952 | * Refers to: | |
1953 | * | |
1954 | * STAR#9000466709: RTL: Device : Disconnect event not | |
1955 | * generated if setup packet pending in FIFO | |
1956 | */ | |
1957 | if (dwc->revision < DWC3_REVISION_188A) { | |
1958 | if (dwc->setup_packet_pending) | |
1959 | dwc3_gadget_disconnect_interrupt(dwc); | |
1960 | } | |
1961 | ||
961906ed FB |
1962 | /* after reset -> Default State */ |
1963 | dwc->dev_state = DWC3_DEFAULT_STATE; | |
1964 | ||
72246da4 FB |
1965 | /* Enable PHYs */ |
1966 | dwc3_gadget_usb2_phy_power(dwc, true); | |
1967 | dwc3_gadget_usb3_phy_power(dwc, true); | |
1968 | ||
1969 | if (dwc->gadget.speed != USB_SPEED_UNKNOWN) | |
1970 | dwc3_disconnect_gadget(dwc); | |
1971 | ||
1972 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
1973 | reg &= ~DWC3_DCTL_TSTCTRL_MASK; | |
e6a3b5e2 | 1974 | reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); |
72246da4 | 1975 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); |
3b637367 | 1976 | dwc->test_mode = false; |
72246da4 FB |
1977 | |
1978 | dwc3_stop_active_transfers(dwc); | |
1979 | dwc3_clear_stall_all_ep(dwc); | |
b23c8439 | 1980 | dwc->start_config_issued = false; |
72246da4 FB |
1981 | |
1982 | /* Reset device address to zero */ | |
1983 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); | |
1984 | reg &= ~(DWC3_DCFG_DEVADDR_MASK); | |
1985 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
72246da4 FB |
1986 | } |
1987 | ||
1988 | static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) | |
1989 | { | |
1990 | u32 reg; | |
1991 | u32 usb30_clock = DWC3_GCTL_CLK_BUS; | |
1992 | ||
1993 | /* | |
1994 | * We change the clock only at SS but I dunno why I would want to do | |
1995 | * this. Maybe it becomes part of the power saving plan. | |
1996 | */ | |
1997 | ||
1998 | if (speed != DWC3_DSTS_SUPERSPEED) | |
1999 | return; | |
2000 | ||
2001 | /* | |
2002 | * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed | |
2003 | * each time on Connect Done. | |
2004 | */ | |
2005 | if (!usb30_clock) | |
2006 | return; | |
2007 | ||
2008 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
2009 | reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); | |
2010 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
2011 | } | |
2012 | ||
2013 | static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed) | |
2014 | { | |
2015 | switch (speed) { | |
2016 | case USB_SPEED_SUPER: | |
2017 | dwc3_gadget_usb2_phy_power(dwc, false); | |
2018 | break; | |
2019 | case USB_SPEED_HIGH: | |
2020 | case USB_SPEED_FULL: | |
2021 | case USB_SPEED_LOW: | |
2022 | dwc3_gadget_usb3_phy_power(dwc, false); | |
2023 | break; | |
2024 | } | |
2025 | } | |
2026 | ||
2027 | static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) | |
2028 | { | |
2029 | struct dwc3_gadget_ep_cmd_params params; | |
2030 | struct dwc3_ep *dep; | |
2031 | int ret; | |
2032 | u32 reg; | |
2033 | u8 speed; | |
2034 | ||
2035 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2036 | ||
2037 | memset(¶ms, 0x00, sizeof(params)); | |
2038 | ||
72246da4 FB |
2039 | reg = dwc3_readl(dwc->regs, DWC3_DSTS); |
2040 | speed = reg & DWC3_DSTS_CONNECTSPD; | |
2041 | dwc->speed = speed; | |
2042 | ||
2043 | dwc3_update_ram_clk_sel(dwc, speed); | |
2044 | ||
2045 | switch (speed) { | |
2046 | case DWC3_DCFG_SUPERSPEED: | |
05870c5b FB |
2047 | /* |
2048 | * WORKAROUND: DWC3 revisions <1.90a have an issue which | |
2049 | * would cause a missing USB3 Reset event. | |
2050 | * | |
2051 | * In such situations, we should force a USB3 Reset | |
2052 | * event by calling our dwc3_gadget_reset_interrupt() | |
2053 | * routine. | |
2054 | * | |
2055 | * Refers to: | |
2056 | * | |
2057 | * STAR#9000483510: RTL: SS : USB3 reset event may | |
2058 | * not be generated always when the link enters poll | |
2059 | */ | |
2060 | if (dwc->revision < DWC3_REVISION_190A) | |
2061 | dwc3_gadget_reset_interrupt(dwc); | |
2062 | ||
72246da4 FB |
2063 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); |
2064 | dwc->gadget.ep0->maxpacket = 512; | |
2065 | dwc->gadget.speed = USB_SPEED_SUPER; | |
2066 | break; | |
2067 | case DWC3_DCFG_HIGHSPEED: | |
2068 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2069 | dwc->gadget.ep0->maxpacket = 64; | |
2070 | dwc->gadget.speed = USB_SPEED_HIGH; | |
2071 | break; | |
2072 | case DWC3_DCFG_FULLSPEED2: | |
2073 | case DWC3_DCFG_FULLSPEED1: | |
2074 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); | |
2075 | dwc->gadget.ep0->maxpacket = 64; | |
2076 | dwc->gadget.speed = USB_SPEED_FULL; | |
2077 | break; | |
2078 | case DWC3_DCFG_LOWSPEED: | |
2079 | dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); | |
2080 | dwc->gadget.ep0->maxpacket = 8; | |
2081 | dwc->gadget.speed = USB_SPEED_LOW; | |
2082 | break; | |
2083 | } | |
2084 | ||
2085 | /* Disable unneded PHY */ | |
2086 | dwc3_gadget_disable_phy(dwc, dwc->gadget.speed); | |
2087 | ||
2088 | dep = dwc->eps[0]; | |
c90bfaec | 2089 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
2090 | if (ret) { |
2091 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2092 | return; | |
2093 | } | |
2094 | ||
2095 | dep = dwc->eps[1]; | |
c90bfaec | 2096 | ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL); |
72246da4 FB |
2097 | if (ret) { |
2098 | dev_err(dwc->dev, "failed to enable %s\n", dep->name); | |
2099 | return; | |
2100 | } | |
2101 | ||
2102 | /* | |
2103 | * Configure PHY via GUSB3PIPECTLn if required. | |
2104 | * | |
2105 | * Update GTXFIFOSIZn | |
2106 | * | |
2107 | * In both cases reset values should be sufficient. | |
2108 | */ | |
2109 | } | |
2110 | ||
2111 | static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) | |
2112 | { | |
2113 | dev_vdbg(dwc->dev, "%s\n", __func__); | |
2114 | ||
2115 | /* | |
2116 | * TODO take core out of low power mode when that's | |
2117 | * implemented. | |
2118 | */ | |
2119 | ||
2120 | dwc->gadget_driver->resume(&dwc->gadget); | |
2121 | } | |
2122 | ||
2123 | static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, | |
2124 | unsigned int evtinfo) | |
2125 | { | |
fae2b904 FB |
2126 | enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; |
2127 | ||
2128 | /* | |
2129 | * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending | |
2130 | * on the link partner, the USB session might do multiple entry/exit | |
2131 | * of low power states before a transfer takes place. | |
2132 | * | |
2133 | * Due to this problem, we might experience lower throughput. The | |
2134 | * suggested workaround is to disable DCTL[12:9] bits if we're | |
2135 | * transitioning from U1/U2 to U0 and enable those bits again | |
2136 | * after a transfer completes and there are no pending transfers | |
2137 | * on any of the enabled endpoints. | |
2138 | * | |
2139 | * This is the first half of that workaround. | |
2140 | * | |
2141 | * Refers to: | |
2142 | * | |
2143 | * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us | |
2144 | * core send LGO_Ux entering U0 | |
2145 | */ | |
2146 | if (dwc->revision < DWC3_REVISION_183A) { | |
2147 | if (next == DWC3_LINK_STATE_U0) { | |
2148 | u32 u1u2; | |
2149 | u32 reg; | |
2150 | ||
2151 | switch (dwc->link_state) { | |
2152 | case DWC3_LINK_STATE_U1: | |
2153 | case DWC3_LINK_STATE_U2: | |
2154 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2155 | u1u2 = reg & (DWC3_DCTL_INITU2ENA | |
2156 | | DWC3_DCTL_ACCEPTU2ENA | |
2157 | | DWC3_DCTL_INITU1ENA | |
2158 | | DWC3_DCTL_ACCEPTU1ENA); | |
2159 | ||
2160 | if (!dwc->u1u2) | |
2161 | dwc->u1u2 = reg & u1u2; | |
2162 | ||
2163 | reg &= ~u1u2; | |
2164 | ||
2165 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2166 | break; | |
2167 | default: | |
2168 | /* do nothing */ | |
2169 | break; | |
2170 | } | |
2171 | } | |
2172 | } | |
2173 | ||
2174 | dwc->link_state = next; | |
019ac832 FB |
2175 | |
2176 | dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state); | |
72246da4 FB |
2177 | } |
2178 | ||
2179 | static void dwc3_gadget_interrupt(struct dwc3 *dwc, | |
2180 | const struct dwc3_event_devt *event) | |
2181 | { | |
2182 | switch (event->type) { | |
2183 | case DWC3_DEVICE_EVENT_DISCONNECT: | |
2184 | dwc3_gadget_disconnect_interrupt(dwc); | |
2185 | break; | |
2186 | case DWC3_DEVICE_EVENT_RESET: | |
2187 | dwc3_gadget_reset_interrupt(dwc); | |
2188 | break; | |
2189 | case DWC3_DEVICE_EVENT_CONNECT_DONE: | |
2190 | dwc3_gadget_conndone_interrupt(dwc); | |
2191 | break; | |
2192 | case DWC3_DEVICE_EVENT_WAKEUP: | |
2193 | dwc3_gadget_wakeup_interrupt(dwc); | |
2194 | break; | |
2195 | case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: | |
2196 | dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); | |
2197 | break; | |
2198 | case DWC3_DEVICE_EVENT_EOPF: | |
2199 | dev_vdbg(dwc->dev, "End of Periodic Frame\n"); | |
2200 | break; | |
2201 | case DWC3_DEVICE_EVENT_SOF: | |
2202 | dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); | |
2203 | break; | |
2204 | case DWC3_DEVICE_EVENT_ERRATIC_ERROR: | |
2205 | dev_vdbg(dwc->dev, "Erratic Error\n"); | |
2206 | break; | |
2207 | case DWC3_DEVICE_EVENT_CMD_CMPL: | |
2208 | dev_vdbg(dwc->dev, "Command Complete\n"); | |
2209 | break; | |
2210 | case DWC3_DEVICE_EVENT_OVERFLOW: | |
2211 | dev_vdbg(dwc->dev, "Overflow\n"); | |
2212 | break; | |
2213 | default: | |
2214 | dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); | |
2215 | } | |
2216 | } | |
2217 | ||
2218 | static void dwc3_process_event_entry(struct dwc3 *dwc, | |
2219 | const union dwc3_event *event) | |
2220 | { | |
2221 | /* Endpoint IRQ, handle it and return early */ | |
2222 | if (event->type.is_devspec == 0) { | |
2223 | /* depevt */ | |
2224 | return dwc3_endpoint_interrupt(dwc, &event->depevt); | |
2225 | } | |
2226 | ||
2227 | switch (event->type.type) { | |
2228 | case DWC3_EVENT_TYPE_DEV: | |
2229 | dwc3_gadget_interrupt(dwc, &event->devt); | |
2230 | break; | |
2231 | /* REVISIT what to do with Carkit and I2C events ? */ | |
2232 | default: | |
2233 | dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); | |
2234 | } | |
2235 | } | |
2236 | ||
2237 | static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) | |
2238 | { | |
2239 | struct dwc3_event_buffer *evt; | |
2240 | int left; | |
2241 | u32 count; | |
2242 | ||
2243 | count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); | |
2244 | count &= DWC3_GEVNTCOUNT_MASK; | |
2245 | if (!count) | |
2246 | return IRQ_NONE; | |
2247 | ||
2248 | evt = dwc->ev_buffs[buf]; | |
2249 | left = count; | |
2250 | ||
2251 | while (left > 0) { | |
2252 | union dwc3_event event; | |
2253 | ||
d70d8442 FB |
2254 | event.raw = *(u32 *) (evt->buf + evt->lpos); |
2255 | ||
72246da4 FB |
2256 | dwc3_process_event_entry(dwc, &event); |
2257 | /* | |
2258 | * XXX we wrap around correctly to the next entry as almost all | |
2259 | * entries are 4 bytes in size. There is one entry which has 12 | |
2260 | * bytes which is a regular entry followed by 8 bytes data. ATM | |
2261 | * I don't know how things are organized if were get next to the | |
2262 | * a boundary so I worry about that once we try to handle that. | |
2263 | */ | |
2264 | evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; | |
2265 | left -= 4; | |
2266 | ||
2267 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); | |
2268 | } | |
2269 | ||
2270 | return IRQ_HANDLED; | |
2271 | } | |
2272 | ||
2273 | static irqreturn_t dwc3_interrupt(int irq, void *_dwc) | |
2274 | { | |
2275 | struct dwc3 *dwc = _dwc; | |
2276 | int i; | |
2277 | irqreturn_t ret = IRQ_NONE; | |
2278 | ||
2279 | spin_lock(&dwc->lock); | |
2280 | ||
9f622b2a | 2281 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 FB |
2282 | irqreturn_t status; |
2283 | ||
2284 | status = dwc3_process_event_buf(dwc, i); | |
2285 | if (status == IRQ_HANDLED) | |
2286 | ret = status; | |
2287 | } | |
2288 | ||
2289 | spin_unlock(&dwc->lock); | |
2290 | ||
2291 | return ret; | |
2292 | } | |
2293 | ||
2294 | /** | |
2295 | * dwc3_gadget_init - Initializes gadget related registers | |
1d046793 | 2296 | * @dwc: pointer to our controller context structure |
72246da4 FB |
2297 | * |
2298 | * Returns 0 on success otherwise negative errno. | |
2299 | */ | |
2300 | int __devinit dwc3_gadget_init(struct dwc3 *dwc) | |
2301 | { | |
2302 | u32 reg; | |
2303 | int ret; | |
2304 | int irq; | |
2305 | ||
2306 | dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2307 | &dwc->ctrl_req_addr, GFP_KERNEL); | |
2308 | if (!dwc->ctrl_req) { | |
2309 | dev_err(dwc->dev, "failed to allocate ctrl request\n"); | |
2310 | ret = -ENOMEM; | |
2311 | goto err0; | |
2312 | } | |
2313 | ||
2314 | dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2315 | &dwc->ep0_trb_addr, GFP_KERNEL); | |
2316 | if (!dwc->ep0_trb) { | |
2317 | dev_err(dwc->dev, "failed to allocate ep0 trb\n"); | |
2318 | ret = -ENOMEM; | |
2319 | goto err1; | |
2320 | } | |
2321 | ||
3ef35faf | 2322 | dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); |
72246da4 FB |
2323 | if (!dwc->setup_buf) { |
2324 | dev_err(dwc->dev, "failed to allocate setup buffer\n"); | |
2325 | ret = -ENOMEM; | |
2326 | goto err2; | |
2327 | } | |
2328 | ||
5812b1c2 | 2329 | dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, |
3ef35faf FB |
2330 | DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, |
2331 | GFP_KERNEL); | |
5812b1c2 FB |
2332 | if (!dwc->ep0_bounce) { |
2333 | dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); | |
2334 | ret = -ENOMEM; | |
2335 | goto err3; | |
2336 | } | |
2337 | ||
72246da4 FB |
2338 | dev_set_name(&dwc->gadget.dev, "gadget"); |
2339 | ||
2340 | dwc->gadget.ops = &dwc3_gadget_ops; | |
d327ab5b | 2341 | dwc->gadget.max_speed = USB_SPEED_SUPER; |
72246da4 FB |
2342 | dwc->gadget.speed = USB_SPEED_UNKNOWN; |
2343 | dwc->gadget.dev.parent = dwc->dev; | |
eeb720fb | 2344 | dwc->gadget.sg_supported = true; |
72246da4 FB |
2345 | |
2346 | dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask); | |
2347 | ||
2348 | dwc->gadget.dev.dma_parms = dwc->dev->dma_parms; | |
2349 | dwc->gadget.dev.dma_mask = dwc->dev->dma_mask; | |
2350 | dwc->gadget.dev.release = dwc3_gadget_release; | |
2351 | dwc->gadget.name = "dwc3-gadget"; | |
2352 | ||
2353 | /* | |
2354 | * REVISIT: Here we should clear all pending IRQs to be | |
2355 | * sure we're starting from a well known location. | |
2356 | */ | |
2357 | ||
2358 | ret = dwc3_gadget_init_endpoints(dwc); | |
2359 | if (ret) | |
5812b1c2 | 2360 | goto err4; |
72246da4 FB |
2361 | |
2362 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); | |
2363 | ||
2364 | ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED, | |
2365 | "dwc3", dwc); | |
2366 | if (ret) { | |
2367 | dev_err(dwc->dev, "failed to request irq #%d --> %d\n", | |
2368 | irq, ret); | |
5812b1c2 | 2369 | goto err5; |
72246da4 FB |
2370 | } |
2371 | ||
e6a3b5e2 SAS |
2372 | reg = dwc3_readl(dwc->regs, DWC3_DCFG); |
2373 | reg |= DWC3_DCFG_LPM_CAP; | |
2374 | dwc3_writel(dwc->regs, DWC3_DCFG, reg); | |
2375 | ||
2376 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
2377 | reg |= DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA; | |
2378 | dwc3_writel(dwc->regs, DWC3_DCTL, reg); | |
2379 | ||
72246da4 FB |
2380 | /* Enable all but Start and End of Frame IRQs */ |
2381 | reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | | |
2382 | DWC3_DEVTEN_EVNTOVERFLOWEN | | |
2383 | DWC3_DEVTEN_CMDCMPLTEN | | |
2384 | DWC3_DEVTEN_ERRTICERREN | | |
2385 | DWC3_DEVTEN_WKUPEVTEN | | |
2386 | DWC3_DEVTEN_ULSTCNGEN | | |
2387 | DWC3_DEVTEN_CONNECTDONEEN | | |
2388 | DWC3_DEVTEN_USBRSTEN | | |
2389 | DWC3_DEVTEN_DISCONNEVTEN); | |
2390 | dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); | |
2391 | ||
2392 | ret = device_register(&dwc->gadget.dev); | |
2393 | if (ret) { | |
2394 | dev_err(dwc->dev, "failed to register gadget device\n"); | |
2395 | put_device(&dwc->gadget.dev); | |
5812b1c2 | 2396 | goto err6; |
72246da4 FB |
2397 | } |
2398 | ||
2399 | ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); | |
2400 | if (ret) { | |
2401 | dev_err(dwc->dev, "failed to register udc\n"); | |
5812b1c2 | 2402 | goto err7; |
72246da4 FB |
2403 | } |
2404 | ||
2405 | return 0; | |
2406 | ||
5812b1c2 | 2407 | err7: |
72246da4 FB |
2408 | device_unregister(&dwc->gadget.dev); |
2409 | ||
5812b1c2 | 2410 | err6: |
72246da4 FB |
2411 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); |
2412 | free_irq(irq, dwc); | |
2413 | ||
5812b1c2 | 2414 | err5: |
72246da4 FB |
2415 | dwc3_gadget_free_endpoints(dwc); |
2416 | ||
5812b1c2 | 2417 | err4: |
3ef35faf FB |
2418 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2419 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2420 | |
72246da4 | 2421 | err3: |
0fc9a1be | 2422 | kfree(dwc->setup_buf); |
72246da4 FB |
2423 | |
2424 | err2: | |
2425 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2426 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2427 | ||
2428 | err1: | |
2429 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2430 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2431 | ||
2432 | err0: | |
2433 | return ret; | |
2434 | } | |
2435 | ||
2436 | void dwc3_gadget_exit(struct dwc3 *dwc) | |
2437 | { | |
2438 | int irq; | |
72246da4 FB |
2439 | |
2440 | usb_del_gadget_udc(&dwc->gadget); | |
2441 | irq = platform_get_irq(to_platform_device(dwc->dev), 0); | |
2442 | ||
2443 | dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); | |
2444 | free_irq(irq, dwc); | |
2445 | ||
72246da4 FB |
2446 | dwc3_gadget_free_endpoints(dwc); |
2447 | ||
3ef35faf FB |
2448 | dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, |
2449 | dwc->ep0_bounce, dwc->ep0_bounce_addr); | |
5812b1c2 | 2450 | |
0fc9a1be | 2451 | kfree(dwc->setup_buf); |
72246da4 FB |
2452 | |
2453 | dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), | |
2454 | dwc->ep0_trb, dwc->ep0_trb_addr); | |
2455 | ||
2456 | dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), | |
2457 | dwc->ctrl_req, dwc->ctrl_req_addr); | |
2458 | ||
2459 | device_unregister(&dwc->gadget.dev); | |
2460 | } |