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usb: dwc3: Fix break from cleanup request loop
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
04a9bfcd
FB		 57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
8598bde7
FB		 90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
aee63e3c 96 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
aee63e3c 100 int retries = 10000;
8598bde7
FB		 101 u32 reg;
102
802fde98
PZ		 103 /*
104 * Wait until device controller is ready. Only applies to 1.94a and
105 * later RTL.
106 */
107 if (dwc->revision >= DWC3_REVISION_194A) {
108 while (--retries) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
111 udelay(5);
112 else
113 break;
114 }
115
116 if (retries <= 0)
117 return -ETIMEDOUT;
118 }
119
8598bde7
FB		 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
122
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
126
802fde98
PZ		 127 /*
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
130 */
131 if (dwc->revision >= DWC3_REVISION_194A)
132 return 0;
133
8598bde7 134 /* wait for a change in DSTS */
aed430e5 135 retries = 10000;
8598bde7
FB		 136 while (--retries) {
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
138
8598bde7
FB		 139 if (DWC3_DSTS_USBLNKST(reg) == state)
140 return 0;
141
aee63e3c 142 udelay(5);
8598bde7
FB		 143 }
144
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
146
147 return -ETIMEDOUT;
148}
149
457e84b6
FB		 150/**
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
153 *
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
157 *
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
162 *
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
165 *
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
168 *
169 * Unfortunately, due to many variables that's not always the case.
170 */
171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
172{
173 int last_fifo_depth = 0;
174 int ram1_depth;
175 int fifo_size;
176 int mdwidth;
177 int num;
178
179 if (!dwc->needs_fifo_resize)
180 return 0;
181
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
184
185 /* MDWIDTH is represented in bits, we need it in bytes */
186 mdwidth >>= 3;
187
188 /*
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
192 * FIFO space
193 */
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
2e81c36a 197 int mult = 1;
457e84b6
FB		 198 int tmp;
199
200 if (!(dep->number & 1))
201 continue;
202
203 if (!(dep->flags & DWC3_EP_ENABLED))
204 continue;
205
16e78db7
IS		 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
2e81c36a
FB		 208 mult = 3;
209
210 /*
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
214 * accordingly.
215 *
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
219 * packets
220 */
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
457e84b6
FB		 222 tmp += mdwidth;
223
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
2e81c36a 225
457e84b6
FB		 226 fifo_size |= (last_fifo_depth << 16);
227
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
230
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
232 fifo_size);
233
234 last_fifo_depth += (fifo_size & 0xffff);
235 }
236
237 return 0;
238}
239
72246da4
FB		 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
241 int status)
242{
243 struct dwc3 *dwc = dep->dwc;
244
245 if (req->queued) {
eeb720fb
FB		 246 if (req->request.num_mapped_sgs)
247 dep->busy_slot += req->request.num_mapped_sgs;
248 else
249 dep->busy_slot++;
250
72246da4
FB		 251 /*
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
255 */
256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
16e78db7 257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
72246da4
FB		 258 dep->busy_slot++;
259 }
260 list_del(&req->list);
eeb720fb 261 req->trb = NULL;
72246da4
FB		 262
263 if (req->request.status == -EINPROGRESS)
264 req->request.status = status;
265
0fc9a1be
FB		 266 usb_gadget_unmap_request(&dwc->gadget, &req->request,
267 req->direction);
72246da4
FB		 268
269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
270 req, dep->name, req->request.actual,
271 req->request.length, status);
272
273 spin_unlock(&dwc->lock);
0fc9a1be 274 req->request.complete(&dep->endpoint, &req->request);
72246da4
FB		 275 spin_lock(&dwc->lock);
276}
277
278static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
279{
280 switch (cmd) {
281 case DWC3_DEPCMD_DEPSTARTCFG:
282 return "Start New Configuration";
283 case DWC3_DEPCMD_ENDTRANSFER:
284 return "End Transfer";
285 case DWC3_DEPCMD_UPDATETRANSFER:
286 return "Update Transfer";
287 case DWC3_DEPCMD_STARTTRANSFER:
288 return "Start Transfer";
289 case DWC3_DEPCMD_CLEARSTALL:
290 return "Clear Stall";
291 case DWC3_DEPCMD_SETSTALL:
292 return "Set Stall";
802fde98
PZ		 293 case DWC3_DEPCMD_GETEPSTATE:
294 return "Get Endpoint State";
72246da4
FB		 295 case DWC3_DEPCMD_SETTRANSFRESOURCE:
296 return "Set Endpoint Transfer Resource";
297 case DWC3_DEPCMD_SETEPCONFIG:
298 return "Set Endpoint Configuration";
299 default:
300 return "UNKNOWN command";
301 }
302}
303
b09bb642
FB		 304int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
305{
306 u32 timeout = 500;
307 u32 reg;
308
309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
311
312 do {
313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
314 if (!(reg & DWC3_DGCMD_CMDACT)) {
315 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
316 DWC3_DGCMD_STATUS(reg));
317 return 0;
318 }
319
320 /*
321 * We can't sleep here, because it's also called from
322 * interrupt context.
323 */
324 timeout--;
325 if (!timeout)
326 return -ETIMEDOUT;
327 udelay(1);
328 } while (1);
329}
330
72246da4
FB		 331int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
333{
334 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 335 u32 timeout = 500;
72246da4
FB		 336 u32 reg;
337
338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
339 dep->name,
dc1c70a7
FB		 340 dwc3_gadget_ep_cmd_string(cmd), params->param0,
341 params->param1, params->param2);
72246da4 342
dc1c70a7
FB		 343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 346
347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
348 do {
349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
350 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 351 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
352 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 353 return 0;
354 }
355
356 /*
72246da4
FB		 357 * We can't sleep here, because it is also called from
358 * interrupt context.
359 */
360 timeout--;
361 if (!timeout)
362 return -ETIMEDOUT;
363
61d58242 364 udelay(1);
72246da4
FB		 365 } while (1);
366}
367
368static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 369 struct dwc3_trb *trb)
72246da4 370{
c439ef87 371 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 372
373 return dep->trb_pool_dma + offset;
374}
375
376static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
377{
378 struct dwc3 *dwc = dep->dwc;
379
380 if (dep->trb_pool)
381 return 0;
382
383 if (dep->number == 0 || dep->number == 1)
384 return 0;
385
386 dep->trb_pool = dma_alloc_coherent(dwc->dev,
387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
388 &dep->trb_pool_dma, GFP_KERNEL);
389 if (!dep->trb_pool) {
390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
391 dep->name);
392 return -ENOMEM;
393 }
394
395 return 0;
396}
397
398static void dwc3_free_trb_pool(struct dwc3_ep *dep)
399{
400 struct dwc3 *dwc = dep->dwc;
401
402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
403 dep->trb_pool, dep->trb_pool_dma);
404
405 dep->trb_pool = NULL;
406 dep->trb_pool_dma = 0;
407}
408
409static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
410{
411 struct dwc3_gadget_ep_cmd_params params;
412 u32 cmd;
413
414 memset(&params, 0x00, sizeof(params));
415
416 if (dep->number != 1) {
417 cmd = DWC3_DEPCMD_DEPSTARTCFG;
418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 419 if (dep->number > 1) {
420 if (dwc->start_config_issued)
421 return 0;
422 dwc->start_config_issued = true;
72246da4 423 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 424 }
72246da4
FB		 425
426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
427 }
428
429 return 0;
430}
431
432static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec
FB		 433 const struct usb_endpoint_descriptor *desc,
434 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 435{
436 struct dwc3_gadget_ep_cmd_params params;
437
438 memset(&params, 0x00, sizeof(params));
439
dc1c70a7
FB		 440 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
442 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
72246da4 443
dc1c70a7
FB		 444 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
445 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 446
18b7ede5 447 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 448 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
449 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 450 dep->stream_capable = true;
451 }
452
72246da4 453 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 454 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 455
456 /*
457 * We are doing 1:1 mapping for endpoints, meaning
458 * Physical Endpoints 2 maps to Logical Endpoint 2 and
459 * so on. We consider the direction bit as part of the physical
460 * endpoint number. So USB endpoint 0x81 is 0x03.
461 */
dc1c70a7 462 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 463
464 /*
465 * We must use the lower 16 TX FIFOs even though
466 * HW might have more
467 */
468 if (dep->direction)
dc1c70a7 469 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 470
471 if (desc->bInterval) {
dc1c70a7 472 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 473 dep->interval = 1 << (desc->bInterval - 1);
474 }
475
476 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
477 DWC3_DEPCMD_SETEPCONFIG, &params);
478}
479
480static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
481{
482 struct dwc3_gadget_ep_cmd_params params;
483
484 memset(&params, 0x00, sizeof(params));
485
dc1c70a7 486 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 487
488 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
489 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
490}
491
492/**
493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
494 * @dep: endpoint to be initialized
495 * @desc: USB Endpoint Descriptor
496 *
497 * Caller should take care of locking
498 */
499static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec
FB		 500 const struct usb_endpoint_descriptor *desc,
501 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 502{
503 struct dwc3 *dwc = dep->dwc;
504 u32 reg;
505 int ret = -ENOMEM;
506
507 if (!(dep->flags & DWC3_EP_ENABLED)) {
508 ret = dwc3_gadget_start_config(dwc, dep);
509 if (ret)
510 return ret;
511 }
512
c90bfaec 513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
72246da4
FB		 514 if (ret)
515 return ret;
516
517 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 518 struct dwc3_trb *trb_st_hw;
519 struct dwc3_trb *trb_link;
72246da4
FB		 520
521 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
522 if (ret)
523 return ret;
524
16e78db7 525 dep->endpoint.desc = desc;
c90bfaec 526 dep->comp_desc = comp_desc;
72246da4
FB		 527 dep->type = usb_endpoint_type(desc);
528 dep->flags |= DWC3_EP_ENABLED;
529
530 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
531 reg |= DWC3_DALEPENA_EP(dep->number);
532 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
533
534 if (!usb_endpoint_xfer_isoc(desc))
535 return 0;
536
537 memset(&trb_link, 0, sizeof(trb_link));
538
1d046793 539 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 540 trb_st_hw = &dep->trb_pool[0];
541
f6bafc6a 542 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
72246da4 543
f6bafc6a
FB		 544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 548 }
549
550 return 0;
551}
552
624407f9
SAS		 553static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
554static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 555{
556 struct dwc3_request *req;
557
624407f9
SAS		 558 if (!list_empty(&dep->req_queued))
559 dwc3_stop_active_transfer(dwc, dep->number);
560
72246da4
FB		 561 while (!list_empty(&dep->request_list)) {
562 req = next_request(&dep->request_list);
563
624407f9 564 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 565 }
72246da4
FB		 566}
567
568/**
569 * __dwc3_gadget_ep_disable - Disables a HW endpoint
570 * @dep: the endpoint to disable
571 *
624407f9
SAS		 572 * This function also removes requests which are currently processed ny the
573 * hardware and those which are not yet scheduled.
574 * Caller should take care of locking.
72246da4 575 */
72246da4
FB		 576static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
577{
578 struct dwc3 *dwc = dep->dwc;
579 u32 reg;
580
624407f9 581 dwc3_remove_requests(dwc, dep);
72246da4
FB		 582
583 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
584 reg &= ~DWC3_DALEPENA_EP(dep->number);
585 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
586
879631aa 587 dep->stream_capable = false;
f9c56cdd 588 dep->endpoint.desc = NULL;
c90bfaec 589 dep->comp_desc = NULL;
72246da4 590 dep->type = 0;
879631aa 591 dep->flags = 0;
72246da4
FB		 592
593 return 0;
594}
595
596/* -------------------------------------------------------------------------- */
597
598static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
599 const struct usb_endpoint_descriptor *desc)
600{
601 return -EINVAL;
602}
603
604static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
605{
606 return -EINVAL;
607}
608
609/* -------------------------------------------------------------------------- */
610
611static int dwc3_gadget_ep_enable(struct usb_ep *ep,
612 const struct usb_endpoint_descriptor *desc)
613{
614 struct dwc3_ep *dep;
615 struct dwc3 *dwc;
616 unsigned long flags;
617 int ret;
618
619 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
620 pr_debug("dwc3: invalid parameters\n");
621 return -EINVAL;
622 }
623
624 if (!desc->wMaxPacketSize) {
625 pr_debug("dwc3: missing wMaxPacketSize\n");
626 return -EINVAL;
627 }
628
629 dep = to_dwc3_ep(ep);
630 dwc = dep->dwc;
631
632 switch (usb_endpoint_type(desc)) {
633 case USB_ENDPOINT_XFER_CONTROL:
27a78d6a 634 strlcat(dep->name, "-control", sizeof(dep->name));
72246da4
FB		 635 break;
636 case USB_ENDPOINT_XFER_ISOC:
27a78d6a 637 strlcat(dep->name, "-isoc", sizeof(dep->name));
72246da4
FB		 638 break;
639 case USB_ENDPOINT_XFER_BULK:
27a78d6a 640 strlcat(dep->name, "-bulk", sizeof(dep->name));
72246da4
FB		 641 break;
642 case USB_ENDPOINT_XFER_INT:
27a78d6a 643 strlcat(dep->name, "-int", sizeof(dep->name));
72246da4
FB		 644 break;
645 default:
646 dev_err(dwc->dev, "invalid endpoint transfer type\n");
647 }
648
649 if (dep->flags & DWC3_EP_ENABLED) {
650 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
651 dep->name);
652 return 0;
653 }
654
655 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
656
657 spin_lock_irqsave(&dwc->lock, flags);
c90bfaec 658 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
72246da4
FB		 659 spin_unlock_irqrestore(&dwc->lock, flags);
660
661 return ret;
662}
663
664static int dwc3_gadget_ep_disable(struct usb_ep *ep)
665{
666 struct dwc3_ep *dep;
667 struct dwc3 *dwc;
668 unsigned long flags;
669 int ret;
670
671 if (!ep) {
672 pr_debug("dwc3: invalid parameters\n");
673 return -EINVAL;
674 }
675
676 dep = to_dwc3_ep(ep);
677 dwc = dep->dwc;
678
679 if (!(dep->flags & DWC3_EP_ENABLED)) {
680 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
681 dep->name);
682 return 0;
683 }
684
685 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
686 dep->number >> 1,
687 (dep->number & 1) ? "in" : "out");
688
689 spin_lock_irqsave(&dwc->lock, flags);
690 ret = __dwc3_gadget_ep_disable(dep);
691 spin_unlock_irqrestore(&dwc->lock, flags);
692
693 return ret;
694}
695
696static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
697 gfp_t gfp_flags)
698{
699 struct dwc3_request *req;
700 struct dwc3_ep *dep = to_dwc3_ep(ep);
701 struct dwc3 *dwc = dep->dwc;
702
703 req = kzalloc(sizeof(*req), gfp_flags);
704 if (!req) {
705 dev_err(dwc->dev, "not enough memory\n");
706 return NULL;
707 }
708
709 req->epnum = dep->number;
710 req->dep = dep;
72246da4
FB		 711
712 return &req->request;
713}
714
715static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
716 struct usb_request *request)
717{
718 struct dwc3_request *req = to_dwc3_request(request);
719
720 kfree(req);
721}
722
c71fc37c
FB		 723/**
724 * dwc3_prepare_one_trb - setup one TRB from one request
725 * @dep: endpoint for which this request is prepared
726 * @req: dwc3_request pointer
727 */
68e823e2 728static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb
FB		 729 struct dwc3_request *req, dma_addr_t dma,
730 unsigned length, unsigned last, unsigned chain)
c71fc37c 731{
eeb720fb 732 struct dwc3 *dwc = dep->dwc;
f6bafc6a 733 struct dwc3_trb *trb;
c71fc37c
FB		 734
735 unsigned int cur_slot;
736
eeb720fb
FB		 737 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
738 dep->name, req, (unsigned long long) dma,
739 length, last ? " last" : "",
740 chain ? " chain" : "");
741
f6bafc6a 742 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c
FB		 743 cur_slot = dep->free_slot;
744 dep->free_slot++;
745
746 /* Skip the LINK-TRB on ISOC */
747 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
16e78db7 748 usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 749 return;
c71fc37c 750
eeb720fb
FB		 751 if (!req->trb) {
752 dwc3_gadget_move_request_queued(req);
f6bafc6a
FB		 753 req->trb = trb;
754 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
eeb720fb 755 }
c71fc37c 756
f6bafc6a
FB		 757 trb->size = DWC3_TRB_SIZE_LENGTH(length);
758 trb->bpl = lower_32_bits(dma);
759 trb->bph = upper_32_bits(dma);
c71fc37c 760
16e78db7 761 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 762 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 763 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 764 break;
765
766 case USB_ENDPOINT_XFER_ISOC:
f6bafc6a 767 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
c71fc37c 768
206dd69a 769 if (!req->request.no_interrupt)
f6bafc6a 770 trb->ctrl |= DWC3_TRB_CTRL_IOC;
c71fc37c
FB		 771 break;
772
773 case USB_ENDPOINT_XFER_BULK:
774 case USB_ENDPOINT_XFER_INT:
f6bafc6a 775 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 776 break;
777 default:
778 /*
779 * This is only possible with faulty memory because we
780 * checked it already :)
781 */
782 BUG();
783 }
784
16e78db7 785 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
f6bafc6a
FB		 786 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
787 trb->ctrl |= DWC3_TRB_CTRL_CSP;
788 } else {
789 if (chain)
790 trb->ctrl |= DWC3_TRB_CTRL_CHN;
791
792 if (last)
793 trb->ctrl |= DWC3_TRB_CTRL_LST;
794 }
c71fc37c 795
16e78db7 796 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 797 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 798
f6bafc6a 799 trb->ctrl |= DWC3_TRB_CTRL_HWO;
c71fc37c
FB		 800}
801
72246da4
FB		 802/*
803 * dwc3_prepare_trbs - setup TRBs from requests
804 * @dep: endpoint for which requests are being prepared
805 * @starting: true if the endpoint is idle and no requests are queued.
806 *
1d046793
PZ		 807 * The function goes through the requests list and sets up TRBs for the
808 * transfers. The function returns once there are no more TRBs available or
809 * it runs out of requests.
72246da4 810 */
68e823e2 811static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 812{
68e823e2 813 struct dwc3_request *req, *n;
72246da4 814 u32 trbs_left;
8d62cd65 815 u32 max;
c71fc37c 816 unsigned int last_one = 0;
72246da4
FB		 817
818 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
819
820 /* the first request must not be queued */
821 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 822
8d62cd65 823 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 824 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 825 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
826 if (trbs_left > max)
827 trbs_left = max;
828 }
829
72246da4 830 /*
1d046793
PZ		 831 * If busy & slot are equal than it is either full or empty. If we are
832 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 833 * full and don't do anything
834 */
835 if (!trbs_left) {
836 if (!starting)
68e823e2 837 return;
72246da4
FB		 838 trbs_left = DWC3_TRB_NUM;
839 /*
840 * In case we start from scratch, we queue the ISOC requests
841 * starting from slot 1. This is done because we use ring
842 * buffer and have no LST bit to stop us. Instead, we place
1d046793 843 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 844 * after the first request so we start at slot 1 and have
845 * 7 requests proceed before we hit the first IOC.
846 * Other transfer types don't use the ring buffer and are
847 * processed from the first TRB until the last one. Since we
848 * don't wrap around we have to start at the beginning.
849 */
16e78db7 850 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 851 dep->busy_slot = 1;
852 dep->free_slot = 1;
853 } else {
854 dep->busy_slot = 0;
855 dep->free_slot = 0;
856 }
857 }
858
859 /* The last TRB is a link TRB, not used for xfer */
16e78db7 860 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 861 return;
72246da4
FB		 862
863 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 864 unsigned length;
865 dma_addr_t dma;
72246da4 866
eeb720fb
FB		 867 if (req->request.num_mapped_sgs > 0) {
868 struct usb_request *request = &req->request;
869 struct scatterlist *sg = request->sg;
870 struct scatterlist *s;
871 int i;
72246da4 872
eeb720fb
FB		 873 for_each_sg(sg, s, request->num_mapped_sgs, i) {
874 unsigned chain = true;
72246da4 875
eeb720fb
FB		 876 length = sg_dma_len(s);
877 dma = sg_dma_address(s);
72246da4 878
1d046793
PZ		 879 if (i == (request->num_mapped_sgs - 1) ||
880 sg_is_last(s)) {
eeb720fb
FB		 881 last_one = true;
882 chain = false;
883 }
72246da4 884
eeb720fb
FB		 885 trbs_left--;
886 if (!trbs_left)
887 last_one = true;
72246da4 888
eeb720fb
FB		 889 if (last_one)
890 chain = false;
72246da4 891
eeb720fb
FB		 892 dwc3_prepare_one_trb(dep, req, dma, length,
893 last_one, chain);
72246da4 894
eeb720fb
FB		 895 if (last_one)
896 break;
897 }
72246da4 898 } else {
eeb720fb
FB		 899 dma = req->request.dma;
900 length = req->request.length;
901 trbs_left--;
72246da4 902
eeb720fb
FB		 903 if (!trbs_left)
904 last_one = 1;
879631aa 905
eeb720fb
FB		 906 /* Is this the last request? */
907 if (list_is_last(&req->list, &dep->request_list))
908 last_one = 1;
72246da4 909
eeb720fb
FB		 910 dwc3_prepare_one_trb(dep, req, dma, length,
911 last_one, false);
72246da4 912
eeb720fb
FB		 913 if (last_one)
914 break;
72246da4 915 }
72246da4 916 }
72246da4
FB		 917}
918
919static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
920 int start_new)
921{
922 struct dwc3_gadget_ep_cmd_params params;
923 struct dwc3_request *req;
924 struct dwc3 *dwc = dep->dwc;
925 int ret;
926 u32 cmd;
927
928 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
929 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
930 return -EBUSY;
931 }
932 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
933
934 /*
935 * If we are getting here after a short-out-packet we don't enqueue any
936 * new requests as we try to set the IOC bit only on the last request.
937 */
938 if (start_new) {
939 if (list_empty(&dep->req_queued))
940 dwc3_prepare_trbs(dep, start_new);
941
942 /* req points to the first request which will be sent */
943 req = next_request(&dep->req_queued);
944 } else {
68e823e2
FB		 945 dwc3_prepare_trbs(dep, start_new);
946
72246da4 947 /*
1d046793 948 * req points to the first request where HWO changed from 0 to 1
72246da4 949 */
68e823e2 950 req = next_request(&dep->req_queued);
72246da4
FB		 951 }
952 if (!req) {
953 dep->flags |= DWC3_EP_PENDING_REQUEST;
954 return 0;
955 }
956
957 memset(&params, 0, sizeof(params));
dc1c70a7
FB		 958 params.param0 = upper_32_bits(req->trb_dma);
959 params.param1 = lower_32_bits(req->trb_dma);
72246da4
FB		 960
961 if (start_new)
962 cmd = DWC3_DEPCMD_STARTTRANSFER;
963 else
964 cmd = DWC3_DEPCMD_UPDATETRANSFER;
965
966 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
967 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
968 if (ret < 0) {
969 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
970
971 /*
972 * FIXME we need to iterate over the list of requests
973 * here and stop, unmap, free and del each of the linked
1d046793 974 * requests instead of what we do now.
72246da4 975 */
0fc9a1be
FB		 976 usb_gadget_unmap_request(&dwc->gadget, &req->request,
977 req->direction);
72246da4
FB		 978 list_del(&req->list);
979 return ret;
980 }
981
982 dep->flags |= DWC3_EP_BUSY;
25b8ff68 983
f898ae09
PZ		 984 if (start_new) {
985 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
986 dep->number);
987 WARN_ON_ONCE(!dep->res_trans_idx);
988 }
25b8ff68 989
72246da4
FB		 990 return 0;
991}
992
d6d6ec7b
PA		 993static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
994 struct dwc3_ep *dep, u32 cur_uf)
995{
996 u32 uf;
997
998 if (list_empty(&dep->request_list)) {
999 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1000 dep->name);
1001 return;
1002 }
1003
1004 /* 4 micro frames in the future */
1005 uf = cur_uf + dep->interval * 4;
1006
1007 __dwc3_gadget_kick_transfer(dep, uf, 1);
1008}
1009
1010static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1011 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1012{
1013 u32 cur_uf, mask;
1014
1015 mask = ~(dep->interval - 1);
1016 cur_uf = event->parameters & mask;
1017
1018 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1019}
1020
72246da4
FB		 1021static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1022{
0fc9a1be
FB		 1023 struct dwc3 *dwc = dep->dwc;
1024 int ret;
1025
72246da4
FB		 1026 req->request.actual = 0;
1027 req->request.status = -EINPROGRESS;
1028 req->direction = dep->direction;
1029 req->epnum = dep->number;
1030
1031 /*
1032 * We only add to our list of requests now and
1033 * start consuming the list once we get XferNotReady
1034 * IRQ.
1035 *
1036 * That way, we avoid doing anything that we don't need
1037 * to do now and defer it until the point we receive a
1038 * particular token from the Host side.
1039 *
1040 * This will also avoid Host cancelling URBs due to too
1d046793 1041 * many NAKs.
72246da4 1042 */
0fc9a1be
FB		 1043 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1044 dep->direction);
1045 if (ret)
1046 return ret;
1047
72246da4
FB		 1048 list_add_tail(&req->list, &dep->request_list);
1049
d6d6ec7b
PA		 1050 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1051 if (dep->flags & DWC3_EP_BUSY) {
1052 dep->flags |= DWC3_EP_PENDING_REQUEST;
1053 } else if (dep->flags & DWC3_EP_MISSED_ISOC) {
1054 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1055 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1056 }
1057 }
f898ae09 1058
72246da4 1059 /*
f898ae09 1060 * There are two special cases:
72246da4 1061 *
f898ae09
PZ		 1062 * 1. XferNotReady with empty list of requests. We need to kick the
1063 * transfer here in that situation, otherwise we will be NAKing
1064 * forever. If we get XferNotReady before gadget driver has a
1065 * chance to queue a request, we will ACK the IRQ but won't be
1066 * able to receive the data until the next request is queued.
1067 * The following code is handling exactly that.
72246da4 1068 *
f898ae09
PZ		 1069 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1070 * kick the transfer here after queuing a request, otherwise the
1071 * core may not see the modified TRB(s).
72246da4
FB		 1072 */
1073 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f898ae09
PZ		 1074 int ret;
1075 int start_trans = 1;
1076 u8 trans_idx = dep->res_trans_idx;
72246da4 1077
16e78db7 1078 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
f898ae09 1079 (dep->flags & DWC3_EP_BUSY)) {
72246da4 1080 start_trans = 0;
f898ae09
PZ		 1081 WARN_ON_ONCE(!trans_idx);
1082 } else {
1083 trans_idx = 0;
1084 }
72246da4 1085
f898ae09 1086 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
72246da4
FB		 1087 if (ret && ret != -EBUSY) {
1088 struct dwc3 *dwc = dep->dwc;
1089
1090 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1091 dep->name);
1092 }
a0925324 1093 }
72246da4
FB		 1094
1095 return 0;
1096}
1097
1098static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1099 gfp_t gfp_flags)
1100{
1101 struct dwc3_request *req = to_dwc3_request(request);
1102 struct dwc3_ep *dep = to_dwc3_ep(ep);
1103 struct dwc3 *dwc = dep->dwc;
1104
1105 unsigned long flags;
1106
1107 int ret;
1108
16e78db7 1109 if (!dep->endpoint.desc) {
72246da4
FB		 1110 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1111 request, ep->name);
1112 return -ESHUTDOWN;
1113 }
1114
1115 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1116 request, ep->name, request->length);
1117
1118 spin_lock_irqsave(&dwc->lock, flags);
1119 ret = __dwc3_gadget_ep_queue(dep, req);
1120 spin_unlock_irqrestore(&dwc->lock, flags);
1121
1122 return ret;
1123}
1124
1125static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1126 struct usb_request *request)
1127{
1128 struct dwc3_request *req = to_dwc3_request(request);
1129 struct dwc3_request *r = NULL;
1130
1131 struct dwc3_ep *dep = to_dwc3_ep(ep);
1132 struct dwc3 *dwc = dep->dwc;
1133
1134 unsigned long flags;
1135 int ret = 0;
1136
1137 spin_lock_irqsave(&dwc->lock, flags);
1138
1139 list_for_each_entry(r, &dep->request_list, list) {
1140 if (r == req)
1141 break;
1142 }
1143
1144 if (r != req) {
1145 list_for_each_entry(r, &dep->req_queued, list) {
1146 if (r == req)
1147 break;
1148 }
1149 if (r == req) {
1150 /* wait until it is processed */
1151 dwc3_stop_active_transfer(dwc, dep->number);
1152 goto out0;
1153 }
1154 dev_err(dwc->dev, "request %p was not queued to %s\n",
1155 request, ep->name);
1156 ret = -EINVAL;
1157 goto out0;
1158 }
1159
1160 /* giveback the request */
1161 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1162
1163out0:
1164 spin_unlock_irqrestore(&dwc->lock, flags);
1165
1166 return ret;
1167}
1168
1169int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1170{
1171 struct dwc3_gadget_ep_cmd_params params;
1172 struct dwc3 *dwc = dep->dwc;
1173 int ret;
1174
1175 memset(&params, 0x00, sizeof(params));
1176
1177 if (value) {
0b7836a9
FB		 1178 if (dep->number == 0 || dep->number == 1) {
1179 /*
1180 * Whenever EP0 is stalled, we will restart
1181 * the state machine, thus moving back to
1182 * Setup Phase
1183 */
1184 dwc->ep0state = EP0_SETUP_PHASE;
1185 }
72246da4
FB		 1186
1187 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1188 DWC3_DEPCMD_SETSTALL, &params);
1189 if (ret)
1190 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1191 value ? "set" : "clear",
1192 dep->name);
1193 else
1194 dep->flags |= DWC3_EP_STALL;
1195 } else {
5275455a
PZ		 1196 if (dep->flags & DWC3_EP_WEDGE)
1197 return 0;
1198
72246da4
FB		 1199 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1200 DWC3_DEPCMD_CLEARSTALL, &params);
1201 if (ret)
1202 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1203 value ? "set" : "clear",
1204 dep->name);
1205 else
1206 dep->flags &= ~DWC3_EP_STALL;
1207 }
5275455a 1208
72246da4
FB		 1209 return ret;
1210}
1211
1212static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1213{
1214 struct dwc3_ep *dep = to_dwc3_ep(ep);
1215 struct dwc3 *dwc = dep->dwc;
1216
1217 unsigned long flags;
1218
1219 int ret;
1220
1221 spin_lock_irqsave(&dwc->lock, flags);
1222
16e78db7 1223 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1224 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1225 ret = -EINVAL;
1226 goto out;
1227 }
1228
1229 ret = __dwc3_gadget_ep_set_halt(dep, value);
1230out:
1231 spin_unlock_irqrestore(&dwc->lock, flags);
1232
1233 return ret;
1234}
1235
1236static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1237{
1238 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1239 struct dwc3 *dwc = dep->dwc;
1240 unsigned long flags;
72246da4 1241
249a4569 1242 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1243 dep->flags |= DWC3_EP_WEDGE;
249a4569 1244 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4 1245
5275455a 1246 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 1247}
1248
1249/* -------------------------------------------------------------------------- */
1250
1251static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1252 .bLength = USB_DT_ENDPOINT_SIZE,
1253 .bDescriptorType = USB_DT_ENDPOINT,
1254 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1255};
1256
1257static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1258 .enable = dwc3_gadget_ep0_enable,
1259 .disable = dwc3_gadget_ep0_disable,
1260 .alloc_request = dwc3_gadget_ep_alloc_request,
1261 .free_request = dwc3_gadget_ep_free_request,
1262 .queue = dwc3_gadget_ep0_queue,
1263 .dequeue = dwc3_gadget_ep_dequeue,
1264 .set_halt = dwc3_gadget_ep_set_halt,
1265 .set_wedge = dwc3_gadget_ep_set_wedge,
1266};
1267
1268static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1269 .enable = dwc3_gadget_ep_enable,
1270 .disable = dwc3_gadget_ep_disable,
1271 .alloc_request = dwc3_gadget_ep_alloc_request,
1272 .free_request = dwc3_gadget_ep_free_request,
1273 .queue = dwc3_gadget_ep_queue,
1274 .dequeue = dwc3_gadget_ep_dequeue,
1275 .set_halt = dwc3_gadget_ep_set_halt,
1276 .set_wedge = dwc3_gadget_ep_set_wedge,
1277};
1278
1279/* -------------------------------------------------------------------------- */
1280
1281static int dwc3_gadget_get_frame(struct usb_gadget *g)
1282{
1283 struct dwc3 *dwc = gadget_to_dwc(g);
1284 u32 reg;
1285
1286 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1287 return DWC3_DSTS_SOFFN(reg);
1288}
1289
1290static int dwc3_gadget_wakeup(struct usb_gadget *g)
1291{
1292 struct dwc3 *dwc = gadget_to_dwc(g);
1293
1294 unsigned long timeout;
1295 unsigned long flags;
1296
1297 u32 reg;
1298
1299 int ret = 0;
1300
1301 u8 link_state;
1302 u8 speed;
1303
1304 spin_lock_irqsave(&dwc->lock, flags);
1305
1306 /*
1307 * According to the Databook Remote wakeup request should
1308 * be issued only when the device is in early suspend state.
1309 *
1310 * We can check that via USB Link State bits in DSTS register.
1311 */
1312 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1313
1314 speed = reg & DWC3_DSTS_CONNECTSPD;
1315 if (speed == DWC3_DSTS_SUPERSPEED) {
1316 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1317 ret = -EINVAL;
1318 goto out;
1319 }
1320
1321 link_state = DWC3_DSTS_USBLNKST(reg);
1322
1323 switch (link_state) {
1324 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1325 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1326 break;
1327 default:
1328 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1329 link_state);
1330 ret = -EINVAL;
1331 goto out;
1332 }
1333
8598bde7
FB		 1334 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1335 if (ret < 0) {
1336 dev_err(dwc->dev, "failed to put link in Recovery\n");
1337 goto out;
1338 }
72246da4 1339
802fde98
PZ		 1340 /* Recent versions do this automatically */
1341 if (dwc->revision < DWC3_REVISION_194A) {
1342 /* write zeroes to Link Change Request */
fcc023c7 1343 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1344 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1345 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1346 }
72246da4 1347
1d046793 1348 /* poll until Link State changes to ON */
72246da4
FB		 1349 timeout = jiffies + msecs_to_jiffies(100);
1350
1d046793 1351 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1352 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1353
1354 /* in HS, means ON */
1355 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1356 break;
1357 }
1358
1359 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1360 dev_err(dwc->dev, "failed to send remote wakeup\n");
1361 ret = -EINVAL;
1362 }
1363
1364out:
1365 spin_unlock_irqrestore(&dwc->lock, flags);
1366
1367 return ret;
1368}
1369
1370static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1371 int is_selfpowered)
1372{
1373 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1374 unsigned long flags;
72246da4 1375
249a4569 1376 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1377 dwc->is_selfpowered = !!is_selfpowered;
249a4569 1378 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1379
1380 return 0;
1381}
1382
1383static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1384{
1385 u32 reg;
61d58242 1386 u32 timeout = 500;
72246da4
FB		 1387
1388 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1389 if (is_on) {
802fde98
PZ		 1390 if (dwc->revision <= DWC3_REVISION_187A) {
1391 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1392 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1393 }
1394
1395 if (dwc->revision >= DWC3_REVISION_194A)
1396 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1397 reg |= DWC3_DCTL_RUN_STOP;
8db7ed15 1398 } else {
72246da4 1399 reg &= ~DWC3_DCTL_RUN_STOP;
8db7ed15 1400 }
72246da4
FB		 1401
1402 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1403
1404 do {
1405 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1406 if (is_on) {
1407 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1408 break;
1409 } else {
1410 if (reg & DWC3_DSTS_DEVCTRLHLT)
1411 break;
1412 }
72246da4
FB		 1413 timeout--;
1414 if (!timeout)
1415 break;
61d58242 1416 udelay(1);
72246da4
FB		 1417 } while (1);
1418
1419 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1420 dwc->gadget_driver
1421 ? dwc->gadget_driver->function : "no-function",
1422 is_on ? "connect" : "disconnect");
1423}
1424
1425static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1426{
1427 struct dwc3 *dwc = gadget_to_dwc(g);
1428 unsigned long flags;
1429
1430 is_on = !!is_on;
1431
1432 spin_lock_irqsave(&dwc->lock, flags);
1433 dwc3_gadget_run_stop(dwc, is_on);
1434 spin_unlock_irqrestore(&dwc->lock, flags);
1435
1436 return 0;
1437}
1438
1439static int dwc3_gadget_start(struct usb_gadget *g,
1440 struct usb_gadget_driver *driver)
1441{
1442 struct dwc3 *dwc = gadget_to_dwc(g);
1443 struct dwc3_ep *dep;
1444 unsigned long flags;
1445 int ret = 0;
1446 u32 reg;
1447
1448 spin_lock_irqsave(&dwc->lock, flags);
1449
1450 if (dwc->gadget_driver) {
1451 dev_err(dwc->dev, "%s is already bound to %s\n",
1452 dwc->gadget.name,
1453 dwc->gadget_driver->driver.name);
1454 ret = -EBUSY;
1455 goto err0;
1456 }
1457
1458 dwc->gadget_driver = driver;
1459 dwc->gadget.dev.driver = &driver->driver;
1460
72246da4
FB		 1461 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1462 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1463
1464 /**
1465 * WORKAROUND: DWC3 revision < 2.20a have an issue
1466 * which would cause metastability state on Run/Stop
1467 * bit if we try to force the IP to USB2-only mode.
1468 *
1469 * Because of that, we cannot configure the IP to any
1470 * speed other than the SuperSpeed
1471 *
1472 * Refers to:
1473 *
1474 * STAR#9000525659: Clock Domain Crossing on DCTL in
1475 * USB 2.0 Mode
1476 */
1477 if (dwc->revision < DWC3_REVISION_220A)
1478 reg |= DWC3_DCFG_SUPERSPEED;
1479 else
1480 reg |= dwc->maximum_speed;
72246da4
FB		 1481 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1482
b23c8439
PZ		 1483 dwc->start_config_issued = false;
1484
72246da4
FB		 1485 /* Start with SuperSpeed Default */
1486 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1487
1488 dep = dwc->eps[0];
c90bfaec 1489 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1490 if (ret) {
1491 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1492 goto err0;
1493 }
1494
1495 dep = dwc->eps[1];
c90bfaec 1496 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1497 if (ret) {
1498 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1499 goto err1;
1500 }
1501
1502 /* begin to receive SETUP packets */
c7fcdeb2 1503 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1504 dwc3_ep0_out_start(dwc);
1505
1506 spin_unlock_irqrestore(&dwc->lock, flags);
1507
1508 return 0;
1509
1510err1:
1511 __dwc3_gadget_ep_disable(dwc->eps[0]);
1512
1513err0:
1514 spin_unlock_irqrestore(&dwc->lock, flags);
1515
1516 return ret;
1517}
1518
1519static int dwc3_gadget_stop(struct usb_gadget *g,
1520 struct usb_gadget_driver *driver)
1521{
1522 struct dwc3 *dwc = gadget_to_dwc(g);
1523 unsigned long flags;
1524
1525 spin_lock_irqsave(&dwc->lock, flags);
1526
1527 __dwc3_gadget_ep_disable(dwc->eps[0]);
1528 __dwc3_gadget_ep_disable(dwc->eps[1]);
1529
1530 dwc->gadget_driver = NULL;
1531 dwc->gadget.dev.driver = NULL;
1532
1533 spin_unlock_irqrestore(&dwc->lock, flags);
1534
1535 return 0;
1536}
802fde98 1537
72246da4
FB		 1538static const struct usb_gadget_ops dwc3_gadget_ops = {
1539 .get_frame = dwc3_gadget_get_frame,
1540 .wakeup = dwc3_gadget_wakeup,
1541 .set_selfpowered = dwc3_gadget_set_selfpowered,
1542 .pullup = dwc3_gadget_pullup,
1543 .udc_start = dwc3_gadget_start,
1544 .udc_stop = dwc3_gadget_stop,
1545};
1546
1547/* -------------------------------------------------------------------------- */
1548
1549static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1550{
1551 struct dwc3_ep *dep;
1552 u8 epnum;
1553
1554 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1555
1556 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1557 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1558 if (!dep) {
1559 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1560 epnum);
1561 return -ENOMEM;
1562 }
1563
1564 dep->dwc = dwc;
1565 dep->number = epnum;
1566 dwc->eps[epnum] = dep;
1567
1568 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1569 (epnum & 1) ? "in" : "out");
1570 dep->endpoint.name = dep->name;
1571 dep->direction = (epnum & 1);
1572
1573 if (epnum == 0 || epnum == 1) {
1574 dep->endpoint.maxpacket = 512;
1575 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1576 if (!epnum)
1577 dwc->gadget.ep0 = &dep->endpoint;
1578 } else {
1579 int ret;
1580
1581 dep->endpoint.maxpacket = 1024;
12d36c16 1582 dep->endpoint.max_streams = 15;
72246da4
FB		 1583 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1584 list_add_tail(&dep->endpoint.ep_list,
1585 &dwc->gadget.ep_list);
1586
1587 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1588 if (ret)
72246da4 1589 return ret;
72246da4 1590 }
25b8ff68 1591
72246da4
FB		 1592 INIT_LIST_HEAD(&dep->request_list);
1593 INIT_LIST_HEAD(&dep->req_queued);
1594 }
1595
1596 return 0;
1597}
1598
1599static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1600{
1601 struct dwc3_ep *dep;
1602 u8 epnum;
1603
1604 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1605 dep = dwc->eps[epnum];
1606 dwc3_free_trb_pool(dep);
1607
1608 if (epnum != 0 && epnum != 1)
1609 list_del(&dep->endpoint.ep_list);
1610
1611 kfree(dep);
1612 }
1613}
1614
1615static void dwc3_gadget_release(struct device *dev)
1616{
1617 dev_dbg(dev, "%s\n", __func__);
1618}
1619
1620/* -------------------------------------------------------------------------- */
1621static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1622 const struct dwc3_event_depevt *event, int status)
1623{
1624 struct dwc3_request *req;
f6bafc6a 1625 struct dwc3_trb *trb;
72246da4
FB		 1626 unsigned int count;
1627 unsigned int s_pkt = 0;
d6d6ec7b 1628 unsigned int trb_status;
72246da4
FB		 1629
1630 do {
1631 req = next_request(&dep->req_queued);
d39ee7be
SAS		 1632 if (!req) {
1633 WARN_ON_ONCE(1);
1634 return 1;
1635 }
72246da4 1636
f6bafc6a 1637 trb = req->trb;
72246da4 1638
f6bafc6a 1639 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
0d2f4758
SAS		 1640 /*
1641 * We continue despite the error. There is not much we
1d046793
PZ		 1642 * can do. If we don't clean it up we loop forever. If
1643 * we skip the TRB then it gets overwritten after a
1644 * while since we use them in a ring buffer. A BUG()
1645 * would help. Lets hope that if this occurs, someone
0d2f4758
SAS		 1646 * fixes the root cause instead of looking away :)
1647 */
72246da4
FB		 1648 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1649 dep->name, req->trb);
f6bafc6a 1650 count = trb->size & DWC3_TRB_SIZE_MASK;
72246da4
FB		 1651
1652 if (dep->direction) {
1653 if (count) {
d6d6ec7b
PA		 1654 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1655 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1656 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1657 dep->name);
1658 dep->current_uf = event->parameters &
1659 ~(dep->interval - 1);
1660 dep->flags |= DWC3_EP_MISSED_ISOC;
1661 } else {
1662 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1663 dep->name);
1664 status = -ECONNRESET;
1665 }
72246da4
FB		 1666 }
1667 } else {
1668 if (count && (event->status & DEPEVT_STATUS_SHORT))
1669 s_pkt = 1;
1670 }
1671
1672 /*
1673 * We assume here we will always receive the entire data block
1674 * which we should receive. Meaning, if we program RX to
1675 * receive 4K but we receive only 2K, we assume that's all we
1676 * should receive and we simply bounce the request back to the
1677 * gadget driver for further processing.
1678 */
1679 req->request.actual += req->request.length - count;
1680 dwc3_gadget_giveback(dep, req, status);
1681 if (s_pkt)
1682 break;
f6bafc6a 1683 if ((event->status & DEPEVT_STATUS_LST) &&
70b674bf
PA		 1684 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1685 DWC3_TRB_CTRL_HWO)))
72246da4 1686 break;
f6bafc6a
FB		 1687 if ((event->status & DEPEVT_STATUS_IOC) &&
1688 (trb->ctrl & DWC3_TRB_CTRL_IOC))
72246da4
FB		 1689 break;
1690 } while (1);
1691
f6bafc6a
FB		 1692 if ((event->status & DEPEVT_STATUS_IOC) &&
1693 (trb->ctrl & DWC3_TRB_CTRL_IOC))
72246da4
FB		 1694 return 0;
1695 return 1;
1696}
1697
1698static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1699 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1700 int start_new)
1701{
1702 unsigned status = 0;
1703 int clean_busy;
1704
1705 if (event->status & DEPEVT_STATUS_BUSERR)
1706 status = -ECONNRESET;
1707
1d046793 1708 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
c2df85ca 1709 if (clean_busy)
72246da4 1710 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 1711
1712 /*
1713 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1714 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1715 */
1716 if (dwc->revision < DWC3_REVISION_183A) {
1717 u32 reg;
1718 int i;
1719
1720 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1721 struct dwc3_ep *dep = dwc->eps[i];
1722
1723 if (!(dep->flags & DWC3_EP_ENABLED))
1724 continue;
1725
1726 if (!list_empty(&dep->req_queued))
1727 return;
1728 }
1729
1730 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1731 reg |= dwc->u1u2;
1732 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1733
1734 dwc->u1u2 = 0;
1735 }
72246da4
FB		 1736}
1737
72246da4
FB		 1738static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1739 const struct dwc3_event_depevt *event)
1740{
1741 struct dwc3 *dwc = dep->dwc;
1742 struct dwc3_event_depevt mod_ev = *event;
1743
1744 /*
1d046793
PZ		 1745 * We were asked to remove one request. It is possible that this
1746 * request and a few others were started together and have the same
72246da4
FB		 1747 * transfer index. Since we stopped the complete endpoint we don't
1748 * know how many requests were already completed (and not yet)
1749 * reported and how could be done (later). We purge them all until
1750 * the end of the list.
1751 */
1752 mod_ev.status = DEPEVT_STATUS_LST;
1753 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1754 dep->flags &= ~DWC3_EP_BUSY;
1d046793 1755 /* pending requests are ignored and are queued on XferNotReady */
72246da4
FB		 1756}
1757
1758static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1759 const struct dwc3_event_depevt *event)
1760{
1761 u32 param = event->parameters;
1762 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1763
1764 switch (cmd_type) {
1765 case DWC3_DEPCMD_ENDTRANSFER:
1766 dwc3_process_ep_cmd_complete(dep, event);
1767 break;
1768 case DWC3_DEPCMD_STARTTRANSFER:
1769 dep->res_trans_idx = param & 0x7f;
1770 break;
1771 default:
1772 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1773 __func__, cmd_type);
1774 break;
1775 };
1776}
1777
1778static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1779 const struct dwc3_event_depevt *event)
1780{
1781 struct dwc3_ep *dep;
1782 u8 epnum = event->endpoint_number;
1783
1784 dep = dwc->eps[epnum];
1785
1786 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1787 dwc3_ep_event_string(event->endpoint_event));
1788
1789 if (epnum == 0 || epnum == 1) {
1790 dwc3_ep0_interrupt(dwc, event);
1791 return;
1792 }
1793
1794 switch (event->endpoint_event) {
1795 case DWC3_DEPEVT_XFERCOMPLETE:
c2df85ca
PZ		 1796 dep->res_trans_idx = 0;
1797
16e78db7 1798 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1799 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1800 dep->name);
1801 return;
1802 }
1803
1804 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1805 break;
1806 case DWC3_DEPEVT_XFERINPROGRESS:
16e78db7 1807 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1808 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1809 dep->name);
1810 return;
1811 }
1812
1813 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1814 break;
1815 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 1816 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1817 dwc3_gadget_start_isoc(dwc, dep, event);
1818 } else {
1819 int ret;
1820
1821 dev_vdbg(dwc->dev, "%s: reason %s\n",
40aa41fb
FB		 1822 dep->name, event->status &
1823 DEPEVT_STATUS_TRANSFER_ACTIVE
72246da4
FB		 1824 ? "Transfer Active"
1825 : "Transfer Not Active");
1826
1827 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1828 if (!ret || ret == -EBUSY)
1829 return;
1830
1831 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1832 dep->name);
1833 }
1834
879631aa
FB		 1835 break;
1836 case DWC3_DEPEVT_STREAMEVT:
16e78db7 1837 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 1838 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1839 dep->name);
1840 return;
1841 }
1842
1843 switch (event->status) {
1844 case DEPEVT_STREAMEVT_FOUND:
1845 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1846 event->parameters);
1847
1848 break;
1849 case DEPEVT_STREAMEVT_NOTFOUND:
1850 /* FALLTHROUGH */
1851 default:
1852 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1853 }
72246da4
FB		 1854 break;
1855 case DWC3_DEPEVT_RXTXFIFOEVT:
1856 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1857 break;
72246da4
FB		 1858 case DWC3_DEPEVT_EPCMDCMPLT:
1859 dwc3_ep_cmd_compl(dep, event);
1860 break;
1861 }
1862}
1863
1864static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1865{
1866 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1867 spin_unlock(&dwc->lock);
1868 dwc->gadget_driver->disconnect(&dwc->gadget);
1869 spin_lock(&dwc->lock);
1870 }
1871}
1872
1873static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1874{
1875 struct dwc3_ep *dep;
1876 struct dwc3_gadget_ep_cmd_params params;
1877 u32 cmd;
1878 int ret;
1879
1880 dep = dwc->eps[epnum];
1881
624407f9 1882 WARN_ON(!dep->res_trans_idx);
72246da4
FB		 1883 if (dep->res_trans_idx) {
1884 cmd = DWC3_DEPCMD_ENDTRANSFER;
1885 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1886 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1887 memset(&params, 0, sizeof(params));
1888 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1889 WARN_ON_ONCE(ret);
a1ae9be5 1890 dep->res_trans_idx = 0;
72246da4
FB		 1891 }
1892}
1893
1894static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1895{
1896 u32 epnum;
1897
1898 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1899 struct dwc3_ep *dep;
1900
1901 dep = dwc->eps[epnum];
1902 if (!(dep->flags & DWC3_EP_ENABLED))
1903 continue;
1904
624407f9 1905 dwc3_remove_requests(dwc, dep);
72246da4
FB		 1906 }
1907}
1908
1909static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1910{
1911 u32 epnum;
1912
1913 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1914 struct dwc3_ep *dep;
1915 struct dwc3_gadget_ep_cmd_params params;
1916 int ret;
1917
1918 dep = dwc->eps[epnum];
1919
1920 if (!(dep->flags & DWC3_EP_STALL))
1921 continue;
1922
1923 dep->flags &= ~DWC3_EP_STALL;
1924
1925 memset(&params, 0, sizeof(params));
1926 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1927 DWC3_DEPCMD_CLEARSTALL, &params);
1928 WARN_ON_ONCE(ret);
1929 }
1930}
1931
1932static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1933{
c4430a26
FB		 1934 int reg;
1935
72246da4 1936 dev_vdbg(dwc->dev, "%s\n", __func__);
72246da4
FB		 1937
1938 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1939 reg &= ~DWC3_DCTL_INITU1ENA;
1940 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1941
1942 reg &= ~DWC3_DCTL_INITU2ENA;
1943 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4
FB		 1944
1945 dwc3_stop_active_transfers(dwc);
1946 dwc3_disconnect_gadget(dwc);
b23c8439 1947 dwc->start_config_issued = false;
72246da4
FB		 1948
1949 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 1950 dwc->setup_packet_pending = false;
72246da4
FB		 1951}
1952
d7a46a8d 1953static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 1954{
1955 u32 reg;
1956
1957 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1958
d7a46a8d 1959 if (suspend)
72246da4 1960 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
d7a46a8d
PZ		 1961 else
1962 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
72246da4
FB		 1963
1964 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1965}
1966
d7a46a8d 1967static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 1968{
1969 u32 reg;
1970
1971 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1972
d7a46a8d 1973 if (suspend)
72246da4 1974 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
d7a46a8d
PZ		 1975 else
1976 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
72246da4
FB		 1977
1978 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1979}
1980
1981static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1982{
1983 u32 reg;
1984
1985 dev_vdbg(dwc->dev, "%s\n", __func__);
1986
df62df56
FB		 1987 /*
1988 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1989 * would cause a missing Disconnect Event if there's a
1990 * pending Setup Packet in the FIFO.
1991 *
1992 * There's no suggested workaround on the official Bug
1993 * report, which states that "unless the driver/application
1994 * is doing any special handling of a disconnect event,
1995 * there is no functional issue".
1996 *
1997 * Unfortunately, it turns out that we _do_ some special
1998 * handling of a disconnect event, namely complete all
1999 * pending transfers, notify gadget driver of the
2000 * disconnection, and so on.
2001 *
2002 * Our suggested workaround is to follow the Disconnect
2003 * Event steps here, instead, based on a setup_packet_pending
2004 * flag. Such flag gets set whenever we have a XferNotReady
2005 * event on EP0 and gets cleared on XferComplete for the
2006 * same endpoint.
2007 *
2008 * Refers to:
2009 *
2010 * STAR#9000466709: RTL: Device : Disconnect event not
2011 * generated if setup packet pending in FIFO
2012 */
2013 if (dwc->revision < DWC3_REVISION_188A) {
2014 if (dwc->setup_packet_pending)
2015 dwc3_gadget_disconnect_interrupt(dwc);
2016 }
2017
961906ed
FB		 2018 /* after reset -> Default State */
2019 dwc->dev_state = DWC3_DEFAULT_STATE;
2020
802fde98
PZ		 2021 /* Recent versions support automatic phy suspend and don't need this */
2022 if (dwc->revision < DWC3_REVISION_194A) {
2023 /* Resume PHYs */
2024 dwc3_gadget_usb2_phy_suspend(dwc, false);
2025 dwc3_gadget_usb3_phy_suspend(dwc, false);
2026 }
72246da4
FB		 2027
2028 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2029 dwc3_disconnect_gadget(dwc);
2030
2031 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2032 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
e6a3b5e2 2033 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
5cbe8c22 2034 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
72246da4 2035 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2036 dwc->test_mode = false;
72246da4
FB		 2037
2038 dwc3_stop_active_transfers(dwc);
2039 dwc3_clear_stall_all_ep(dwc);
b23c8439 2040 dwc->start_config_issued = false;
72246da4
FB		 2041
2042 /* Reset device address to zero */
2043 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2044 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2045 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2046}
2047
2048static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2049{
2050 u32 reg;
2051 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2052
2053 /*
2054 * We change the clock only at SS but I dunno why I would want to do
2055 * this. Maybe it becomes part of the power saving plan.
2056 */
2057
2058 if (speed != DWC3_DSTS_SUPERSPEED)
2059 return;
2060
2061 /*
2062 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2063 * each time on Connect Done.
2064 */
2065 if (!usb30_clock)
2066 return;
2067
2068 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2069 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2070 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2071}
2072
d7a46a8d 2073static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
72246da4
FB		 2074{
2075 switch (speed) {
2076 case USB_SPEED_SUPER:
d7a46a8d 2077 dwc3_gadget_usb2_phy_suspend(dwc, true);
72246da4
FB		 2078 break;
2079 case USB_SPEED_HIGH:
2080 case USB_SPEED_FULL:
2081 case USB_SPEED_LOW:
d7a46a8d 2082 dwc3_gadget_usb3_phy_suspend(dwc, true);
72246da4
FB		 2083 break;
2084 }
2085}
2086
2087static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2088{
2089 struct dwc3_gadget_ep_cmd_params params;
2090 struct dwc3_ep *dep;
2091 int ret;
2092 u32 reg;
2093 u8 speed;
2094
2095 dev_vdbg(dwc->dev, "%s\n", __func__);
2096
2097 memset(&params, 0x00, sizeof(params));
2098
72246da4
FB		 2099 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2100 speed = reg & DWC3_DSTS_CONNECTSPD;
2101 dwc->speed = speed;
2102
2103 dwc3_update_ram_clk_sel(dwc, speed);
2104
2105 switch (speed) {
2106 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2107 /*
2108 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2109 * would cause a missing USB3 Reset event.
2110 *
2111 * In such situations, we should force a USB3 Reset
2112 * event by calling our dwc3_gadget_reset_interrupt()
2113 * routine.
2114 *
2115 * Refers to:
2116 *
2117 * STAR#9000483510: RTL: SS : USB3 reset event may
2118 * not be generated always when the link enters poll
2119 */
2120 if (dwc->revision < DWC3_REVISION_190A)
2121 dwc3_gadget_reset_interrupt(dwc);
2122
72246da4
FB		 2123 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2124 dwc->gadget.ep0->maxpacket = 512;
2125 dwc->gadget.speed = USB_SPEED_SUPER;
2126 break;
2127 case DWC3_DCFG_HIGHSPEED:
2128 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2129 dwc->gadget.ep0->maxpacket = 64;
2130 dwc->gadget.speed = USB_SPEED_HIGH;
2131 break;
2132 case DWC3_DCFG_FULLSPEED2:
2133 case DWC3_DCFG_FULLSPEED1:
2134 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2135 dwc->gadget.ep0->maxpacket = 64;
2136 dwc->gadget.speed = USB_SPEED_FULL;
2137 break;
2138 case DWC3_DCFG_LOWSPEED:
2139 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2140 dwc->gadget.ep0->maxpacket = 8;
2141 dwc->gadget.speed = USB_SPEED_LOW;
2142 break;
2143 }
2144
802fde98
PZ		 2145 /* Recent versions support automatic phy suspend and don't need this */
2146 if (dwc->revision < DWC3_REVISION_194A) {
2147 /* Suspend unneeded PHY */
2148 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2149 }
72246da4
FB		 2150
2151 dep = dwc->eps[0];
c90bfaec 2152 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 2153 if (ret) {
2154 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2155 return;
2156 }
2157
2158 dep = dwc->eps[1];
c90bfaec 2159 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 2160 if (ret) {
2161 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2162 return;
2163 }
2164
2165 /*
2166 * Configure PHY via GUSB3PIPECTLn if required.
2167 *
2168 * Update GTXFIFOSIZn
2169 *
2170 * In both cases reset values should be sufficient.
2171 */
2172}
2173
2174static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2175{
2176 dev_vdbg(dwc->dev, "%s\n", __func__);
2177
2178 /*
2179 * TODO take core out of low power mode when that's
2180 * implemented.
2181 */
2182
2183 dwc->gadget_driver->resume(&dwc->gadget);
2184}
2185
2186static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2187 unsigned int evtinfo)
2188{
fae2b904
FB		 2189 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2190
2191 /*
2192 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2193 * on the link partner, the USB session might do multiple entry/exit
2194 * of low power states before a transfer takes place.
2195 *
2196 * Due to this problem, we might experience lower throughput. The
2197 * suggested workaround is to disable DCTL[12:9] bits if we're
2198 * transitioning from U1/U2 to U0 and enable those bits again
2199 * after a transfer completes and there are no pending transfers
2200 * on any of the enabled endpoints.
2201 *
2202 * This is the first half of that workaround.
2203 *
2204 * Refers to:
2205 *
2206 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2207 * core send LGO_Ux entering U0
2208 */
2209 if (dwc->revision < DWC3_REVISION_183A) {
2210 if (next == DWC3_LINK_STATE_U0) {
2211 u32 u1u2;
2212 u32 reg;
2213
2214 switch (dwc->link_state) {
2215 case DWC3_LINK_STATE_U1:
2216 case DWC3_LINK_STATE_U2:
2217 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2218 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2219 | DWC3_DCTL_ACCEPTU2ENA
2220 | DWC3_DCTL_INITU1ENA
2221 | DWC3_DCTL_ACCEPTU1ENA);
2222
2223 if (!dwc->u1u2)
2224 dwc->u1u2 = reg & u1u2;
2225
2226 reg &= ~u1u2;
2227
2228 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2229 break;
2230 default:
2231 /* do nothing */
2232 break;
2233 }
2234 }
2235 }
2236
2237 dwc->link_state = next;
019ac832
FB		 2238
2239 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 2240}
2241
2242static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2243 const struct dwc3_event_devt *event)
2244{
2245 switch (event->type) {
2246 case DWC3_DEVICE_EVENT_DISCONNECT:
2247 dwc3_gadget_disconnect_interrupt(dwc);
2248 break;
2249 case DWC3_DEVICE_EVENT_RESET:
2250 dwc3_gadget_reset_interrupt(dwc);
2251 break;
2252 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2253 dwc3_gadget_conndone_interrupt(dwc);
2254 break;
2255 case DWC3_DEVICE_EVENT_WAKEUP:
2256 dwc3_gadget_wakeup_interrupt(dwc);
2257 break;
2258 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2259 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2260 break;
2261 case DWC3_DEVICE_EVENT_EOPF:
2262 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2263 break;
2264 case DWC3_DEVICE_EVENT_SOF:
2265 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2266 break;
2267 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2268 dev_vdbg(dwc->dev, "Erratic Error\n");
2269 break;
2270 case DWC3_DEVICE_EVENT_CMD_CMPL:
2271 dev_vdbg(dwc->dev, "Command Complete\n");
2272 break;
2273 case DWC3_DEVICE_EVENT_OVERFLOW:
2274 dev_vdbg(dwc->dev, "Overflow\n");
2275 break;
2276 default:
2277 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2278 }
2279}
2280
2281static void dwc3_process_event_entry(struct dwc3 *dwc,
2282 const union dwc3_event *event)
2283{
2284 /* Endpoint IRQ, handle it and return early */
2285 if (event->type.is_devspec == 0) {
2286 /* depevt */
2287 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2288 }
2289
2290 switch (event->type.type) {
2291 case DWC3_EVENT_TYPE_DEV:
2292 dwc3_gadget_interrupt(dwc, &event->devt);
2293 break;
2294 /* REVISIT what to do with Carkit and I2C events ? */
2295 default:
2296 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2297 }
2298}
2299
2300static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2301{
2302 struct dwc3_event_buffer *evt;
2303 int left;
2304 u32 count;
2305
2306 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2307 count &= DWC3_GEVNTCOUNT_MASK;
2308 if (!count)
2309 return IRQ_NONE;
2310
2311 evt = dwc->ev_buffs[buf];
2312 left = count;
2313
2314 while (left > 0) {
2315 union dwc3_event event;
2316
d70d8442
FB		 2317 event.raw = *(u32 *) (evt->buf + evt->lpos);
2318
72246da4
FB		 2319 dwc3_process_event_entry(dwc, &event);
2320 /*
2321 * XXX we wrap around correctly to the next entry as almost all
2322 * entries are 4 bytes in size. There is one entry which has 12
2323 * bytes which is a regular entry followed by 8 bytes data. ATM
2324 * I don't know how things are organized if were get next to the
2325 * a boundary so I worry about that once we try to handle that.
2326 */
2327 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2328 left -= 4;
2329
2330 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2331 }
2332
2333 return IRQ_HANDLED;
2334}
2335
2336static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2337{
2338 struct dwc3 *dwc = _dwc;
2339 int i;
2340 irqreturn_t ret = IRQ_NONE;
2341
2342 spin_lock(&dwc->lock);
2343
9f622b2a 2344 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2345 irqreturn_t status;
2346
2347 status = dwc3_process_event_buf(dwc, i);
2348 if (status == IRQ_HANDLED)
2349 ret = status;
2350 }
2351
2352 spin_unlock(&dwc->lock);
2353
2354 return ret;
2355}
2356
2357/**
2358 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2359 * @dwc: pointer to our controller context structure
72246da4
FB		 2360 *
2361 * Returns 0 on success otherwise negative errno.
2362 */
2363int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2364{
2365 u32 reg;
2366 int ret;
2367 int irq;
2368
2369 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2370 &dwc->ctrl_req_addr, GFP_KERNEL);
2371 if (!dwc->ctrl_req) {
2372 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2373 ret = -ENOMEM;
2374 goto err0;
2375 }
2376
2377 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2378 &dwc->ep0_trb_addr, GFP_KERNEL);
2379 if (!dwc->ep0_trb) {
2380 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2381 ret = -ENOMEM;
2382 goto err1;
2383 }
2384
3ef35faf 2385 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4
FB		 2386 if (!dwc->setup_buf) {
2387 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2388 ret = -ENOMEM;
2389 goto err2;
2390 }
2391
5812b1c2 2392 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2393 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2394 GFP_KERNEL);
5812b1c2
FB		 2395 if (!dwc->ep0_bounce) {
2396 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2397 ret = -ENOMEM;
2398 goto err3;
2399 }
2400
72246da4
FB		 2401 dev_set_name(&dwc->gadget.dev, "gadget");
2402
2403 dwc->gadget.ops = &dwc3_gadget_ops;
d327ab5b 2404 dwc->gadget.max_speed = USB_SPEED_SUPER;
72246da4
FB		 2405 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2406 dwc->gadget.dev.parent = dwc->dev;
eeb720fb 2407 dwc->gadget.sg_supported = true;
72246da4
FB		 2408
2409 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2410
2411 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2412 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2413 dwc->gadget.dev.release = dwc3_gadget_release;
2414 dwc->gadget.name = "dwc3-gadget";
2415
2416 /*
2417 * REVISIT: Here we should clear all pending IRQs to be
2418 * sure we're starting from a well known location.
2419 */
2420
2421 ret = dwc3_gadget_init_endpoints(dwc);
2422 if (ret)
5812b1c2 2423 goto err4;
72246da4
FB		 2424
2425 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2426
2427 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2428 "dwc3", dwc);
2429 if (ret) {
2430 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2431 irq, ret);
5812b1c2 2432 goto err5;
72246da4
FB		 2433 }
2434
e6a3b5e2
SAS		 2435 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2436 reg |= DWC3_DCFG_LPM_CAP;
2437 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2438
72246da4
FB		 2439 /* Enable all but Start and End of Frame IRQs */
2440 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2441 DWC3_DEVTEN_EVNTOVERFLOWEN |
2442 DWC3_DEVTEN_CMDCMPLTEN |
2443 DWC3_DEVTEN_ERRTICERREN |
2444 DWC3_DEVTEN_WKUPEVTEN |
2445 DWC3_DEVTEN_ULSTCNGEN |
2446 DWC3_DEVTEN_CONNECTDONEEN |
2447 DWC3_DEVTEN_USBRSTEN |
2448 DWC3_DEVTEN_DISCONNEVTEN);
2449 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2450
802fde98
PZ		 2451 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2452 if (dwc->revision >= DWC3_REVISION_194A) {
2453 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2454 reg |= DWC3_DCFG_LPM_CAP;
2455 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2456
2457 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2458 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2459
2460 /* TODO: This should be configurable */
2461 reg |= DWC3_DCTL_HIRD_THRES(31);
2462
2463 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2464
2465 dwc3_gadget_usb2_phy_suspend(dwc, true);
2466 dwc3_gadget_usb3_phy_suspend(dwc, true);
2467 }
2468
72246da4
FB		 2469 ret = device_register(&dwc->gadget.dev);
2470 if (ret) {
2471 dev_err(dwc->dev, "failed to register gadget device\n");
2472 put_device(&dwc->gadget.dev);
5812b1c2 2473 goto err6;
72246da4
FB		 2474 }
2475
2476 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2477 if (ret) {
2478 dev_err(dwc->dev, "failed to register udc\n");
5812b1c2 2479 goto err7;
72246da4
FB		 2480 }
2481
2482 return 0;
2483
5812b1c2 2484err7:
72246da4
FB		 2485 device_unregister(&dwc->gadget.dev);
2486
5812b1c2 2487err6:
72246da4
FB		 2488 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2489 free_irq(irq, dwc);
2490
5812b1c2 2491err5:
72246da4
FB		 2492 dwc3_gadget_free_endpoints(dwc);
2493
5812b1c2 2494err4:
3ef35faf
FB		 2495 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2496 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2497
72246da4 2498err3:
0fc9a1be 2499 kfree(dwc->setup_buf);
72246da4
FB		 2500
2501err2:
2502 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2503 dwc->ep0_trb, dwc->ep0_trb_addr);
2504
2505err1:
2506 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2507 dwc->ctrl_req, dwc->ctrl_req_addr);
2508
2509err0:
2510 return ret;
2511}
2512
2513void dwc3_gadget_exit(struct dwc3 *dwc)
2514{
2515 int irq;
72246da4
FB		 2516
2517 usb_del_gadget_udc(&dwc->gadget);
2518 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2519
2520 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2521 free_irq(irq, dwc);
2522
72246da4
FB		 2523 dwc3_gadget_free_endpoints(dwc);
2524
3ef35faf
FB		 2525 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2526 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2527
0fc9a1be 2528 kfree(dwc->setup_buf);
72246da4
FB		 2529
2530 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2531 dwc->ep0_trb, dwc->ep0_trb_addr);
2532
2533 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2534 dwc->ctrl_req, dwc->ctrl_req_addr);
2535
2536 device_unregister(&dwc->gadget.dev);
2537}
Linux kernel - Deliverables
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