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usb: dwc3: omap: fix ordering for runtime pm calls
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "core.h"
34#include "gadget.h"
35#include "io.h"
36
04a9bfcd
FB		 37/**
38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
39 * @dwc: pointer to our context structure
40 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
41 *
42 * Caller should take care of locking. This function will
43 * return 0 on success or -EINVAL if wrong Test Selector
44 * is passed
45 */
46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
47{
48 u32 reg;
49
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
52
53 switch (mode) {
54 case TEST_J:
55 case TEST_K:
56 case TEST_SE0_NAK:
57 case TEST_PACKET:
58 case TEST_FORCE_EN:
59 reg |= mode << 1;
60 break;
61 default:
62 return -EINVAL;
63 }
64
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66
67 return 0;
68}
69
911f1f88
PZ		 70/**
71 * dwc3_gadget_get_link_state - Gets current state of USB Link
72 * @dwc: pointer to our context structure
73 *
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
76 */
77int dwc3_gadget_get_link_state(struct dwc3 *dwc)
78{
79 u32 reg;
80
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
82
83 return DWC3_DSTS_USBLNKST(reg);
84}
85
8598bde7
FB		 86/**
87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
90 *
91 * Caller should take care of locking. This function will
aee63e3c 92 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 93 */
94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95{
aee63e3c 96 int retries = 10000;
8598bde7
FB		 97 u32 reg;
98
802fde98
PZ		 99 /*
100 * Wait until device controller is ready. Only applies to 1.94a and
101 * later RTL.
102 */
103 if (dwc->revision >= DWC3_REVISION_194A) {
104 while (--retries) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
107 udelay(5);
108 else
109 break;
110 }
111
112 if (retries <= 0)
113 return -ETIMEDOUT;
114 }
115
8598bde7
FB		 116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
118
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122
802fde98
PZ		 123 /*
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
126 */
127 if (dwc->revision >= DWC3_REVISION_194A)
128 return 0;
129
8598bde7 130 /* wait for a change in DSTS */
aed430e5 131 retries = 10000;
8598bde7
FB		 132 while (--retries) {
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
134
8598bde7
FB		 135 if (DWC3_DSTS_USBLNKST(reg) == state)
136 return 0;
137
aee63e3c 138 udelay(5);
8598bde7
FB		 139 }
140
141 dev_vdbg(dwc->dev, "link state change request timed out\n");
142
143 return -ETIMEDOUT;
144}
145
457e84b6
FB		 146/**
147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
148 * @dwc: pointer to our context structure
149 *
150 * This function will a best effort FIFO allocation in order
151 * to improve FIFO usage and throughput, while still allowing
152 * us to enable as many endpoints as possible.
153 *
154 * Keep in mind that this operation will be highly dependent
155 * on the configured size for RAM1 - which contains TxFifo -,
156 * the amount of endpoints enabled on coreConsultant tool, and
157 * the width of the Master Bus.
158 *
159 * In the ideal world, we would always be able to satisfy the
160 * following equation:
161 *
162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
164 *
165 * Unfortunately, due to many variables that's not always the case.
166 */
167int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
168{
169 int last_fifo_depth = 0;
170 int ram1_depth;
171 int fifo_size;
172 int mdwidth;
173 int num;
174
175 if (!dwc->needs_fifo_resize)
176 return 0;
177
178 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
179 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
180
181 /* MDWIDTH is represented in bits, we need it in bytes */
182 mdwidth >>= 3;
183
184 /*
185 * FIXME For now we will only allocate 1 wMaxPacketSize space
186 * for each enabled endpoint, later patches will come to
187 * improve this algorithm so that we better use the internal
188 * FIFO space
189 */
32702e96
JP		 190 for (num = 0; num < dwc->num_in_eps; num++) {
191 /* bit0 indicates direction; 1 means IN ep */
192 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
2e81c36a 193 int mult = 1;
457e84b6
FB		 194 int tmp;
195
457e84b6
FB		 196 if (!(dep->flags & DWC3_EP_ENABLED))
197 continue;
198
16e78db7
IS		 199 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
200 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
2e81c36a
FB		 201 mult = 3;
202
203 /*
204 * REVISIT: the following assumes we will always have enough
205 * space available on the FIFO RAM for all possible use cases.
206 * Make sure that's true somehow and change FIFO allocation
207 * accordingly.
208 *
209 * If we have Bulk or Isochronous endpoints, we want
210 * them to be able to be very, very fast. So we're giving
211 * those endpoints a fifo_size which is enough for 3 full
212 * packets
213 */
214 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
457e84b6
FB		 215 tmp += mdwidth;
216
217 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
2e81c36a 218
457e84b6
FB		 219 fifo_size |= (last_fifo_depth << 16);
220
221 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
222 dep->name, last_fifo_depth, fifo_size & 0xffff);
223
32702e96 224 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
457e84b6
FB		 225
226 last_fifo_depth += (fifo_size & 0xffff);
227 }
228
229 return 0;
230}
231
72246da4
FB		 232void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
233 int status)
234{
235 struct dwc3 *dwc = dep->dwc;
e5ba5ec8 236 int i;
72246da4
FB		 237
238 if (req->queued) {
e5ba5ec8
PA		 239 i = 0;
240 do {
eeb720fb 241 dep->busy_slot++;
e5ba5ec8
PA		 242 /*
243 * Skip LINK TRB. We can't use req->trb and check for
244 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
245 * just completed (not the LINK TRB).
246 */
247 if (((dep->busy_slot & DWC3_TRB_MASK) ==
248 DWC3_TRB_NUM- 1) &&
16e78db7 249 usb_endpoint_xfer_isoc(dep->endpoint.desc))
e5ba5ec8
PA		 250 dep->busy_slot++;
251 } while(++i < req->request.num_mapped_sgs);
c9fda7d6 252 req->queued = false;
72246da4
FB		 253 }
254 list_del(&req->list);
eeb720fb 255 req->trb = NULL;
72246da4
FB		 256
257 if (req->request.status == -EINPROGRESS)
258 req->request.status = status;
259
0416e494
PA		 260 if (dwc->ep0_bounced && dep->number == 0)
261 dwc->ep0_bounced = false;
262 else
263 usb_gadget_unmap_request(&dwc->gadget, &req->request,
264 req->direction);
72246da4
FB		 265
266 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
267 req, dep->name, req->request.actual,
268 req->request.length, status);
269
270 spin_unlock(&dwc->lock);
0fc9a1be 271 req->request.complete(&dep->endpoint, &req->request);
72246da4
FB		 272 spin_lock(&dwc->lock);
273}
274
275static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
276{
277 switch (cmd) {
278 case DWC3_DEPCMD_DEPSTARTCFG:
279 return "Start New Configuration";
280 case DWC3_DEPCMD_ENDTRANSFER:
281 return "End Transfer";
282 case DWC3_DEPCMD_UPDATETRANSFER:
283 return "Update Transfer";
284 case DWC3_DEPCMD_STARTTRANSFER:
285 return "Start Transfer";
286 case DWC3_DEPCMD_CLEARSTALL:
287 return "Clear Stall";
288 case DWC3_DEPCMD_SETSTALL:
289 return "Set Stall";
802fde98
PZ		 290 case DWC3_DEPCMD_GETEPSTATE:
291 return "Get Endpoint State";
72246da4
FB		 292 case DWC3_DEPCMD_SETTRANSFRESOURCE:
293 return "Set Endpoint Transfer Resource";
294 case DWC3_DEPCMD_SETEPCONFIG:
295 return "Set Endpoint Configuration";
296 default:
297 return "UNKNOWN command";
298 }
299}
300
427c3df6
FB		 301static const char *dwc3_gadget_generic_cmd_string(u8 cmd)
302{
303 switch (cmd) {
304 case DWC3_DGCMD_SET_LMP:
305 return "Set LMP";
306 case DWC3_DGCMD_SET_PERIODIC_PAR:
307 return "Set Periodic Parameters";
308 case DWC3_DGCMD_XMIT_FUNCTION:
309 return "Transmit Function Wake Device Notification";
310 case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO:
311 return "Set Scratchpad Buffer Array Address Lo";
312 case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI:
313 return "Set Scratchpad Buffer Array Address Hi";
314 case DWC3_DGCMD_SELECTED_FIFO_FLUSH:
315 return "Selected FIFO Flush";
316 case DWC3_DGCMD_ALL_FIFO_FLUSH:
317 return "All FIFO Flush";
318 case DWC3_DGCMD_SET_ENDPOINT_NRDY:
319 return "Set Endpoint NRDY";
320 case DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK:
321 return "Run SoC Bus Loopback Test";
322 default:
323 return "UNKNOWN";
324 }
325}
326
e57ebc1d
FB		 327static const char *dwc3_gadget_link_string(enum dwc3_link_state link_state)
328{
329 switch (link_state) {
330 case DWC3_LINK_STATE_U0:
331 return "U0";
332 case DWC3_LINK_STATE_U1:
333 return "U1";
334 case DWC3_LINK_STATE_U2:
335 return "U2";
336 case DWC3_LINK_STATE_U3:
337 return "U3";
338 case DWC3_LINK_STATE_SS_DIS:
339 return "SS.Disabled";
340 case DWC3_LINK_STATE_RX_DET:
341 return "RX.Detect";
342 case DWC3_LINK_STATE_SS_INACT:
343 return "SS.Inactive";
344 case DWC3_LINK_STATE_POLL:
345 return "Polling";
346 case DWC3_LINK_STATE_RECOV:
347 return "Recovery";
348 case DWC3_LINK_STATE_HRESET:
349 return "Hot Reset";
350 case DWC3_LINK_STATE_CMPLY:
351 return "Compliance";
352 case DWC3_LINK_STATE_LPBK:
353 return "Loopback";
354 case DWC3_LINK_STATE_RESET:
355 return "Reset";
356 case DWC3_LINK_STATE_RESUME:
357 return "Resume";
358 default:
359 return "UNKNOWN link state\n";
360 }
361}
362
b09bb642
FB		 363int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
364{
365 u32 timeout = 500;
366 u32 reg;
367
427c3df6
FB		 368 dev_vdbg(dwc->dev, "generic cmd '%s' [%d] param %08x\n",
369 dwc3_gadget_generic_cmd_string(cmd), cmd, param);
370
b09bb642
FB		 371 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
372 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
373
374 do {
375 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
376 if (!(reg & DWC3_DGCMD_CMDACT)) {
377 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
378 DWC3_DGCMD_STATUS(reg));
379 return 0;
380 }
381
382 /*
383 * We can't sleep here, because it's also called from
384 * interrupt context.
385 */
386 timeout--;
387 if (!timeout)
388 return -ETIMEDOUT;
389 udelay(1);
390 } while (1);
391}
392
72246da4
FB		 393int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
394 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
395{
396 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 397 u32 timeout = 500;
72246da4
FB		 398 u32 reg;
399
40cc57c7 400 dev_vdbg(dwc->dev, "%s: cmd '%s' [%d] params %08x %08x %08x\n",
72246da4 401 dep->name,
40cc57c7 402 dwc3_gadget_ep_cmd_string(cmd), cmd, params->param0,
dc1c70a7 403 params->param1, params->param2);
72246da4 404
dc1c70a7
FB		 405 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
406 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
407 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 408
409 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
410 do {
411 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
412 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 413 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
414 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 415 return 0;
416 }
417
418 /*
72246da4
FB		 419 * We can't sleep here, because it is also called from
420 * interrupt context.
421 */
422 timeout--;
423 if (!timeout)
424 return -ETIMEDOUT;
425
61d58242 426 udelay(1);
72246da4
FB		 427 } while (1);
428}
429
430static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 431 struct dwc3_trb *trb)
72246da4 432{
c439ef87 433 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 434
435 return dep->trb_pool_dma + offset;
436}
437
438static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
439{
440 struct dwc3 *dwc = dep->dwc;
441
442 if (dep->trb_pool)
443 return 0;
444
445 if (dep->number == 0 || dep->number == 1)
446 return 0;
447
448 dep->trb_pool = dma_alloc_coherent(dwc->dev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
453 dep->name);
454 return -ENOMEM;
455 }
456
457 return 0;
458}
459
460static void dwc3_free_trb_pool(struct dwc3_ep *dep)
461{
462 struct dwc3 *dwc = dep->dwc;
463
464 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
466
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
469}
470
471static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
472{
473 struct dwc3_gadget_ep_cmd_params params;
474 u32 cmd;
475
476 memset(&params, 0x00, sizeof(params));
477
478 if (dep->number != 1) {
479 cmd = DWC3_DEPCMD_DEPSTARTCFG;
480 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 481 if (dep->number > 1) {
482 if (dwc->start_config_issued)
483 return 0;
484 dwc->start_config_issued = true;
72246da4 485 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 486 }
72246da4
FB		 487
488 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
489 }
490
491 return 0;
492}
493
494static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec 495 const struct usb_endpoint_descriptor *desc,
4b345c9a 496 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 497 bool ignore, bool restore)
72246da4
FB		 498{
499 struct dwc3_gadget_ep_cmd_params params;
500
501 memset(&params, 0x00, sizeof(params));
502
dc1c70a7 503 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 504 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
505
506 /* Burst size is only needed in SuperSpeed mode */
507 if (dwc->gadget.speed == USB_SPEED_SUPER) {
508 u32 burst = dep->endpoint.maxburst - 1;
509
510 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
511 }
72246da4 512
4b345c9a
FB		 513 if (ignore)
514 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
515
265b70a7
PZ		 516 if (restore) {
517 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
518 params.param2 |= dep->saved_state;
519 }
520
dc1c70a7
FB		 521 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
522 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 523
18b7ede5 524 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 525 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
526 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 527 dep->stream_capable = true;
528 }
529
72246da4 530 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 531 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 532
533 /*
534 * We are doing 1:1 mapping for endpoints, meaning
535 * Physical Endpoints 2 maps to Logical Endpoint 2 and
536 * so on. We consider the direction bit as part of the physical
537 * endpoint number. So USB endpoint 0x81 is 0x03.
538 */
dc1c70a7 539 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 540
541 /*
542 * We must use the lower 16 TX FIFOs even though
543 * HW might have more
544 */
545 if (dep->direction)
dc1c70a7 546 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 547
548 if (desc->bInterval) {
dc1c70a7 549 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 550 dep->interval = 1 << (desc->bInterval - 1);
551 }
552
553 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
554 DWC3_DEPCMD_SETEPCONFIG, &params);
555}
556
557static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
558{
559 struct dwc3_gadget_ep_cmd_params params;
560
561 memset(&params, 0x00, sizeof(params));
562
dc1c70a7 563 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 564
565 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
566 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
567}
568
569/**
570 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
571 * @dep: endpoint to be initialized
572 * @desc: USB Endpoint Descriptor
573 *
574 * Caller should take care of locking
575 */
576static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec 577 const struct usb_endpoint_descriptor *desc,
4b345c9a 578 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 579 bool ignore, bool restore)
72246da4
FB		 580{
581 struct dwc3 *dwc = dep->dwc;
582 u32 reg;
b09e99ee 583 int ret;
72246da4 584
ff62d6b6
FB		 585 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
586
72246da4
FB		 587 if (!(dep->flags & DWC3_EP_ENABLED)) {
588 ret = dwc3_gadget_start_config(dwc, dep);
589 if (ret)
590 return ret;
591 }
592
265b70a7
PZ		 593 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
594 restore);
72246da4
FB		 595 if (ret)
596 return ret;
597
598 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 599 struct dwc3_trb *trb_st_hw;
600 struct dwc3_trb *trb_link;
72246da4
FB		 601
602 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
603 if (ret)
604 return ret;
605
16e78db7 606 dep->endpoint.desc = desc;
c90bfaec 607 dep->comp_desc = comp_desc;
72246da4
FB		 608 dep->type = usb_endpoint_type(desc);
609 dep->flags |= DWC3_EP_ENABLED;
610
611 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
612 reg |= DWC3_DALEPENA_EP(dep->number);
613 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
614
615 if (!usb_endpoint_xfer_isoc(desc))
616 return 0;
617
618 memset(&trb_link, 0, sizeof(trb_link));
619
1d046793 620 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 621 trb_st_hw = &dep->trb_pool[0];
622
f6bafc6a 623 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
72246da4 624
f6bafc6a
FB		 625 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
626 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
627 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
628 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 629 }
630
631 return 0;
632}
633
b992e681 634static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 635static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 636{
637 struct dwc3_request *req;
638
ea53b882 639 if (!list_empty(&dep->req_queued)) {
b992e681 640 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 641
57911504 642 /* - giveback all requests to gadget driver */
1591633e
PA		 643 while (!list_empty(&dep->req_queued)) {
644 req = next_request(&dep->req_queued);
645
646 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
647 }
ea53b882
FB		 648 }
649
72246da4
FB		 650 while (!list_empty(&dep->request_list)) {
651 req = next_request(&dep->request_list);
652
624407f9 653 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 654 }
72246da4
FB		 655}
656
657/**
658 * __dwc3_gadget_ep_disable - Disables a HW endpoint
659 * @dep: the endpoint to disable
660 *
624407f9
SAS		 661 * This function also removes requests which are currently processed ny the
662 * hardware and those which are not yet scheduled.
663 * Caller should take care of locking.
72246da4 664 */
72246da4
FB		 665static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
666{
667 struct dwc3 *dwc = dep->dwc;
668 u32 reg;
669
624407f9 670 dwc3_remove_requests(dwc, dep);
72246da4 671
687ef981
FB		 672 /* make sure HW endpoint isn't stalled */
673 if (dep->flags & DWC3_EP_STALL)
674 __dwc3_gadget_ep_set_halt(dep, 0);
675
72246da4
FB		 676 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
677 reg &= ~DWC3_DALEPENA_EP(dep->number);
678 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
679
879631aa 680 dep->stream_capable = false;
f9c56cdd 681 dep->endpoint.desc = NULL;
c90bfaec 682 dep->comp_desc = NULL;
72246da4 683 dep->type = 0;
879631aa 684 dep->flags = 0;
72246da4
FB		 685
686 return 0;
687}
688
689/* -------------------------------------------------------------------------- */
690
691static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
692 const struct usb_endpoint_descriptor *desc)
693{
694 return -EINVAL;
695}
696
697static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
698{
699 return -EINVAL;
700}
701
702/* -------------------------------------------------------------------------- */
703
704static int dwc3_gadget_ep_enable(struct usb_ep *ep,
705 const struct usb_endpoint_descriptor *desc)
706{
707 struct dwc3_ep *dep;
708 struct dwc3 *dwc;
709 unsigned long flags;
710 int ret;
711
712 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
713 pr_debug("dwc3: invalid parameters\n");
714 return -EINVAL;
715 }
716
717 if (!desc->wMaxPacketSize) {
718 pr_debug("dwc3: missing wMaxPacketSize\n");
719 return -EINVAL;
720 }
721
722 dep = to_dwc3_ep(ep);
723 dwc = dep->dwc;
724
c6f83f38
FB		 725 if (dep->flags & DWC3_EP_ENABLED) {
726 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
727 dep->name);
728 return 0;
729 }
730
72246da4
FB		 731 switch (usb_endpoint_type(desc)) {
732 case USB_ENDPOINT_XFER_CONTROL:
27a78d6a 733 strlcat(dep->name, "-control", sizeof(dep->name));
72246da4
FB		 734 break;
735 case USB_ENDPOINT_XFER_ISOC:
27a78d6a 736 strlcat(dep->name, "-isoc", sizeof(dep->name));
72246da4
FB		 737 break;
738 case USB_ENDPOINT_XFER_BULK:
27a78d6a 739 strlcat(dep->name, "-bulk", sizeof(dep->name));
72246da4
FB		 740 break;
741 case USB_ENDPOINT_XFER_INT:
27a78d6a 742 strlcat(dep->name, "-int", sizeof(dep->name));
72246da4
FB		 743 break;
744 default:
745 dev_err(dwc->dev, "invalid endpoint transfer type\n");
746 }
747
72246da4 748 spin_lock_irqsave(&dwc->lock, flags);
265b70a7 749 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
72246da4
FB		 750 spin_unlock_irqrestore(&dwc->lock, flags);
751
752 return ret;
753}
754
755static int dwc3_gadget_ep_disable(struct usb_ep *ep)
756{
757 struct dwc3_ep *dep;
758 struct dwc3 *dwc;
759 unsigned long flags;
760 int ret;
761
762 if (!ep) {
763 pr_debug("dwc3: invalid parameters\n");
764 return -EINVAL;
765 }
766
767 dep = to_dwc3_ep(ep);
768 dwc = dep->dwc;
769
770 if (!(dep->flags & DWC3_EP_ENABLED)) {
771 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
772 dep->name);
773 return 0;
774 }
775
776 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
777 dep->number >> 1,
778 (dep->number & 1) ? "in" : "out");
779
780 spin_lock_irqsave(&dwc->lock, flags);
781 ret = __dwc3_gadget_ep_disable(dep);
782 spin_unlock_irqrestore(&dwc->lock, flags);
783
784 return ret;
785}
786
787static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
788 gfp_t gfp_flags)
789{
790 struct dwc3_request *req;
791 struct dwc3_ep *dep = to_dwc3_ep(ep);
792 struct dwc3 *dwc = dep->dwc;
793
794 req = kzalloc(sizeof(*req), gfp_flags);
795 if (!req) {
796 dev_err(dwc->dev, "not enough memory\n");
797 return NULL;
798 }
799
800 req->epnum = dep->number;
801 req->dep = dep;
72246da4
FB		 802
803 return &req->request;
804}
805
806static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
807 struct usb_request *request)
808{
809 struct dwc3_request *req = to_dwc3_request(request);
810
811 kfree(req);
812}
813
c71fc37c
FB		 814/**
815 * dwc3_prepare_one_trb - setup one TRB from one request
816 * @dep: endpoint for which this request is prepared
817 * @req: dwc3_request pointer
818 */
68e823e2 819static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 820 struct dwc3_request *req, dma_addr_t dma,
e5ba5ec8 821 unsigned length, unsigned last, unsigned chain, unsigned node)
c71fc37c 822{
eeb720fb 823 struct dwc3 *dwc = dep->dwc;
f6bafc6a 824 struct dwc3_trb *trb;
c71fc37c 825
eeb720fb
FB		 826 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
827 dep->name, req, (unsigned long long) dma,
828 length, last ? " last" : "",
829 chain ? " chain" : "");
830
915e202a
PA		 831
832 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c 833
eeb720fb
FB		 834 if (!req->trb) {
835 dwc3_gadget_move_request_queued(req);
f6bafc6a
FB		 836 req->trb = trb;
837 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
e5ba5ec8 838 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
eeb720fb 839 }
c71fc37c 840
e5ba5ec8 841 dep->free_slot++;
5cd8c48d
ZJC		 842 /* Skip the LINK-TRB on ISOC */
843 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
844 usb_endpoint_xfer_isoc(dep->endpoint.desc))
845 dep->free_slot++;
e5ba5ec8 846
f6bafc6a
FB		 847 trb->size = DWC3_TRB_SIZE_LENGTH(length);
848 trb->bpl = lower_32_bits(dma);
849 trb->bph = upper_32_bits(dma);
c71fc37c 850
16e78db7 851 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 852 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 853 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 854 break;
855
856 case USB_ENDPOINT_XFER_ISOC:
e5ba5ec8
PA		 857 if (!node)
858 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
859 else
860 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
c71fc37c
FB		 861 break;
862
863 case USB_ENDPOINT_XFER_BULK:
864 case USB_ENDPOINT_XFER_INT:
f6bafc6a 865 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 866 break;
867 default:
868 /*
869 * This is only possible with faulty memory because we
870 * checked it already :)
871 */
872 BUG();
873 }
874
f3af3651
FB		 875 if (!req->request.no_interrupt && !chain)
876 trb->ctrl |= DWC3_TRB_CTRL_IOC;
877
16e78db7 878 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
f6bafc6a
FB		 879 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
880 trb->ctrl |= DWC3_TRB_CTRL_CSP;
e5ba5ec8
PA		 881 } else if (last) {
882 trb->ctrl |= DWC3_TRB_CTRL_LST;
f6bafc6a 883 }
c71fc37c 884
e5ba5ec8
PA		 885 if (chain)
886 trb->ctrl |= DWC3_TRB_CTRL_CHN;
887
16e78db7 888 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 889 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 890
f6bafc6a 891 trb->ctrl |= DWC3_TRB_CTRL_HWO;
c71fc37c
FB		 892}
893
72246da4
FB		 894/*
895 * dwc3_prepare_trbs - setup TRBs from requests
896 * @dep: endpoint for which requests are being prepared
897 * @starting: true if the endpoint is idle and no requests are queued.
898 *
1d046793
PZ		 899 * The function goes through the requests list and sets up TRBs for the
900 * transfers. The function returns once there are no more TRBs available or
901 * it runs out of requests.
72246da4 902 */
68e823e2 903static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 904{
68e823e2 905 struct dwc3_request *req, *n;
72246da4 906 u32 trbs_left;
8d62cd65 907 u32 max;
c71fc37c 908 unsigned int last_one = 0;
72246da4
FB		 909
910 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
911
912 /* the first request must not be queued */
913 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 914
8d62cd65 915 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 916 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 917 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
918 if (trbs_left > max)
919 trbs_left = max;
920 }
921
72246da4 922 /*
1d046793
PZ		 923 * If busy & slot are equal than it is either full or empty. If we are
924 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 925 * full and don't do anything
926 */
927 if (!trbs_left) {
928 if (!starting)
68e823e2 929 return;
72246da4
FB		 930 trbs_left = DWC3_TRB_NUM;
931 /*
932 * In case we start from scratch, we queue the ISOC requests
933 * starting from slot 1. This is done because we use ring
934 * buffer and have no LST bit to stop us. Instead, we place
1d046793 935 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 936 * after the first request so we start at slot 1 and have
937 * 7 requests proceed before we hit the first IOC.
938 * Other transfer types don't use the ring buffer and are
939 * processed from the first TRB until the last one. Since we
940 * don't wrap around we have to start at the beginning.
941 */
16e78db7 942 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 943 dep->busy_slot = 1;
944 dep->free_slot = 1;
945 } else {
946 dep->busy_slot = 0;
947 dep->free_slot = 0;
948 }
949 }
950
951 /* The last TRB is a link TRB, not used for xfer */
16e78db7 952 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 953 return;
72246da4
FB		 954
955 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 956 unsigned length;
957 dma_addr_t dma;
e5ba5ec8 958 last_one = false;
72246da4 959
eeb720fb
FB		 960 if (req->request.num_mapped_sgs > 0) {
961 struct usb_request *request = &req->request;
962 struct scatterlist *sg = request->sg;
963 struct scatterlist *s;
964 int i;
72246da4 965
eeb720fb
FB		 966 for_each_sg(sg, s, request->num_mapped_sgs, i) {
967 unsigned chain = true;
72246da4 968
eeb720fb
FB		 969 length = sg_dma_len(s);
970 dma = sg_dma_address(s);
72246da4 971
1d046793
PZ		 972 if (i == (request->num_mapped_sgs - 1) ||
973 sg_is_last(s)) {
e5ba5ec8
PA		 974 if (list_is_last(&req->list,
975 &dep->request_list))
976 last_one = true;
eeb720fb
FB		 977 chain = false;
978 }
72246da4 979
eeb720fb
FB		 980 trbs_left--;
981 if (!trbs_left)
982 last_one = true;
72246da4 983
eeb720fb
FB		 984 if (last_one)
985 chain = false;
72246da4 986
eeb720fb 987 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 988 last_one, chain, i);
72246da4 989
eeb720fb
FB		 990 if (last_one)
991 break;
992 }
72246da4 993 } else {
eeb720fb
FB		 994 dma = req->request.dma;
995 length = req->request.length;
996 trbs_left--;
72246da4 997
eeb720fb
FB		 998 if (!trbs_left)
999 last_one = 1;
879631aa 1000
eeb720fb
FB		 1001 /* Is this the last request? */
1002 if (list_is_last(&req->list, &dep->request_list))
1003 last_one = 1;
72246da4 1004
eeb720fb 1005 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 1006 last_one, false, 0);
72246da4 1007
eeb720fb
FB		 1008 if (last_one)
1009 break;
72246da4 1010 }
72246da4 1011 }
72246da4
FB		 1012}
1013
1014static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
1015 int start_new)
1016{
1017 struct dwc3_gadget_ep_cmd_params params;
1018 struct dwc3_request *req;
1019 struct dwc3 *dwc = dep->dwc;
1020 int ret;
1021 u32 cmd;
1022
1023 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
1024 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
1025 return -EBUSY;
1026 }
1027 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1028
1029 /*
1030 * If we are getting here after a short-out-packet we don't enqueue any
1031 * new requests as we try to set the IOC bit only on the last request.
1032 */
1033 if (start_new) {
1034 if (list_empty(&dep->req_queued))
1035 dwc3_prepare_trbs(dep, start_new);
1036
1037 /* req points to the first request which will be sent */
1038 req = next_request(&dep->req_queued);
1039 } else {
68e823e2
FB		 1040 dwc3_prepare_trbs(dep, start_new);
1041
72246da4 1042 /*
1d046793 1043 * req points to the first request where HWO changed from 0 to 1
72246da4 1044 */
68e823e2 1045 req = next_request(&dep->req_queued);
72246da4
FB		 1046 }
1047 if (!req) {
1048 dep->flags |= DWC3_EP_PENDING_REQUEST;
1049 return 0;
1050 }
1051
1052 memset(&params, 0, sizeof(params));
72246da4 1053
1877d6c9
PA		 1054 if (start_new) {
1055 params.param0 = upper_32_bits(req->trb_dma);
1056 params.param1 = lower_32_bits(req->trb_dma);
72246da4 1057 cmd = DWC3_DEPCMD_STARTTRANSFER;
1877d6c9 1058 } else {
72246da4 1059 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1877d6c9 1060 }
72246da4
FB		 1061
1062 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1063 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1064 if (ret < 0) {
1065 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1066
1067 /*
1068 * FIXME we need to iterate over the list of requests
1069 * here and stop, unmap, free and del each of the linked
1d046793 1070 * requests instead of what we do now.
72246da4 1071 */
0fc9a1be
FB		 1072 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1073 req->direction);
72246da4
FB		 1074 list_del(&req->list);
1075 return ret;
1076 }
1077
1078 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1079
f898ae09 1080 if (start_new) {
b4996a86 1081 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
f898ae09 1082 dep->number);
b4996a86 1083 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1084 }
25b8ff68 1085
72246da4
FB		 1086 return 0;
1087}
1088
d6d6ec7b
PA		 1089static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1090 struct dwc3_ep *dep, u32 cur_uf)
1091{
1092 u32 uf;
1093
1094 if (list_empty(&dep->request_list)) {
1095 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1096 dep->name);
f4a53c55 1097 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1098 return;
1099 }
1100
1101 /* 4 micro frames in the future */
1102 uf = cur_uf + dep->interval * 4;
1103
1104 __dwc3_gadget_kick_transfer(dep, uf, 1);
1105}
1106
1107static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1108 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1109{
1110 u32 cur_uf, mask;
1111
1112 mask = ~(dep->interval - 1);
1113 cur_uf = event->parameters & mask;
1114
1115 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1116}
1117
72246da4
FB		 1118static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1119{
0fc9a1be
FB		 1120 struct dwc3 *dwc = dep->dwc;
1121 int ret;
1122
72246da4
FB		 1123 req->request.actual = 0;
1124 req->request.status = -EINPROGRESS;
1125 req->direction = dep->direction;
1126 req->epnum = dep->number;
1127
1128 /*
1129 * We only add to our list of requests now and
1130 * start consuming the list once we get XferNotReady
1131 * IRQ.
1132 *
1133 * That way, we avoid doing anything that we don't need
1134 * to do now and defer it until the point we receive a
1135 * particular token from the Host side.
1136 *
1137 * This will also avoid Host cancelling URBs due to too
1d046793 1138 * many NAKs.
72246da4 1139 */
0fc9a1be
FB		 1140 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1141 dep->direction);
1142 if (ret)
1143 return ret;
1144
72246da4
FB		 1145 list_add_tail(&req->list, &dep->request_list);
1146
1147 /*
b511e5e7 1148 * There are a few special cases:
72246da4 1149 *
f898ae09
PZ		 1150 * 1. XferNotReady with empty list of requests. We need to kick the
1151 * transfer here in that situation, otherwise we will be NAKing
1152 * forever. If we get XferNotReady before gadget driver has a
1153 * chance to queue a request, we will ACK the IRQ but won't be
1154 * able to receive the data until the next request is queued.
1155 * The following code is handling exactly that.
72246da4 1156 *
72246da4
FB		 1157 */
1158 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f4a53c55
PA		 1159 /*
1160 * If xfernotready is already elapsed and it is a case
1161 * of isoc transfer, then issue END TRANSFER, so that
1162 * you can receive xfernotready again and can have
1163 * notion of current microframe.
1164 */
1165 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
cdc359dd 1166 if (list_empty(&dep->req_queued)) {
b992e681 1167 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1168 dep->flags = DWC3_EP_ENABLED;
1169 }
f4a53c55
PA		 1170 return 0;
1171 }
1172
b511e5e7 1173 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
348e026f 1174 if (ret && ret != -EBUSY)
b511e5e7
FB		 1175 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1176 dep->name);
15f86bde 1177 return ret;
b511e5e7 1178 }
72246da4 1179
b511e5e7
FB		 1180 /*
1181 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1182 * kick the transfer here after queuing a request, otherwise the
1183 * core may not see the modified TRB(s).
1184 */
1185 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
79c9046e
PA		 1186 (dep->flags & DWC3_EP_BUSY) &&
1187 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
b4996a86
FB		 1188 WARN_ON_ONCE(!dep->resource_index);
1189 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
b511e5e7 1190 false);
348e026f 1191 if (ret && ret != -EBUSY)
72246da4
FB		 1192 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1193 dep->name);
15f86bde 1194 return ret;
a0925324 1195 }
72246da4 1196
b997ada5
FB		 1197 /*
1198 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1199 * right away, otherwise host will not know we have streams to be
1200 * handled.
1201 */
1202 if (dep->stream_capable) {
1203 int ret;
1204
1205 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1206 if (ret && ret != -EBUSY) {
1207 struct dwc3 *dwc = dep->dwc;
1208
1209 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1210 dep->name);
1211 }
1212 }
1213
72246da4
FB		 1214 return 0;
1215}
1216
1217static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1218 gfp_t gfp_flags)
1219{
1220 struct dwc3_request *req = to_dwc3_request(request);
1221 struct dwc3_ep *dep = to_dwc3_ep(ep);
1222 struct dwc3 *dwc = dep->dwc;
1223
1224 unsigned long flags;
1225
1226 int ret;
1227
fdee4eba 1228 spin_lock_irqsave(&dwc->lock, flags);
16e78db7 1229 if (!dep->endpoint.desc) {
72246da4
FB		 1230 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1231 request, ep->name);
fdee4eba 1232 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1233 return -ESHUTDOWN;
1234 }
1235
1236 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1237 request, ep->name, request->length);
1238
72246da4
FB		 1239 ret = __dwc3_gadget_ep_queue(dep, req);
1240 spin_unlock_irqrestore(&dwc->lock, flags);
1241
1242 return ret;
1243}
1244
1245static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1246 struct usb_request *request)
1247{
1248 struct dwc3_request *req = to_dwc3_request(request);
1249 struct dwc3_request *r = NULL;
1250
1251 struct dwc3_ep *dep = to_dwc3_ep(ep);
1252 struct dwc3 *dwc = dep->dwc;
1253
1254 unsigned long flags;
1255 int ret = 0;
1256
1257 spin_lock_irqsave(&dwc->lock, flags);
1258
1259 list_for_each_entry(r, &dep->request_list, list) {
1260 if (r == req)
1261 break;
1262 }
1263
1264 if (r != req) {
1265 list_for_each_entry(r, &dep->req_queued, list) {
1266 if (r == req)
1267 break;
1268 }
1269 if (r == req) {
1270 /* wait until it is processed */
b992e681 1271 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1272 goto out1;
72246da4
FB		 1273 }
1274 dev_err(dwc->dev, "request %p was not queued to %s\n",
1275 request, ep->name);
1276 ret = -EINVAL;
1277 goto out0;
1278 }
1279
e8d4e8be 1280out1:
72246da4
FB		 1281 /* giveback the request */
1282 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1283
1284out0:
1285 spin_unlock_irqrestore(&dwc->lock, flags);
1286
1287 return ret;
1288}
1289
1290int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1291{
1292 struct dwc3_gadget_ep_cmd_params params;
1293 struct dwc3 *dwc = dep->dwc;
1294 int ret;
1295
1296 memset(&params, 0x00, sizeof(params));
1297
1298 if (value) {
72246da4
FB		 1299 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1300 DWC3_DEPCMD_SETSTALL, &params);
1301 if (ret)
3f89204b 1302 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1303 dep->name);
1304 else
1305 dep->flags |= DWC3_EP_STALL;
1306 } else {
1307 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1308 DWC3_DEPCMD_CLEARSTALL, &params);
1309 if (ret)
3f89204b 1310 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1311 dep->name);
1312 else
a535d81c 1313 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1314 }
5275455a 1315
72246da4
FB		 1316 return ret;
1317}
1318
1319static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1320{
1321 struct dwc3_ep *dep = to_dwc3_ep(ep);
1322 struct dwc3 *dwc = dep->dwc;
1323
1324 unsigned long flags;
1325
1326 int ret;
1327
1328 spin_lock_irqsave(&dwc->lock, flags);
1329
16e78db7 1330 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1331 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1332 ret = -EINVAL;
1333 goto out;
1334 }
1335
1336 ret = __dwc3_gadget_ep_set_halt(dep, value);
1337out:
1338 spin_unlock_irqrestore(&dwc->lock, flags);
1339
1340 return ret;
1341}
1342
1343static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1344{
1345 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1346 struct dwc3 *dwc = dep->dwc;
1347 unsigned long flags;
72246da4 1348
249a4569 1349 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1350 dep->flags |= DWC3_EP_WEDGE;
249a4569 1351 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4 1352
08f0d966
PA		 1353 if (dep->number == 0 || dep->number == 1)
1354 return dwc3_gadget_ep0_set_halt(ep, 1);
1355 else
1356 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 1357}
1358
1359/* -------------------------------------------------------------------------- */
1360
1361static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1362 .bLength = USB_DT_ENDPOINT_SIZE,
1363 .bDescriptorType = USB_DT_ENDPOINT,
1364 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1365};
1366
1367static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1368 .enable = dwc3_gadget_ep0_enable,
1369 .disable = dwc3_gadget_ep0_disable,
1370 .alloc_request = dwc3_gadget_ep_alloc_request,
1371 .free_request = dwc3_gadget_ep_free_request,
1372 .queue = dwc3_gadget_ep0_queue,
1373 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1374 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1375 .set_wedge = dwc3_gadget_ep_set_wedge,
1376};
1377
1378static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1379 .enable = dwc3_gadget_ep_enable,
1380 .disable = dwc3_gadget_ep_disable,
1381 .alloc_request = dwc3_gadget_ep_alloc_request,
1382 .free_request = dwc3_gadget_ep_free_request,
1383 .queue = dwc3_gadget_ep_queue,
1384 .dequeue = dwc3_gadget_ep_dequeue,
1385 .set_halt = dwc3_gadget_ep_set_halt,
1386 .set_wedge = dwc3_gadget_ep_set_wedge,
1387};
1388
1389/* -------------------------------------------------------------------------- */
1390
1391static int dwc3_gadget_get_frame(struct usb_gadget *g)
1392{
1393 struct dwc3 *dwc = gadget_to_dwc(g);
1394 u32 reg;
1395
1396 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1397 return DWC3_DSTS_SOFFN(reg);
1398}
1399
1400static int dwc3_gadget_wakeup(struct usb_gadget *g)
1401{
1402 struct dwc3 *dwc = gadget_to_dwc(g);
1403
1404 unsigned long timeout;
1405 unsigned long flags;
1406
1407 u32 reg;
1408
1409 int ret = 0;
1410
1411 u8 link_state;
1412 u8 speed;
1413
1414 spin_lock_irqsave(&dwc->lock, flags);
1415
1416 /*
1417 * According to the Databook Remote wakeup request should
1418 * be issued only when the device is in early suspend state.
1419 *
1420 * We can check that via USB Link State bits in DSTS register.
1421 */
1422 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1423
1424 speed = reg & DWC3_DSTS_CONNECTSPD;
1425 if (speed == DWC3_DSTS_SUPERSPEED) {
1426 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1427 ret = -EINVAL;
1428 goto out;
1429 }
1430
1431 link_state = DWC3_DSTS_USBLNKST(reg);
1432
1433 switch (link_state) {
1434 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1435 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1436 break;
1437 default:
1438 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1439 link_state);
1440 ret = -EINVAL;
1441 goto out;
1442 }
1443
8598bde7
FB		 1444 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1445 if (ret < 0) {
1446 dev_err(dwc->dev, "failed to put link in Recovery\n");
1447 goto out;
1448 }
72246da4 1449
802fde98
PZ		 1450 /* Recent versions do this automatically */
1451 if (dwc->revision < DWC3_REVISION_194A) {
1452 /* write zeroes to Link Change Request */
fcc023c7 1453 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1454 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1455 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1456 }
72246da4 1457
1d046793 1458 /* poll until Link State changes to ON */
72246da4
FB		 1459 timeout = jiffies + msecs_to_jiffies(100);
1460
1d046793 1461 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1462 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1463
1464 /* in HS, means ON */
1465 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1466 break;
1467 }
1468
1469 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1470 dev_err(dwc->dev, "failed to send remote wakeup\n");
1471 ret = -EINVAL;
1472 }
1473
1474out:
1475 spin_unlock_irqrestore(&dwc->lock, flags);
1476
1477 return ret;
1478}
1479
1480static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1481 int is_selfpowered)
1482{
1483 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1484 unsigned long flags;
72246da4 1485
249a4569 1486 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1487 dwc->is_selfpowered = !!is_selfpowered;
249a4569 1488 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1489
1490 return 0;
1491}
1492
7b2a0368 1493static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1494{
1495 u32 reg;
61d58242 1496 u32 timeout = 500;
72246da4
FB		 1497
1498 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1499 if (is_on) {
802fde98
PZ		 1500 if (dwc->revision <= DWC3_REVISION_187A) {
1501 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1502 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1503 }
1504
1505 if (dwc->revision >= DWC3_REVISION_194A)
1506 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1507 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1508
1509 if (dwc->has_hibernation)
1510 reg |= DWC3_DCTL_KEEP_CONNECT;
1511
9fcb3bd8 1512 dwc->pullups_connected = true;
8db7ed15 1513 } else {
72246da4 1514 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1515
1516 if (dwc->has_hibernation && !suspend)
1517 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1518
9fcb3bd8 1519 dwc->pullups_connected = false;
8db7ed15 1520 }
72246da4
FB		 1521
1522 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1523
1524 do {
1525 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1526 if (is_on) {
1527 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1528 break;
1529 } else {
1530 if (reg & DWC3_DSTS_DEVCTRLHLT)
1531 break;
1532 }
72246da4
FB		 1533 timeout--;
1534 if (!timeout)
6f17f74b 1535 return -ETIMEDOUT;
61d58242 1536 udelay(1);
72246da4
FB		 1537 } while (1);
1538
1539 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1540 dwc->gadget_driver
1541 ? dwc->gadget_driver->function : "no-function",
1542 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1543
1544 return 0;
72246da4
FB		 1545}
1546
1547static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1548{
1549 struct dwc3 *dwc = gadget_to_dwc(g);
1550 unsigned long flags;
6f17f74b 1551 int ret;
72246da4
FB		 1552
1553 is_on = !!is_on;
1554
1555 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1556 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1557 spin_unlock_irqrestore(&dwc->lock, flags);
1558
6f17f74b 1559 return ret;
72246da4
FB		 1560}
1561
8698e2ac
FB		 1562static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1563{
1564 u32 reg;
1565
1566 /* Enable all but Start and End of Frame IRQs */
1567 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1568 DWC3_DEVTEN_EVNTOVERFLOWEN |
1569 DWC3_DEVTEN_CMDCMPLTEN |
1570 DWC3_DEVTEN_ERRTICERREN |
1571 DWC3_DEVTEN_WKUPEVTEN |
1572 DWC3_DEVTEN_ULSTCNGEN |
1573 DWC3_DEVTEN_CONNECTDONEEN |
1574 DWC3_DEVTEN_USBRSTEN |
1575 DWC3_DEVTEN_DISCONNEVTEN);
1576
1577 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1578}
1579
1580static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1581{
1582 /* mask all interrupts */
1583 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1584}
1585
1586static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1587static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1588
72246da4
FB		 1589static int dwc3_gadget_start(struct usb_gadget *g,
1590 struct usb_gadget_driver *driver)
1591{
1592 struct dwc3 *dwc = gadget_to_dwc(g);
1593 struct dwc3_ep *dep;
1594 unsigned long flags;
1595 int ret = 0;
8698e2ac 1596 int irq;
72246da4
FB		 1597 u32 reg;
1598
b0d7ffd4
FB		 1599 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1600 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
e8adfc30 1601 IRQF_SHARED, "dwc3", dwc);
b0d7ffd4
FB		 1602 if (ret) {
1603 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1604 irq, ret);
1605 goto err0;
1606 }
1607
72246da4
FB		 1608 spin_lock_irqsave(&dwc->lock, flags);
1609
1610 if (dwc->gadget_driver) {
1611 dev_err(dwc->dev, "%s is already bound to %s\n",
1612 dwc->gadget.name,
1613 dwc->gadget_driver->driver.name);
1614 ret = -EBUSY;
b0d7ffd4 1615 goto err1;
72246da4
FB		 1616 }
1617
1618 dwc->gadget_driver = driver;
72246da4 1619
72246da4
FB		 1620 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1621 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1622
1623 /**
1624 * WORKAROUND: DWC3 revision < 2.20a have an issue
1625 * which would cause metastability state on Run/Stop
1626 * bit if we try to force the IP to USB2-only mode.
1627 *
1628 * Because of that, we cannot configure the IP to any
1629 * speed other than the SuperSpeed
1630 *
1631 * Refers to:
1632 *
1633 * STAR#9000525659: Clock Domain Crossing on DCTL in
1634 * USB 2.0 Mode
1635 */
f7e846f0 1636 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1637 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1638 } else {
1639 switch (dwc->maximum_speed) {
1640 case USB_SPEED_LOW:
1641 reg |= DWC3_DSTS_LOWSPEED;
1642 break;
1643 case USB_SPEED_FULL:
1644 reg |= DWC3_DSTS_FULLSPEED1;
1645 break;
1646 case USB_SPEED_HIGH:
1647 reg |= DWC3_DSTS_HIGHSPEED;
1648 break;
1649 case USB_SPEED_SUPER: /* FALLTHROUGH */
1650 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1651 default:
1652 reg |= DWC3_DSTS_SUPERSPEED;
1653 }
1654 }
72246da4
FB		 1655 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1656
b23c8439
PZ		 1657 dwc->start_config_issued = false;
1658
72246da4
FB		 1659 /* Start with SuperSpeed Default */
1660 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1661
1662 dep = dwc->eps[0];
265b70a7
PZ		 1663 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1664 false);
72246da4
FB		 1665 if (ret) {
1666 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1667 goto err2;
72246da4
FB		 1668 }
1669
1670 dep = dwc->eps[1];
265b70a7
PZ		 1671 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1672 false);
72246da4
FB		 1673 if (ret) {
1674 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1675 goto err3;
72246da4
FB		 1676 }
1677
1678 /* begin to receive SETUP packets */
c7fcdeb2 1679 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1680 dwc3_ep0_out_start(dwc);
1681
8698e2ac
FB		 1682 dwc3_gadget_enable_irq(dwc);
1683
72246da4
FB		 1684 spin_unlock_irqrestore(&dwc->lock, flags);
1685
1686 return 0;
1687
b0d7ffd4 1688err3:
72246da4
FB		 1689 __dwc3_gadget_ep_disable(dwc->eps[0]);
1690
b0d7ffd4 1691err2:
cdcedd69 1692 dwc->gadget_driver = NULL;
b0d7ffd4
FB		 1693
1694err1:
72246da4
FB		 1695 spin_unlock_irqrestore(&dwc->lock, flags);
1696
b0d7ffd4
FB		 1697 free_irq(irq, dwc);
1698
1699err0:
72246da4
FB		 1700 return ret;
1701}
1702
1703static int dwc3_gadget_stop(struct usb_gadget *g,
1704 struct usb_gadget_driver *driver)
1705{
1706 struct dwc3 *dwc = gadget_to_dwc(g);
1707 unsigned long flags;
8698e2ac 1708 int irq;
72246da4
FB		 1709
1710 spin_lock_irqsave(&dwc->lock, flags);
1711
8698e2ac 1712 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1713 __dwc3_gadget_ep_disable(dwc->eps[0]);
1714 __dwc3_gadget_ep_disable(dwc->eps[1]);
1715
1716 dwc->gadget_driver = NULL;
72246da4
FB		 1717
1718 spin_unlock_irqrestore(&dwc->lock, flags);
1719
b0d7ffd4
FB		 1720 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1721 free_irq(irq, dwc);
1722
72246da4
FB		 1723 return 0;
1724}
802fde98 1725
72246da4
FB		 1726static const struct usb_gadget_ops dwc3_gadget_ops = {
1727 .get_frame = dwc3_gadget_get_frame,
1728 .wakeup = dwc3_gadget_wakeup,
1729 .set_selfpowered = dwc3_gadget_set_selfpowered,
1730 .pullup = dwc3_gadget_pullup,
1731 .udc_start = dwc3_gadget_start,
1732 .udc_stop = dwc3_gadget_stop,
1733};
1734
1735/* -------------------------------------------------------------------------- */
1736
6a1e3ef4
FB		 1737static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1738 u8 num, u32 direction)
72246da4
FB		 1739{
1740 struct dwc3_ep *dep;
6a1e3ef4 1741 u8 i;
72246da4 1742
6a1e3ef4
FB		 1743 for (i = 0; i < num; i++) {
1744 u8 epnum = (i << 1) | (!!direction);
72246da4 1745
72246da4
FB		 1746 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1747 if (!dep) {
1748 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1749 epnum);
1750 return -ENOMEM;
1751 }
1752
1753 dep->dwc = dwc;
1754 dep->number = epnum;
9aa62ae4 1755 dep->direction = !!direction;
72246da4
FB		 1756 dwc->eps[epnum] = dep;
1757
1758 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1759 (epnum & 1) ? "in" : "out");
6a1e3ef4 1760
72246da4 1761 dep->endpoint.name = dep->name;
72246da4 1762
653df35e
FB		 1763 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1764
72246da4 1765 if (epnum == 0 || epnum == 1) {
e117e742 1766 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1767 dep->endpoint.maxburst = 1;
72246da4
FB		 1768 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1769 if (!epnum)
1770 dwc->gadget.ep0 = &dep->endpoint;
1771 } else {
1772 int ret;
1773
e117e742 1774 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1775 dep->endpoint.max_streams = 15;
72246da4
FB		 1776 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1777 list_add_tail(&dep->endpoint.ep_list,
1778 &dwc->gadget.ep_list);
1779
1780 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1781 if (ret)
72246da4 1782 return ret;
72246da4 1783 }
25b8ff68 1784
72246da4
FB		 1785 INIT_LIST_HEAD(&dep->request_list);
1786 INIT_LIST_HEAD(&dep->req_queued);
1787 }
1788
1789 return 0;
1790}
1791
6a1e3ef4
FB		 1792static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1793{
1794 int ret;
1795
1796 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1797
1798 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1799 if (ret < 0) {
1800 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1801 return ret;
1802 }
1803
1804 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1805 if (ret < 0) {
1806 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1807 return ret;
1808 }
1809
1810 return 0;
1811}
1812
72246da4
FB		 1813static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1814{
1815 struct dwc3_ep *dep;
1816 u8 epnum;
1817
1818 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1819 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1820 if (!dep)
1821 continue;
5bf8fae3
GC		 1822 /*
1823 * Physical endpoints 0 and 1 are special; they form the
1824 * bi-directional USB endpoint 0.
1825 *
1826 * For those two physical endpoints, we don't allocate a TRB
1827 * pool nor do we add them the endpoints list. Due to that, we
1828 * shouldn't do these two operations otherwise we would end up
1829 * with all sorts of bugs when removing dwc3.ko.
1830 */
1831 if (epnum != 0 && epnum != 1) {
1832 dwc3_free_trb_pool(dep);
72246da4 1833 list_del(&dep->endpoint.ep_list);
5bf8fae3 1834 }
72246da4
FB		 1835
1836 kfree(dep);
1837 }
1838}
1839
72246da4 1840/* -------------------------------------------------------------------------- */
e5caff68 1841
e5ba5ec8
PA		 1842static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1843 struct dwc3_request *req, struct dwc3_trb *trb,
72246da4
FB		 1844 const struct dwc3_event_depevt *event, int status)
1845{
72246da4
FB		 1846 unsigned int count;
1847 unsigned int s_pkt = 0;
d6d6ec7b 1848 unsigned int trb_status;
72246da4 1849
e5ba5ec8
PA		 1850 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1851 /*
1852 * We continue despite the error. There is not much we
1853 * can do. If we don't clean it up we loop forever. If
1854 * we skip the TRB then it gets overwritten after a
1855 * while since we use them in a ring buffer. A BUG()
1856 * would help. Lets hope that if this occurs, someone
1857 * fixes the root cause instead of looking away :)
1858 */
1859 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1860 dep->name, trb);
1861 count = trb->size & DWC3_TRB_SIZE_MASK;
1862
1863 if (dep->direction) {
1864 if (count) {
1865 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1866 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1867 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1868 dep->name);
1869 /*
1870 * If missed isoc occurred and there is
1871 * no request queued then issue END
1872 * TRANSFER, so that core generates
1873 * next xfernotready and we will issue
1874 * a fresh START TRANSFER.
1875 * If there are still queued request
1876 * then wait, do not issue either END
1877 * or UPDATE TRANSFER, just attach next
1878 * request in request_list during
1879 * giveback.If any future queued request
1880 * is successfully transferred then we
1881 * will issue UPDATE TRANSFER for all
1882 * request in the request_list.
1883 */
1884 dep->flags |= DWC3_EP_MISSED_ISOC;
1885 } else {
1886 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1887 dep->name);
1888 status = -ECONNRESET;
1889 }
1890 } else {
1891 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1892 }
1893 } else {
1894 if (count && (event->status & DEPEVT_STATUS_SHORT))
1895 s_pkt = 1;
1896 }
1897
1898 /*
1899 * We assume here we will always receive the entire data block
1900 * which we should receive. Meaning, if we program RX to
1901 * receive 4K but we receive only 2K, we assume that's all we
1902 * should receive and we simply bounce the request back to the
1903 * gadget driver for further processing.
1904 */
1905 req->request.actual += req->request.length - count;
1906 if (s_pkt)
1907 return 1;
1908 if ((event->status & DEPEVT_STATUS_LST) &&
1909 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1910 DWC3_TRB_CTRL_HWO)))
1911 return 1;
1912 if ((event->status & DEPEVT_STATUS_IOC) &&
1913 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1914 return 1;
1915 return 0;
1916}
1917
1918static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1919 const struct dwc3_event_depevt *event, int status)
1920{
1921 struct dwc3_request *req;
1922 struct dwc3_trb *trb;
1923 unsigned int slot;
1924 unsigned int i;
1925 int ret;
1926
72246da4
FB		 1927 do {
1928 req = next_request(&dep->req_queued);
d39ee7be
SAS		 1929 if (!req) {
1930 WARN_ON_ONCE(1);
1931 return 1;
1932 }
e5ba5ec8
PA		 1933 i = 0;
1934 do {
1935 slot = req->start_slot + i;
1936 if ((slot == DWC3_TRB_NUM - 1) &&
1937 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1938 slot++;
1939 slot %= DWC3_TRB_NUM;
1940 trb = &dep->trb_pool[slot];
72246da4 1941
e5ba5ec8
PA		 1942 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1943 event, status);
1944 if (ret)
1945 break;
1946 }while (++i < req->request.num_mapped_sgs);
72246da4 1947
72246da4 1948 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8
PA		 1949
1950 if (ret)
72246da4
FB		 1951 break;
1952 } while (1);
1953
cdc359dd
PA		 1954 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1955 list_empty(&dep->req_queued)) {
1956 if (list_empty(&dep->request_list)) {
1957 /*
1958 * If there is no entry in request list then do
1959 * not issue END TRANSFER now. Just set PENDING
1960 * flag, so that END TRANSFER is issued when an
1961 * entry is added into request list.
1962 */
1963 dep->flags = DWC3_EP_PENDING_REQUEST;
1964 } else {
b992e681 1965 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1966 dep->flags = DWC3_EP_ENABLED;
1967 }
7efea86c
PA		 1968 return 1;
1969 }
1970
72246da4
FB		 1971 return 1;
1972}
1973
1974static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 1975 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 1976{
1977 unsigned status = 0;
1978 int clean_busy;
1979
1980 if (event->status & DEPEVT_STATUS_BUSERR)
1981 status = -ECONNRESET;
1982
1d046793 1983 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
c2df85ca 1984 if (clean_busy)
72246da4 1985 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 1986
1987 /*
1988 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1989 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1990 */
1991 if (dwc->revision < DWC3_REVISION_183A) {
1992 u32 reg;
1993 int i;
1994
1995 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 1996 dep = dwc->eps[i];
fae2b904
FB		 1997
1998 if (!(dep->flags & DWC3_EP_ENABLED))
1999 continue;
2000
2001 if (!list_empty(&dep->req_queued))
2002 return;
2003 }
2004
2005 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2006 reg |= dwc->u1u2;
2007 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2008
2009 dwc->u1u2 = 0;
2010 }
72246da4
FB		 2011}
2012
72246da4
FB		 2013static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2014 const struct dwc3_event_depevt *event)
2015{
2016 struct dwc3_ep *dep;
2017 u8 epnum = event->endpoint_number;
2018
2019 dep = dwc->eps[epnum];
2020
3336abb5
FB		 2021 if (!(dep->flags & DWC3_EP_ENABLED))
2022 return;
2023
72246da4
FB		 2024 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
2025 dwc3_ep_event_string(event->endpoint_event));
2026
2027 if (epnum == 0 || epnum == 1) {
2028 dwc3_ep0_interrupt(dwc, event);
2029 return;
2030 }
2031
2032 switch (event->endpoint_event) {
2033 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2034 dep->resource_index = 0;
c2df85ca 2035
16e78db7 2036 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2037 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
2038 dep->name);
2039 return;
2040 }
2041
029d97ff 2042 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2043 break;
2044 case DWC3_DEPEVT_XFERINPROGRESS:
16e78db7 2045 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2046 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
2047 dep->name);
2048 return;
2049 }
2050
029d97ff 2051 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2052 break;
2053 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2054 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2055 dwc3_gadget_start_isoc(dwc, dep, event);
2056 } else {
2057 int ret;
2058
2059 dev_vdbg(dwc->dev, "%s: reason %s\n",
40aa41fb
FB		 2060 dep->name, event->status &
2061 DEPEVT_STATUS_TRANSFER_ACTIVE
72246da4
FB		 2062 ? "Transfer Active"
2063 : "Transfer Not Active");
2064
2065 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
2066 if (!ret || ret == -EBUSY)
2067 return;
2068
2069 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2070 dep->name);
2071 }
2072
879631aa
FB		 2073 break;
2074 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2075 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2076 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2077 dep->name);
2078 return;
2079 }
2080
2081 switch (event->status) {
2082 case DEPEVT_STREAMEVT_FOUND:
2083 dev_vdbg(dwc->dev, "Stream %d found and started\n",
2084 event->parameters);
2085
2086 break;
2087 case DEPEVT_STREAMEVT_NOTFOUND:
2088 /* FALLTHROUGH */
2089 default:
2090 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2091 }
72246da4
FB		 2092 break;
2093 case DWC3_DEPEVT_RXTXFIFOEVT:
2094 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2095 break;
72246da4 2096 case DWC3_DEPEVT_EPCMDCMPLT:
ea53b882 2097 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
72246da4
FB		 2098 break;
2099 }
2100}
2101
2102static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2103{
2104 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2105 spin_unlock(&dwc->lock);
2106 dwc->gadget_driver->disconnect(&dwc->gadget);
2107 spin_lock(&dwc->lock);
2108 }
2109}
2110
bc5ba2e0
FB		 2111static void dwc3_suspend_gadget(struct dwc3 *dwc)
2112{
73a30bfc 2113 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2114 spin_unlock(&dwc->lock);
2115 dwc->gadget_driver->suspend(&dwc->gadget);
2116 spin_lock(&dwc->lock);
2117 }
2118}
2119
2120static void dwc3_resume_gadget(struct dwc3 *dwc)
2121{
73a30bfc 2122 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2123 spin_unlock(&dwc->lock);
2124 dwc->gadget_driver->resume(&dwc->gadget);
2125 spin_lock(&dwc->lock);
2126 }
2127}
2128
b992e681 2129static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2130{
2131 struct dwc3_ep *dep;
2132 struct dwc3_gadget_ep_cmd_params params;
2133 u32 cmd;
2134 int ret;
2135
2136 dep = dwc->eps[epnum];
2137
b4996a86 2138 if (!dep->resource_index)
3daf74d7
PA		 2139 return;
2140
57911504
PA		 2141 /*
2142 * NOTICE: We are violating what the Databook says about the
2143 * EndTransfer command. Ideally we would _always_ wait for the
2144 * EndTransfer Command Completion IRQ, but that's causing too
2145 * much trouble synchronizing between us and gadget driver.
2146 *
2147 * We have discussed this with the IP Provider and it was
2148 * suggested to giveback all requests here, but give HW some
2149 * extra time to synchronize with the interconnect. We're using
2150 * an arbitraty 100us delay for that.
2151 *
2152 * Note also that a similar handling was tested by Synopsys
2153 * (thanks a lot Paul) and nothing bad has come out of it.
2154 * In short, what we're doing is:
2155 *
2156 * - Issue EndTransfer WITH CMDIOC bit set
2157 * - Wait 100us
2158 */
2159
3daf74d7 2160 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2161 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2162 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2163 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7
PA		 2164 memset(&params, 0, sizeof(params));
2165 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2166 WARN_ON_ONCE(ret);
b4996a86 2167 dep->resource_index = 0;
041d81f4 2168 dep->flags &= ~DWC3_EP_BUSY;
57911504 2169 udelay(100);
72246da4
FB		 2170}
2171
2172static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2173{
2174 u32 epnum;
2175
2176 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2177 struct dwc3_ep *dep;
2178
2179 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2180 if (!dep)
2181 continue;
2182
72246da4
FB		 2183 if (!(dep->flags & DWC3_EP_ENABLED))
2184 continue;
2185
624407f9 2186 dwc3_remove_requests(dwc, dep);
72246da4
FB		 2187 }
2188}
2189
2190static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2191{
2192 u32 epnum;
2193
2194 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2195 struct dwc3_ep *dep;
2196 struct dwc3_gadget_ep_cmd_params params;
2197 int ret;
2198
2199 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2200 if (!dep)
2201 continue;
72246da4
FB		 2202
2203 if (!(dep->flags & DWC3_EP_STALL))
2204 continue;
2205
2206 dep->flags &= ~DWC3_EP_STALL;
2207
2208 memset(&params, 0, sizeof(params));
2209 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2210 DWC3_DEPCMD_CLEARSTALL, &params);
2211 WARN_ON_ONCE(ret);
2212 }
2213}
2214
2215static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2216{
c4430a26
FB		 2217 int reg;
2218
72246da4 2219 dev_vdbg(dwc->dev, "%s\n", __func__);
72246da4
FB		 2220
2221 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2222 reg &= ~DWC3_DCTL_INITU1ENA;
2223 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2224
2225 reg &= ~DWC3_DCTL_INITU2ENA;
2226 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2227
72246da4 2228 dwc3_disconnect_gadget(dwc);
b23c8439 2229 dwc->start_config_issued = false;
72246da4
FB		 2230
2231 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2232 dwc->setup_packet_pending = false;
72246da4
FB		 2233}
2234
72246da4
FB		 2235static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2236{
2237 u32 reg;
2238
2239 dev_vdbg(dwc->dev, "%s\n", __func__);
2240
df62df56
FB		 2241 /*
2242 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2243 * would cause a missing Disconnect Event if there's a
2244 * pending Setup Packet in the FIFO.
2245 *
2246 * There's no suggested workaround on the official Bug
2247 * report, which states that "unless the driver/application
2248 * is doing any special handling of a disconnect event,
2249 * there is no functional issue".
2250 *
2251 * Unfortunately, it turns out that we _do_ some special
2252 * handling of a disconnect event, namely complete all
2253 * pending transfers, notify gadget driver of the
2254 * disconnection, and so on.
2255 *
2256 * Our suggested workaround is to follow the Disconnect
2257 * Event steps here, instead, based on a setup_packet_pending
2258 * flag. Such flag gets set whenever we have a XferNotReady
2259 * event on EP0 and gets cleared on XferComplete for the
2260 * same endpoint.
2261 *
2262 * Refers to:
2263 *
2264 * STAR#9000466709: RTL: Device : Disconnect event not
2265 * generated if setup packet pending in FIFO
2266 */
2267 if (dwc->revision < DWC3_REVISION_188A) {
2268 if (dwc->setup_packet_pending)
2269 dwc3_gadget_disconnect_interrupt(dwc);
2270 }
2271
961906ed 2272 /* after reset -> Default State */
14cd592f 2273 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
961906ed 2274
72246da4
FB		 2275 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2276 dwc3_disconnect_gadget(dwc);
2277
2278 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2279 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2280 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2281 dwc->test_mode = false;
72246da4
FB		 2282
2283 dwc3_stop_active_transfers(dwc);
2284 dwc3_clear_stall_all_ep(dwc);
b23c8439 2285 dwc->start_config_issued = false;
72246da4
FB		 2286
2287 /* Reset device address to zero */
2288 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2289 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2290 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2291}
2292
2293static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2294{
2295 u32 reg;
2296 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2297
2298 /*
2299 * We change the clock only at SS but I dunno why I would want to do
2300 * this. Maybe it becomes part of the power saving plan.
2301 */
2302
2303 if (speed != DWC3_DSTS_SUPERSPEED)
2304 return;
2305
2306 /*
2307 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2308 * each time on Connect Done.
2309 */
2310 if (!usb30_clock)
2311 return;
2312
2313 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2314 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2315 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2316}
2317
72246da4
FB		 2318static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2319{
72246da4
FB		 2320 struct dwc3_ep *dep;
2321 int ret;
2322 u32 reg;
2323 u8 speed;
2324
2325 dev_vdbg(dwc->dev, "%s\n", __func__);
2326
72246da4
FB		 2327 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2328 speed = reg & DWC3_DSTS_CONNECTSPD;
2329 dwc->speed = speed;
2330
2331 dwc3_update_ram_clk_sel(dwc, speed);
2332
2333 switch (speed) {
2334 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2335 /*
2336 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2337 * would cause a missing USB3 Reset event.
2338 *
2339 * In such situations, we should force a USB3 Reset
2340 * event by calling our dwc3_gadget_reset_interrupt()
2341 * routine.
2342 *
2343 * Refers to:
2344 *
2345 * STAR#9000483510: RTL: SS : USB3 reset event may
2346 * not be generated always when the link enters poll
2347 */
2348 if (dwc->revision < DWC3_REVISION_190A)
2349 dwc3_gadget_reset_interrupt(dwc);
2350
72246da4
FB		 2351 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2352 dwc->gadget.ep0->maxpacket = 512;
2353 dwc->gadget.speed = USB_SPEED_SUPER;
2354 break;
2355 case DWC3_DCFG_HIGHSPEED:
2356 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2357 dwc->gadget.ep0->maxpacket = 64;
2358 dwc->gadget.speed = USB_SPEED_HIGH;
2359 break;
2360 case DWC3_DCFG_FULLSPEED2:
2361 case DWC3_DCFG_FULLSPEED1:
2362 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2363 dwc->gadget.ep0->maxpacket = 64;
2364 dwc->gadget.speed = USB_SPEED_FULL;
2365 break;
2366 case DWC3_DCFG_LOWSPEED:
2367 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2368 dwc->gadget.ep0->maxpacket = 8;
2369 dwc->gadget.speed = USB_SPEED_LOW;
2370 break;
2371 }
2372
2b758350
PA		 2373 /* Enable USB2 LPM Capability */
2374
2375 if ((dwc->revision > DWC3_REVISION_194A)
2376 && (speed != DWC3_DCFG_SUPERSPEED)) {
2377 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2378 reg |= DWC3_DCFG_LPM_CAP;
2379 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2380
2381 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2382 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2383
1a947746
FB		 2384 /*
2385 * TODO: This should be configurable. For now using
2386 * maximum allowed HIRD threshold value of 0b1100
2387 */
2388 reg |= DWC3_DCTL_HIRD_THRES(12);
2b758350 2389
356363bf
FB		 2390 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2391 } else {
2392 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2393 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2394 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2395 }
2396
72246da4 2397 dep = dwc->eps[0];
265b70a7
PZ		 2398 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2399 false);
72246da4
FB		 2400 if (ret) {
2401 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2402 return;
2403 }
2404
2405 dep = dwc->eps[1];
265b70a7
PZ		 2406 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2407 false);
72246da4
FB		 2408 if (ret) {
2409 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2410 return;
2411 }
2412
2413 /*
2414 * Configure PHY via GUSB3PIPECTLn if required.
2415 *
2416 * Update GTXFIFOSIZn
2417 *
2418 * In both cases reset values should be sufficient.
2419 */
2420}
2421
2422static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2423{
2424 dev_vdbg(dwc->dev, "%s\n", __func__);
2425
2426 /*
2427 * TODO take core out of low power mode when that's
2428 * implemented.
2429 */
2430
2431 dwc->gadget_driver->resume(&dwc->gadget);
2432}
2433
2434static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2435 unsigned int evtinfo)
2436{
fae2b904 2437 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2438 unsigned int pwropt;
2439
2440 /*
2441 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2442 * Hibernation mode enabled which would show up when device detects
2443 * host-initiated U3 exit.
2444 *
2445 * In that case, device will generate a Link State Change Interrupt
2446 * from U3 to RESUME which is only necessary if Hibernation is
2447 * configured in.
2448 *
2449 * There are no functional changes due to such spurious event and we
2450 * just need to ignore it.
2451 *
2452 * Refers to:
2453 *
2454 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2455 * operational mode
2456 */
2457 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2458 if ((dwc->revision < DWC3_REVISION_250A) &&
2459 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2460 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2461 (next == DWC3_LINK_STATE_RESUME)) {
2462 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2463 return;
2464 }
2465 }
fae2b904
FB		 2466
2467 /*
2468 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2469 * on the link partner, the USB session might do multiple entry/exit
2470 * of low power states before a transfer takes place.
2471 *
2472 * Due to this problem, we might experience lower throughput. The
2473 * suggested workaround is to disable DCTL[12:9] bits if we're
2474 * transitioning from U1/U2 to U0 and enable those bits again
2475 * after a transfer completes and there are no pending transfers
2476 * on any of the enabled endpoints.
2477 *
2478 * This is the first half of that workaround.
2479 *
2480 * Refers to:
2481 *
2482 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2483 * core send LGO_Ux entering U0
2484 */
2485 if (dwc->revision < DWC3_REVISION_183A) {
2486 if (next == DWC3_LINK_STATE_U0) {
2487 u32 u1u2;
2488 u32 reg;
2489
2490 switch (dwc->link_state) {
2491 case DWC3_LINK_STATE_U1:
2492 case DWC3_LINK_STATE_U2:
2493 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2494 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2495 | DWC3_DCTL_ACCEPTU2ENA
2496 | DWC3_DCTL_INITU1ENA
2497 | DWC3_DCTL_ACCEPTU1ENA);
2498
2499 if (!dwc->u1u2)
2500 dwc->u1u2 = reg & u1u2;
2501
2502 reg &= ~u1u2;
2503
2504 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2505 break;
2506 default:
2507 /* do nothing */
2508 break;
2509 }
2510 }
2511 }
2512
bc5ba2e0
FB		 2513 switch (next) {
2514 case DWC3_LINK_STATE_U1:
2515 if (dwc->speed == USB_SPEED_SUPER)
2516 dwc3_suspend_gadget(dwc);
2517 break;
2518 case DWC3_LINK_STATE_U2:
2519 case DWC3_LINK_STATE_U3:
2520 dwc3_suspend_gadget(dwc);
2521 break;
2522 case DWC3_LINK_STATE_RESUME:
2523 dwc3_resume_gadget(dwc);
2524 break;
2525 default:
2526 /* do nothing */
2527 break;
2528 }
2529
e57ebc1d
FB		 2530 dev_vdbg(dwc->dev, "link change: %s [%d] -> %s [%d]\n",
2531 dwc3_gadget_link_string(dwc->link_state),
2532 dwc->link_state, dwc3_gadget_link_string(next), next);
2533
2534 dwc->link_state = next;
72246da4
FB		 2535}
2536
e1dadd3b
FB		 2537static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2538 unsigned int evtinfo)
2539{
2540 unsigned int is_ss = evtinfo & BIT(4);
2541
2542 /**
2543 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2544 * have a known issue which can cause USB CV TD.9.23 to fail
2545 * randomly.
2546 *
2547 * Because of this issue, core could generate bogus hibernation
2548 * events which SW needs to ignore.
2549 *
2550 * Refers to:
2551 *
2552 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2553 * Device Fallback from SuperSpeed
2554 */
2555 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2556 return;
2557
2558 /* enter hibernation here */
2559}
2560
72246da4
FB		 2561static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2562 const struct dwc3_event_devt *event)
2563{
2564 switch (event->type) {
2565 case DWC3_DEVICE_EVENT_DISCONNECT:
2566 dwc3_gadget_disconnect_interrupt(dwc);
2567 break;
2568 case DWC3_DEVICE_EVENT_RESET:
2569 dwc3_gadget_reset_interrupt(dwc);
2570 break;
2571 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2572 dwc3_gadget_conndone_interrupt(dwc);
2573 break;
2574 case DWC3_DEVICE_EVENT_WAKEUP:
2575 dwc3_gadget_wakeup_interrupt(dwc);
2576 break;
e1dadd3b
FB		 2577 case DWC3_DEVICE_EVENT_HIBER_REQ:
2578 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2579 "unexpected hibernation event\n"))
2580 break;
2581
2582 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2583 break;
72246da4
FB		 2584 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2585 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2586 break;
2587 case DWC3_DEVICE_EVENT_EOPF:
2588 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2589 break;
2590 case DWC3_DEVICE_EVENT_SOF:
2591 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2592 break;
2593 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2594 dev_vdbg(dwc->dev, "Erratic Error\n");
2595 break;
2596 case DWC3_DEVICE_EVENT_CMD_CMPL:
2597 dev_vdbg(dwc->dev, "Command Complete\n");
2598 break;
2599 case DWC3_DEVICE_EVENT_OVERFLOW:
2600 dev_vdbg(dwc->dev, "Overflow\n");
2601 break;
2602 default:
2603 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2604 }
2605}
2606
2607static void dwc3_process_event_entry(struct dwc3 *dwc,
2608 const union dwc3_event *event)
2609{
2610 /* Endpoint IRQ, handle it and return early */
2611 if (event->type.is_devspec == 0) {
2612 /* depevt */
2613 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2614 }
2615
2616 switch (event->type.type) {
2617 case DWC3_EVENT_TYPE_DEV:
2618 dwc3_gadget_interrupt(dwc, &event->devt);
2619 break;
2620 /* REVISIT what to do with Carkit and I2C events ? */
2621 default:
2622 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2623 }
2624}
2625
f42f2447 2626static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
b15a762f 2627{
f42f2447 2628 struct dwc3_event_buffer *evt;
b15a762f 2629 irqreturn_t ret = IRQ_NONE;
f42f2447 2630 int left;
e8adfc30 2631 u32 reg;
b15a762f 2632
f42f2447
FB		 2633 evt = dwc->ev_buffs[buf];
2634 left = evt->count;
b15a762f 2635
f42f2447
FB		 2636 if (!(evt->flags & DWC3_EVENT_PENDING))
2637 return IRQ_NONE;
b15a762f 2638
f42f2447
FB		 2639 while (left > 0) {
2640 union dwc3_event event;
b15a762f 2641
f42f2447 2642 event.raw = *(u32 *) (evt->buf + evt->lpos);
b15a762f 2643
f42f2447 2644 dwc3_process_event_entry(dwc, &event);
b15a762f 2645
f42f2447
FB		 2646 /*
2647 * FIXME we wrap around correctly to the next entry as
2648 * almost all entries are 4 bytes in size. There is one
2649 * entry which has 12 bytes which is a regular entry
2650 * followed by 8 bytes data. ATM I don't know how
2651 * things are organized if we get next to the a
2652 * boundary so I worry about that once we try to handle
2653 * that.
2654 */
2655 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2656 left -= 4;
b15a762f 2657
f42f2447
FB		 2658 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2659 }
b15a762f 2660
f42f2447
FB		 2661 evt->count = 0;
2662 evt->flags &= ~DWC3_EVENT_PENDING;
2663 ret = IRQ_HANDLED;
b15a762f 2664
f42f2447
FB		 2665 /* Unmask interrupt */
2666 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2667 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2668 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
b15a762f 2669
f42f2447
FB		 2670 return ret;
2671}
e8adfc30 2672
f42f2447
FB		 2673static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2674{
2675 struct dwc3 *dwc = _dwc;
2676 unsigned long flags;
2677 irqreturn_t ret = IRQ_NONE;
2678 int i;
2679
2680 spin_lock_irqsave(&dwc->lock, flags);
2681
2682 for (i = 0; i < dwc->num_event_buffers; i++)
2683 ret |= dwc3_process_event_buf(dwc, i);
b15a762f
FB		 2684
2685 spin_unlock_irqrestore(&dwc->lock, flags);
2686
2687 return ret;
2688}
2689
7f97aa98 2690static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
72246da4
FB		 2691{
2692 struct dwc3_event_buffer *evt;
72246da4 2693 u32 count;
e8adfc30 2694 u32 reg;
72246da4 2695
b15a762f
FB		 2696 evt = dwc->ev_buffs[buf];
2697
72246da4
FB		 2698 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2699 count &= DWC3_GEVNTCOUNT_MASK;
2700 if (!count)
2701 return IRQ_NONE;
2702
b15a762f
FB		 2703 evt->count = count;
2704 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2705
e8adfc30
FB		 2706 /* Mask interrupt */
2707 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2708 reg |= DWC3_GEVNTSIZ_INTMASK;
2709 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2710
b15a762f 2711 return IRQ_WAKE_THREAD;
72246da4
FB		 2712}
2713
2714static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2715{
2716 struct dwc3 *dwc = _dwc;
2717 int i;
2718 irqreturn_t ret = IRQ_NONE;
2719
2720 spin_lock(&dwc->lock);
2721
9f622b2a 2722 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2723 irqreturn_t status;
2724
7f97aa98 2725 status = dwc3_check_event_buf(dwc, i);
b15a762f 2726 if (status == IRQ_WAKE_THREAD)
72246da4
FB		 2727 ret = status;
2728 }
2729
2730 spin_unlock(&dwc->lock);
2731
2732 return ret;
2733}
2734
2735/**
2736 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2737 * @dwc: pointer to our controller context structure
72246da4
FB		 2738 *
2739 * Returns 0 on success otherwise negative errno.
2740 */
41ac7b3a 2741int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2742{
72246da4 2743 int ret;
72246da4
FB		 2744
2745 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2746 &dwc->ctrl_req_addr, GFP_KERNEL);
2747 if (!dwc->ctrl_req) {
2748 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2749 ret = -ENOMEM;
2750 goto err0;
2751 }
2752
2753 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2754 &dwc->ep0_trb_addr, GFP_KERNEL);
2755 if (!dwc->ep0_trb) {
2756 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2757 ret = -ENOMEM;
2758 goto err1;
2759 }
2760
3ef35faf 2761 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4
FB		 2762 if (!dwc->setup_buf) {
2763 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2764 ret = -ENOMEM;
2765 goto err2;
2766 }
2767
5812b1c2 2768 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2769 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2770 GFP_KERNEL);
5812b1c2
FB		 2771 if (!dwc->ep0_bounce) {
2772 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2773 ret = -ENOMEM;
2774 goto err3;
2775 }
2776
72246da4 2777 dwc->gadget.ops = &dwc3_gadget_ops;
d327ab5b 2778 dwc->gadget.max_speed = USB_SPEED_SUPER;
72246da4 2779 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 2780 dwc->gadget.sg_supported = true;
72246da4
FB		 2781 dwc->gadget.name = "dwc3-gadget";
2782
a4b9d94b
DC		 2783 /*
2784 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2785 * on ep out.
2786 */
2787 dwc->gadget.quirk_ep_out_aligned_size = true;
2788
72246da4
FB		 2789 /*
2790 * REVISIT: Here we should clear all pending IRQs to be
2791 * sure we're starting from a well known location.
2792 */
2793
2794 ret = dwc3_gadget_init_endpoints(dwc);
2795 if (ret)
5812b1c2 2796 goto err4;
72246da4 2797
72246da4
FB		 2798 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2799 if (ret) {
2800 dev_err(dwc->dev, "failed to register udc\n");
e1f80467 2801 goto err4;
72246da4
FB		 2802 }
2803
2804 return 0;
2805
5812b1c2 2806err4:
e1f80467 2807 dwc3_gadget_free_endpoints(dwc);
3ef35faf
FB		 2808 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2809 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2810
72246da4 2811err3:
0fc9a1be 2812 kfree(dwc->setup_buf);
72246da4
FB		 2813
2814err2:
2815 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2816 dwc->ep0_trb, dwc->ep0_trb_addr);
2817
2818err1:
2819 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2820 dwc->ctrl_req, dwc->ctrl_req_addr);
2821
2822err0:
2823 return ret;
2824}
2825
7415f17c
FB		 2826/* -------------------------------------------------------------------------- */
2827
72246da4
FB		 2828void dwc3_gadget_exit(struct dwc3 *dwc)
2829{
72246da4 2830 usb_del_gadget_udc(&dwc->gadget);
72246da4 2831
72246da4
FB		 2832 dwc3_gadget_free_endpoints(dwc);
2833
3ef35faf
FB		 2834 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2835 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2836
0fc9a1be 2837 kfree(dwc->setup_buf);
72246da4
FB		 2838
2839 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2840 dwc->ep0_trb, dwc->ep0_trb_addr);
2841
2842 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2843 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 2844}
7415f17c
FB		 2845
2846int dwc3_gadget_prepare(struct dwc3 *dwc)
2847{
7b2a0368 2848 if (dwc->pullups_connected) {
7415f17c 2849 dwc3_gadget_disable_irq(dwc);
7b2a0368
FB		 2850 dwc3_gadget_run_stop(dwc, true, true);
2851 }
7415f17c
FB		 2852
2853 return 0;
2854}
2855
2856void dwc3_gadget_complete(struct dwc3 *dwc)
2857{
2858 if (dwc->pullups_connected) {
2859 dwc3_gadget_enable_irq(dwc);
7b2a0368 2860 dwc3_gadget_run_stop(dwc, true, false);
7415f17c
FB		 2861 }
2862}
2863
2864int dwc3_gadget_suspend(struct dwc3 *dwc)
2865{
2866 __dwc3_gadget_ep_disable(dwc->eps[0]);
2867 __dwc3_gadget_ep_disable(dwc->eps[1]);
2868
2869 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2870
2871 return 0;
2872}
2873
2874int dwc3_gadget_resume(struct dwc3 *dwc)
2875{
2876 struct dwc3_ep *dep;
2877 int ret;
2878
2879 /* Start with SuperSpeed Default */
2880 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2881
2882 dep = dwc->eps[0];
265b70a7
PZ		 2883 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2884 false);
7415f17c
FB		 2885 if (ret)
2886 goto err0;
2887
2888 dep = dwc->eps[1];
265b70a7
PZ		 2889 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2890 false);
7415f17c
FB		 2891 if (ret)
2892 goto err1;
2893
2894 /* begin to receive SETUP packets */
2895 dwc->ep0state = EP0_SETUP_PHASE;
2896 dwc3_ep0_out_start(dwc);
2897
2898 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2899
2900 return 0;
2901
2902err1:
2903 __dwc3_gadget_ep_disable(dwc->eps[0]);
2904
2905err0:
2906 return ret;
2907}
Linux kernel - Deliverables
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