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Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
04a9bfcd
FB		 57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
8598bde7
FB		 90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
aee63e3c 96 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
aee63e3c 100 int retries = 10000;
8598bde7
FB		 101 u32 reg;
102
802fde98
PZ		 103 /*
104 * Wait until device controller is ready. Only applies to 1.94a and
105 * later RTL.
106 */
107 if (dwc->revision >= DWC3_REVISION_194A) {
108 while (--retries) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
111 udelay(5);
112 else
113 break;
114 }
115
116 if (retries <= 0)
117 return -ETIMEDOUT;
118 }
119
8598bde7
FB		 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
122
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
126
802fde98
PZ		 127 /*
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
130 */
131 if (dwc->revision >= DWC3_REVISION_194A)
132 return 0;
133
8598bde7 134 /* wait for a change in DSTS */
aed430e5 135 retries = 10000;
8598bde7
FB		 136 while (--retries) {
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
138
8598bde7
FB		 139 if (DWC3_DSTS_USBLNKST(reg) == state)
140 return 0;
141
aee63e3c 142 udelay(5);
8598bde7
FB		 143 }
144
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
146
147 return -ETIMEDOUT;
148}
149
457e84b6
FB		 150/**
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
153 *
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
157 *
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
162 *
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
165 *
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
168 *
169 * Unfortunately, due to many variables that's not always the case.
170 */
171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
172{
173 int last_fifo_depth = 0;
174 int ram1_depth;
175 int fifo_size;
176 int mdwidth;
177 int num;
178
179 if (!dwc->needs_fifo_resize)
180 return 0;
181
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
184
185 /* MDWIDTH is represented in bits, we need it in bytes */
186 mdwidth >>= 3;
187
188 /*
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
192 * FIFO space
193 */
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
2e81c36a 197 int mult = 1;
457e84b6
FB		 198 int tmp;
199
200 if (!(dep->number & 1))
201 continue;
202
203 if (!(dep->flags & DWC3_EP_ENABLED))
204 continue;
205
16e78db7
IS		 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
2e81c36a
FB		 208 mult = 3;
209
210 /*
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
214 * accordingly.
215 *
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
219 * packets
220 */
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
457e84b6
FB		 222 tmp += mdwidth;
223
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
2e81c36a 225
457e84b6
FB		 226 fifo_size |= (last_fifo_depth << 16);
227
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
230
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
232 fifo_size);
233
234 last_fifo_depth += (fifo_size & 0xffff);
235 }
236
237 return 0;
238}
239
72246da4
FB		 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
241 int status)
242{
243 struct dwc3 *dwc = dep->dwc;
244
245 if (req->queued) {
eeb720fb
FB		 246 if (req->request.num_mapped_sgs)
247 dep->busy_slot += req->request.num_mapped_sgs;
248 else
249 dep->busy_slot++;
250
72246da4
FB		 251 /*
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
255 */
256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
16e78db7 257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
72246da4
FB		 258 dep->busy_slot++;
259 }
260 list_del(&req->list);
eeb720fb 261 req->trb = NULL;
72246da4
FB		 262
263 if (req->request.status == -EINPROGRESS)
264 req->request.status = status;
265
0416e494
PA		 266 if (dwc->ep0_bounced && dep->number == 0)
267 dwc->ep0_bounced = false;
268 else
269 usb_gadget_unmap_request(&dwc->gadget, &req->request,
270 req->direction);
72246da4
FB		 271
272 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
273 req, dep->name, req->request.actual,
274 req->request.length, status);
275
276 spin_unlock(&dwc->lock);
0fc9a1be 277 req->request.complete(&dep->endpoint, &req->request);
72246da4
FB		 278 spin_lock(&dwc->lock);
279}
280
281static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
282{
283 switch (cmd) {
284 case DWC3_DEPCMD_DEPSTARTCFG:
285 return "Start New Configuration";
286 case DWC3_DEPCMD_ENDTRANSFER:
287 return "End Transfer";
288 case DWC3_DEPCMD_UPDATETRANSFER:
289 return "Update Transfer";
290 case DWC3_DEPCMD_STARTTRANSFER:
291 return "Start Transfer";
292 case DWC3_DEPCMD_CLEARSTALL:
293 return "Clear Stall";
294 case DWC3_DEPCMD_SETSTALL:
295 return "Set Stall";
802fde98
PZ		 296 case DWC3_DEPCMD_GETEPSTATE:
297 return "Get Endpoint State";
72246da4
FB		 298 case DWC3_DEPCMD_SETTRANSFRESOURCE:
299 return "Set Endpoint Transfer Resource";
300 case DWC3_DEPCMD_SETEPCONFIG:
301 return "Set Endpoint Configuration";
302 default:
303 return "UNKNOWN command";
304 }
305}
306
b09bb642
FB		 307int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
308{
309 u32 timeout = 500;
310 u32 reg;
311
312 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
313 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
314
315 do {
316 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
317 if (!(reg & DWC3_DGCMD_CMDACT)) {
318 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
319 DWC3_DGCMD_STATUS(reg));
320 return 0;
321 }
322
323 /*
324 * We can't sleep here, because it's also called from
325 * interrupt context.
326 */
327 timeout--;
328 if (!timeout)
329 return -ETIMEDOUT;
330 udelay(1);
331 } while (1);
332}
333
72246da4
FB		 334int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
335 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
336{
337 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 338 u32 timeout = 500;
72246da4
FB		 339 u32 reg;
340
341 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
342 dep->name,
dc1c70a7
FB		 343 dwc3_gadget_ep_cmd_string(cmd), params->param0,
344 params->param1, params->param2);
72246da4 345
dc1c70a7
FB		 346 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
347 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
348 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 349
350 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
351 do {
352 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
353 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 354 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
355 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 356 return 0;
357 }
358
359 /*
72246da4
FB		 360 * We can't sleep here, because it is also called from
361 * interrupt context.
362 */
363 timeout--;
364 if (!timeout)
365 return -ETIMEDOUT;
366
61d58242 367 udelay(1);
72246da4
FB		 368 } while (1);
369}
370
371static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 372 struct dwc3_trb *trb)
72246da4 373{
c439ef87 374 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 375
376 return dep->trb_pool_dma + offset;
377}
378
379static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
380{
381 struct dwc3 *dwc = dep->dwc;
382
383 if (dep->trb_pool)
384 return 0;
385
386 if (dep->number == 0 || dep->number == 1)
387 return 0;
388
389 dep->trb_pool = dma_alloc_coherent(dwc->dev,
390 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
391 &dep->trb_pool_dma, GFP_KERNEL);
392 if (!dep->trb_pool) {
393 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
394 dep->name);
395 return -ENOMEM;
396 }
397
398 return 0;
399}
400
401static void dwc3_free_trb_pool(struct dwc3_ep *dep)
402{
403 struct dwc3 *dwc = dep->dwc;
404
405 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
406 dep->trb_pool, dep->trb_pool_dma);
407
408 dep->trb_pool = NULL;
409 dep->trb_pool_dma = 0;
410}
411
412static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
413{
414 struct dwc3_gadget_ep_cmd_params params;
415 u32 cmd;
416
417 memset(&params, 0x00, sizeof(params));
418
419 if (dep->number != 1) {
420 cmd = DWC3_DEPCMD_DEPSTARTCFG;
421 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 422 if (dep->number > 1) {
423 if (dwc->start_config_issued)
424 return 0;
425 dwc->start_config_issued = true;
72246da4 426 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 427 }
72246da4
FB		 428
429 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
430 }
431
432 return 0;
433}
434
435static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec
FB		 436 const struct usb_endpoint_descriptor *desc,
437 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 438{
439 struct dwc3_gadget_ep_cmd_params params;
440
441 memset(&params, 0x00, sizeof(params));
442
dc1c70a7
FB		 443 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
444 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
b785ea7c 445 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst - 1);
72246da4 446
dc1c70a7
FB		 447 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
448 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 449
18b7ede5 450 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 451 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
452 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 453 dep->stream_capable = true;
454 }
455
72246da4 456 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 457 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 458
459 /*
460 * We are doing 1:1 mapping for endpoints, meaning
461 * Physical Endpoints 2 maps to Logical Endpoint 2 and
462 * so on. We consider the direction bit as part of the physical
463 * endpoint number. So USB endpoint 0x81 is 0x03.
464 */
dc1c70a7 465 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 466
467 /*
468 * We must use the lower 16 TX FIFOs even though
469 * HW might have more
470 */
471 if (dep->direction)
dc1c70a7 472 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 473
474 if (desc->bInterval) {
dc1c70a7 475 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 476 dep->interval = 1 << (desc->bInterval - 1);
477 }
478
479 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
480 DWC3_DEPCMD_SETEPCONFIG, &params);
481}
482
483static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
484{
485 struct dwc3_gadget_ep_cmd_params params;
486
487 memset(&params, 0x00, sizeof(params));
488
dc1c70a7 489 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 490
491 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
492 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
493}
494
495/**
496 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
497 * @dep: endpoint to be initialized
498 * @desc: USB Endpoint Descriptor
499 *
500 * Caller should take care of locking
501 */
502static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec
FB		 503 const struct usb_endpoint_descriptor *desc,
504 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 505{
506 struct dwc3 *dwc = dep->dwc;
507 u32 reg;
508 int ret = -ENOMEM;
509
510 if (!(dep->flags & DWC3_EP_ENABLED)) {
511 ret = dwc3_gadget_start_config(dwc, dep);
512 if (ret)
513 return ret;
514 }
515
c90bfaec 516 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
72246da4
FB		 517 if (ret)
518 return ret;
519
520 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 521 struct dwc3_trb *trb_st_hw;
522 struct dwc3_trb *trb_link;
72246da4
FB		 523
524 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
525 if (ret)
526 return ret;
527
16e78db7 528 dep->endpoint.desc = desc;
c90bfaec 529 dep->comp_desc = comp_desc;
72246da4
FB		 530 dep->type = usb_endpoint_type(desc);
531 dep->flags |= DWC3_EP_ENABLED;
532
533 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
534 reg |= DWC3_DALEPENA_EP(dep->number);
535 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
536
537 if (!usb_endpoint_xfer_isoc(desc))
538 return 0;
539
540 memset(&trb_link, 0, sizeof(trb_link));
541
1d046793 542 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 543 trb_st_hw = &dep->trb_pool[0];
544
f6bafc6a 545 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
72246da4 546
f6bafc6a
FB		 547 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
548 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
549 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
550 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 551 }
552
553 return 0;
554}
555
624407f9
SAS		 556static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
557static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 558{
559 struct dwc3_request *req;
560
ea53b882 561 if (!list_empty(&dep->req_queued)) {
624407f9
SAS		 562 dwc3_stop_active_transfer(dwc, dep->number);
563
ea53b882
FB		 564 /*
565 * NOTICE: We are violating what the Databook says about the
566 * EndTransfer command. Ideally we would _always_ wait for the
567 * EndTransfer Command Completion IRQ, but that's causing too
568 * much trouble synchronizing between us and gadget driver.
569 *
570 * We have discussed this with the IP Provider and it was
571 * suggested to giveback all requests here, but give HW some
572 * extra time to synchronize with the interconnect. We're using
573 * an arbitraty 100us delay for that.
574 *
575 * Note also that a similar handling was tested by Synopsys
576 * (thanks a lot Paul) and nothing bad has come out of it.
577 * In short, what we're doing is:
578 *
579 * - Issue EndTransfer WITH CMDIOC bit set
580 * - Wait 100us
581 * - giveback all requests to gadget driver
582 */
583 udelay(100);
584
1591633e
PA		 585 while (!list_empty(&dep->req_queued)) {
586 req = next_request(&dep->req_queued);
587
588 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
589 }
ea53b882
FB		 590 }
591
72246da4
FB		 592 while (!list_empty(&dep->request_list)) {
593 req = next_request(&dep->request_list);
594
624407f9 595 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 596 }
72246da4
FB		 597}
598
599/**
600 * __dwc3_gadget_ep_disable - Disables a HW endpoint
601 * @dep: the endpoint to disable
602 *
624407f9
SAS		 603 * This function also removes requests which are currently processed ny the
604 * hardware and those which are not yet scheduled.
605 * Caller should take care of locking.
72246da4 606 */
72246da4
FB		 607static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
608{
609 struct dwc3 *dwc = dep->dwc;
610 u32 reg;
611
624407f9 612 dwc3_remove_requests(dwc, dep);
72246da4
FB		 613
614 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
615 reg &= ~DWC3_DALEPENA_EP(dep->number);
616 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
617
879631aa 618 dep->stream_capable = false;
f9c56cdd 619 dep->endpoint.desc = NULL;
c90bfaec 620 dep->comp_desc = NULL;
72246da4 621 dep->type = 0;
879631aa 622 dep->flags = 0;
72246da4
FB		 623
624 return 0;
625}
626
627/* -------------------------------------------------------------------------- */
628
629static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
630 const struct usb_endpoint_descriptor *desc)
631{
632 return -EINVAL;
633}
634
635static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
636{
637 return -EINVAL;
638}
639
640/* -------------------------------------------------------------------------- */
641
642static int dwc3_gadget_ep_enable(struct usb_ep *ep,
643 const struct usb_endpoint_descriptor *desc)
644{
645 struct dwc3_ep *dep;
646 struct dwc3 *dwc;
647 unsigned long flags;
648 int ret;
649
650 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
651 pr_debug("dwc3: invalid parameters\n");
652 return -EINVAL;
653 }
654
655 if (!desc->wMaxPacketSize) {
656 pr_debug("dwc3: missing wMaxPacketSize\n");
657 return -EINVAL;
658 }
659
660 dep = to_dwc3_ep(ep);
661 dwc = dep->dwc;
662
663 switch (usb_endpoint_type(desc)) {
664 case USB_ENDPOINT_XFER_CONTROL:
27a78d6a 665 strlcat(dep->name, "-control", sizeof(dep->name));
72246da4
FB		 666 break;
667 case USB_ENDPOINT_XFER_ISOC:
27a78d6a 668 strlcat(dep->name, "-isoc", sizeof(dep->name));
72246da4
FB		 669 break;
670 case USB_ENDPOINT_XFER_BULK:
27a78d6a 671 strlcat(dep->name, "-bulk", sizeof(dep->name));
72246da4
FB		 672 break;
673 case USB_ENDPOINT_XFER_INT:
27a78d6a 674 strlcat(dep->name, "-int", sizeof(dep->name));
72246da4
FB		 675 break;
676 default:
677 dev_err(dwc->dev, "invalid endpoint transfer type\n");
678 }
679
680 if (dep->flags & DWC3_EP_ENABLED) {
681 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
682 dep->name);
683 return 0;
684 }
685
686 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
687
688 spin_lock_irqsave(&dwc->lock, flags);
c90bfaec 689 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
72246da4
FB		 690 spin_unlock_irqrestore(&dwc->lock, flags);
691
692 return ret;
693}
694
695static int dwc3_gadget_ep_disable(struct usb_ep *ep)
696{
697 struct dwc3_ep *dep;
698 struct dwc3 *dwc;
699 unsigned long flags;
700 int ret;
701
702 if (!ep) {
703 pr_debug("dwc3: invalid parameters\n");
704 return -EINVAL;
705 }
706
707 dep = to_dwc3_ep(ep);
708 dwc = dep->dwc;
709
710 if (!(dep->flags & DWC3_EP_ENABLED)) {
711 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
712 dep->name);
713 return 0;
714 }
715
716 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
717 dep->number >> 1,
718 (dep->number & 1) ? "in" : "out");
719
720 spin_lock_irqsave(&dwc->lock, flags);
721 ret = __dwc3_gadget_ep_disable(dep);
722 spin_unlock_irqrestore(&dwc->lock, flags);
723
724 return ret;
725}
726
727static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
728 gfp_t gfp_flags)
729{
730 struct dwc3_request *req;
731 struct dwc3_ep *dep = to_dwc3_ep(ep);
732 struct dwc3 *dwc = dep->dwc;
733
734 req = kzalloc(sizeof(*req), gfp_flags);
735 if (!req) {
736 dev_err(dwc->dev, "not enough memory\n");
737 return NULL;
738 }
739
740 req->epnum = dep->number;
741 req->dep = dep;
72246da4
FB		 742
743 return &req->request;
744}
745
746static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
747 struct usb_request *request)
748{
749 struct dwc3_request *req = to_dwc3_request(request);
750
751 kfree(req);
752}
753
c71fc37c
FB		 754/**
755 * dwc3_prepare_one_trb - setup one TRB from one request
756 * @dep: endpoint for which this request is prepared
757 * @req: dwc3_request pointer
758 */
68e823e2 759static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb
FB		 760 struct dwc3_request *req, dma_addr_t dma,
761 unsigned length, unsigned last, unsigned chain)
c71fc37c 762{
eeb720fb 763 struct dwc3 *dwc = dep->dwc;
f6bafc6a 764 struct dwc3_trb *trb;
c71fc37c
FB		 765
766 unsigned int cur_slot;
767
eeb720fb
FB		 768 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
769 dep->name, req, (unsigned long long) dma,
770 length, last ? " last" : "",
771 chain ? " chain" : "");
772
f6bafc6a 773 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c
FB		 774 cur_slot = dep->free_slot;
775 dep->free_slot++;
776
777 /* Skip the LINK-TRB on ISOC */
778 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
16e78db7 779 usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 780 return;
c71fc37c 781
eeb720fb
FB		 782 if (!req->trb) {
783 dwc3_gadget_move_request_queued(req);
f6bafc6a
FB		 784 req->trb = trb;
785 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
eeb720fb 786 }
c71fc37c 787
f6bafc6a
FB		 788 trb->size = DWC3_TRB_SIZE_LENGTH(length);
789 trb->bpl = lower_32_bits(dma);
790 trb->bph = upper_32_bits(dma);
c71fc37c 791
16e78db7 792 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 793 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 794 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 795 break;
796
797 case USB_ENDPOINT_XFER_ISOC:
f6bafc6a 798 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
c71fc37c 799
206dd69a 800 if (!req->request.no_interrupt)
f6bafc6a 801 trb->ctrl |= DWC3_TRB_CTRL_IOC;
c71fc37c
FB		 802 break;
803
804 case USB_ENDPOINT_XFER_BULK:
805 case USB_ENDPOINT_XFER_INT:
f6bafc6a 806 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 807 break;
808 default:
809 /*
810 * This is only possible with faulty memory because we
811 * checked it already :)
812 */
813 BUG();
814 }
815
16e78db7 816 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
f6bafc6a
FB		 817 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
818 trb->ctrl |= DWC3_TRB_CTRL_CSP;
819 } else {
820 if (chain)
821 trb->ctrl |= DWC3_TRB_CTRL_CHN;
822
823 if (last)
824 trb->ctrl |= DWC3_TRB_CTRL_LST;
825 }
c71fc37c 826
16e78db7 827 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 828 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 829
f6bafc6a 830 trb->ctrl |= DWC3_TRB_CTRL_HWO;
c71fc37c
FB		 831}
832
72246da4
FB		 833/*
834 * dwc3_prepare_trbs - setup TRBs from requests
835 * @dep: endpoint for which requests are being prepared
836 * @starting: true if the endpoint is idle and no requests are queued.
837 *
1d046793
PZ		 838 * The function goes through the requests list and sets up TRBs for the
839 * transfers. The function returns once there are no more TRBs available or
840 * it runs out of requests.
72246da4 841 */
68e823e2 842static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 843{
68e823e2 844 struct dwc3_request *req, *n;
72246da4 845 u32 trbs_left;
8d62cd65 846 u32 max;
c71fc37c 847 unsigned int last_one = 0;
72246da4
FB		 848
849 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
850
851 /* the first request must not be queued */
852 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 853
8d62cd65 854 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 855 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 856 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
857 if (trbs_left > max)
858 trbs_left = max;
859 }
860
72246da4 861 /*
1d046793
PZ		 862 * If busy & slot are equal than it is either full or empty. If we are
863 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 864 * full and don't do anything
865 */
866 if (!trbs_left) {
867 if (!starting)
68e823e2 868 return;
72246da4
FB		 869 trbs_left = DWC3_TRB_NUM;
870 /*
871 * In case we start from scratch, we queue the ISOC requests
872 * starting from slot 1. This is done because we use ring
873 * buffer and have no LST bit to stop us. Instead, we place
1d046793 874 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 875 * after the first request so we start at slot 1 and have
876 * 7 requests proceed before we hit the first IOC.
877 * Other transfer types don't use the ring buffer and are
878 * processed from the first TRB until the last one. Since we
879 * don't wrap around we have to start at the beginning.
880 */
16e78db7 881 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 882 dep->busy_slot = 1;
883 dep->free_slot = 1;
884 } else {
885 dep->busy_slot = 0;
886 dep->free_slot = 0;
887 }
888 }
889
890 /* The last TRB is a link TRB, not used for xfer */
16e78db7 891 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 892 return;
72246da4
FB		 893
894 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 895 unsigned length;
896 dma_addr_t dma;
72246da4 897
eeb720fb
FB		 898 if (req->request.num_mapped_sgs > 0) {
899 struct usb_request *request = &req->request;
900 struct scatterlist *sg = request->sg;
901 struct scatterlist *s;
902 int i;
72246da4 903
eeb720fb
FB		 904 for_each_sg(sg, s, request->num_mapped_sgs, i) {
905 unsigned chain = true;
72246da4 906
eeb720fb
FB		 907 length = sg_dma_len(s);
908 dma = sg_dma_address(s);
72246da4 909
1d046793
PZ		 910 if (i == (request->num_mapped_sgs - 1) ||
911 sg_is_last(s)) {
eeb720fb
FB		 912 last_one = true;
913 chain = false;
914 }
72246da4 915
eeb720fb
FB		 916 trbs_left--;
917 if (!trbs_left)
918 last_one = true;
72246da4 919
eeb720fb
FB		 920 if (last_one)
921 chain = false;
72246da4 922
eeb720fb
FB		 923 dwc3_prepare_one_trb(dep, req, dma, length,
924 last_one, chain);
72246da4 925
eeb720fb
FB		 926 if (last_one)
927 break;
928 }
72246da4 929 } else {
eeb720fb
FB		 930 dma = req->request.dma;
931 length = req->request.length;
932 trbs_left--;
72246da4 933
eeb720fb
FB		 934 if (!trbs_left)
935 last_one = 1;
879631aa 936
eeb720fb
FB		 937 /* Is this the last request? */
938 if (list_is_last(&req->list, &dep->request_list))
939 last_one = 1;
72246da4 940
eeb720fb
FB		 941 dwc3_prepare_one_trb(dep, req, dma, length,
942 last_one, false);
72246da4 943
eeb720fb
FB		 944 if (last_one)
945 break;
72246da4 946 }
72246da4 947 }
72246da4
FB		 948}
949
950static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
951 int start_new)
952{
953 struct dwc3_gadget_ep_cmd_params params;
954 struct dwc3_request *req;
955 struct dwc3 *dwc = dep->dwc;
956 int ret;
957 u32 cmd;
958
959 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
960 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
961 return -EBUSY;
962 }
963 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
964
965 /*
966 * If we are getting here after a short-out-packet we don't enqueue any
967 * new requests as we try to set the IOC bit only on the last request.
968 */
969 if (start_new) {
970 if (list_empty(&dep->req_queued))
971 dwc3_prepare_trbs(dep, start_new);
972
973 /* req points to the first request which will be sent */
974 req = next_request(&dep->req_queued);
975 } else {
68e823e2
FB		 976 dwc3_prepare_trbs(dep, start_new);
977
72246da4 978 /*
1d046793 979 * req points to the first request where HWO changed from 0 to 1
72246da4 980 */
68e823e2 981 req = next_request(&dep->req_queued);
72246da4
FB		 982 }
983 if (!req) {
984 dep->flags |= DWC3_EP_PENDING_REQUEST;
985 return 0;
986 }
987
988 memset(&params, 0, sizeof(params));
dc1c70a7
FB		 989 params.param0 = upper_32_bits(req->trb_dma);
990 params.param1 = lower_32_bits(req->trb_dma);
72246da4
FB		 991
992 if (start_new)
993 cmd = DWC3_DEPCMD_STARTTRANSFER;
994 else
995 cmd = DWC3_DEPCMD_UPDATETRANSFER;
996
997 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
998 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
999 if (ret < 0) {
1000 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1001
1002 /*
1003 * FIXME we need to iterate over the list of requests
1004 * here and stop, unmap, free and del each of the linked
1d046793 1005 * requests instead of what we do now.
72246da4 1006 */
0fc9a1be
FB		 1007 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1008 req->direction);
72246da4
FB		 1009 list_del(&req->list);
1010 return ret;
1011 }
1012
1013 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1014
f898ae09 1015 if (start_new) {
b4996a86 1016 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
f898ae09 1017 dep->number);
b4996a86 1018 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1019 }
25b8ff68 1020
72246da4
FB		 1021 return 0;
1022}
1023
d6d6ec7b
PA		 1024static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1025 struct dwc3_ep *dep, u32 cur_uf)
1026{
1027 u32 uf;
1028
1029 if (list_empty(&dep->request_list)) {
1030 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1031 dep->name);
f4a53c55 1032 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1033 return;
1034 }
1035
1036 /* 4 micro frames in the future */
1037 uf = cur_uf + dep->interval * 4;
1038
1039 __dwc3_gadget_kick_transfer(dep, uf, 1);
1040}
1041
1042static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1043 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1044{
1045 u32 cur_uf, mask;
1046
1047 mask = ~(dep->interval - 1);
1048 cur_uf = event->parameters & mask;
1049
1050 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1051}
1052
72246da4
FB		 1053static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1054{
0fc9a1be
FB		 1055 struct dwc3 *dwc = dep->dwc;
1056 int ret;
1057
72246da4
FB		 1058 req->request.actual = 0;
1059 req->request.status = -EINPROGRESS;
1060 req->direction = dep->direction;
1061 req->epnum = dep->number;
1062
1063 /*
1064 * We only add to our list of requests now and
1065 * start consuming the list once we get XferNotReady
1066 * IRQ.
1067 *
1068 * That way, we avoid doing anything that we don't need
1069 * to do now and defer it until the point we receive a
1070 * particular token from the Host side.
1071 *
1072 * This will also avoid Host cancelling URBs due to too
1d046793 1073 * many NAKs.
72246da4 1074 */
0fc9a1be
FB		 1075 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1076 dep->direction);
1077 if (ret)
1078 return ret;
1079
72246da4
FB		 1080 list_add_tail(&req->list, &dep->request_list);
1081
1082 /*
b511e5e7 1083 * There are a few special cases:
72246da4 1084 *
f898ae09
PZ		 1085 * 1. XferNotReady with empty list of requests. We need to kick the
1086 * transfer here in that situation, otherwise we will be NAKing
1087 * forever. If we get XferNotReady before gadget driver has a
1088 * chance to queue a request, we will ACK the IRQ but won't be
1089 * able to receive the data until the next request is queued.
1090 * The following code is handling exactly that.
72246da4 1091 *
72246da4
FB		 1092 */
1093 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f898ae09 1094 int ret;
72246da4 1095
f4a53c55
PA		 1096 /*
1097 * If xfernotready is already elapsed and it is a case
1098 * of isoc transfer, then issue END TRANSFER, so that
1099 * you can receive xfernotready again and can have
1100 * notion of current microframe.
1101 */
1102 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1103 dwc3_stop_active_transfer(dwc, dep->number);
1104 return 0;
1105 }
1106
b511e5e7
FB		 1107 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1108 if (ret && ret != -EBUSY) {
1109 struct dwc3 *dwc = dep->dwc;
1110
1111 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1112 dep->name);
f898ae09 1113 }
b511e5e7 1114 }
72246da4 1115
b511e5e7
FB		 1116 /*
1117 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1118 * kick the transfer here after queuing a request, otherwise the
1119 * core may not see the modified TRB(s).
1120 */
1121 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1122 (dep->flags & DWC3_EP_BUSY)) {
b4996a86
FB		 1123 WARN_ON_ONCE(!dep->resource_index);
1124 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
b511e5e7 1125 false);
72246da4
FB		 1126 if (ret && ret != -EBUSY) {
1127 struct dwc3 *dwc = dep->dwc;
1128
1129 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1130 dep->name);
1131 }
a0925324 1132 }
72246da4 1133
b511e5e7
FB		 1134 /*
1135 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved
1136 * uframe number.
1137 */
1138 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1139 (dep->flags & DWC3_EP_MISSED_ISOC)) {
1140 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1141 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1142 }
72246da4
FB		 1143
1144 return 0;
1145}
1146
1147static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1148 gfp_t gfp_flags)
1149{
1150 struct dwc3_request *req = to_dwc3_request(request);
1151 struct dwc3_ep *dep = to_dwc3_ep(ep);
1152 struct dwc3 *dwc = dep->dwc;
1153
1154 unsigned long flags;
1155
1156 int ret;
1157
16e78db7 1158 if (!dep->endpoint.desc) {
72246da4
FB		 1159 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1160 request, ep->name);
1161 return -ESHUTDOWN;
1162 }
1163
1164 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1165 request, ep->name, request->length);
1166
1167 spin_lock_irqsave(&dwc->lock, flags);
1168 ret = __dwc3_gadget_ep_queue(dep, req);
1169 spin_unlock_irqrestore(&dwc->lock, flags);
1170
1171 return ret;
1172}
1173
1174static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1175 struct usb_request *request)
1176{
1177 struct dwc3_request *req = to_dwc3_request(request);
1178 struct dwc3_request *r = NULL;
1179
1180 struct dwc3_ep *dep = to_dwc3_ep(ep);
1181 struct dwc3 *dwc = dep->dwc;
1182
1183 unsigned long flags;
1184 int ret = 0;
1185
1186 spin_lock_irqsave(&dwc->lock, flags);
1187
1188 list_for_each_entry(r, &dep->request_list, list) {
1189 if (r == req)
1190 break;
1191 }
1192
1193 if (r != req) {
1194 list_for_each_entry(r, &dep->req_queued, list) {
1195 if (r == req)
1196 break;
1197 }
1198 if (r == req) {
1199 /* wait until it is processed */
1200 dwc3_stop_active_transfer(dwc, dep->number);
e8d4e8be 1201 goto out1;
72246da4
FB		 1202 }
1203 dev_err(dwc->dev, "request %p was not queued to %s\n",
1204 request, ep->name);
1205 ret = -EINVAL;
1206 goto out0;
1207 }
1208
e8d4e8be 1209out1:
72246da4
FB		 1210 /* giveback the request */
1211 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1212
1213out0:
1214 spin_unlock_irqrestore(&dwc->lock, flags);
1215
1216 return ret;
1217}
1218
1219int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1220{
1221 struct dwc3_gadget_ep_cmd_params params;
1222 struct dwc3 *dwc = dep->dwc;
1223 int ret;
1224
1225 memset(&params, 0x00, sizeof(params));
1226
1227 if (value) {
72246da4
FB		 1228 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1229 DWC3_DEPCMD_SETSTALL, &params);
1230 if (ret)
1231 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1232 value ? "set" : "clear",
1233 dep->name);
1234 else
1235 dep->flags |= DWC3_EP_STALL;
1236 } else {
5275455a
PZ		 1237 if (dep->flags & DWC3_EP_WEDGE)
1238 return 0;
1239
72246da4
FB		 1240 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1241 DWC3_DEPCMD_CLEARSTALL, &params);
1242 if (ret)
1243 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1244 value ? "set" : "clear",
1245 dep->name);
1246 else
1247 dep->flags &= ~DWC3_EP_STALL;
1248 }
5275455a 1249
72246da4
FB		 1250 return ret;
1251}
1252
1253static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1254{
1255 struct dwc3_ep *dep = to_dwc3_ep(ep);
1256 struct dwc3 *dwc = dep->dwc;
1257
1258 unsigned long flags;
1259
1260 int ret;
1261
1262 spin_lock_irqsave(&dwc->lock, flags);
1263
16e78db7 1264 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1265 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1266 ret = -EINVAL;
1267 goto out;
1268 }
1269
1270 ret = __dwc3_gadget_ep_set_halt(dep, value);
1271out:
1272 spin_unlock_irqrestore(&dwc->lock, flags);
1273
1274 return ret;
1275}
1276
1277static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1278{
1279 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1280 struct dwc3 *dwc = dep->dwc;
1281 unsigned long flags;
72246da4 1282
249a4569 1283 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1284 dep->flags |= DWC3_EP_WEDGE;
249a4569 1285 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4 1286
08f0d966
PA		 1287 if (dep->number == 0 || dep->number == 1)
1288 return dwc3_gadget_ep0_set_halt(ep, 1);
1289 else
1290 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 1291}
1292
1293/* -------------------------------------------------------------------------- */
1294
1295static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1296 .bLength = USB_DT_ENDPOINT_SIZE,
1297 .bDescriptorType = USB_DT_ENDPOINT,
1298 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1299};
1300
1301static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1302 .enable = dwc3_gadget_ep0_enable,
1303 .disable = dwc3_gadget_ep0_disable,
1304 .alloc_request = dwc3_gadget_ep_alloc_request,
1305 .free_request = dwc3_gadget_ep_free_request,
1306 .queue = dwc3_gadget_ep0_queue,
1307 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1308 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1309 .set_wedge = dwc3_gadget_ep_set_wedge,
1310};
1311
1312static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1313 .enable = dwc3_gadget_ep_enable,
1314 .disable = dwc3_gadget_ep_disable,
1315 .alloc_request = dwc3_gadget_ep_alloc_request,
1316 .free_request = dwc3_gadget_ep_free_request,
1317 .queue = dwc3_gadget_ep_queue,
1318 .dequeue = dwc3_gadget_ep_dequeue,
1319 .set_halt = dwc3_gadget_ep_set_halt,
1320 .set_wedge = dwc3_gadget_ep_set_wedge,
1321};
1322
1323/* -------------------------------------------------------------------------- */
1324
1325static int dwc3_gadget_get_frame(struct usb_gadget *g)
1326{
1327 struct dwc3 *dwc = gadget_to_dwc(g);
1328 u32 reg;
1329
1330 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1331 return DWC3_DSTS_SOFFN(reg);
1332}
1333
1334static int dwc3_gadget_wakeup(struct usb_gadget *g)
1335{
1336 struct dwc3 *dwc = gadget_to_dwc(g);
1337
1338 unsigned long timeout;
1339 unsigned long flags;
1340
1341 u32 reg;
1342
1343 int ret = 0;
1344
1345 u8 link_state;
1346 u8 speed;
1347
1348 spin_lock_irqsave(&dwc->lock, flags);
1349
1350 /*
1351 * According to the Databook Remote wakeup request should
1352 * be issued only when the device is in early suspend state.
1353 *
1354 * We can check that via USB Link State bits in DSTS register.
1355 */
1356 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1357
1358 speed = reg & DWC3_DSTS_CONNECTSPD;
1359 if (speed == DWC3_DSTS_SUPERSPEED) {
1360 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1361 ret = -EINVAL;
1362 goto out;
1363 }
1364
1365 link_state = DWC3_DSTS_USBLNKST(reg);
1366
1367 switch (link_state) {
1368 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1369 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1370 break;
1371 default:
1372 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1373 link_state);
1374 ret = -EINVAL;
1375 goto out;
1376 }
1377
8598bde7
FB		 1378 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1379 if (ret < 0) {
1380 dev_err(dwc->dev, "failed to put link in Recovery\n");
1381 goto out;
1382 }
72246da4 1383
802fde98
PZ		 1384 /* Recent versions do this automatically */
1385 if (dwc->revision < DWC3_REVISION_194A) {
1386 /* write zeroes to Link Change Request */
fcc023c7 1387 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1388 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1389 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1390 }
72246da4 1391
1d046793 1392 /* poll until Link State changes to ON */
72246da4
FB		 1393 timeout = jiffies + msecs_to_jiffies(100);
1394
1d046793 1395 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1396 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1397
1398 /* in HS, means ON */
1399 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1400 break;
1401 }
1402
1403 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1404 dev_err(dwc->dev, "failed to send remote wakeup\n");
1405 ret = -EINVAL;
1406 }
1407
1408out:
1409 spin_unlock_irqrestore(&dwc->lock, flags);
1410
1411 return ret;
1412}
1413
1414static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1415 int is_selfpowered)
1416{
1417 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1418 unsigned long flags;
72246da4 1419
249a4569 1420 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1421 dwc->is_selfpowered = !!is_selfpowered;
249a4569 1422 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1423
1424 return 0;
1425}
1426
6f17f74b 1427static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
72246da4
FB		 1428{
1429 u32 reg;
61d58242 1430 u32 timeout = 500;
72246da4
FB		 1431
1432 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1433 if (is_on) {
802fde98
PZ		 1434 if (dwc->revision <= DWC3_REVISION_187A) {
1435 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1436 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1437 }
1438
1439 if (dwc->revision >= DWC3_REVISION_194A)
1440 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1441 reg |= DWC3_DCTL_RUN_STOP;
8db7ed15 1442 } else {
72246da4 1443 reg &= ~DWC3_DCTL_RUN_STOP;
8db7ed15 1444 }
72246da4
FB		 1445
1446 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1447
1448 do {
1449 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1450 if (is_on) {
1451 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1452 break;
1453 } else {
1454 if (reg & DWC3_DSTS_DEVCTRLHLT)
1455 break;
1456 }
72246da4
FB		 1457 timeout--;
1458 if (!timeout)
6f17f74b 1459 return -ETIMEDOUT;
61d58242 1460 udelay(1);
72246da4
FB		 1461 } while (1);
1462
1463 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1464 dwc->gadget_driver
1465 ? dwc->gadget_driver->function : "no-function",
1466 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1467
1468 return 0;
72246da4
FB		 1469}
1470
1471static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1472{
1473 struct dwc3 *dwc = gadget_to_dwc(g);
1474 unsigned long flags;
6f17f74b 1475 int ret;
72246da4
FB		 1476
1477 is_on = !!is_on;
1478
1479 spin_lock_irqsave(&dwc->lock, flags);
6f17f74b 1480 ret = dwc3_gadget_run_stop(dwc, is_on);
72246da4
FB		 1481 spin_unlock_irqrestore(&dwc->lock, flags);
1482
6f17f74b 1483 return ret;
72246da4
FB		 1484}
1485
1486static int dwc3_gadget_start(struct usb_gadget *g,
1487 struct usb_gadget_driver *driver)
1488{
1489 struct dwc3 *dwc = gadget_to_dwc(g);
1490 struct dwc3_ep *dep;
1491 unsigned long flags;
1492 int ret = 0;
1493 u32 reg;
1494
1495 spin_lock_irqsave(&dwc->lock, flags);
1496
1497 if (dwc->gadget_driver) {
1498 dev_err(dwc->dev, "%s is already bound to %s\n",
1499 dwc->gadget.name,
1500 dwc->gadget_driver->driver.name);
1501 ret = -EBUSY;
1502 goto err0;
1503 }
1504
1505 dwc->gadget_driver = driver;
1506 dwc->gadget.dev.driver = &driver->driver;
1507
72246da4
FB		 1508 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1509 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1510
1511 /**
1512 * WORKAROUND: DWC3 revision < 2.20a have an issue
1513 * which would cause metastability state on Run/Stop
1514 * bit if we try to force the IP to USB2-only mode.
1515 *
1516 * Because of that, we cannot configure the IP to any
1517 * speed other than the SuperSpeed
1518 *
1519 * Refers to:
1520 *
1521 * STAR#9000525659: Clock Domain Crossing on DCTL in
1522 * USB 2.0 Mode
1523 */
1524 if (dwc->revision < DWC3_REVISION_220A)
1525 reg |= DWC3_DCFG_SUPERSPEED;
1526 else
1527 reg |= dwc->maximum_speed;
72246da4
FB		 1528 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1529
b23c8439
PZ		 1530 dwc->start_config_issued = false;
1531
72246da4
FB		 1532 /* Start with SuperSpeed Default */
1533 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1534
1535 dep = dwc->eps[0];
c90bfaec 1536 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1537 if (ret) {
1538 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1539 goto err0;
1540 }
1541
1542 dep = dwc->eps[1];
c90bfaec 1543 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1544 if (ret) {
1545 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1546 goto err1;
1547 }
1548
1549 /* begin to receive SETUP packets */
c7fcdeb2 1550 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1551 dwc3_ep0_out_start(dwc);
1552
1553 spin_unlock_irqrestore(&dwc->lock, flags);
1554
1555 return 0;
1556
1557err1:
1558 __dwc3_gadget_ep_disable(dwc->eps[0]);
1559
1560err0:
1561 spin_unlock_irqrestore(&dwc->lock, flags);
1562
1563 return ret;
1564}
1565
1566static int dwc3_gadget_stop(struct usb_gadget *g,
1567 struct usb_gadget_driver *driver)
1568{
1569 struct dwc3 *dwc = gadget_to_dwc(g);
1570 unsigned long flags;
1571
1572 spin_lock_irqsave(&dwc->lock, flags);
1573
1574 __dwc3_gadget_ep_disable(dwc->eps[0]);
1575 __dwc3_gadget_ep_disable(dwc->eps[1]);
1576
1577 dwc->gadget_driver = NULL;
1578 dwc->gadget.dev.driver = NULL;
1579
1580 spin_unlock_irqrestore(&dwc->lock, flags);
1581
1582 return 0;
1583}
802fde98 1584
72246da4
FB		 1585static const struct usb_gadget_ops dwc3_gadget_ops = {
1586 .get_frame = dwc3_gadget_get_frame,
1587 .wakeup = dwc3_gadget_wakeup,
1588 .set_selfpowered = dwc3_gadget_set_selfpowered,
1589 .pullup = dwc3_gadget_pullup,
1590 .udc_start = dwc3_gadget_start,
1591 .udc_stop = dwc3_gadget_stop,
1592};
1593
1594/* -------------------------------------------------------------------------- */
1595
1596static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1597{
1598 struct dwc3_ep *dep;
1599 u8 epnum;
1600
1601 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1602
1603 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1604 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1605 if (!dep) {
1606 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1607 epnum);
1608 return -ENOMEM;
1609 }
1610
1611 dep->dwc = dwc;
1612 dep->number = epnum;
1613 dwc->eps[epnum] = dep;
1614
1615 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1616 (epnum & 1) ? "in" : "out");
1617 dep->endpoint.name = dep->name;
1618 dep->direction = (epnum & 1);
1619
1620 if (epnum == 0 || epnum == 1) {
1621 dep->endpoint.maxpacket = 512;
1622 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1623 if (!epnum)
1624 dwc->gadget.ep0 = &dep->endpoint;
1625 } else {
1626 int ret;
1627
1628 dep->endpoint.maxpacket = 1024;
12d36c16 1629 dep->endpoint.max_streams = 15;
72246da4
FB		 1630 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1631 list_add_tail(&dep->endpoint.ep_list,
1632 &dwc->gadget.ep_list);
1633
1634 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1635 if (ret)
72246da4 1636 return ret;
72246da4 1637 }
25b8ff68 1638
72246da4
FB		 1639 INIT_LIST_HEAD(&dep->request_list);
1640 INIT_LIST_HEAD(&dep->req_queued);
1641 }
1642
1643 return 0;
1644}
1645
1646static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1647{
1648 struct dwc3_ep *dep;
1649 u8 epnum;
1650
1651 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1652 dep = dwc->eps[epnum];
1653 dwc3_free_trb_pool(dep);
1654
1655 if (epnum != 0 && epnum != 1)
1656 list_del(&dep->endpoint.ep_list);
1657
1658 kfree(dep);
1659 }
1660}
1661
1662static void dwc3_gadget_release(struct device *dev)
1663{
1664 dev_dbg(dev, "%s\n", __func__);
1665}
1666
1667/* -------------------------------------------------------------------------- */
1668static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1669 const struct dwc3_event_depevt *event, int status)
1670{
1671 struct dwc3_request *req;
f6bafc6a 1672 struct dwc3_trb *trb;
72246da4
FB		 1673 unsigned int count;
1674 unsigned int s_pkt = 0;
d6d6ec7b 1675 unsigned int trb_status;
72246da4
FB		 1676
1677 do {
1678 req = next_request(&dep->req_queued);
d39ee7be
SAS		 1679 if (!req) {
1680 WARN_ON_ONCE(1);
1681 return 1;
1682 }
72246da4 1683
f6bafc6a 1684 trb = req->trb;
72246da4 1685
f6bafc6a 1686 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
0d2f4758
SAS		 1687 /*
1688 * We continue despite the error. There is not much we
1d046793
PZ		 1689 * can do. If we don't clean it up we loop forever. If
1690 * we skip the TRB then it gets overwritten after a
1691 * while since we use them in a ring buffer. A BUG()
1692 * would help. Lets hope that if this occurs, someone
0d2f4758
SAS		 1693 * fixes the root cause instead of looking away :)
1694 */
72246da4
FB		 1695 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1696 dep->name, req->trb);
f6bafc6a 1697 count = trb->size & DWC3_TRB_SIZE_MASK;
72246da4
FB		 1698
1699 if (dep->direction) {
1700 if (count) {
d6d6ec7b
PA		 1701 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1702 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1703 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1704 dep->name);
1705 dep->current_uf = event->parameters &
1706 ~(dep->interval - 1);
1707 dep->flags |= DWC3_EP_MISSED_ISOC;
1708 } else {
1709 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1710 dep->name);
1711 status = -ECONNRESET;
1712 }
72246da4
FB		 1713 }
1714 } else {
1715 if (count && (event->status & DEPEVT_STATUS_SHORT))
1716 s_pkt = 1;
1717 }
1718
1719 /*
1720 * We assume here we will always receive the entire data block
1721 * which we should receive. Meaning, if we program RX to
1722 * receive 4K but we receive only 2K, we assume that's all we
1723 * should receive and we simply bounce the request back to the
1724 * gadget driver for further processing.
1725 */
1726 req->request.actual += req->request.length - count;
1727 dwc3_gadget_giveback(dep, req, status);
1728 if (s_pkt)
1729 break;
f6bafc6a 1730 if ((event->status & DEPEVT_STATUS_LST) &&
70b674bf
PA		 1731 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1732 DWC3_TRB_CTRL_HWO)))
72246da4 1733 break;
f6bafc6a
FB		 1734 if ((event->status & DEPEVT_STATUS_IOC) &&
1735 (trb->ctrl & DWC3_TRB_CTRL_IOC))
72246da4
FB		 1736 break;
1737 } while (1);
1738
f6bafc6a
FB		 1739 if ((event->status & DEPEVT_STATUS_IOC) &&
1740 (trb->ctrl & DWC3_TRB_CTRL_IOC))
72246da4
FB		 1741 return 0;
1742 return 1;
1743}
1744
1745static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1746 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1747 int start_new)
1748{
1749 unsigned status = 0;
1750 int clean_busy;
1751
1752 if (event->status & DEPEVT_STATUS_BUSERR)
1753 status = -ECONNRESET;
1754
1d046793 1755 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
c2df85ca 1756 if (clean_busy)
72246da4 1757 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 1758
1759 /*
1760 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1761 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1762 */
1763 if (dwc->revision < DWC3_REVISION_183A) {
1764 u32 reg;
1765 int i;
1766
1767 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1768 struct dwc3_ep *dep = dwc->eps[i];
1769
1770 if (!(dep->flags & DWC3_EP_ENABLED))
1771 continue;
1772
1773 if (!list_empty(&dep->req_queued))
1774 return;
1775 }
1776
1777 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1778 reg |= dwc->u1u2;
1779 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1780
1781 dwc->u1u2 = 0;
1782 }
72246da4
FB		 1783}
1784
72246da4
FB		 1785static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1786 const struct dwc3_event_depevt *event)
1787{
1788 struct dwc3_ep *dep;
1789 u8 epnum = event->endpoint_number;
1790
1791 dep = dwc->eps[epnum];
1792
3336abb5
FB		 1793 if (!(dep->flags & DWC3_EP_ENABLED))
1794 return;
1795
72246da4
FB		 1796 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1797 dwc3_ep_event_string(event->endpoint_event));
1798
1799 if (epnum == 0 || epnum == 1) {
1800 dwc3_ep0_interrupt(dwc, event);
1801 return;
1802 }
1803
1804 switch (event->endpoint_event) {
1805 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 1806 dep->resource_index = 0;
c2df85ca 1807
16e78db7 1808 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1809 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1810 dep->name);
1811 return;
1812 }
1813
1814 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1815 break;
1816 case DWC3_DEPEVT_XFERINPROGRESS:
16e78db7 1817 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1818 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1819 dep->name);
1820 return;
1821 }
1822
1823 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1824 break;
1825 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 1826 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1827 dwc3_gadget_start_isoc(dwc, dep, event);
1828 } else {
1829 int ret;
1830
1831 dev_vdbg(dwc->dev, "%s: reason %s\n",
40aa41fb
FB		 1832 dep->name, event->status &
1833 DEPEVT_STATUS_TRANSFER_ACTIVE
72246da4
FB		 1834 ? "Transfer Active"
1835 : "Transfer Not Active");
1836
1837 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1838 if (!ret || ret == -EBUSY)
1839 return;
1840
1841 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1842 dep->name);
1843 }
1844
879631aa
FB		 1845 break;
1846 case DWC3_DEPEVT_STREAMEVT:
16e78db7 1847 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 1848 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1849 dep->name);
1850 return;
1851 }
1852
1853 switch (event->status) {
1854 case DEPEVT_STREAMEVT_FOUND:
1855 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1856 event->parameters);
1857
1858 break;
1859 case DEPEVT_STREAMEVT_NOTFOUND:
1860 /* FALLTHROUGH */
1861 default:
1862 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1863 }
72246da4
FB		 1864 break;
1865 case DWC3_DEPEVT_RXTXFIFOEVT:
1866 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1867 break;
72246da4 1868 case DWC3_DEPEVT_EPCMDCMPLT:
ea53b882 1869 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
72246da4
FB		 1870 break;
1871 }
1872}
1873
1874static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1875{
1876 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1877 spin_unlock(&dwc->lock);
1878 dwc->gadget_driver->disconnect(&dwc->gadget);
1879 spin_lock(&dwc->lock);
1880 }
1881}
1882
1883static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1884{
1885 struct dwc3_ep *dep;
1886 struct dwc3_gadget_ep_cmd_params params;
1887 u32 cmd;
1888 int ret;
1889
1890 dep = dwc->eps[epnum];
1891
b4996a86 1892 if (!dep->resource_index)
3daf74d7
PA		 1893 return;
1894
1895 cmd = DWC3_DEPCMD_ENDTRANSFER;
1896 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
b4996a86 1897 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7
PA		 1898 memset(&params, 0, sizeof(params));
1899 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1900 WARN_ON_ONCE(ret);
b4996a86 1901 dep->resource_index = 0;
72246da4
FB		 1902}
1903
1904static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1905{
1906 u32 epnum;
1907
1908 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1909 struct dwc3_ep *dep;
1910
1911 dep = dwc->eps[epnum];
1912 if (!(dep->flags & DWC3_EP_ENABLED))
1913 continue;
1914
624407f9 1915 dwc3_remove_requests(dwc, dep);
72246da4
FB		 1916 }
1917}
1918
1919static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1920{
1921 u32 epnum;
1922
1923 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1924 struct dwc3_ep *dep;
1925 struct dwc3_gadget_ep_cmd_params params;
1926 int ret;
1927
1928 dep = dwc->eps[epnum];
1929
1930 if (!(dep->flags & DWC3_EP_STALL))
1931 continue;
1932
1933 dep->flags &= ~DWC3_EP_STALL;
1934
1935 memset(&params, 0, sizeof(params));
1936 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1937 DWC3_DEPCMD_CLEARSTALL, &params);
1938 WARN_ON_ONCE(ret);
1939 }
1940}
1941
1942static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1943{
c4430a26
FB		 1944 int reg;
1945
72246da4 1946 dev_vdbg(dwc->dev, "%s\n", __func__);
72246da4
FB		 1947
1948 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1949 reg &= ~DWC3_DCTL_INITU1ENA;
1950 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1951
1952 reg &= ~DWC3_DCTL_INITU2ENA;
1953 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 1954
72246da4 1955 dwc3_disconnect_gadget(dwc);
b23c8439 1956 dwc->start_config_issued = false;
72246da4
FB		 1957
1958 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 1959 dwc->setup_packet_pending = false;
72246da4
FB		 1960}
1961
d7a46a8d 1962static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 1963{
1964 u32 reg;
1965
1966 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1967
d7a46a8d 1968 if (suspend)
72246da4 1969 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
d7a46a8d
PZ		 1970 else
1971 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
72246da4
FB		 1972
1973 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1974}
1975
d7a46a8d 1976static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 1977{
1978 u32 reg;
1979
1980 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1981
d7a46a8d 1982 if (suspend)
72246da4 1983 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
d7a46a8d
PZ		 1984 else
1985 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
72246da4
FB		 1986
1987 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1988}
1989
1990static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1991{
1992 u32 reg;
1993
1994 dev_vdbg(dwc->dev, "%s\n", __func__);
1995
df62df56
FB		 1996 /*
1997 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1998 * would cause a missing Disconnect Event if there's a
1999 * pending Setup Packet in the FIFO.
2000 *
2001 * There's no suggested workaround on the official Bug
2002 * report, which states that "unless the driver/application
2003 * is doing any special handling of a disconnect event,
2004 * there is no functional issue".
2005 *
2006 * Unfortunately, it turns out that we _do_ some special
2007 * handling of a disconnect event, namely complete all
2008 * pending transfers, notify gadget driver of the
2009 * disconnection, and so on.
2010 *
2011 * Our suggested workaround is to follow the Disconnect
2012 * Event steps here, instead, based on a setup_packet_pending
2013 * flag. Such flag gets set whenever we have a XferNotReady
2014 * event on EP0 and gets cleared on XferComplete for the
2015 * same endpoint.
2016 *
2017 * Refers to:
2018 *
2019 * STAR#9000466709: RTL: Device : Disconnect event not
2020 * generated if setup packet pending in FIFO
2021 */
2022 if (dwc->revision < DWC3_REVISION_188A) {
2023 if (dwc->setup_packet_pending)
2024 dwc3_gadget_disconnect_interrupt(dwc);
2025 }
2026
961906ed
FB		 2027 /* after reset -> Default State */
2028 dwc->dev_state = DWC3_DEFAULT_STATE;
2029
802fde98
PZ		 2030 /* Recent versions support automatic phy suspend and don't need this */
2031 if (dwc->revision < DWC3_REVISION_194A) {
2032 /* Resume PHYs */
2033 dwc3_gadget_usb2_phy_suspend(dwc, false);
2034 dwc3_gadget_usb3_phy_suspend(dwc, false);
2035 }
72246da4
FB		 2036
2037 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2038 dwc3_disconnect_gadget(dwc);
2039
2040 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2041 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2042 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2043 dwc->test_mode = false;
72246da4
FB		 2044
2045 dwc3_stop_active_transfers(dwc);
2046 dwc3_clear_stall_all_ep(dwc);
b23c8439 2047 dwc->start_config_issued = false;
72246da4
FB		 2048
2049 /* Reset device address to zero */
2050 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2051 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2052 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2053}
2054
2055static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2056{
2057 u32 reg;
2058 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2059
2060 /*
2061 * We change the clock only at SS but I dunno why I would want to do
2062 * this. Maybe it becomes part of the power saving plan.
2063 */
2064
2065 if (speed != DWC3_DSTS_SUPERSPEED)
2066 return;
2067
2068 /*
2069 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2070 * each time on Connect Done.
2071 */
2072 if (!usb30_clock)
2073 return;
2074
2075 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2076 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2077 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2078}
2079
d7a46a8d 2080static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
72246da4
FB		 2081{
2082 switch (speed) {
2083 case USB_SPEED_SUPER:
d7a46a8d 2084 dwc3_gadget_usb2_phy_suspend(dwc, true);
72246da4
FB		 2085 break;
2086 case USB_SPEED_HIGH:
2087 case USB_SPEED_FULL:
2088 case USB_SPEED_LOW:
d7a46a8d 2089 dwc3_gadget_usb3_phy_suspend(dwc, true);
72246da4
FB		 2090 break;
2091 }
2092}
2093
2094static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2095{
2096 struct dwc3_gadget_ep_cmd_params params;
2097 struct dwc3_ep *dep;
2098 int ret;
2099 u32 reg;
2100 u8 speed;
2101
2102 dev_vdbg(dwc->dev, "%s\n", __func__);
2103
2104 memset(&params, 0x00, sizeof(params));
2105
72246da4
FB		 2106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2107 speed = reg & DWC3_DSTS_CONNECTSPD;
2108 dwc->speed = speed;
2109
2110 dwc3_update_ram_clk_sel(dwc, speed);
2111
2112 switch (speed) {
2113 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2114 /*
2115 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2116 * would cause a missing USB3 Reset event.
2117 *
2118 * In such situations, we should force a USB3 Reset
2119 * event by calling our dwc3_gadget_reset_interrupt()
2120 * routine.
2121 *
2122 * Refers to:
2123 *
2124 * STAR#9000483510: RTL: SS : USB3 reset event may
2125 * not be generated always when the link enters poll
2126 */
2127 if (dwc->revision < DWC3_REVISION_190A)
2128 dwc3_gadget_reset_interrupt(dwc);
2129
72246da4
FB		 2130 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2131 dwc->gadget.ep0->maxpacket = 512;
2132 dwc->gadget.speed = USB_SPEED_SUPER;
2133 break;
2134 case DWC3_DCFG_HIGHSPEED:
2135 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2136 dwc->gadget.ep0->maxpacket = 64;
2137 dwc->gadget.speed = USB_SPEED_HIGH;
2138 break;
2139 case DWC3_DCFG_FULLSPEED2:
2140 case DWC3_DCFG_FULLSPEED1:
2141 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2142 dwc->gadget.ep0->maxpacket = 64;
2143 dwc->gadget.speed = USB_SPEED_FULL;
2144 break;
2145 case DWC3_DCFG_LOWSPEED:
2146 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2147 dwc->gadget.ep0->maxpacket = 8;
2148 dwc->gadget.speed = USB_SPEED_LOW;
2149 break;
2150 }
2151
802fde98
PZ		 2152 /* Recent versions support automatic phy suspend and don't need this */
2153 if (dwc->revision < DWC3_REVISION_194A) {
2154 /* Suspend unneeded PHY */
2155 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2156 }
72246da4
FB		 2157
2158 dep = dwc->eps[0];
c90bfaec 2159 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 2160 if (ret) {
2161 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2162 return;
2163 }
2164
2165 dep = dwc->eps[1];
c90bfaec 2166 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 2167 if (ret) {
2168 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2169 return;
2170 }
2171
2172 /*
2173 * Configure PHY via GUSB3PIPECTLn if required.
2174 *
2175 * Update GTXFIFOSIZn
2176 *
2177 * In both cases reset values should be sufficient.
2178 */
2179}
2180
2181static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2182{
2183 dev_vdbg(dwc->dev, "%s\n", __func__);
2184
2185 /*
2186 * TODO take core out of low power mode when that's
2187 * implemented.
2188 */
2189
2190 dwc->gadget_driver->resume(&dwc->gadget);
2191}
2192
2193static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2194 unsigned int evtinfo)
2195{
fae2b904
FB		 2196 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2197
2198 /*
2199 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2200 * on the link partner, the USB session might do multiple entry/exit
2201 * of low power states before a transfer takes place.
2202 *
2203 * Due to this problem, we might experience lower throughput. The
2204 * suggested workaround is to disable DCTL[12:9] bits if we're
2205 * transitioning from U1/U2 to U0 and enable those bits again
2206 * after a transfer completes and there are no pending transfers
2207 * on any of the enabled endpoints.
2208 *
2209 * This is the first half of that workaround.
2210 *
2211 * Refers to:
2212 *
2213 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2214 * core send LGO_Ux entering U0
2215 */
2216 if (dwc->revision < DWC3_REVISION_183A) {
2217 if (next == DWC3_LINK_STATE_U0) {
2218 u32 u1u2;
2219 u32 reg;
2220
2221 switch (dwc->link_state) {
2222 case DWC3_LINK_STATE_U1:
2223 case DWC3_LINK_STATE_U2:
2224 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2225 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2226 | DWC3_DCTL_ACCEPTU2ENA
2227 | DWC3_DCTL_INITU1ENA
2228 | DWC3_DCTL_ACCEPTU1ENA);
2229
2230 if (!dwc->u1u2)
2231 dwc->u1u2 = reg & u1u2;
2232
2233 reg &= ~u1u2;
2234
2235 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2236 break;
2237 default:
2238 /* do nothing */
2239 break;
2240 }
2241 }
2242 }
2243
2244 dwc->link_state = next;
019ac832
FB		 2245
2246 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 2247}
2248
2249static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2250 const struct dwc3_event_devt *event)
2251{
2252 switch (event->type) {
2253 case DWC3_DEVICE_EVENT_DISCONNECT:
2254 dwc3_gadget_disconnect_interrupt(dwc);
2255 break;
2256 case DWC3_DEVICE_EVENT_RESET:
2257 dwc3_gadget_reset_interrupt(dwc);
2258 break;
2259 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2260 dwc3_gadget_conndone_interrupt(dwc);
2261 break;
2262 case DWC3_DEVICE_EVENT_WAKEUP:
2263 dwc3_gadget_wakeup_interrupt(dwc);
2264 break;
2265 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2266 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2267 break;
2268 case DWC3_DEVICE_EVENT_EOPF:
2269 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2270 break;
2271 case DWC3_DEVICE_EVENT_SOF:
2272 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2273 break;
2274 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2275 dev_vdbg(dwc->dev, "Erratic Error\n");
2276 break;
2277 case DWC3_DEVICE_EVENT_CMD_CMPL:
2278 dev_vdbg(dwc->dev, "Command Complete\n");
2279 break;
2280 case DWC3_DEVICE_EVENT_OVERFLOW:
2281 dev_vdbg(dwc->dev, "Overflow\n");
2282 break;
2283 default:
2284 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2285 }
2286}
2287
2288static void dwc3_process_event_entry(struct dwc3 *dwc,
2289 const union dwc3_event *event)
2290{
2291 /* Endpoint IRQ, handle it and return early */
2292 if (event->type.is_devspec == 0) {
2293 /* depevt */
2294 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2295 }
2296
2297 switch (event->type.type) {
2298 case DWC3_EVENT_TYPE_DEV:
2299 dwc3_gadget_interrupt(dwc, &event->devt);
2300 break;
2301 /* REVISIT what to do with Carkit and I2C events ? */
2302 default:
2303 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2304 }
2305}
2306
2307static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2308{
2309 struct dwc3_event_buffer *evt;
2310 int left;
2311 u32 count;
2312
2313 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2314 count &= DWC3_GEVNTCOUNT_MASK;
2315 if (!count)
2316 return IRQ_NONE;
2317
2318 evt = dwc->ev_buffs[buf];
2319 left = count;
2320
2321 while (left > 0) {
2322 union dwc3_event event;
2323
d70d8442
FB		 2324 event.raw = *(u32 *) (evt->buf + evt->lpos);
2325
72246da4
FB		 2326 dwc3_process_event_entry(dwc, &event);
2327 /*
2328 * XXX we wrap around correctly to the next entry as almost all
2329 * entries are 4 bytes in size. There is one entry which has 12
2330 * bytes which is a regular entry followed by 8 bytes data. ATM
2331 * I don't know how things are organized if were get next to the
2332 * a boundary so I worry about that once we try to handle that.
2333 */
2334 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2335 left -= 4;
2336
2337 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2338 }
2339
2340 return IRQ_HANDLED;
2341}
2342
2343static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2344{
2345 struct dwc3 *dwc = _dwc;
2346 int i;
2347 irqreturn_t ret = IRQ_NONE;
2348
2349 spin_lock(&dwc->lock);
2350
9f622b2a 2351 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2352 irqreturn_t status;
2353
2354 status = dwc3_process_event_buf(dwc, i);
2355 if (status == IRQ_HANDLED)
2356 ret = status;
2357 }
2358
2359 spin_unlock(&dwc->lock);
2360
2361 return ret;
2362}
2363
2364/**
2365 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2366 * @dwc: pointer to our controller context structure
72246da4
FB		 2367 *
2368 * Returns 0 on success otherwise negative errno.
2369 */
2370int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2371{
2372 u32 reg;
2373 int ret;
2374 int irq;
2375
2376 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2377 &dwc->ctrl_req_addr, GFP_KERNEL);
2378 if (!dwc->ctrl_req) {
2379 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2380 ret = -ENOMEM;
2381 goto err0;
2382 }
2383
2384 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2385 &dwc->ep0_trb_addr, GFP_KERNEL);
2386 if (!dwc->ep0_trb) {
2387 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2388 ret = -ENOMEM;
2389 goto err1;
2390 }
2391
3ef35faf 2392 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4
FB		 2393 if (!dwc->setup_buf) {
2394 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2395 ret = -ENOMEM;
2396 goto err2;
2397 }
2398
5812b1c2 2399 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2400 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2401 GFP_KERNEL);
5812b1c2
FB		 2402 if (!dwc->ep0_bounce) {
2403 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2404 ret = -ENOMEM;
2405 goto err3;
2406 }
2407
72246da4
FB		 2408 dev_set_name(&dwc->gadget.dev, "gadget");
2409
2410 dwc->gadget.ops = &dwc3_gadget_ops;
d327ab5b 2411 dwc->gadget.max_speed = USB_SPEED_SUPER;
72246da4
FB		 2412 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2413 dwc->gadget.dev.parent = dwc->dev;
eeb720fb 2414 dwc->gadget.sg_supported = true;
72246da4
FB		 2415
2416 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2417
2418 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2419 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2420 dwc->gadget.dev.release = dwc3_gadget_release;
2421 dwc->gadget.name = "dwc3-gadget";
2422
2423 /*
2424 * REVISIT: Here we should clear all pending IRQs to be
2425 * sure we're starting from a well known location.
2426 */
2427
2428 ret = dwc3_gadget_init_endpoints(dwc);
2429 if (ret)
5812b1c2 2430 goto err4;
72246da4
FB		 2431
2432 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2433
2434 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2435 "dwc3", dwc);
2436 if (ret) {
2437 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2438 irq, ret);
5812b1c2 2439 goto err5;
72246da4
FB		 2440 }
2441
e6a3b5e2
SAS		 2442 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2443 reg |= DWC3_DCFG_LPM_CAP;
2444 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2445
72246da4
FB		 2446 /* Enable all but Start and End of Frame IRQs */
2447 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2448 DWC3_DEVTEN_EVNTOVERFLOWEN |
2449 DWC3_DEVTEN_CMDCMPLTEN |
2450 DWC3_DEVTEN_ERRTICERREN |
2451 DWC3_DEVTEN_WKUPEVTEN |
2452 DWC3_DEVTEN_ULSTCNGEN |
2453 DWC3_DEVTEN_CONNECTDONEEN |
2454 DWC3_DEVTEN_USBRSTEN |
2455 DWC3_DEVTEN_DISCONNEVTEN);
2456 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2457
802fde98
PZ		 2458 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2459 if (dwc->revision >= DWC3_REVISION_194A) {
2460 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2461 reg |= DWC3_DCFG_LPM_CAP;
2462 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2463
2464 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2465 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2466
2467 /* TODO: This should be configurable */
cbc725b3 2468 reg |= DWC3_DCTL_HIRD_THRES(28);
802fde98
PZ		 2469
2470 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2471
dcae3573
PA		 2472 dwc3_gadget_usb2_phy_suspend(dwc, false);
2473 dwc3_gadget_usb3_phy_suspend(dwc, false);
802fde98
PZ		 2474 }
2475
72246da4
FB		 2476 ret = device_register(&dwc->gadget.dev);
2477 if (ret) {
2478 dev_err(dwc->dev, "failed to register gadget device\n");
2479 put_device(&dwc->gadget.dev);
5812b1c2 2480 goto err6;
72246da4
FB		 2481 }
2482
2483 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2484 if (ret) {
2485 dev_err(dwc->dev, "failed to register udc\n");
5812b1c2 2486 goto err7;
72246da4
FB		 2487 }
2488
2489 return 0;
2490
5812b1c2 2491err7:
72246da4
FB		 2492 device_unregister(&dwc->gadget.dev);
2493
5812b1c2 2494err6:
72246da4
FB		 2495 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2496 free_irq(irq, dwc);
2497
5812b1c2 2498err5:
72246da4
FB		 2499 dwc3_gadget_free_endpoints(dwc);
2500
5812b1c2 2501err4:
3ef35faf
FB		 2502 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2503 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2504
72246da4 2505err3:
0fc9a1be 2506 kfree(dwc->setup_buf);
72246da4
FB		 2507
2508err2:
2509 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2510 dwc->ep0_trb, dwc->ep0_trb_addr);
2511
2512err1:
2513 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2514 dwc->ctrl_req, dwc->ctrl_req_addr);
2515
2516err0:
2517 return ret;
2518}
2519
2520void dwc3_gadget_exit(struct dwc3 *dwc)
2521{
2522 int irq;
72246da4
FB		 2523
2524 usb_del_gadget_udc(&dwc->gadget);
2525 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2526
2527 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2528 free_irq(irq, dwc);
2529
72246da4
FB		 2530 dwc3_gadget_free_endpoints(dwc);
2531
3ef35faf
FB		 2532 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2533 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2534
0fc9a1be 2535 kfree(dwc->setup_buf);
72246da4
FB		 2536
2537 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2538 dwc->ep0_trb, dwc->ep0_trb_addr);
2539
2540 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2541 dwc->ctrl_req, dwc->ctrl_req_addr);
2542
2543 device_unregister(&dwc->gadget.dev);
2544}
Linux kernel - Deliverables
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