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bae4bd84 DB |
1 | /* |
2 | * at91_udc -- driver for at91-series USB peripheral controller | |
3 | * | |
4 | * Copyright (C) 2004 by Thomas Rathbone | |
5 | * Copyright (C) 2005 by HP Labs | |
6 | * Copyright (C) 2005 by David Brownell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
bae4bd84 DB |
12 | */ |
13 | ||
f3db6e82 | 14 | #undef VERBOSE_DEBUG |
bae4bd84 DB |
15 | #undef PACKET_TRACE |
16 | ||
bae4bd84 DB |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/ioport.h> | |
bae4bd84 | 22 | #include <linux/slab.h> |
bae4bd84 DB |
23 | #include <linux/errno.h> |
24 | #include <linux/init.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/proc_fs.h> | |
eed39366 | 28 | #include <linux/prefetch.h> |
bae4bd84 | 29 | #include <linux/clk.h> |
5f848137 | 30 | #include <linux/usb/ch9.h> |
9454a57a | 31 | #include <linux/usb/gadget.h> |
d1494a34 JCPV |
32 | #include <linux/of.h> |
33 | #include <linux/of_gpio.h> | |
bae4bd84 DB |
34 | |
35 | #include <asm/byteorder.h> | |
a09e64fb | 36 | #include <mach/hardware.h> |
bae4bd84 DB |
37 | #include <asm/io.h> |
38 | #include <asm/irq.h> | |
f3db6e82 | 39 | #include <asm/gpio.h> |
bae4bd84 | 40 | |
a09e64fb RK |
41 | #include <mach/board.h> |
42 | #include <mach/cpu.h> | |
43 | #include <mach/at91sam9261_matrix.h> | |
4342d647 | 44 | #include <mach/at91_matrix.h> |
bae4bd84 DB |
45 | |
46 | #include "at91_udc.h" | |
47 | ||
48 | ||
49 | /* | |
50 | * This controller is simple and PIO-only. It's used in many AT91-series | |
8b2e7668 DB |
51 | * full speed USB controllers, including the at91rm9200 (arm920T, with MMU), |
52 | * at91sam926x (arm926ejs, with MMU), and several no-mmu versions. | |
bae4bd84 DB |
53 | * |
54 | * This driver expects the board has been wired with two GPIOs suppporting | |
55 | * a VBUS sensing IRQ, and a D+ pullup. (They may be omitted, but the | |
8b2e7668 DB |
56 | * testing hasn't covered such cases.) |
57 | * | |
58 | * The pullup is most important (so it's integrated on sam926x parts). It | |
bae4bd84 | 59 | * provides software control over whether the host enumerates the device. |
8b2e7668 | 60 | * |
bae4bd84 DB |
61 | * The VBUS sensing helps during enumeration, and allows both USB clocks |
62 | * (and the transceiver) to stay gated off until they're necessary, saving | |
8b2e7668 DB |
63 | * power. During USB suspend, the 48 MHz clock is gated off in hardware; |
64 | * it may also be gated off by software during some Linux sleep states. | |
bae4bd84 DB |
65 | */ |
66 | ||
8b2e7668 | 67 | #define DRIVER_VERSION "3 May 2006" |
bae4bd84 DB |
68 | |
69 | static const char driver_name [] = "at91_udc"; | |
70 | static const char ep0name[] = "ep0"; | |
71 | ||
4037242c | 72 | #define VBUS_POLL_TIMEOUT msecs_to_jiffies(1000) |
bae4bd84 | 73 | |
4f4c5e36 HH |
74 | #define at91_udp_read(udc, reg) \ |
75 | __raw_readl((udc)->udp_baseaddr + (reg)) | |
76 | #define at91_udp_write(udc, reg, val) \ | |
77 | __raw_writel((val), (udc)->udp_baseaddr + (reg)) | |
bae4bd84 DB |
78 | |
79 | /*-------------------------------------------------------------------------*/ | |
80 | ||
81 | #ifdef CONFIG_USB_GADGET_DEBUG_FILES | |
82 | ||
83 | #include <linux/seq_file.h> | |
84 | ||
85 | static const char debug_filename[] = "driver/udc"; | |
86 | ||
87 | #define FOURBITS "%s%s%s%s" | |
88 | #define EIGHTBITS FOURBITS FOURBITS | |
89 | ||
90 | static void proc_ep_show(struct seq_file *s, struct at91_ep *ep) | |
91 | { | |
92 | static char *types[] = { | |
93 | "control", "out-iso", "out-bulk", "out-int", | |
94 | "BOGUS", "in-iso", "in-bulk", "in-int"}; | |
95 | ||
96 | u32 csr; | |
97 | struct at91_request *req; | |
98 | unsigned long flags; | |
4f4c5e36 | 99 | struct at91_udc *udc = ep->udc; |
bae4bd84 | 100 | |
4f4c5e36 | 101 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
102 | |
103 | csr = __raw_readl(ep->creg); | |
104 | ||
105 | /* NOTE: not collecting per-endpoint irq statistics... */ | |
106 | ||
107 | seq_printf(s, "\n"); | |
108 | seq_printf(s, "%s, maxpacket %d %s%s %s%s\n", | |
109 | ep->ep.name, ep->ep.maxpacket, | |
110 | ep->is_in ? "in" : "out", | |
111 | ep->is_iso ? " iso" : "", | |
112 | ep->is_pingpong | |
113 | ? (ep->fifo_bank ? "pong" : "ping") | |
114 | : "", | |
115 | ep->stopped ? " stopped" : ""); | |
116 | seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", | |
117 | csr, | |
118 | (csr & 0x07ff0000) >> 16, | |
119 | (csr & (1 << 15)) ? "enabled" : "disabled", | |
120 | (csr & (1 << 11)) ? "DATA1" : "DATA0", | |
121 | types[(csr & 0x700) >> 8], | |
122 | ||
123 | /* iff type is control then print current direction */ | |
124 | (!(csr & 0x700)) | |
125 | ? ((csr & (1 << 7)) ? " IN" : " OUT") | |
126 | : "", | |
127 | (csr & (1 << 6)) ? " rxdatabk1" : "", | |
128 | (csr & (1 << 5)) ? " forcestall" : "", | |
129 | (csr & (1 << 4)) ? " txpktrdy" : "", | |
130 | ||
131 | (csr & (1 << 3)) ? " stallsent" : "", | |
132 | (csr & (1 << 2)) ? " rxsetup" : "", | |
133 | (csr & (1 << 1)) ? " rxdatabk0" : "", | |
134 | (csr & (1 << 0)) ? " txcomp" : ""); | |
135 | if (list_empty (&ep->queue)) | |
136 | seq_printf(s, "\t(queue empty)\n"); | |
137 | ||
138 | else list_for_each_entry (req, &ep->queue, queue) { | |
139 | unsigned length = req->req.actual; | |
140 | ||
141 | seq_printf(s, "\treq %p len %d/%d buf %p\n", | |
142 | &req->req, length, | |
143 | req->req.length, req->req.buf); | |
144 | } | |
4f4c5e36 | 145 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
146 | } |
147 | ||
148 | static void proc_irq_show(struct seq_file *s, const char *label, u32 mask) | |
149 | { | |
150 | int i; | |
151 | ||
152 | seq_printf(s, "%s %04x:%s%s" FOURBITS, label, mask, | |
153 | (mask & (1 << 13)) ? " wakeup" : "", | |
154 | (mask & (1 << 12)) ? " endbusres" : "", | |
155 | ||
156 | (mask & (1 << 11)) ? " sofint" : "", | |
157 | (mask & (1 << 10)) ? " extrsm" : "", | |
158 | (mask & (1 << 9)) ? " rxrsm" : "", | |
159 | (mask & (1 << 8)) ? " rxsusp" : ""); | |
160 | for (i = 0; i < 8; i++) { | |
161 | if (mask & (1 << i)) | |
162 | seq_printf(s, " ep%d", i); | |
163 | } | |
164 | seq_printf(s, "\n"); | |
165 | } | |
166 | ||
167 | static int proc_udc_show(struct seq_file *s, void *unused) | |
168 | { | |
169 | struct at91_udc *udc = s->private; | |
170 | struct at91_ep *ep; | |
171 | u32 tmp; | |
172 | ||
173 | seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); | |
174 | ||
175 | seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", | |
176 | udc->vbus ? "present" : "off", | |
177 | udc->enabled | |
178 | ? (udc->vbus ? "active" : "enabled") | |
179 | : "disabled", | |
180 | udc->selfpowered ? "self" : "VBUS", | |
181 | udc->suspended ? ", suspended" : "", | |
182 | udc->driver ? udc->driver->driver.name : "(none)"); | |
183 | ||
184 | /* don't access registers when interface isn't clocked */ | |
185 | if (!udc->clocked) { | |
186 | seq_printf(s, "(not clocked)\n"); | |
187 | return 0; | |
188 | } | |
189 | ||
ffd3326b | 190 | tmp = at91_udp_read(udc, AT91_UDP_FRM_NUM); |
bae4bd84 DB |
191 | seq_printf(s, "frame %05x:%s%s frame=%d\n", tmp, |
192 | (tmp & AT91_UDP_FRM_OK) ? " ok" : "", | |
193 | (tmp & AT91_UDP_FRM_ERR) ? " err" : "", | |
194 | (tmp & AT91_UDP_NUM)); | |
195 | ||
ffd3326b | 196 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
197 | seq_printf(s, "glbstate %02x:%s" FOURBITS "\n", tmp, |
198 | (tmp & AT91_UDP_RMWUPE) ? " rmwupe" : "", | |
199 | (tmp & AT91_UDP_RSMINPR) ? " rsminpr" : "", | |
200 | (tmp & AT91_UDP_ESR) ? " esr" : "", | |
201 | (tmp & AT91_UDP_CONFG) ? " confg" : "", | |
202 | (tmp & AT91_UDP_FADDEN) ? " fadden" : ""); | |
203 | ||
ffd3326b | 204 | tmp = at91_udp_read(udc, AT91_UDP_FADDR); |
bae4bd84 DB |
205 | seq_printf(s, "faddr %03x:%s fadd=%d\n", tmp, |
206 | (tmp & AT91_UDP_FEN) ? " fen" : "", | |
207 | (tmp & AT91_UDP_FADD)); | |
208 | ||
ffd3326b AV |
209 | proc_irq_show(s, "imr ", at91_udp_read(udc, AT91_UDP_IMR)); |
210 | proc_irq_show(s, "isr ", at91_udp_read(udc, AT91_UDP_ISR)); | |
bae4bd84 DB |
211 | |
212 | if (udc->enabled && udc->vbus) { | |
213 | proc_ep_show(s, &udc->ep[0]); | |
214 | list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) { | |
5a6506f0 | 215 | if (ep->ep.desc) |
bae4bd84 DB |
216 | proc_ep_show(s, ep); |
217 | } | |
218 | } | |
219 | return 0; | |
220 | } | |
221 | ||
222 | static int proc_udc_open(struct inode *inode, struct file *file) | |
223 | { | |
224 | return single_open(file, proc_udc_show, PDE(inode)->data); | |
225 | } | |
226 | ||
066202dd | 227 | static const struct file_operations proc_ops = { |
cdefa185 | 228 | .owner = THIS_MODULE, |
bae4bd84 DB |
229 | .open = proc_udc_open, |
230 | .read = seq_read, | |
231 | .llseek = seq_lseek, | |
232 | .release = single_release, | |
233 | }; | |
234 | ||
235 | static void create_debug_file(struct at91_udc *udc) | |
236 | { | |
cdefa185 | 237 | udc->pde = proc_create_data(debug_filename, 0, NULL, &proc_ops, udc); |
bae4bd84 DB |
238 | } |
239 | ||
240 | static void remove_debug_file(struct at91_udc *udc) | |
241 | { | |
242 | if (udc->pde) | |
243 | remove_proc_entry(debug_filename, NULL); | |
244 | } | |
245 | ||
246 | #else | |
247 | ||
248 | static inline void create_debug_file(struct at91_udc *udc) {} | |
249 | static inline void remove_debug_file(struct at91_udc *udc) {} | |
250 | ||
251 | #endif | |
252 | ||
253 | ||
254 | /*-------------------------------------------------------------------------*/ | |
255 | ||
256 | static void done(struct at91_ep *ep, struct at91_request *req, int status) | |
257 | { | |
258 | unsigned stopped = ep->stopped; | |
ffd3326b | 259 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
260 | |
261 | list_del_init(&req->queue); | |
262 | if (req->req.status == -EINPROGRESS) | |
263 | req->req.status = status; | |
264 | else | |
265 | status = req->req.status; | |
266 | if (status && status != -ESHUTDOWN) | |
267 | VDBG("%s done %p, status %d\n", ep->ep.name, req, status); | |
268 | ||
269 | ep->stopped = 1; | |
4f4c5e36 | 270 | spin_unlock(&udc->lock); |
bae4bd84 | 271 | req->req.complete(&ep->ep, &req->req); |
4f4c5e36 | 272 | spin_lock(&udc->lock); |
bae4bd84 DB |
273 | ep->stopped = stopped; |
274 | ||
275 | /* ep0 is always ready; other endpoints need a non-empty queue */ | |
276 | if (list_empty(&ep->queue) && ep->int_mask != (1 << 0)) | |
ffd3326b | 277 | at91_udp_write(udc, AT91_UDP_IDR, ep->int_mask); |
bae4bd84 DB |
278 | } |
279 | ||
280 | /*-------------------------------------------------------------------------*/ | |
281 | ||
282 | /* bits indicating OUT fifo has data ready */ | |
283 | #define RX_DATA_READY (AT91_UDP_RX_DATA_BK0 | AT91_UDP_RX_DATA_BK1) | |
284 | ||
285 | /* | |
286 | * Endpoint FIFO CSR bits have a mix of bits, making it unsafe to just write | |
287 | * back most of the value you just read (because of side effects, including | |
288 | * bits that may change after reading and before writing). | |
289 | * | |
290 | * Except when changing a specific bit, always write values which: | |
291 | * - clear SET_FX bits (setting them could change something) | |
292 | * - set CLR_FX bits (clearing them could change something) | |
293 | * | |
294 | * There are also state bits like FORCESTALL, EPEDS, DIR, and EPTYPE | |
295 | * that shouldn't normally be changed. | |
8b2e7668 DB |
296 | * |
297 | * NOTE at91sam9260 docs mention synch between UDPCK and MCK clock domains, | |
298 | * implying a need to wait for one write to complete (test relevant bits) | |
299 | * before starting the next write. This shouldn't be an issue given how | |
300 | * infrequently we write, except maybe for write-then-read idioms. | |
bae4bd84 DB |
301 | */ |
302 | #define SET_FX (AT91_UDP_TXPKTRDY) | |
8b2e7668 DB |
303 | #define CLR_FX (RX_DATA_READY | AT91_UDP_RXSETUP \ |
304 | | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP) | |
bae4bd84 DB |
305 | |
306 | /* pull OUT packet data from the endpoint's fifo */ | |
307 | static int read_fifo (struct at91_ep *ep, struct at91_request *req) | |
308 | { | |
309 | u32 __iomem *creg = ep->creg; | |
310 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
311 | u32 csr; | |
312 | u8 *buf; | |
313 | unsigned int count, bufferspace, is_done; | |
314 | ||
315 | buf = req->req.buf + req->req.actual; | |
316 | bufferspace = req->req.length - req->req.actual; | |
317 | ||
318 | /* | |
319 | * there might be nothing to read if ep_queue() calls us, | |
320 | * or if we already emptied both pingpong buffers | |
321 | */ | |
322 | rescan: | |
323 | csr = __raw_readl(creg); | |
324 | if ((csr & RX_DATA_READY) == 0) | |
325 | return 0; | |
326 | ||
327 | count = (csr & AT91_UDP_RXBYTECNT) >> 16; | |
328 | if (count > ep->ep.maxpacket) | |
329 | count = ep->ep.maxpacket; | |
330 | if (count > bufferspace) { | |
331 | DBG("%s buffer overflow\n", ep->ep.name); | |
332 | req->req.status = -EOVERFLOW; | |
333 | count = bufferspace; | |
334 | } | |
335 | __raw_readsb(dreg, buf, count); | |
336 | ||
337 | /* release and swap pingpong mem bank */ | |
338 | csr |= CLR_FX; | |
339 | if (ep->is_pingpong) { | |
340 | if (ep->fifo_bank == 0) { | |
341 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
342 | ep->fifo_bank = 1; | |
343 | } else { | |
344 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); | |
345 | ep->fifo_bank = 0; | |
346 | } | |
347 | } else | |
348 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
349 | __raw_writel(csr, creg); | |
350 | ||
351 | req->req.actual += count; | |
352 | is_done = (count < ep->ep.maxpacket); | |
353 | if (count == bufferspace) | |
354 | is_done = 1; | |
355 | ||
356 | PACKET("%s %p out/%d%s\n", ep->ep.name, &req->req, count, | |
357 | is_done ? " (done)" : ""); | |
358 | ||
359 | /* | |
360 | * avoid extra trips through IRQ logic for packets already in | |
361 | * the fifo ... maybe preventing an extra (expensive) OUT-NAK | |
362 | */ | |
363 | if (is_done) | |
364 | done(ep, req, 0); | |
365 | else if (ep->is_pingpong) { | |
76225374 HH |
366 | /* |
367 | * One dummy read to delay the code because of a HW glitch: | |
368 | * CSR returns bad RXCOUNT when read too soon after updating | |
369 | * RX_DATA_BK flags. | |
370 | */ | |
371 | csr = __raw_readl(creg); | |
372 | ||
bae4bd84 DB |
373 | bufferspace -= count; |
374 | buf += count; | |
375 | goto rescan; | |
376 | } | |
377 | ||
378 | return is_done; | |
379 | } | |
380 | ||
381 | /* load fifo for an IN packet */ | |
382 | static int write_fifo(struct at91_ep *ep, struct at91_request *req) | |
383 | { | |
384 | u32 __iomem *creg = ep->creg; | |
385 | u32 csr = __raw_readl(creg); | |
386 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
387 | unsigned total, count, is_last; | |
3cf27234 | 388 | u8 *buf; |
bae4bd84 DB |
389 | |
390 | /* | |
391 | * TODO: allow for writing two packets to the fifo ... that'll | |
392 | * reduce the amount of IN-NAKing, but probably won't affect | |
393 | * throughput much. (Unlike preventing OUT-NAKing!) | |
394 | */ | |
395 | ||
396 | /* | |
397 | * If ep_queue() calls us, the queue is empty and possibly in | |
398 | * odd states like TXCOMP not yet cleared (we do it, saving at | |
399 | * least one IRQ) or the fifo not yet being free. Those aren't | |
400 | * issues normally (IRQ handler fast path). | |
401 | */ | |
402 | if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) { | |
403 | if (csr & AT91_UDP_TXCOMP) { | |
404 | csr |= CLR_FX; | |
405 | csr &= ~(SET_FX | AT91_UDP_TXCOMP); | |
406 | __raw_writel(csr, creg); | |
407 | csr = __raw_readl(creg); | |
408 | } | |
409 | if (csr & AT91_UDP_TXPKTRDY) | |
410 | return 0; | |
411 | } | |
412 | ||
3cf27234 DB |
413 | buf = req->req.buf + req->req.actual; |
414 | prefetch(buf); | |
bae4bd84 DB |
415 | total = req->req.length - req->req.actual; |
416 | if (ep->ep.maxpacket < total) { | |
417 | count = ep->ep.maxpacket; | |
418 | is_last = 0; | |
419 | } else { | |
420 | count = total; | |
421 | is_last = (count < ep->ep.maxpacket) || !req->req.zero; | |
422 | } | |
423 | ||
424 | /* | |
425 | * Write the packet, maybe it's a ZLP. | |
426 | * | |
427 | * NOTE: incrementing req->actual before we receive the ACK means | |
428 | * gadget driver IN bytecounts can be wrong in fault cases. That's | |
429 | * fixable with PIO drivers like this one (save "count" here, and | |
430 | * do the increment later on TX irq), but not for most DMA hardware. | |
431 | * | |
432 | * So all gadget drivers must accept that potential error. Some | |
433 | * hardware supports precise fifo status reporting, letting them | |
434 | * recover when the actual bytecount matters (e.g. for USB Test | |
435 | * and Measurement Class devices). | |
436 | */ | |
3cf27234 | 437 | __raw_writesb(dreg, buf, count); |
bae4bd84 DB |
438 | csr &= ~SET_FX; |
439 | csr |= CLR_FX | AT91_UDP_TXPKTRDY; | |
440 | __raw_writel(csr, creg); | |
441 | req->req.actual += count; | |
442 | ||
443 | PACKET("%s %p in/%d%s\n", ep->ep.name, &req->req, count, | |
444 | is_last ? " (done)" : ""); | |
445 | if (is_last) | |
446 | done(ep, req, 0); | |
447 | return is_last; | |
448 | } | |
449 | ||
450 | static void nuke(struct at91_ep *ep, int status) | |
451 | { | |
452 | struct at91_request *req; | |
453 | ||
1a8060d9 | 454 | /* terminate any request in the queue */ |
bae4bd84 DB |
455 | ep->stopped = 1; |
456 | if (list_empty(&ep->queue)) | |
457 | return; | |
458 | ||
441b62c1 | 459 | VDBG("%s %s\n", __func__, ep->ep.name); |
bae4bd84 DB |
460 | while (!list_empty(&ep->queue)) { |
461 | req = list_entry(ep->queue.next, struct at91_request, queue); | |
462 | done(ep, req, status); | |
463 | } | |
464 | } | |
465 | ||
466 | /*-------------------------------------------------------------------------*/ | |
467 | ||
8b2e7668 DB |
468 | static int at91_ep_enable(struct usb_ep *_ep, |
469 | const struct usb_endpoint_descriptor *desc) | |
bae4bd84 DB |
470 | { |
471 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
4f4c5e36 | 472 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
473 | u16 maxpacket; |
474 | u32 tmp; | |
475 | unsigned long flags; | |
476 | ||
477 | if (!_ep || !ep | |
f3bb8e63 | 478 | || !desc || _ep->name == ep0name |
bae4bd84 | 479 | || desc->bDescriptorType != USB_DT_ENDPOINT |
29cc8897 | 480 | || (maxpacket = usb_endpoint_maxp(desc)) == 0 |
bae4bd84 DB |
481 | || maxpacket > ep->maxpacket) { |
482 | DBG("bad ep or descriptor\n"); | |
483 | return -EINVAL; | |
484 | } | |
485 | ||
4f4c5e36 | 486 | if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { |
bae4bd84 DB |
487 | DBG("bogus device state\n"); |
488 | return -ESHUTDOWN; | |
489 | } | |
490 | ||
81c8d8d2 | 491 | tmp = usb_endpoint_type(desc); |
bae4bd84 DB |
492 | switch (tmp) { |
493 | case USB_ENDPOINT_XFER_CONTROL: | |
494 | DBG("only one control endpoint\n"); | |
495 | return -EINVAL; | |
496 | case USB_ENDPOINT_XFER_INT: | |
497 | if (maxpacket > 64) | |
498 | goto bogus_max; | |
499 | break; | |
500 | case USB_ENDPOINT_XFER_BULK: | |
501 | switch (maxpacket) { | |
502 | case 8: | |
503 | case 16: | |
504 | case 32: | |
505 | case 64: | |
506 | goto ok; | |
507 | } | |
508 | bogus_max: | |
509 | DBG("bogus maxpacket %d\n", maxpacket); | |
510 | return -EINVAL; | |
511 | case USB_ENDPOINT_XFER_ISOC: | |
512 | if (!ep->is_pingpong) { | |
513 | DBG("iso requires double buffering\n"); | |
514 | return -EINVAL; | |
515 | } | |
516 | break; | |
517 | } | |
518 | ||
519 | ok: | |
4f4c5e36 | 520 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
521 | |
522 | /* initialize endpoint to match this descriptor */ | |
81c8d8d2 | 523 | ep->is_in = usb_endpoint_dir_in(desc); |
bae4bd84 DB |
524 | ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC); |
525 | ep->stopped = 0; | |
526 | if (ep->is_in) | |
527 | tmp |= 0x04; | |
528 | tmp <<= 8; | |
529 | tmp |= AT91_UDP_EPEDS; | |
530 | __raw_writel(tmp, ep->creg); | |
531 | ||
bae4bd84 DB |
532 | ep->ep.maxpacket = maxpacket; |
533 | ||
534 | /* | |
535 | * reset/init endpoint fifo. NOTE: leaves fifo_bank alone, | |
536 | * since endpoint resets don't reset hw pingpong state. | |
537 | */ | |
4f4c5e36 HH |
538 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
539 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 | 540 | |
4f4c5e36 | 541 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
542 | return 0; |
543 | } | |
544 | ||
545 | static int at91_ep_disable (struct usb_ep * _ep) | |
546 | { | |
547 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
ffd3326b | 548 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
549 | unsigned long flags; |
550 | ||
551 | if (ep == &ep->udc->ep[0]) | |
552 | return -EINVAL; | |
553 | ||
4f4c5e36 | 554 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
555 | |
556 | nuke(ep, -ESHUTDOWN); | |
557 | ||
558 | /* restore the endpoint's pristine config */ | |
f9c56cdd | 559 | ep->ep.desc = NULL; |
bae4bd84 DB |
560 | ep->ep.maxpacket = ep->maxpacket; |
561 | ||
562 | /* reset fifos and endpoint */ | |
563 | if (ep->udc->clocked) { | |
ffd3326b AV |
564 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
565 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
566 | __raw_writel(0, ep->creg); |
567 | } | |
568 | ||
4f4c5e36 | 569 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
570 | return 0; |
571 | } | |
572 | ||
573 | /* | |
574 | * this is a PIO-only driver, so there's nothing | |
575 | * interesting for request or buffer allocation. | |
576 | */ | |
577 | ||
8b2e7668 | 578 | static struct usb_request * |
f3db6e82 | 579 | at91_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) |
bae4bd84 DB |
580 | { |
581 | struct at91_request *req; | |
582 | ||
cd861280 | 583 | req = kzalloc(sizeof (struct at91_request), gfp_flags); |
bae4bd84 DB |
584 | if (!req) |
585 | return NULL; | |
586 | ||
587 | INIT_LIST_HEAD(&req->queue); | |
588 | return &req->req; | |
589 | } | |
590 | ||
591 | static void at91_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) | |
592 | { | |
593 | struct at91_request *req; | |
594 | ||
595 | req = container_of(_req, struct at91_request, req); | |
596 | BUG_ON(!list_empty(&req->queue)); | |
597 | kfree(req); | |
598 | } | |
599 | ||
bae4bd84 DB |
600 | static int at91_ep_queue(struct usb_ep *_ep, |
601 | struct usb_request *_req, gfp_t gfp_flags) | |
602 | { | |
603 | struct at91_request *req; | |
604 | struct at91_ep *ep; | |
4f4c5e36 | 605 | struct at91_udc *udc; |
bae4bd84 DB |
606 | int status; |
607 | unsigned long flags; | |
608 | ||
609 | req = container_of(_req, struct at91_request, req); | |
610 | ep = container_of(_ep, struct at91_ep, ep); | |
611 | ||
612 | if (!_req || !_req->complete | |
613 | || !_req->buf || !list_empty(&req->queue)) { | |
614 | DBG("invalid request\n"); | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
5a6506f0 | 618 | if (!_ep || (!ep->ep.desc && ep->ep.name != ep0name)) { |
bae4bd84 DB |
619 | DBG("invalid ep\n"); |
620 | return -EINVAL; | |
621 | } | |
622 | ||
4f4c5e36 | 623 | udc = ep->udc; |
bae4bd84 | 624 | |
4f4c5e36 | 625 | if (!udc || !udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { |
bae4bd84 DB |
626 | DBG("invalid device\n"); |
627 | return -EINVAL; | |
628 | } | |
629 | ||
630 | _req->status = -EINPROGRESS; | |
631 | _req->actual = 0; | |
632 | ||
4f4c5e36 | 633 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
634 | |
635 | /* try to kickstart any empty and idle queue */ | |
636 | if (list_empty(&ep->queue) && !ep->stopped) { | |
637 | int is_ep0; | |
638 | ||
639 | /* | |
640 | * If this control request has a non-empty DATA stage, this | |
641 | * will start that stage. It works just like a non-control | |
642 | * request (until the status stage starts, maybe early). | |
643 | * | |
644 | * If the data stage is empty, then this starts a successful | |
645 | * IN/STATUS stage. (Unsuccessful ones use set_halt.) | |
646 | */ | |
647 | is_ep0 = (ep->ep.name == ep0name); | |
648 | if (is_ep0) { | |
649 | u32 tmp; | |
650 | ||
4f4c5e36 | 651 | if (!udc->req_pending) { |
bae4bd84 DB |
652 | status = -EINVAL; |
653 | goto done; | |
654 | } | |
655 | ||
656 | /* | |
657 | * defer changing CONFG until after the gadget driver | |
658 | * reconfigures the endpoints. | |
659 | */ | |
4f4c5e36 HH |
660 | if (udc->wait_for_config_ack) { |
661 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); | |
bae4bd84 DB |
662 | tmp ^= AT91_UDP_CONFG; |
663 | VDBG("toggle config\n"); | |
4f4c5e36 | 664 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
665 | } |
666 | if (req->req.length == 0) { | |
667 | ep0_in_status: | |
668 | PACKET("ep0 in/status\n"); | |
669 | status = 0; | |
670 | tmp = __raw_readl(ep->creg); | |
671 | tmp &= ~SET_FX; | |
672 | tmp |= CLR_FX | AT91_UDP_TXPKTRDY; | |
673 | __raw_writel(tmp, ep->creg); | |
4f4c5e36 | 674 | udc->req_pending = 0; |
bae4bd84 DB |
675 | goto done; |
676 | } | |
677 | } | |
678 | ||
679 | if (ep->is_in) | |
680 | status = write_fifo(ep, req); | |
681 | else { | |
682 | status = read_fifo(ep, req); | |
683 | ||
684 | /* IN/STATUS stage is otherwise triggered by irq */ | |
685 | if (status && is_ep0) | |
686 | goto ep0_in_status; | |
687 | } | |
688 | } else | |
689 | status = 0; | |
690 | ||
691 | if (req && !status) { | |
692 | list_add_tail (&req->queue, &ep->queue); | |
4f4c5e36 | 693 | at91_udp_write(udc, AT91_UDP_IER, ep->int_mask); |
bae4bd84 DB |
694 | } |
695 | done: | |
4f4c5e36 | 696 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
697 | return (status < 0) ? status : 0; |
698 | } | |
699 | ||
700 | static int at91_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |
701 | { | |
4f4c5e36 | 702 | struct at91_ep *ep; |
bae4bd84 | 703 | struct at91_request *req; |
4f4c5e36 HH |
704 | unsigned long flags; |
705 | struct at91_udc *udc; | |
bae4bd84 DB |
706 | |
707 | ep = container_of(_ep, struct at91_ep, ep); | |
708 | if (!_ep || ep->ep.name == ep0name) | |
709 | return -EINVAL; | |
710 | ||
4f4c5e36 HH |
711 | udc = ep->udc; |
712 | ||
713 | spin_lock_irqsave(&udc->lock, flags); | |
714 | ||
bae4bd84 DB |
715 | /* make sure it's actually queued on this endpoint */ |
716 | list_for_each_entry (req, &ep->queue, queue) { | |
717 | if (&req->req == _req) | |
718 | break; | |
719 | } | |
4f4c5e36 HH |
720 | if (&req->req != _req) { |
721 | spin_unlock_irqrestore(&udc->lock, flags); | |
bae4bd84 | 722 | return -EINVAL; |
4f4c5e36 | 723 | } |
bae4bd84 DB |
724 | |
725 | done(ep, req, -ECONNRESET); | |
4f4c5e36 | 726 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
727 | return 0; |
728 | } | |
729 | ||
730 | static int at91_ep_set_halt(struct usb_ep *_ep, int value) | |
731 | { | |
732 | struct at91_ep *ep = container_of(_ep, struct at91_ep, ep); | |
ffd3326b | 733 | struct at91_udc *udc = ep->udc; |
bae4bd84 DB |
734 | u32 __iomem *creg; |
735 | u32 csr; | |
736 | unsigned long flags; | |
737 | int status = 0; | |
738 | ||
739 | if (!_ep || ep->is_iso || !ep->udc->clocked) | |
740 | return -EINVAL; | |
741 | ||
742 | creg = ep->creg; | |
4f4c5e36 | 743 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
744 | |
745 | csr = __raw_readl(creg); | |
746 | ||
747 | /* | |
748 | * fail with still-busy IN endpoints, ensuring correct sequencing | |
749 | * of data tx then stall. note that the fifo rx bytecount isn't | |
750 | * completely accurate as a tx bytecount. | |
751 | */ | |
752 | if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0)) | |
753 | status = -EAGAIN; | |
754 | else { | |
755 | csr |= CLR_FX; | |
756 | csr &= ~SET_FX; | |
757 | if (value) { | |
758 | csr |= AT91_UDP_FORCESTALL; | |
759 | VDBG("halt %s\n", ep->ep.name); | |
760 | } else { | |
ffd3326b AV |
761 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
762 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
763 | csr &= ~AT91_UDP_FORCESTALL; |
764 | } | |
765 | __raw_writel(csr, creg); | |
766 | } | |
767 | ||
4f4c5e36 | 768 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
769 | return status; |
770 | } | |
771 | ||
398acce7 | 772 | static const struct usb_ep_ops at91_ep_ops = { |
bae4bd84 DB |
773 | .enable = at91_ep_enable, |
774 | .disable = at91_ep_disable, | |
775 | .alloc_request = at91_ep_alloc_request, | |
776 | .free_request = at91_ep_free_request, | |
bae4bd84 DB |
777 | .queue = at91_ep_queue, |
778 | .dequeue = at91_ep_dequeue, | |
779 | .set_halt = at91_ep_set_halt, | |
1a8060d9 | 780 | /* there's only imprecise fifo status reporting */ |
bae4bd84 DB |
781 | }; |
782 | ||
783 | /*-------------------------------------------------------------------------*/ | |
784 | ||
785 | static int at91_get_frame(struct usb_gadget *gadget) | |
786 | { | |
ffd3326b AV |
787 | struct at91_udc *udc = to_udc(gadget); |
788 | ||
bae4bd84 DB |
789 | if (!to_udc(gadget)->clocked) |
790 | return -EINVAL; | |
ffd3326b | 791 | return at91_udp_read(udc, AT91_UDP_FRM_NUM) & AT91_UDP_NUM; |
bae4bd84 DB |
792 | } |
793 | ||
794 | static int at91_wakeup(struct usb_gadget *gadget) | |
795 | { | |
796 | struct at91_udc *udc = to_udc(gadget); | |
797 | u32 glbstate; | |
798 | int status = -EINVAL; | |
799 | unsigned long flags; | |
800 | ||
441b62c1 | 801 | DBG("%s\n", __func__ ); |
4f4c5e36 | 802 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
803 | |
804 | if (!udc->clocked || !udc->suspended) | |
805 | goto done; | |
806 | ||
807 | /* NOTE: some "early versions" handle ESR differently ... */ | |
808 | ||
ffd3326b | 809 | glbstate = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
810 | if (!(glbstate & AT91_UDP_ESR)) |
811 | goto done; | |
812 | glbstate |= AT91_UDP_ESR; | |
ffd3326b | 813 | at91_udp_write(udc, AT91_UDP_GLB_STAT, glbstate); |
bae4bd84 DB |
814 | |
815 | done: | |
4f4c5e36 | 816 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
817 | return status; |
818 | } | |
819 | ||
25985edc | 820 | /* reinit == restore initial software state */ |
bae4bd84 DB |
821 | static void udc_reinit(struct at91_udc *udc) |
822 | { | |
823 | u32 i; | |
824 | ||
825 | INIT_LIST_HEAD(&udc->gadget.ep_list); | |
826 | INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); | |
827 | ||
828 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
829 | struct at91_ep *ep = &udc->ep[i]; | |
830 | ||
831 | if (i != 0) | |
832 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); | |
5a6506f0 | 833 | ep->ep.desc = NULL; |
bae4bd84 DB |
834 | ep->stopped = 0; |
835 | ep->fifo_bank = 0; | |
836 | ep->ep.maxpacket = ep->maxpacket; | |
ffd3326b | 837 | ep->creg = (void __iomem *) udc->udp_baseaddr + AT91_UDP_CSR(i); |
1a8060d9 | 838 | /* initialize one queue per endpoint */ |
bae4bd84 DB |
839 | INIT_LIST_HEAD(&ep->queue); |
840 | } | |
841 | } | |
842 | ||
843 | static void stop_activity(struct at91_udc *udc) | |
844 | { | |
845 | struct usb_gadget_driver *driver = udc->driver; | |
846 | int i; | |
847 | ||
848 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) | |
849 | driver = NULL; | |
850 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
8b2e7668 | 851 | udc->suspended = 0; |
bae4bd84 DB |
852 | |
853 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
854 | struct at91_ep *ep = &udc->ep[i]; | |
855 | ep->stopped = 1; | |
856 | nuke(ep, -ESHUTDOWN); | |
857 | } | |
4f4c5e36 HH |
858 | if (driver) { |
859 | spin_unlock(&udc->lock); | |
bae4bd84 | 860 | driver->disconnect(&udc->gadget); |
4f4c5e36 HH |
861 | spin_lock(&udc->lock); |
862 | } | |
bae4bd84 DB |
863 | |
864 | udc_reinit(udc); | |
865 | } | |
866 | ||
867 | static void clk_on(struct at91_udc *udc) | |
868 | { | |
869 | if (udc->clocked) | |
870 | return; | |
871 | udc->clocked = 1; | |
872 | clk_enable(udc->iclk); | |
873 | clk_enable(udc->fclk); | |
874 | } | |
875 | ||
876 | static void clk_off(struct at91_udc *udc) | |
877 | { | |
878 | if (!udc->clocked) | |
879 | return; | |
880 | udc->clocked = 0; | |
881 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
bae4bd84 | 882 | clk_disable(udc->fclk); |
8b2e7668 | 883 | clk_disable(udc->iclk); |
bae4bd84 DB |
884 | } |
885 | ||
886 | /* | |
887 | * activate/deactivate link with host; minimize power usage for | |
888 | * inactive links by cutting clocks and transceiver power. | |
889 | */ | |
890 | static void pullup(struct at91_udc *udc, int is_on) | |
891 | { | |
f3db6e82 DB |
892 | int active = !udc->board.pullup_active_low; |
893 | ||
bae4bd84 DB |
894 | if (!udc->enabled || !udc->vbus) |
895 | is_on = 0; | |
896 | DBG("%sactive\n", is_on ? "" : "in"); | |
ffd3326b | 897 | |
bae4bd84 DB |
898 | if (is_on) { |
899 | clk_on(udc); | |
08cbc706 | 900 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM); |
ffd3326b | 901 | at91_udp_write(udc, AT91_UDP_TXVC, 0); |
29ba4b53 | 902 | if (cpu_is_at91rm9200()) |
f3db6e82 | 903 | gpio_set_value(udc->board.pullup_pin, active); |
61352667 | 904 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
29ba4b53 AV |
905 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); |
906 | ||
907 | txvc |= AT91_UDP_TXVC_PUON; | |
908 | at91_udp_write(udc, AT91_UDP_TXVC, txvc); | |
23f6d914 | 909 | } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { |
29ba4b53 AV |
910 | u32 usbpucr; |
911 | ||
4342d647 | 912 | usbpucr = at91_matrix_read(AT91_MATRIX_USBPUCR); |
29ba4b53 | 913 | usbpucr |= AT91_MATRIX_USBPUCR_PUON; |
4342d647 | 914 | at91_matrix_write(AT91_MATRIX_USBPUCR, usbpucr); |
29ba4b53 | 915 | } |
ffd3326b | 916 | } else { |
bae4bd84 | 917 | stop_activity(udc); |
08cbc706 | 918 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM); |
ffd3326b | 919 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); |
29ba4b53 | 920 | if (cpu_is_at91rm9200()) |
f3db6e82 | 921 | gpio_set_value(udc->board.pullup_pin, !active); |
61352667 | 922 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
29ba4b53 AV |
923 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); |
924 | ||
925 | txvc &= ~AT91_UDP_TXVC_PUON; | |
926 | at91_udp_write(udc, AT91_UDP_TXVC, txvc); | |
23f6d914 | 927 | } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { |
29ba4b53 AV |
928 | u32 usbpucr; |
929 | ||
4342d647 | 930 | usbpucr = at91_matrix_read(AT91_MATRIX_USBPUCR); |
29ba4b53 | 931 | usbpucr &= ~AT91_MATRIX_USBPUCR_PUON; |
4342d647 | 932 | at91_matrix_write(AT91_MATRIX_USBPUCR, usbpucr); |
29ba4b53 | 933 | } |
bae4bd84 | 934 | clk_off(udc); |
bae4bd84 DB |
935 | } |
936 | } | |
937 | ||
938 | /* vbus is here! turn everything on that's ready */ | |
939 | static int at91_vbus_session(struct usb_gadget *gadget, int is_active) | |
940 | { | |
941 | struct at91_udc *udc = to_udc(gadget); | |
942 | unsigned long flags; | |
943 | ||
1a8060d9 | 944 | /* VDBG("vbus %s\n", is_active ? "on" : "off"); */ |
4f4c5e36 | 945 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 946 | udc->vbus = (is_active != 0); |
bfb7fb79 WK |
947 | if (udc->driver) |
948 | pullup(udc, is_active); | |
949 | else | |
950 | pullup(udc, 0); | |
4f4c5e36 | 951 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
952 | return 0; |
953 | } | |
954 | ||
955 | static int at91_pullup(struct usb_gadget *gadget, int is_on) | |
956 | { | |
957 | struct at91_udc *udc = to_udc(gadget); | |
958 | unsigned long flags; | |
959 | ||
4f4c5e36 | 960 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 DB |
961 | udc->enabled = is_on = !!is_on; |
962 | pullup(udc, is_on); | |
4f4c5e36 | 963 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
964 | return 0; |
965 | } | |
966 | ||
967 | static int at91_set_selfpowered(struct usb_gadget *gadget, int is_on) | |
968 | { | |
969 | struct at91_udc *udc = to_udc(gadget); | |
970 | unsigned long flags; | |
971 | ||
4f4c5e36 | 972 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 973 | udc->selfpowered = (is_on != 0); |
4f4c5e36 | 974 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
975 | return 0; |
976 | } | |
977 | ||
f3d8bf34 SAS |
978 | static int at91_start(struct usb_gadget *gadget, |
979 | struct usb_gadget_driver *driver); | |
980 | static int at91_stop(struct usb_gadget *gadget, | |
981 | struct usb_gadget_driver *driver); | |
bae4bd84 DB |
982 | static const struct usb_gadget_ops at91_udc_ops = { |
983 | .get_frame = at91_get_frame, | |
984 | .wakeup = at91_wakeup, | |
985 | .set_selfpowered = at91_set_selfpowered, | |
986 | .vbus_session = at91_vbus_session, | |
987 | .pullup = at91_pullup, | |
f3d8bf34 SAS |
988 | .udc_start = at91_start, |
989 | .udc_stop = at91_stop, | |
bae4bd84 DB |
990 | |
991 | /* | |
992 | * VBUS-powered devices may also also want to support bigger | |
993 | * power budgets after an appropriate SET_CONFIGURATION. | |
994 | */ | |
1a8060d9 | 995 | /* .vbus_power = at91_vbus_power, */ |
bae4bd84 DB |
996 | }; |
997 | ||
998 | /*-------------------------------------------------------------------------*/ | |
999 | ||
1000 | static int handle_ep(struct at91_ep *ep) | |
1001 | { | |
1002 | struct at91_request *req; | |
1003 | u32 __iomem *creg = ep->creg; | |
1004 | u32 csr = __raw_readl(creg); | |
1005 | ||
1006 | if (!list_empty(&ep->queue)) | |
1007 | req = list_entry(ep->queue.next, | |
1008 | struct at91_request, queue); | |
1009 | else | |
1010 | req = NULL; | |
1011 | ||
1012 | if (ep->is_in) { | |
1013 | if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { | |
1014 | csr |= CLR_FX; | |
1015 | csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); | |
1016 | __raw_writel(csr, creg); | |
1017 | } | |
1018 | if (req) | |
1019 | return write_fifo(ep, req); | |
1020 | ||
1021 | } else { | |
1022 | if (csr & AT91_UDP_STALLSENT) { | |
1023 | /* STALLSENT bit == ISOERR */ | |
1024 | if (ep->is_iso && req) | |
1025 | req->req.status = -EILSEQ; | |
1026 | csr |= CLR_FX; | |
1027 | csr &= ~(SET_FX | AT91_UDP_STALLSENT); | |
1028 | __raw_writel(csr, creg); | |
1029 | csr = __raw_readl(creg); | |
1030 | } | |
1031 | if (req && (csr & RX_DATA_READY)) | |
1032 | return read_fifo(ep, req); | |
1033 | } | |
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | union setup { | |
1038 | u8 raw[8]; | |
1039 | struct usb_ctrlrequest r; | |
1040 | }; | |
1041 | ||
1042 | static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) | |
1043 | { | |
1044 | u32 __iomem *creg = ep->creg; | |
1045 | u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); | |
1046 | unsigned rxcount, i = 0; | |
1047 | u32 tmp; | |
1048 | union setup pkt; | |
1049 | int status = 0; | |
1050 | ||
1051 | /* read and ack SETUP; hard-fail for bogus packets */ | |
1052 | rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; | |
1053 | if (likely(rxcount == 8)) { | |
1054 | while (rxcount--) | |
1055 | pkt.raw[i++] = __raw_readb(dreg); | |
1056 | if (pkt.r.bRequestType & USB_DIR_IN) { | |
1057 | csr |= AT91_UDP_DIR; | |
1058 | ep->is_in = 1; | |
1059 | } else { | |
1060 | csr &= ~AT91_UDP_DIR; | |
1061 | ep->is_in = 0; | |
1062 | } | |
1063 | } else { | |
1a8060d9 | 1064 | /* REVISIT this happens sometimes under load; why?? */ |
bae4bd84 DB |
1065 | ERR("SETUP len %d, csr %08x\n", rxcount, csr); |
1066 | status = -EINVAL; | |
1067 | } | |
1068 | csr |= CLR_FX; | |
1069 | csr &= ~(SET_FX | AT91_UDP_RXSETUP); | |
1070 | __raw_writel(csr, creg); | |
1071 | udc->wait_for_addr_ack = 0; | |
1072 | udc->wait_for_config_ack = 0; | |
1073 | ep->stopped = 0; | |
1074 | if (unlikely(status != 0)) | |
1075 | goto stall; | |
1076 | ||
1077 | #define w_index le16_to_cpu(pkt.r.wIndex) | |
1078 | #define w_value le16_to_cpu(pkt.r.wValue) | |
1079 | #define w_length le16_to_cpu(pkt.r.wLength) | |
1080 | ||
1081 | VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n", | |
1082 | pkt.r.bRequestType, pkt.r.bRequest, | |
1083 | w_value, w_index, w_length); | |
1084 | ||
1085 | /* | |
1086 | * A few standard requests get handled here, ones that touch | |
1087 | * hardware ... notably for device and endpoint features. | |
1088 | */ | |
1089 | udc->req_pending = 1; | |
1090 | csr = __raw_readl(creg); | |
1091 | csr |= CLR_FX; | |
1092 | csr &= ~SET_FX; | |
1093 | switch ((pkt.r.bRequestType << 8) | pkt.r.bRequest) { | |
1094 | ||
1095 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1096 | | USB_REQ_SET_ADDRESS: | |
1097 | __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); | |
1098 | udc->addr = w_value; | |
1099 | udc->wait_for_addr_ack = 1; | |
1100 | udc->req_pending = 0; | |
1101 | /* FADDR is set later, when we ack host STATUS */ | |
1102 | return; | |
1103 | ||
1104 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1105 | | USB_REQ_SET_CONFIGURATION: | |
ffd3326b | 1106 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_CONFG; |
bae4bd84 DB |
1107 | if (pkt.r.wValue) |
1108 | udc->wait_for_config_ack = (tmp == 0); | |
1109 | else | |
1110 | udc->wait_for_config_ack = (tmp != 0); | |
1111 | if (udc->wait_for_config_ack) | |
1112 | VDBG("wait for config\n"); | |
1113 | /* CONFG is toggled later, if gadget driver succeeds */ | |
1114 | break; | |
1115 | ||
1116 | /* | |
1117 | * Hosts may set or clear remote wakeup status, and | |
1118 | * devices may report they're VBUS powered. | |
1119 | */ | |
1120 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1121 | | USB_REQ_GET_STATUS: | |
1122 | tmp = (udc->selfpowered << USB_DEVICE_SELF_POWERED); | |
ffd3326b | 1123 | if (at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_ESR) |
bae4bd84 DB |
1124 | tmp |= (1 << USB_DEVICE_REMOTE_WAKEUP); |
1125 | PACKET("get device status\n"); | |
1126 | __raw_writeb(tmp, dreg); | |
1127 | __raw_writeb(0, dreg); | |
1128 | goto write_in; | |
1129 | /* then STATUS starts later, automatically */ | |
1130 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1131 | | USB_REQ_SET_FEATURE: | |
1132 | if (w_value != USB_DEVICE_REMOTE_WAKEUP) | |
1133 | goto stall; | |
ffd3326b | 1134 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 | 1135 | tmp |= AT91_UDP_ESR; |
ffd3326b | 1136 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1137 | goto succeed; |
1138 | case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | |
1139 | | USB_REQ_CLEAR_FEATURE: | |
1140 | if (w_value != USB_DEVICE_REMOTE_WAKEUP) | |
1141 | goto stall; | |
ffd3326b | 1142 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 | 1143 | tmp &= ~AT91_UDP_ESR; |
ffd3326b | 1144 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1145 | goto succeed; |
1146 | ||
1147 | /* | |
1148 | * Interfaces have no feature settings; this is pretty useless. | |
1149 | * we won't even insist the interface exists... | |
1150 | */ | |
1151 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1152 | | USB_REQ_GET_STATUS: | |
1153 | PACKET("get interface status\n"); | |
1154 | __raw_writeb(0, dreg); | |
1155 | __raw_writeb(0, dreg); | |
1156 | goto write_in; | |
1157 | /* then STATUS starts later, automatically */ | |
1158 | case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1159 | | USB_REQ_SET_FEATURE: | |
1160 | case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | |
1161 | | USB_REQ_CLEAR_FEATURE: | |
1162 | goto stall; | |
1163 | ||
1164 | /* | |
1165 | * Hosts may clear bulk/intr endpoint halt after the gadget | |
1166 | * driver sets it (not widely used); or set it (for testing) | |
1167 | */ | |
1168 | case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1169 | | USB_REQ_GET_STATUS: | |
1170 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1171 | ep = &udc->ep[tmp]; | |
5a6506f0 | 1172 | if (tmp >= NUM_ENDPOINTS || (tmp && !ep->ep.desc)) |
bae4bd84 DB |
1173 | goto stall; |
1174 | ||
1175 | if (tmp) { | |
1176 | if ((w_index & USB_DIR_IN)) { | |
1177 | if (!ep->is_in) | |
1178 | goto stall; | |
1179 | } else if (ep->is_in) | |
1180 | goto stall; | |
1181 | } | |
1182 | PACKET("get %s status\n", ep->ep.name); | |
1183 | if (__raw_readl(ep->creg) & AT91_UDP_FORCESTALL) | |
1184 | tmp = (1 << USB_ENDPOINT_HALT); | |
1185 | else | |
1186 | tmp = 0; | |
1187 | __raw_writeb(tmp, dreg); | |
1188 | __raw_writeb(0, dreg); | |
1189 | goto write_in; | |
1190 | /* then STATUS starts later, automatically */ | |
1191 | case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1192 | | USB_REQ_SET_FEATURE: | |
1193 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1194 | ep = &udc->ep[tmp]; | |
1440e096 | 1195 | if (w_value != USB_ENDPOINT_HALT || tmp >= NUM_ENDPOINTS) |
bae4bd84 | 1196 | goto stall; |
5a6506f0 | 1197 | if (!ep->ep.desc || ep->is_iso) |
bae4bd84 DB |
1198 | goto stall; |
1199 | if ((w_index & USB_DIR_IN)) { | |
1200 | if (!ep->is_in) | |
1201 | goto stall; | |
1202 | } else if (ep->is_in) | |
1203 | goto stall; | |
1204 | ||
1205 | tmp = __raw_readl(ep->creg); | |
1206 | tmp &= ~SET_FX; | |
1207 | tmp |= CLR_FX | AT91_UDP_FORCESTALL; | |
1208 | __raw_writel(tmp, ep->creg); | |
1209 | goto succeed; | |
1210 | case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | |
1211 | | USB_REQ_CLEAR_FEATURE: | |
1212 | tmp = w_index & USB_ENDPOINT_NUMBER_MASK; | |
1213 | ep = &udc->ep[tmp]; | |
1440e096 | 1214 | if (w_value != USB_ENDPOINT_HALT || tmp >= NUM_ENDPOINTS) |
bae4bd84 DB |
1215 | goto stall; |
1216 | if (tmp == 0) | |
1217 | goto succeed; | |
5a6506f0 | 1218 | if (!ep->ep.desc || ep->is_iso) |
bae4bd84 DB |
1219 | goto stall; |
1220 | if ((w_index & USB_DIR_IN)) { | |
1221 | if (!ep->is_in) | |
1222 | goto stall; | |
1223 | } else if (ep->is_in) | |
1224 | goto stall; | |
1225 | ||
ffd3326b AV |
1226 | at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); |
1227 | at91_udp_write(udc, AT91_UDP_RST_EP, 0); | |
bae4bd84 DB |
1228 | tmp = __raw_readl(ep->creg); |
1229 | tmp |= CLR_FX; | |
1230 | tmp &= ~(SET_FX | AT91_UDP_FORCESTALL); | |
1231 | __raw_writel(tmp, ep->creg); | |
1232 | if (!list_empty(&ep->queue)) | |
1233 | handle_ep(ep); | |
1234 | goto succeed; | |
1235 | } | |
1236 | ||
1237 | #undef w_value | |
1238 | #undef w_index | |
1239 | #undef w_length | |
1240 | ||
1241 | /* pass request up to the gadget driver */ | |
4f4c5e36 HH |
1242 | if (udc->driver) { |
1243 | spin_unlock(&udc->lock); | |
bfb7fb79 | 1244 | status = udc->driver->setup(&udc->gadget, &pkt.r); |
4f4c5e36 HH |
1245 | spin_lock(&udc->lock); |
1246 | } | |
bfb7fb79 WK |
1247 | else |
1248 | status = -ENODEV; | |
bae4bd84 DB |
1249 | if (status < 0) { |
1250 | stall: | |
1251 | VDBG("req %02x.%02x protocol STALL; stat %d\n", | |
1252 | pkt.r.bRequestType, pkt.r.bRequest, status); | |
1253 | csr |= AT91_UDP_FORCESTALL; | |
1254 | __raw_writel(csr, creg); | |
1255 | udc->req_pending = 0; | |
1256 | } | |
1257 | return; | |
1258 | ||
1259 | succeed: | |
1260 | /* immediate successful (IN) STATUS after zero length DATA */ | |
1261 | PACKET("ep0 in/status\n"); | |
1262 | write_in: | |
1263 | csr |= AT91_UDP_TXPKTRDY; | |
1264 | __raw_writel(csr, creg); | |
1265 | udc->req_pending = 0; | |
bae4bd84 DB |
1266 | } |
1267 | ||
1268 | static void handle_ep0(struct at91_udc *udc) | |
1269 | { | |
1270 | struct at91_ep *ep0 = &udc->ep[0]; | |
1271 | u32 __iomem *creg = ep0->creg; | |
1272 | u32 csr = __raw_readl(creg); | |
1273 | struct at91_request *req; | |
1274 | ||
1275 | if (unlikely(csr & AT91_UDP_STALLSENT)) { | |
1276 | nuke(ep0, -EPROTO); | |
1277 | udc->req_pending = 0; | |
1278 | csr |= CLR_FX; | |
1279 | csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); | |
1280 | __raw_writel(csr, creg); | |
1281 | VDBG("ep0 stalled\n"); | |
1282 | csr = __raw_readl(creg); | |
1283 | } | |
1284 | if (csr & AT91_UDP_RXSETUP) { | |
1285 | nuke(ep0, 0); | |
1286 | udc->req_pending = 0; | |
1287 | handle_setup(udc, ep0, csr); | |
1288 | return; | |
1289 | } | |
1290 | ||
1291 | if (list_empty(&ep0->queue)) | |
1292 | req = NULL; | |
1293 | else | |
1294 | req = list_entry(ep0->queue.next, struct at91_request, queue); | |
1295 | ||
1296 | /* host ACKed an IN packet that we sent */ | |
1297 | if (csr & AT91_UDP_TXCOMP) { | |
1298 | csr |= CLR_FX; | |
1299 | csr &= ~(SET_FX | AT91_UDP_TXCOMP); | |
1300 | ||
1301 | /* write more IN DATA? */ | |
1302 | if (req && ep0->is_in) { | |
1303 | if (handle_ep(ep0)) | |
1304 | udc->req_pending = 0; | |
1305 | ||
1306 | /* | |
1307 | * Ack after: | |
1308 | * - last IN DATA packet (including GET_STATUS) | |
1309 | * - IN/STATUS for OUT DATA | |
1310 | * - IN/STATUS for any zero-length DATA stage | |
1311 | * except for the IN DATA case, the host should send | |
1312 | * an OUT status later, which we'll ack. | |
1313 | */ | |
1314 | } else { | |
1315 | udc->req_pending = 0; | |
1316 | __raw_writel(csr, creg); | |
1317 | ||
1318 | /* | |
1319 | * SET_ADDRESS takes effect only after the STATUS | |
1320 | * (to the original address) gets acked. | |
1321 | */ | |
1322 | if (udc->wait_for_addr_ack) { | |
1323 | u32 tmp; | |
1324 | ||
ffd3326b | 1325 | at91_udp_write(udc, AT91_UDP_FADDR, |
8b2e7668 | 1326 | AT91_UDP_FEN | udc->addr); |
ffd3326b | 1327 | tmp = at91_udp_read(udc, AT91_UDP_GLB_STAT); |
bae4bd84 DB |
1328 | tmp &= ~AT91_UDP_FADDEN; |
1329 | if (udc->addr) | |
1330 | tmp |= AT91_UDP_FADDEN; | |
ffd3326b | 1331 | at91_udp_write(udc, AT91_UDP_GLB_STAT, tmp); |
bae4bd84 DB |
1332 | |
1333 | udc->wait_for_addr_ack = 0; | |
1334 | VDBG("address %d\n", udc->addr); | |
1335 | } | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | /* OUT packet arrived ... */ | |
1340 | else if (csr & AT91_UDP_RX_DATA_BK0) { | |
1341 | csr |= CLR_FX; | |
1342 | csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); | |
1343 | ||
1344 | /* OUT DATA stage */ | |
1345 | if (!ep0->is_in) { | |
1346 | if (req) { | |
1347 | if (handle_ep(ep0)) { | |
1348 | /* send IN/STATUS */ | |
1349 | PACKET("ep0 in/status\n"); | |
1350 | csr = __raw_readl(creg); | |
1351 | csr &= ~SET_FX; | |
1352 | csr |= CLR_FX | AT91_UDP_TXPKTRDY; | |
1353 | __raw_writel(csr, creg); | |
1354 | udc->req_pending = 0; | |
1355 | } | |
1356 | } else if (udc->req_pending) { | |
1357 | /* | |
1358 | * AT91 hardware has a hard time with this | |
1359 | * "deferred response" mode for control-OUT | |
1360 | * transfers. (For control-IN it's fine.) | |
1361 | * | |
1362 | * The normal solution leaves OUT data in the | |
1363 | * fifo until the gadget driver is ready. | |
1364 | * We couldn't do that here without disabling | |
1365 | * the IRQ that tells about SETUP packets, | |
1366 | * e.g. when the host gets impatient... | |
1367 | * | |
1368 | * Working around it by copying into a buffer | |
1369 | * would almost be a non-deferred response, | |
1370 | * except that it wouldn't permit reliable | |
1371 | * stalling of the request. Instead, demand | |
1372 | * that gadget drivers not use this mode. | |
1373 | */ | |
1374 | DBG("no control-OUT deferred responses!\n"); | |
1375 | __raw_writel(csr | AT91_UDP_FORCESTALL, creg); | |
1376 | udc->req_pending = 0; | |
1377 | } | |
1378 | ||
1379 | /* STATUS stage for control-IN; ack. */ | |
1380 | } else { | |
1381 | PACKET("ep0 out/status ACK\n"); | |
1382 | __raw_writel(csr, creg); | |
1383 | ||
1384 | /* "early" status stage */ | |
1385 | if (req) | |
1386 | done(ep0, req, 0); | |
1387 | } | |
1388 | } | |
1389 | } | |
1390 | ||
7d12e780 | 1391 | static irqreturn_t at91_udc_irq (int irq, void *_udc) |
bae4bd84 DB |
1392 | { |
1393 | struct at91_udc *udc = _udc; | |
1394 | u32 rescans = 5; | |
c6c35237 | 1395 | int disable_clock = 0; |
4f4c5e36 HH |
1396 | unsigned long flags; |
1397 | ||
1398 | spin_lock_irqsave(&udc->lock, flags); | |
c6c35237 HH |
1399 | |
1400 | if (!udc->clocked) { | |
1401 | clk_on(udc); | |
1402 | disable_clock = 1; | |
1403 | } | |
bae4bd84 DB |
1404 | |
1405 | while (rescans--) { | |
8b2e7668 | 1406 | u32 status; |
bae4bd84 | 1407 | |
ffd3326b AV |
1408 | status = at91_udp_read(udc, AT91_UDP_ISR) |
1409 | & at91_udp_read(udc, AT91_UDP_IMR); | |
bae4bd84 DB |
1410 | if (!status) |
1411 | break; | |
1412 | ||
1413 | /* USB reset irq: not maskable */ | |
1414 | if (status & AT91_UDP_ENDBUSRES) { | |
ffd3326b AV |
1415 | at91_udp_write(udc, AT91_UDP_IDR, ~MINIMUS_INTERRUPTUS); |
1416 | at91_udp_write(udc, AT91_UDP_IER, MINIMUS_INTERRUPTUS); | |
bae4bd84 | 1417 | /* Atmel code clears this irq twice */ |
ffd3326b AV |
1418 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES); |
1419 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_ENDBUSRES); | |
bae4bd84 DB |
1420 | VDBG("end bus reset\n"); |
1421 | udc->addr = 0; | |
1422 | stop_activity(udc); | |
1423 | ||
1424 | /* enable ep0 */ | |
ffd3326b | 1425 | at91_udp_write(udc, AT91_UDP_CSR(0), |
8b2e7668 | 1426 | AT91_UDP_EPEDS | AT91_UDP_EPTYPE_CTRL); |
bae4bd84 DB |
1427 | udc->gadget.speed = USB_SPEED_FULL; |
1428 | udc->suspended = 0; | |
ffd3326b | 1429 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_EP(0)); |
bae4bd84 DB |
1430 | |
1431 | /* | |
1432 | * NOTE: this driver keeps clocks off unless the | |
8b2e7668 DB |
1433 | * USB host is present. That saves power, but for |
1434 | * boards that don't support VBUS detection, both | |
1435 | * clocks need to be active most of the time. | |
bae4bd84 DB |
1436 | */ |
1437 | ||
1438 | /* host initiated suspend (3+ms bus idle) */ | |
1439 | } else if (status & AT91_UDP_RXSUSP) { | |
ffd3326b AV |
1440 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXSUSP); |
1441 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXRSM); | |
1442 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXSUSP); | |
1a8060d9 | 1443 | /* VDBG("bus suspend\n"); */ |
bae4bd84 DB |
1444 | if (udc->suspended) |
1445 | continue; | |
1446 | udc->suspended = 1; | |
1447 | ||
1448 | /* | |
1449 | * NOTE: when suspending a VBUS-powered device, the | |
1450 | * gadget driver should switch into slow clock mode | |
1451 | * and then into standby to avoid drawing more than | |
1452 | * 500uA power (2500uA for some high-power configs). | |
1453 | */ | |
4f4c5e36 HH |
1454 | if (udc->driver && udc->driver->suspend) { |
1455 | spin_unlock(&udc->lock); | |
bae4bd84 | 1456 | udc->driver->suspend(&udc->gadget); |
4f4c5e36 HH |
1457 | spin_lock(&udc->lock); |
1458 | } | |
bae4bd84 DB |
1459 | |
1460 | /* host initiated resume */ | |
1461 | } else if (status & AT91_UDP_RXRSM) { | |
ffd3326b AV |
1462 | at91_udp_write(udc, AT91_UDP_IDR, AT91_UDP_RXRSM); |
1463 | at91_udp_write(udc, AT91_UDP_IER, AT91_UDP_RXSUSP); | |
1464 | at91_udp_write(udc, AT91_UDP_ICR, AT91_UDP_RXRSM); | |
1a8060d9 | 1465 | /* VDBG("bus resume\n"); */ |
bae4bd84 DB |
1466 | if (!udc->suspended) |
1467 | continue; | |
1468 | udc->suspended = 0; | |
1469 | ||
1470 | /* | |
1471 | * NOTE: for a VBUS-powered device, the gadget driver | |
1472 | * would normally want to switch out of slow clock | |
1473 | * mode into normal mode. | |
1474 | */ | |
4f4c5e36 HH |
1475 | if (udc->driver && udc->driver->resume) { |
1476 | spin_unlock(&udc->lock); | |
bae4bd84 | 1477 | udc->driver->resume(&udc->gadget); |
4f4c5e36 HH |
1478 | spin_lock(&udc->lock); |
1479 | } | |
bae4bd84 DB |
1480 | |
1481 | /* endpoint IRQs are cleared by handling them */ | |
1482 | } else { | |
1483 | int i; | |
1484 | unsigned mask = 1; | |
1485 | struct at91_ep *ep = &udc->ep[1]; | |
1486 | ||
1487 | if (status & mask) | |
1488 | handle_ep0(udc); | |
1489 | for (i = 1; i < NUM_ENDPOINTS; i++) { | |
1490 | mask <<= 1; | |
1491 | if (status & mask) | |
1492 | handle_ep(ep); | |
1493 | ep++; | |
1494 | } | |
1495 | } | |
1496 | } | |
1497 | ||
c6c35237 HH |
1498 | if (disable_clock) |
1499 | clk_off(udc); | |
1500 | ||
4f4c5e36 HH |
1501 | spin_unlock_irqrestore(&udc->lock, flags); |
1502 | ||
bae4bd84 DB |
1503 | return IRQ_HANDLED; |
1504 | } | |
1505 | ||
1506 | /*-------------------------------------------------------------------------*/ | |
1507 | ||
8b2e7668 DB |
1508 | static void nop_release(struct device *dev) |
1509 | { | |
1510 | /* nothing to free */ | |
1511 | } | |
1512 | ||
bae4bd84 DB |
1513 | static struct at91_udc controller = { |
1514 | .gadget = { | |
8b2e7668 DB |
1515 | .ops = &at91_udc_ops, |
1516 | .ep0 = &controller.ep[0].ep, | |
1517 | .name = driver_name, | |
1518 | .dev = { | |
c682b170 | 1519 | .init_name = "gadget", |
8b2e7668 | 1520 | .release = nop_release, |
bae4bd84 DB |
1521 | } |
1522 | }, | |
1523 | .ep[0] = { | |
1524 | .ep = { | |
1525 | .name = ep0name, | |
1526 | .ops = &at91_ep_ops, | |
1527 | }, | |
1528 | .udc = &controller, | |
1529 | .maxpacket = 8, | |
bae4bd84 DB |
1530 | .int_mask = 1 << 0, |
1531 | }, | |
1532 | .ep[1] = { | |
1533 | .ep = { | |
1534 | .name = "ep1", | |
1535 | .ops = &at91_ep_ops, | |
1536 | }, | |
1537 | .udc = &controller, | |
1538 | .is_pingpong = 1, | |
1539 | .maxpacket = 64, | |
bae4bd84 DB |
1540 | .int_mask = 1 << 1, |
1541 | }, | |
1542 | .ep[2] = { | |
1543 | .ep = { | |
1544 | .name = "ep2", | |
1545 | .ops = &at91_ep_ops, | |
1546 | }, | |
1547 | .udc = &controller, | |
1548 | .is_pingpong = 1, | |
1549 | .maxpacket = 64, | |
bae4bd84 DB |
1550 | .int_mask = 1 << 2, |
1551 | }, | |
1552 | .ep[3] = { | |
1553 | .ep = { | |
1554 | /* could actually do bulk too */ | |
1555 | .name = "ep3-int", | |
1556 | .ops = &at91_ep_ops, | |
1557 | }, | |
1558 | .udc = &controller, | |
1559 | .maxpacket = 8, | |
bae4bd84 DB |
1560 | .int_mask = 1 << 3, |
1561 | }, | |
1562 | .ep[4] = { | |
1563 | .ep = { | |
1564 | .name = "ep4", | |
1565 | .ops = &at91_ep_ops, | |
1566 | }, | |
1567 | .udc = &controller, | |
1568 | .is_pingpong = 1, | |
1569 | .maxpacket = 256, | |
bae4bd84 DB |
1570 | .int_mask = 1 << 4, |
1571 | }, | |
1572 | .ep[5] = { | |
1573 | .ep = { | |
1574 | .name = "ep5", | |
1575 | .ops = &at91_ep_ops, | |
1576 | }, | |
1577 | .udc = &controller, | |
1578 | .is_pingpong = 1, | |
1579 | .maxpacket = 256, | |
bae4bd84 DB |
1580 | .int_mask = 1 << 5, |
1581 | }, | |
8b2e7668 | 1582 | /* ep6 and ep7 are also reserved (custom silicon might use them) */ |
bae4bd84 DB |
1583 | }; |
1584 | ||
4037242c RM |
1585 | static void at91_vbus_update(struct at91_udc *udc, unsigned value) |
1586 | { | |
1587 | value ^= udc->board.vbus_active_low; | |
1588 | if (value != udc->vbus) | |
1589 | at91_vbus_session(&udc->gadget, value); | |
1590 | } | |
1591 | ||
7d12e780 | 1592 | static irqreturn_t at91_vbus_irq(int irq, void *_udc) |
bae4bd84 DB |
1593 | { |
1594 | struct at91_udc *udc = _udc; | |
bae4bd84 DB |
1595 | |
1596 | /* vbus needs at least brief debouncing */ | |
1597 | udelay(10); | |
4037242c | 1598 | at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin)); |
bae4bd84 DB |
1599 | |
1600 | return IRQ_HANDLED; | |
1601 | } | |
1602 | ||
4037242c RM |
1603 | static void at91_vbus_timer_work(struct work_struct *work) |
1604 | { | |
1605 | struct at91_udc *udc = container_of(work, struct at91_udc, | |
1606 | vbus_timer_work); | |
1607 | ||
1608 | at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin)); | |
1609 | ||
1610 | if (!timer_pending(&udc->vbus_timer)) | |
1611 | mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT); | |
1612 | } | |
1613 | ||
1614 | static void at91_vbus_timer(unsigned long data) | |
1615 | { | |
1616 | struct at91_udc *udc = (struct at91_udc *)data; | |
1617 | ||
1618 | /* | |
1619 | * If we are polling vbus it is likely that the gpio is on an | |
1620 | * bus such as i2c or spi which may sleep, so schedule some work | |
1621 | * to read the vbus gpio | |
1622 | */ | |
1623 | if (!work_pending(&udc->vbus_timer_work)) | |
1624 | schedule_work(&udc->vbus_timer_work); | |
1625 | } | |
1626 | ||
f3d8bf34 SAS |
1627 | static int at91_start(struct usb_gadget *gadget, |
1628 | struct usb_gadget_driver *driver) | |
bae4bd84 | 1629 | { |
f3d8bf34 | 1630 | struct at91_udc *udc; |
bae4bd84 | 1631 | |
f3d8bf34 | 1632 | udc = container_of(gadget, struct at91_udc, gadget); |
bae4bd84 DB |
1633 | udc->driver = driver; |
1634 | udc->gadget.dev.driver = &driver->driver; | |
65c84ea1 | 1635 | udc->gadget.dev.of_node = udc->pdev->dev.of_node; |
bae4bd84 DB |
1636 | udc->enabled = 1; |
1637 | udc->selfpowered = 1; | |
1638 | ||
bae4bd84 DB |
1639 | DBG("bound to %s\n", driver->driver.name); |
1640 | return 0; | |
1641 | } | |
bae4bd84 | 1642 | |
f3d8bf34 SAS |
1643 | static int at91_stop(struct usb_gadget *gadget, |
1644 | struct usb_gadget_driver *driver) | |
bae4bd84 | 1645 | { |
f3d8bf34 | 1646 | struct at91_udc *udc; |
4f4c5e36 | 1647 | unsigned long flags; |
bae4bd84 | 1648 | |
f3d8bf34 | 1649 | udc = container_of(gadget, struct at91_udc, gadget); |
4f4c5e36 | 1650 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1651 | udc->enabled = 0; |
ffd3326b | 1652 | at91_udp_write(udc, AT91_UDP_IDR, ~0); |
4f4c5e36 | 1653 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 | 1654 | |
eb0be47d | 1655 | udc->gadget.dev.driver = NULL; |
bae4bd84 DB |
1656 | udc->driver = NULL; |
1657 | ||
1658 | DBG("unbound from %s\n", driver->driver.name); | |
1659 | return 0; | |
1660 | } | |
bae4bd84 DB |
1661 | |
1662 | /*-------------------------------------------------------------------------*/ | |
1663 | ||
1664 | static void at91udc_shutdown(struct platform_device *dev) | |
1665 | { | |
4f4c5e36 HH |
1666 | struct at91_udc *udc = platform_get_drvdata(dev); |
1667 | unsigned long flags; | |
1668 | ||
bae4bd84 | 1669 | /* force disconnect on reboot */ |
4f4c5e36 | 1670 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1671 | pullup(platform_get_drvdata(dev), 0); |
4f4c5e36 | 1672 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 DB |
1673 | } |
1674 | ||
d1494a34 JCPV |
1675 | static void __devinit at91udc_of_init(struct at91_udc *udc, |
1676 | struct device_node *np) | |
1677 | { | |
1678 | struct at91_udc_data *board = &udc->board; | |
1679 | u32 val; | |
1680 | enum of_gpio_flags flags; | |
1681 | ||
1682 | if (of_property_read_u32(np, "atmel,vbus-polled", &val) == 0) | |
1683 | board->vbus_polled = 1; | |
1684 | ||
1685 | board->vbus_pin = of_get_named_gpio_flags(np, "atmel,vbus-gpio", 0, | |
1686 | &flags); | |
1687 | board->vbus_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0; | |
1688 | ||
1689 | board->pullup_pin = of_get_named_gpio_flags(np, "atmel,pullup-gpio", 0, | |
1690 | &flags); | |
1691 | ||
1692 | board->pullup_active_low = (flags & OF_GPIO_ACTIVE_LOW) ? 1 : 0; | |
1693 | } | |
1694 | ||
1695 | static int __devinit at91udc_probe(struct platform_device *pdev) | |
bae4bd84 DB |
1696 | { |
1697 | struct device *dev = &pdev->dev; | |
1698 | struct at91_udc *udc; | |
1699 | int retval; | |
ffd3326b | 1700 | struct resource *res; |
bae4bd84 DB |
1701 | |
1702 | if (!dev->platform_data) { | |
1703 | /* small (so we copy it) but critical! */ | |
1704 | DBG("missing platform_data\n"); | |
1705 | return -ENODEV; | |
1706 | } | |
1707 | ||
8b2e7668 | 1708 | if (pdev->num_resources != 2) { |
f3db6e82 | 1709 | DBG("invalid num_resources\n"); |
8b2e7668 DB |
1710 | return -ENODEV; |
1711 | } | |
1712 | if ((pdev->resource[0].flags != IORESOURCE_MEM) | |
1713 | || (pdev->resource[1].flags != IORESOURCE_IRQ)) { | |
f3db6e82 | 1714 | DBG("invalid resource type\n"); |
8b2e7668 DB |
1715 | return -ENODEV; |
1716 | } | |
1717 | ||
ffd3326b AV |
1718 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1719 | if (!res) | |
1720 | return -ENXIO; | |
1721 | ||
d8bb0fd2 | 1722 | if (!request_mem_region(res->start, resource_size(res), driver_name)) { |
bae4bd84 DB |
1723 | DBG("someone's using UDC memory\n"); |
1724 | return -EBUSY; | |
1725 | } | |
1726 | ||
1727 | /* init software state */ | |
1728 | udc = &controller; | |
1729 | udc->gadget.dev.parent = dev; | |
d1494a34 JCPV |
1730 | if (pdev->dev.of_node) |
1731 | at91udc_of_init(udc, pdev->dev.of_node); | |
1732 | else | |
1733 | memcpy(&udc->board, dev->platform_data, | |
1734 | sizeof(struct at91_udc_data)); | |
bae4bd84 | 1735 | udc->pdev = pdev; |
bae4bd84 | 1736 | udc->enabled = 0; |
4f4c5e36 | 1737 | spin_lock_init(&udc->lock); |
bae4bd84 | 1738 | |
f3db6e82 DB |
1739 | /* rm9200 needs manual D+ pullup; off by default */ |
1740 | if (cpu_is_at91rm9200()) { | |
3285e0ec | 1741 | if (gpio_is_valid(udc->board.pullup_pin)) { |
f3db6e82 DB |
1742 | DBG("no D+ pullup?\n"); |
1743 | retval = -ENODEV; | |
1744 | goto fail0; | |
1745 | } | |
1746 | retval = gpio_request(udc->board.pullup_pin, "udc_pullup"); | |
1747 | if (retval) { | |
1748 | DBG("D+ pullup is busy\n"); | |
1749 | goto fail0; | |
1750 | } | |
1751 | gpio_direction_output(udc->board.pullup_pin, | |
1752 | udc->board.pullup_active_low); | |
1753 | } | |
1754 | ||
bb24280f | 1755 | /* newer chips have more FIFO memory than rm9200 */ |
bf1f0a05 | 1756 | if (cpu_is_at91sam9260() || cpu_is_at91sam9g20()) { |
bb24280f DB |
1757 | udc->ep[0].maxpacket = 64; |
1758 | udc->ep[3].maxpacket = 64; | |
1759 | udc->ep[4].maxpacket = 512; | |
1760 | udc->ep[5].maxpacket = 512; | |
23f6d914 | 1761 | } else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) { |
bb24280f DB |
1762 | udc->ep[3].maxpacket = 64; |
1763 | } else if (cpu_is_at91sam9263()) { | |
1764 | udc->ep[0].maxpacket = 64; | |
1765 | udc->ep[3].maxpacket = 64; | |
1766 | } | |
1767 | ||
d8bb0fd2 | 1768 | udc->udp_baseaddr = ioremap(res->start, resource_size(res)); |
ffd3326b | 1769 | if (!udc->udp_baseaddr) { |
f3db6e82 DB |
1770 | retval = -ENOMEM; |
1771 | goto fail0a; | |
ffd3326b AV |
1772 | } |
1773 | ||
1774 | udc_reinit(udc); | |
1775 | ||
bae4bd84 DB |
1776 | /* get interface and function clocks */ |
1777 | udc->iclk = clk_get(dev, "udc_clk"); | |
1778 | udc->fclk = clk_get(dev, "udpck"); | |
1779 | if (IS_ERR(udc->iclk) || IS_ERR(udc->fclk)) { | |
1780 | DBG("clocks missing\n"); | |
29ba4b53 | 1781 | retval = -ENODEV; |
f3db6e82 DB |
1782 | /* NOTE: we "know" here that refcounts on these are NOPs */ |
1783 | goto fail0b; | |
bae4bd84 DB |
1784 | } |
1785 | ||
1786 | retval = device_register(&udc->gadget.dev); | |
8ab10400 RR |
1787 | if (retval < 0) { |
1788 | put_device(&udc->gadget.dev); | |
f3db6e82 | 1789 | goto fail0b; |
8ab10400 | 1790 | } |
bae4bd84 | 1791 | |
8b2e7668 DB |
1792 | /* don't do anything until we have both gadget driver and VBUS */ |
1793 | clk_enable(udc->iclk); | |
ffd3326b AV |
1794 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); |
1795 | at91_udp_write(udc, AT91_UDP_IDR, 0xffffffff); | |
29ba4b53 AV |
1796 | /* Clear all pending interrupts - UDP may be used by bootloader. */ |
1797 | at91_udp_write(udc, AT91_UDP_ICR, 0xffffffff); | |
8b2e7668 | 1798 | clk_disable(udc->iclk); |
bae4bd84 DB |
1799 | |
1800 | /* request UDC and maybe VBUS irqs */ | |
8b2e7668 | 1801 | udc->udp_irq = platform_get_irq(pdev, 0); |
f3db6e82 | 1802 | retval = request_irq(udc->udp_irq, at91_udc_irq, |
b5dd18d8 | 1803 | 0, driver_name, udc); |
f3db6e82 | 1804 | if (retval < 0) { |
8b2e7668 | 1805 | DBG("request irq %d failed\n", udc->udp_irq); |
bae4bd84 DB |
1806 | goto fail1; |
1807 | } | |
3285e0ec | 1808 | if (gpio_is_valid(udc->board.vbus_pin)) { |
f3db6e82 DB |
1809 | retval = gpio_request(udc->board.vbus_pin, "udc_vbus"); |
1810 | if (retval < 0) { | |
1811 | DBG("request vbus pin failed\n"); | |
1812 | goto fail2; | |
1813 | } | |
1814 | gpio_direction_input(udc->board.vbus_pin); | |
1815 | ||
29ba4b53 AV |
1816 | /* |
1817 | * Get the initial state of VBUS - we cannot expect | |
1818 | * a pending interrupt. | |
1819 | */ | |
4037242c RM |
1820 | udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin) ^ |
1821 | udc->board.vbus_active_low; | |
1822 | ||
1823 | if (udc->board.vbus_polled) { | |
1824 | INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work); | |
1825 | setup_timer(&udc->vbus_timer, at91_vbus_timer, | |
1826 | (unsigned long)udc); | |
1827 | mod_timer(&udc->vbus_timer, | |
1828 | jiffies + VBUS_POLL_TIMEOUT); | |
1829 | } else { | |
70756027 NF |
1830 | if (request_irq(gpio_to_irq(udc->board.vbus_pin), |
1831 | at91_vbus_irq, 0, driver_name, udc)) { | |
4037242c RM |
1832 | DBG("request vbus irq %d failed\n", |
1833 | udc->board.vbus_pin); | |
1834 | retval = -EBUSY; | |
1835 | goto fail3; | |
1836 | } | |
bae4bd84 DB |
1837 | } |
1838 | } else { | |
1839 | DBG("no VBUS detection, assuming always-on\n"); | |
1840 | udc->vbus = 1; | |
1841 | } | |
0f91349b SAS |
1842 | retval = usb_add_gadget_udc(dev, &udc->gadget); |
1843 | if (retval) | |
1844 | goto fail4; | |
bae4bd84 | 1845 | dev_set_drvdata(dev, udc); |
8b2e7668 | 1846 | device_init_wakeup(dev, 1); |
bae4bd84 DB |
1847 | create_debug_file(udc); |
1848 | ||
1849 | INFO("%s version %s\n", driver_name, DRIVER_VERSION); | |
1850 | return 0; | |
0f91349b | 1851 | fail4: |
3285e0ec | 1852 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled) |
70756027 | 1853 | free_irq(gpio_to_irq(udc->board.vbus_pin), udc); |
f3db6e82 | 1854 | fail3: |
3285e0ec | 1855 | if (gpio_is_valid(udc->board.vbus_pin)) |
f3db6e82 DB |
1856 | gpio_free(udc->board.vbus_pin); |
1857 | fail2: | |
1858 | free_irq(udc->udp_irq, udc); | |
bae4bd84 DB |
1859 | fail1: |
1860 | device_unregister(&udc->gadget.dev); | |
f3db6e82 DB |
1861 | fail0b: |
1862 | iounmap(udc->udp_baseaddr); | |
1863 | fail0a: | |
1864 | if (cpu_is_at91rm9200()) | |
1865 | gpio_free(udc->board.pullup_pin); | |
bae4bd84 | 1866 | fail0: |
d8bb0fd2 | 1867 | release_mem_region(res->start, resource_size(res)); |
bae4bd84 DB |
1868 | DBG("%s probe failed, %d\n", driver_name, retval); |
1869 | return retval; | |
1870 | } | |
1871 | ||
398acce7 | 1872 | static int __exit at91udc_remove(struct platform_device *pdev) |
bae4bd84 | 1873 | { |
8b2e7668 | 1874 | struct at91_udc *udc = platform_get_drvdata(pdev); |
ffd3326b | 1875 | struct resource *res; |
4f4c5e36 | 1876 | unsigned long flags; |
bae4bd84 DB |
1877 | |
1878 | DBG("remove\n"); | |
1879 | ||
0f91349b | 1880 | usb_del_gadget_udc(&udc->gadget); |
6bea476c DB |
1881 | if (udc->driver) |
1882 | return -EBUSY; | |
bae4bd84 | 1883 | |
4f4c5e36 | 1884 | spin_lock_irqsave(&udc->lock, flags); |
6bea476c | 1885 | pullup(udc, 0); |
4f4c5e36 | 1886 | spin_unlock_irqrestore(&udc->lock, flags); |
bae4bd84 | 1887 | |
8b2e7668 | 1888 | device_init_wakeup(&pdev->dev, 0); |
bae4bd84 | 1889 | remove_debug_file(udc); |
3285e0ec | 1890 | if (gpio_is_valid(udc->board.vbus_pin)) { |
70756027 | 1891 | free_irq(gpio_to_irq(udc->board.vbus_pin), udc); |
f3db6e82 DB |
1892 | gpio_free(udc->board.vbus_pin); |
1893 | } | |
8b2e7668 | 1894 | free_irq(udc->udp_irq, udc); |
bae4bd84 | 1895 | device_unregister(&udc->gadget.dev); |
ffd3326b AV |
1896 | |
1897 | iounmap(udc->udp_baseaddr); | |
f3db6e82 DB |
1898 | |
1899 | if (cpu_is_at91rm9200()) | |
1900 | gpio_free(udc->board.pullup_pin); | |
1901 | ||
ffd3326b | 1902 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
d8bb0fd2 | 1903 | release_mem_region(res->start, resource_size(res)); |
bae4bd84 DB |
1904 | |
1905 | clk_put(udc->iclk); | |
1906 | clk_put(udc->fclk); | |
1907 | ||
1908 | return 0; | |
1909 | } | |
1910 | ||
1911 | #ifdef CONFIG_PM | |
8b2e7668 | 1912 | static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg) |
bae4bd84 | 1913 | { |
8b2e7668 DB |
1914 | struct at91_udc *udc = platform_get_drvdata(pdev); |
1915 | int wake = udc->driver && device_may_wakeup(&pdev->dev); | |
4f4c5e36 | 1916 | unsigned long flags; |
bae4bd84 | 1917 | |
8b2e7668 DB |
1918 | /* Unless we can act normally to the host (letting it wake us up |
1919 | * whenever it has work for us) force disconnect. Wakeup requires | |
1920 | * PLLB for USB events (signaling for reset, wakeup, or incoming | |
1921 | * tokens) and VBUS irqs (on systems which support them). | |
bae4bd84 | 1922 | */ |
8b2e7668 DB |
1923 | if ((!udc->suspended && udc->addr) |
1924 | || !wake | |
1925 | || at91_suspend_entering_slow_clock()) { | |
4f4c5e36 | 1926 | spin_lock_irqsave(&udc->lock, flags); |
bae4bd84 | 1927 | pullup(udc, 0); |
66e56ce7 | 1928 | wake = 0; |
4f4c5e36 | 1929 | spin_unlock_irqrestore(&udc->lock, flags); |
8b2e7668 DB |
1930 | } else |
1931 | enable_irq_wake(udc->udp_irq); | |
1932 | ||
66e56ce7 | 1933 | udc->active_suspend = wake; |
3285e0ec | 1934 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled && wake) |
66e56ce7 | 1935 | enable_irq_wake(udc->board.vbus_pin); |
bae4bd84 DB |
1936 | return 0; |
1937 | } | |
1938 | ||
8b2e7668 | 1939 | static int at91udc_resume(struct platform_device *pdev) |
bae4bd84 | 1940 | { |
8b2e7668 | 1941 | struct at91_udc *udc = platform_get_drvdata(pdev); |
4f4c5e36 | 1942 | unsigned long flags; |
bae4bd84 | 1943 | |
3285e0ec | 1944 | if (gpio_is_valid(udc->board.vbus_pin) && !udc->board.vbus_polled && |
4037242c | 1945 | udc->active_suspend) |
66e56ce7 DB |
1946 | disable_irq_wake(udc->board.vbus_pin); |
1947 | ||
bae4bd84 | 1948 | /* maybe reconnect to host; if so, clocks on */ |
66e56ce7 DB |
1949 | if (udc->active_suspend) |
1950 | disable_irq_wake(udc->udp_irq); | |
4f4c5e36 HH |
1951 | else { |
1952 | spin_lock_irqsave(&udc->lock, flags); | |
66e56ce7 | 1953 | pullup(udc, 1); |
4f4c5e36 HH |
1954 | spin_unlock_irqrestore(&udc->lock, flags); |
1955 | } | |
bae4bd84 DB |
1956 | return 0; |
1957 | } | |
1958 | #else | |
1959 | #define at91udc_suspend NULL | |
1960 | #define at91udc_resume NULL | |
1961 | #endif | |
1962 | ||
d1494a34 JCPV |
1963 | #if defined(CONFIG_OF) |
1964 | static const struct of_device_id at91_udc_dt_ids[] = { | |
1965 | { .compatible = "atmel,at91rm9200-udc" }, | |
1966 | { /* sentinel */ } | |
1967 | }; | |
1968 | ||
1969 | MODULE_DEVICE_TABLE(of, at91_udc_dt_ids); | |
1970 | #endif | |
1971 | ||
dee497df | 1972 | static struct platform_driver at91_udc_driver = { |
398acce7 | 1973 | .remove = __exit_p(at91udc_remove), |
bae4bd84 DB |
1974 | .shutdown = at91udc_shutdown, |
1975 | .suspend = at91udc_suspend, | |
8b2e7668 | 1976 | .resume = at91udc_resume, |
bae4bd84 DB |
1977 | .driver = { |
1978 | .name = (char *) driver_name, | |
1979 | .owner = THIS_MODULE, | |
d1494a34 | 1980 | .of_match_table = of_match_ptr(at91_udc_dt_ids), |
bae4bd84 DB |
1981 | }, |
1982 | }; | |
1983 | ||
398acce7 | 1984 | static int __init udc_init_module(void) |
bae4bd84 | 1985 | { |
dee497df | 1986 | return platform_driver_probe(&at91_udc_driver, at91udc_probe); |
bae4bd84 DB |
1987 | } |
1988 | module_init(udc_init_module); | |
1989 | ||
398acce7 | 1990 | static void __exit udc_exit_module(void) |
bae4bd84 | 1991 | { |
dee497df | 1992 | platform_driver_unregister(&at91_udc_driver); |
bae4bd84 DB |
1993 | } |
1994 | module_exit(udc_exit_module); | |
1995 | ||
8b2e7668 | 1996 | MODULE_DESCRIPTION("AT91 udc driver"); |
bae4bd84 DB |
1997 | MODULE_AUTHOR("Thomas Rathbone, David Brownell"); |
1998 | MODULE_LICENSE("GPL"); | |
f34c32f1 | 1999 | MODULE_ALIAS("platform:at91_udc"); |